Release_Notes.html 6.0 KB

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  7. <title>Release Notes for STM32H5xx CMSIS</title>
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  24. <h1 id="release-notes-for-stm32h5xx-cmsis">Release Notes for <mark> STM32H5xx CMSIS </mark></h1>
  25. <p>Copyright © 2023 STMicroelectronics<br />
  26. </p>
  27. <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
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  31. <h1 id="update-history"><strong>Update History</strong></h1>
  32. <div class="collapse">
  33. <input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" checked aria-hidden="true"><strong>V1.4.0 / 05-February-2025</strong></label>
  34. <div>
  35. <h2 id="main-changes">Main Changes</h2>
  36. <p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H523xx, STM32H533xx, STM32H562xx, STM32H563xx and STM32H573xx reference manual) and <strong>RM0492</strong> (STM32H503xx reference manual)</p>
  37. <ul>
  38. <li>Rename ADC_AWD3CR_AWD2CH_19 to ADC_AWD3CR_AWD3CH_19 define</li>
  39. <li>Remove HWCFGR, VERR, PIDR and SIDR registers from CRC_TypeDef</li>
  40. </ul>
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  43. <div class="collapse">
  44. <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" checked aria-hidden="true"><strong>V1.3.1 / 30-October-2024</strong></label>
  45. <div>
  46. <h2 id="main-changes-1">Main Changes</h2>
  47. <p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
  48. <ul>
  49. <li>Update to use #include "core_cm33.h" instead of #include &lt;core_cm33.h&gt; to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)</li>
  50. <li>Update IS_SPI_LIMITED macro to return an essential boolean</li>
  51. </ul>
  52. </div>
  53. </div>
  54. <div class="collapse">
  55. <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 05-June-2024</strong></label>
  56. <div>
  57. <h2 id="main-changes-2">Main Changes</h2>
  58. <p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
  59. <ul>
  60. <li>Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines</li>
  61. <li>Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines</li>
  62. <li>Add USART_DMAREQUESTS_SW_WA define</li>
  63. <li>Rename EXTI_RTSR2_TR to EXTI_RTSR2_RT define</li>
  64. <li>Rename EXTI_FTSR2_TR to EXTI_FTSR2_FT define</li>
  65. <li>Remove unused ADC common status and ADC common group regular data registers for STM32H503xx devices</li>
  66. <li>Fix __SAUREGION_PRESENT value to 0 for STM32H503xx devices</li>
  67. <li>Fix incorrect character in the definition of OCTOSPI_CR register</li>
  68. <li>Correct TIM_CCRx_CCRx constants</li>
  69. </ul>
  70. </div>
  71. </div>
  72. <div class="collapse">
  73. <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0 / 09-February-2024</strong></label>
  74. <div>
  75. <h2 id="main-changes-3">Main Changes</h2>
  76. <ul>
  77. <li>First official release of STM32H5xx CMSIS drivers to support <strong>STM32H533xx and STM32H523xx</strong> devices</li>
  78. <li>Add bit definition for I3C_BCR register</li>
  79. <li>Add IS_DMA_PFREQ_INSTANCE macro</li>
  80. <li>Fix Ticket 163445: [FLASH][CMSIS] Wrong EDATA_STRT start sectors mask size</li>
  81. <li>Fix Ticket 163090: [FOSS-Audit] Licensing issues: Missing copyright from Arm Limited and original header not retained</li>
  82. <li>Update CubeIDE projects to be compliant with GCC12 diagnostics</li>
  83. <li>Fix Ticket 165407: [H5][GTZC][CMSIS]: wrong Flash illegal access bit definition</li>
  84. <li>Fix Ticket 147880: [STM32H5]|FLASH_HAL] Some option bytes are missing in stm32h5xx_hal_flash_ex.h</li>
  85. <li>Set FMC_SDCMR_MODE_2 bit field definition to 0x4</li>
  86. <li>Fix Ticket 162902: [GitHub] Wrong declaration of g_pfnVectors size in gcc/startup files</li>
  87. <li>Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions</li>
  88. </ul>
  89. </div>
  90. </div>
  91. <div class="collapse">
  92. <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
  93. <div>
  94. <h2 id="main-changes-4">Main Changes</h2>
  95. <ul>
  96. <li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
  97. <li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
  98. <li>Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.</li>
  99. </ul>
  100. </div>
  101. </div>
  102. <div class="collapse">
  103. <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
  104. <div>
  105. <h2 id="main-changes-5">Main Changes</h2>
  106. <ul>
  107. <li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
  108. </ul>
  109. </div>
  110. </div>
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