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@@ -57,7 +57,7 @@
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/****** Cortex-M0 Processor Exceptions Numbers ****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt */
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- SVC_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */
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+ SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt */
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PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< Cortex-M0+ System Tick Interrupt */
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@@ -239,10 +239,10 @@ typedef struct
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__IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
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uint32_t RESERVED1; /*!< Reserved, 0x18 */
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uint32_t RESERVED2; /*!< Reserved, 0x1C */
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- __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
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- __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
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+ __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
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+ __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
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__IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
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- __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
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+ __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
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uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
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__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
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uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
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@@ -257,6 +257,11 @@ typedef struct
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__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */
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} ADC_Common_TypeDef;
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+/* Legacy registers naming */
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+#define TR1 AWD1TR
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+#define TR2 AWD2TR
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+#define TR3 AWD3TR
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+
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/**
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* @brief AES hardware accelerator
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*/
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@@ -1470,71 +1475,129 @@ typedef struct
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#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
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#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
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-/******************** Bit definition for ADC_TR1 register *******************/
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-#define ADC_TR1_LT1_Pos (0U)
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-#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
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-#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
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-#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
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-#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
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-#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
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-#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
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-#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
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-#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
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-#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
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-#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
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-#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
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-#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
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-#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
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-#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
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-
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-#define ADC_TR1_HT1_Pos (16U)
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-#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
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-#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
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-#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
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-#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
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-#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
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-#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
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-#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
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-#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
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-#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
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-#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
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-#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
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-#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
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-#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
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-#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
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-
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-/******************** Bit definition for ADC_TR2 register *******************/
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-#define ADC_TR2_LT2_Pos (0U)
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-#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
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-#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
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-#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
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-#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
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-#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
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-#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
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-#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
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-#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
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-#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
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-#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
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-#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
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-#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
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-#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
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-#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
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-
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-#define ADC_TR2_HT2_Pos (16U)
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-#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
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-#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
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-#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
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-#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
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-#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
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-#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
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-#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
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-#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
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-#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
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-#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
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-#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
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-#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
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-#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
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-#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
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+/******************** Bit definition for ADC_AWD1TR register ****************/
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+#define ADC_AWD1TR_LT1_Pos (0U)
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+#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */
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+#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
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+#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */
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+#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */
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+#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */
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+#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */
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+#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */
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+#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */
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+#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */
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+#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */
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+#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */
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+#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */
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+#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */
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+#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */
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+
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+#define ADC_AWD1TR_HT1_Pos (16U)
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+#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */
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+#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
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+#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */
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+#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */
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+#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */
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+#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */
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+#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */
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+#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */
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+#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */
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+#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */
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+#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */
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+#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */
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+#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */
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+#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */
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+
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+/* Legacy definitions */
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+#define ADC_TR1_LT1 ADC_AWD1TR_LT1
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+#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0
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+#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1
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+#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
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+#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3
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+#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4
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+#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
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+#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6
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+#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7
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+#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8
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+#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9
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+#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10
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+#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11
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+
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+#define ADC_TR1_HT1 ADC_AWD1TR_HT1
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+#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0
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+#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1
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+#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2
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+#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3
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+#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4
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+#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5
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+#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6
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+#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7
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+#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8
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+#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9
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+#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10
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+#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11
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+
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+/******************** Bit definition for ADC_AWD2TR register *******************/
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+#define ADC_AWD2TR_LT2_Pos (0U)
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+#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */
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+#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
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+#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */
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+#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */
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+#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */
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+#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */
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+#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */
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+#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */
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+#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */
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+#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */
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+#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */
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+#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */
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+#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */
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+#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */
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+
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+#define ADC_AWD2TR_HT2_Pos (16U)
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+#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */
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+#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
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+#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */
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+#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */
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+#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */
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+#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */
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+#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */
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+#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */
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+#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */
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+#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */
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+#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */
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+#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */
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+#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */
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+#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */
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+
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+/* Legacy definitions */
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+#define ADC_TR2_LT2 ADC_AWD2TR_LT2
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+#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0
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+#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1
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+#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2
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+#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3
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+#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4
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+#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5
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+#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6
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+#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7
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+#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8
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+#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9
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+#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10
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+#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11
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+
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+#define ADC_TR2_HT2 ADC_AWD2TR_HT2
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+#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
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+#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1
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+#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2
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+#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3
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+#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4
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+#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5
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+#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6
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+#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7
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+#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8
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+#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9
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+#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10
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+#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11
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/******************** Bit definition for ADC_CHSELR register ****************/
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#define ADC_CHSELR_CHSEL_Pos (0U)
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@@ -1663,39 +1726,67 @@ typedef struct
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#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
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#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
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-/******************** Bit definition for ADC_TR3 register *******************/
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-#define ADC_TR3_LT3_Pos (0U)
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-#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
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-#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
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-#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
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-#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
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-#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
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-#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
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-#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
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-#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
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-#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
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-#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
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-#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
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-#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
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-#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
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-#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
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-
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-#define ADC_TR3_HT3_Pos (16U)
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-#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
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-#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
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-#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
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-#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
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-#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
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-#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
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-#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
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-#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
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-#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
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-#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
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-#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
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-#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
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-#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
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-#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
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-
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+/******************** Bit definition for ADC_AWD3TR register *******************/
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+#define ADC_AWD3TR_LT3_Pos (0U)
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+#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */
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+#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
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+#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */
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+#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */
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+#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */
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+#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */
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+#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */
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+#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */
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+#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */
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+#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */
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+#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */
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+#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */
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+#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */
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+#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */
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+
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+#define ADC_AWD3TR_HT3_Pos (16U)
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+#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
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+#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
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+#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
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+#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
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+#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
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+#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
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+#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
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+#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
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+#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
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+#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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+#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */
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+#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */
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+#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */
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+#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */
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+
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+/* Legacy definitions */
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+#define ADC_TR3_LT3 ADC_AWD3TR_LT3
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+#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0
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+#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1
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+#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2
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+#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3
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+#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4
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+#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5
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+#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6
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+#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7
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+#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8
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+#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9
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+#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10
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+#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11
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+
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+#define ADC_TR3_HT3 ADC_AWD3TR_HT3
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+#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0
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+#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
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+#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2
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+#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3
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+#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4
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+#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5
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+#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6
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+#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7
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+#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8
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+#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9
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+#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
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+#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11
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/******************** Bit definition for ADC_DR register ********************/
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#define ADC_DR_DATA_Pos (0U)
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#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
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@@ -11432,6 +11523,18 @@ typedef struct
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/******************** LPUART Instance *****************************************/
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#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
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+
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+/******************************************************************************/
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+/* For a painless codes migration between the STM32WLxx device product */
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+/* lines, the aliases defined below are put in place to overcome the */
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+/* differences in the interrupt handlers and IRQn definitions. */
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+/* No need to update developed interrupt code when moving across */
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+/* product lines within the same STM32WL Family */
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+/******************************************************************************/
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+#if defined(CORE_CM0PLUS)
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+/* Aliases for __IRQn */
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+#define SVC_IRQn SVCall_IRQn
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+#endif /* CORE_CM0PLUS */
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/**
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* @}
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*/
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Rania JMAI