fix(lp_i2c): Fixed a bug where the LP_I2C did not send NACK for 16-byte reads

This commit updates the LP_I2C driver used by the LP CPU wherein the
driver did not send out a NACK when we do a read of multiple of the FIFO
depth bytes. This was because the LP I2C controller was configured to
send an ACK when the Rx FIFO reaches the threshold instead of a NACK.
This commit updates the behavior.

components/hal/esp32c6/include/hal/i2c_ll.h

@@ -655,6 +655,20 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
     hw->ctr.conf_upgate = 1;
 }
 
+/**
+ * @brief Set the ACK level that the I2C master must send when the Rx FIFO count has reached the threshold value.
+ *        ack_level: 1 (NACK)
+ *        ack_level: 0 (ACK)
+ *
+ * @param  hw Beginning address of the peripheral registers
+ *
+ * @return None
+ */
+static inline void i2c_ll_master_rx_full_ack_level(i2c_dev_t *hw, int ack_level)
+{
+    hw->ctr.rx_full_ack_level = ack_level;
+}
+
 /**
  * @brief Set I2C source clock
  *

components/ulp/lp_core/lp_core_i2c.c

@@ -143,6 +143,9 @@ esp_err_t lp_core_i2c_master_init(i2c_port_t lp_i2c_num, const lp_core_i2c_cfg_t
     /* Enable SDA and SCL filtering. This configuration matches the HP I2C filter config */
     i2c_ll_set_filter(i2c_hal.dev, LP_I2C_FILTER_CYC_NUM_DEF);
 
+    /* Configure the I2C master to send a NACK when the Rx FIFO count is full */
+    i2c_ll_master_rx_full_ack_level(i2c_hal.dev, 1);
+
     /* Synchronize the config register values to the LP I2C peripheral clock */
     i2c_ll_update(i2c_hal.dev);