Merge branch 'bugfix/init_memctl' into 'master'

bootloader, esp32: add workaround for Tensilica erratum 572

See merge request idf/esp-idf!3605

components/bootloader_support/src/bootloader_init.c

@@ -72,6 +72,7 @@ static void wdt_reset_check(void);
 esp_err_t bootloader_init()
 {
     cpu_configure_region_protection();
+    cpu_init_memctl();
 
     /* Sanity check that static RAM is after the stack */
 #ifndef NDEBUG

components/esp32/cpu_start.c

@@ -124,6 +124,7 @@ void IRAM_ATTR call_start_cpu0()
     RESET_REASON rst_reas[2];
 #endif
     cpu_configure_region_protection();
+    cpu_init_memctl();
 
     //Move exception vectors to IRAM
     asm volatile (\
@@ -249,6 +250,7 @@ void IRAM_ATTR call_start_cpu1()
 
     ets_set_appcpu_boot_addr(0);
     cpu_configure_region_protection();
+    cpu_init_memctl();
 
 #if CONFIG_CONSOLE_UART_NONE
     ets_install_putc1(NULL);

components/esp32/include/xtensa/config/core.h

@@ -1401,5 +1401,16 @@ extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
 #define XCHAL_ERRATUM_497	0
 #endif
 
+/*
+ * Erratum 572 (releases TBD, but present in ESP32)
+ * Disable zero-overhead loop buffer to prevent rare illegal instruction
+ * exceptions while executing zero-overhead loops.
+ */
+#if ( XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 )
+#define XCHAL_ERRATUM_572   1
+#else
+#define XCHAL_ERRATUM_572   0
+#endif
+
 #endif /*XTENSA_CONFIG_CORE_H*/
 

components/soc/esp32/include/soc/cpu.h

@@ -19,6 +19,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include "xtensa/corebits.h"
+#include "xtensa/config/core.h"
 
 /* C macros for xtensa special register read/write/exchange */
 
@@ -51,6 +52,14 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
     asm volatile ("witlb  %1, %0; isync\n" :: "r" (vpn), "r" (attr));
 }
 
+static inline void cpu_init_memctl()
+{
+#if XCHAL_ERRATUM_572
+    uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
+    WSR(MEMCTL, memctl);
+#endif // XCHAL_ERRATUM_572
+}
+
 /**
  * @brief Configure memory region protection
  *