ulp: migrate tests to pytest embedded

components/ulp/.build-test-rules.yml

@@ -0,0 +1,9 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/ulp/test_apps/ulp_fsm:
+  enable:
+    - if: SOC_ULP_SUPPORTED == 1
+
+components/ulp/test_apps/ulp_riscv:
+  enable:
+    - if: SOC_RISCV_COPROC_SUPPORTED == 1

components/ulp/test/CMakeLists.txt

@@ -1,24 +0,0 @@
-if(NOT CONFIG_ULP_COPROC_TYPE_FSM AND NOT CONFIG_ULP_COPROC_TYPE_RISCV)
-    # Nothing to test if no co-processor enabled
-    return()
-endif()
-
-if(CONFIG_ULP_COPROC_TYPE_FSM)
-
-    set(src_dirs "ulp_fsm")
-    set(ulp_sources "ulp_fsm/ulp/test_jumps.S")
-
-elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
-
-    set(src_dirs "ulp_riscv")
-    set(ulp_sources "ulp_riscv/ulp/test_main.c")
-
-endif()
-
-idf_component_register(SRC_DIRS ${src_dirs}
-PRIV_INCLUDE_DIRS .
-PRIV_REQUIRES cmock ulp soc esp_common driver)
-
-set(ulp_app_name ulp_test_app)
-set(ulp_exp_dep_srcs ${src_dirs})
-ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")

components/ulp/test_apps/ulp_fsm/CMakeLists.txt

@@ -0,0 +1,5 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(ulp_fsm_test)

components/ulp/test_apps/ulp_fsm/README.md

@@ -0,0 +1,3 @@
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- |
+

components/ulp/test_apps/ulp_fsm/main/CMakeLists.txt

@@ -0,0 +1,10 @@
+set(app_sources "test_app_main.c" "test_ulp.c")
+set(ulp_sources "ulp/test_jumps.S")
+
+idf_component_register(SRCS ${app_sources}
+                       REQUIRES ulp unity
+                       WHOLE_ARCHIVE)
+
+set(ulp_app_name ulp_test_app)
+set(ulp_exp_dep_srcs ${app_sources})
+ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")

components/ulp/test_apps/ulp_fsm/main/test_app_main.c

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+
+// Some resources are lazy allocated in the sleep code, the threshold is left for that case
+#define TEST_MEMORY_LEAK_THRESHOLD (-500)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}

components/ulp/test/ulp_fsm/test_ulp.c → components/ulp/test_apps/ulp_fsm/main/test_ulp.c

@@ -205,8 +205,6 @@ TEST_CASE("ULP FSM light-sleep wakeup test", "[ulp]")
     TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
-//IDF-5131
 TEST_CASE("ULP FSM deep-sleep wakeup test", "[ulp][reset=SW_CPU_RESET][ignore]")
 {
     assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -250,7 +248,6 @@ TEST_CASE("ULP FSM deep-sleep wakeup test", "[ulp][reset=SW_CPU_RESET][ignore]")
     UNITY_TEST_FAIL(__LINE__, "Should not get here!");
 }
 
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
 
 TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
 {
@@ -265,6 +262,8 @@ TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
     /* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
     memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
 #pragma GCC diagnostic pop
+    uint32_t rtc_store0 = REG_READ(RTC_CNTL_STORE0_REG);
+    uint32_t rtc_store1 = REG_READ(RTC_CNTL_STORE1_REG);
 
     /* ULP co-processor program to read from and write to peripheral registers */
     const ulp_insn_t program[] = {
@@ -306,6 +305,10 @@ TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
     TEST_ASSERT_EQUAL_HEX16(0x89ab, RTC_SLOW_MEM[66] & 0xffff);
     TEST_ASSERT_EQUAL_HEX16(0x9a, RTC_SLOW_MEM[67] & 0xffff);
     TEST_ASSERT_EQUAL_HEX16(1, RTC_SLOW_MEM[68] & 0xffff);
+
+    /* Restore initial calibration values */
+    REG_WRITE(RTC_CNTL_STORE0_REG, rtc_store0);
+    REG_WRITE(RTC_CNTL_STORE1_REG, rtc_store1);
 }
 
 TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
@@ -344,6 +347,8 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
                 mask, not_mask);
 
         /* Set all bits in RTC_CNTL_STORE0_REG and reset all bits in RTC_CNTL_STORE1_REG */
+        uint32_t rtc_store0 = REG_READ(RTC_CNTL_STORE0_REG);
+        uint32_t rtc_store1 = REG_READ(RTC_CNTL_STORE1_REG);
         REG_WRITE(RTC_CNTL_STORE0_REG, 0xffffffff);
         REG_WRITE(RTC_CNTL_STORE1_REG, 0x00000000);
 
@@ -373,13 +378,17 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
         uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
         uint32_t set = REG_READ(RTC_CNTL_STORE1_REG);
         printf("clear: %08x set: %08x\n", clear, set);
+
+        /* Restore initial calibration values */
+        REG_WRITE(RTC_CNTL_STORE0_REG, rtc_store0);
+        REG_WRITE(RTC_CNTL_STORE1_REG, rtc_store1);
+
         TEST_ASSERT_EQUAL_HEX32(not_mask, clear);
         TEST_ASSERT_EQUAL_HEX32(mask, set);
     }
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
-//IDF-5131
+
 TEST_CASE("ULP FSM controls RTC_IO", "[ulp][ignore]")
 {
     assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -480,8 +489,6 @@ TEST_CASE("ULP FSM power consumption in deep sleep", "[ulp][ignore]")
     UNITY_TEST_FAIL(__LINE__, "Should not get here!");
 }
 
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
-
 TEST_CASE("ULP FSM timer setting", "[ulp]")
 {
     assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -547,8 +554,6 @@ TEST_CASE("ULP FSM timer setting", "[ulp]")
     }
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
-//IDF-5131
 #if !DISABLED_FOR_TARGETS(ESP32)
 TEST_CASE("ULP FSM can use temperature sensor (TSENS) in deep sleep", "[ulp][ignore]")
 {
@@ -719,5 +724,3 @@ TEST_CASE("ULP FSM can use ADC in deep sleep", "[ulp][ignore]")
     esp_deep_sleep_start();
     UNITY_TEST_FAIL(__LINE__, "Should not get here!");
 }
-
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)

components/ulp/test_apps/ulp_fsm/pytest_ulp_fsm_app.py

@@ -0,0 +1,15 @@
+# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.generic
+def test_ulp_fsm(dut: Dut) -> None:
+    dut.expect('Press ENTER to see the list of tests')
+    dut.write('![ignore]')
+    dut.expect_unity_test_output()

components/ulp/test_apps/ulp_fsm/sdkconfig.defaults

@@ -0,0 +1,5 @@
+CONFIG_ESP_TASK_WDT=n
+
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_FSM=y
+CONFIG_ULP_COPROC_RESERVE_MEM=4096

components/ulp/test_apps/ulp_riscv/CMakeLists.txt

@@ -0,0 +1,5 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(ulp_riscv_test)

components/ulp/test_apps/ulp_riscv/README.md

@@ -0,0 +1,3 @@
+| Supported Targets | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- |
+

components/ulp/test_apps/ulp_riscv/main/CMakeLists.txt

@@ -0,0 +1,10 @@
+set(app_sources "test_app_main.c" "test_ulp_riscv.c")
+set(ulp_sources "ulp/test_main.c")
+
+idf_component_register(SRCS ${app_sources}
+                       REQUIRES ulp unity
+                       WHOLE_ARCHIVE)
+
+set(ulp_app_name ulp_test_app)
+set(ulp_exp_dep_srcs ${app_sources})
+ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")

components/ulp/test_apps/ulp_riscv/main/test_app_main.c

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+
+// Some resources are lazy allocated in the sleep code, the threshold is left for that case
+#define TEST_MEMORY_LEAK_THRESHOLD (-500)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}

components/ulp/test/ulp_riscv/test_ulp_riscv_main.c → components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c

@@ -67,10 +67,7 @@ TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp]")
     ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
 
     /* Enter Light Sleep */
-    TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
-
-    /* Wait for wakeup from ULP RISC-V Coprocessor */
-    TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
+    esp_light_sleep_start();
 
     /* Wait till we receive the correct command response */
     gettimeofday(&start, NULL);
@@ -103,10 +100,7 @@ TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp]")
     ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
 
     /* Enter Light Sleep */
-    TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
-
-    /* Wait for wakeup from ULP RISC-V Coprocessor */
-    TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
+    esp_light_sleep_start();
 
     /* Wait till we receive the correct command response */
     gettimeofday(&start, NULL);
@@ -120,10 +114,7 @@ TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp]")
     TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
 
     /* Enter Light Sleep again */
-    TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
-
-    /* Wait for wakeup from ULP RISC-V Coprocessor */
-    TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
+    esp_light_sleep_start();
 
     /* Wait till we receive the correct command response */
     gettimeofday(&start, NULL);
@@ -201,8 +192,6 @@ TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]"
     TEST_ASSERT(ulp_riscv_is_running());
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
-//IDF-5131
 /*
 * Keep this test case as the last test case in this suite as a CPU reset occurs.
 * Add new test cases above in order to ensure they run when all test cases are run together.
@@ -222,5 +211,3 @@ TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=
     esp_deep_sleep_start();
     UNITY_TEST_FAIL(__LINE__, "Should not get here!");
 }
-
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)

components/ulp/test_apps/ulp_riscv/pytest_ulp_riscv.py

@@ -0,0 +1,14 @@
+# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.generic
+def test_ulp_riscv(dut: Dut) -> None:
+    dut.expect('Press ENTER to see the list of tests')
+    dut.write('![ignore]')
+    dut.expect_unity_test_output()

components/ulp/test_apps/ulp_riscv/sdkconfig.defaults

@@ -0,0 +1,5 @@
+CONFIG_ESP_TASK_WDT=n
+
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_RISCV=y
+CONFIG_ULP_COPROC_RESERVE_MEM=4096

components/ulp/ulp_riscv/ulp_core/ulp_riscv_adc.c

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "ulp_riscv_adc.h"
+#include "ulp_riscv_adc_ulp_core.h"
 #include "hal/adc_ll.h"
 
 int32_t ulp_riscv_adc_read_channel(adc_unit_t adc_n, int channel)

tools/unit-test-app/configs/default_2_c3

@@ -1,3 +1,3 @@
 # This config is split between targets since different component needs to be excluded
 CONFIG_IDF_TARGET="esp32c3"
-TEST_EXCLUDE_COMPONENTS=bt app_update esp_pm freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs lwip spiffs experimental_cpp_component ulp perfmon esp-tls test_utils
+TEST_EXCLUDE_COMPONENTS=bt app_update esp_pm freertos esp_hw_support esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon esp-tls test_utils

tools/unit-test-app/sdkconfig.defaults.esp32

@@ -1,6 +1,3 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
 CONFIG_ESP32_XTAL_FREQ_AUTO=y
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_TYPE_FSM=y
-CONFIG_ULP_COPROC_RESERVE_MEM=4096
 CONFIG_SPI_FLASH_SHARE_SPI1_BUS=y

tools/unit-test-app/sdkconfig.defaults.esp32s2

@@ -1,6 +1,2 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n
-
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_TYPE_RISCV=y
-CONFIG_ULP_COPROC_RESERVE_MEM=4096

tools/unit-test-app/sdkconfig.defaults.esp32s3

@@ -1,6 +1,2 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n
-
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_TYPE_RISCV=y
-CONFIG_ULP_COPROC_RESERVE_MEM=4096