esp_mm: h2 support

components/esp_mm/.build-test-rules.yml

@@ -1,7 +0,0 @@
-# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
-
-components/spi_flash/test_apps/mmap:
-  disable_test:
-    - if: IDF_TARGET == "esp32h2"
-      temporary: true
-      reason: h2 not supported yet

components/esp_mm/port/esp32h2/ext_mem_layout.c

@@ -15,5 +15,12 @@
  * coalesce adjacent regions
  */
 const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
-    [0] = {},
+    [0] = {
+        .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
+        .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
+        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
+        .targets = MMU_TARGET_FLASH0,
+        .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
+    },
 };

components/esp_system/ld/esp32h2/memory.ld.in

@@ -64,7 +64,7 @@ MEMORY
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped instruction data */
-  iram0_2_seg (RX) :                 org = 0x42000020, len = (IDRAM0_2_SEG_SIZE >> 1) -0x20
+  irom_seg (RX) :                    org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 
   /**
    * (0x20 offset above is a convenience for the app binary image generation.
@@ -83,9 +83,9 @@ MEMORY
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x42000020 + (IDRAM0_2_SEG_SIZE >> 1), len = (IDRAM0_2_SEG_SIZE >> 1)-0x20
+  drom_seg (R) :                     org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 
-  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+  /* (See irom_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
   /**
@@ -122,19 +122,19 @@ REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
 REGION_ALIAS("rtc_data_location", rtc_iram_seg );
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
-  REGION_ALIAS("default_code_seg", iram0_2_seg);
+  REGION_ALIAS("default_code_seg", irom_seg);
 #else
   REGION_ALIAS("default_code_seg", iram0_0_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
-  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+  REGION_ALIAS("default_rodata_seg", drom_seg);
 #else
   REGION_ALIAS("default_rodata_seg", dram0_0_seg);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 /**
- *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
+ *  If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
  *  also be first in the segment.
  */
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS

components/esp_system/port/cpu_start.c

@@ -400,10 +400,7 @@ void IRAM_ATTR call_start_cpu0(void)
     mspi_timing_flash_tuning();
 #endif
 
-#if !CONFIG_IDF_TARGET_ESP32H2
-    //ESP32H2 MMU-TODO: IDF-6251
     esp_mmu_map_init();
-#endif  //!CONFIG_IDF_TARGET_ESP32H2
 
 #if CONFIG_SPIRAM_BOOT_INIT
     if (esp_psram_init() != ESP_OK) {

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -223,10 +223,18 @@ config SOC_MMU_PAGE_SIZE_CONFIGURABLE
     bool
     default y
 
+config SOC_MMU_PERIPH_NUM
+    int
+    default 1
+
 config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
     int
     default 1
 
+config SOC_MMU_DI_VADDR_SHARED
+    bool
+    default y
+
 config SOC_DS_SIGNATURE_MAX_BIT_LEN
     int
     default 3072

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -13,14 +13,12 @@
 extern "C" {
 #endif
 
-/*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_CACHE_ADDRESS_LOW             0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH            (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * 128)) // MMU has 256 pages, first 128 for instruction
+#define IRAM0_CACHE_ADDRESS_LOW                  0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH                 (IRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
 
-/*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_CACHE_ADDRESS_LOW             IRAM0_CACHE_ADDRESS_HIGH // ESP32H2-TODO : IDF-6370
-#define DRAM0_CACHE_ADDRESS_HIGH            (DRAM0_CACHE_ADDRESS_LOW + ((CONFIG_MMU_PAGE_SIZE) * 128)) // MMU has 256 pages, second 128 for data
-#define DRAM0_CACHE_OPERATION_HIGH          DRAM0_CACHE_ADDRESS_HIGH
+#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
+#define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
+#define DRAM0_CACHE_OPERATION_HIGH               DRAM0_CACHE_ADDRESS_HIGH
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
 #define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
@@ -33,14 +31,6 @@ extern "C" {
 #define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE)
 #define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE)
 
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x200
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x200
-
 //TODO, remove these cache function dependencies
 #define CACHE_IROM_MMU_START            0
 #define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
@@ -64,11 +54,9 @@ extern "C" {
 #define MMU_MSPI_SENSITIVE              BIT(10)
 
 #define MMU_ACCESS_FLASH                MMU_MSPI_ACCESS_FLASH
-#define MMU_ACCESS_SPIRAM               MMU_MSPI_ACCESS_SPIRAM
 #define MMU_VALID                       MMU_MSPI_VALID
 #define MMU_SENSITIVE                   MMU_MSPI_SENSITIVE
 
-// ESP32H2-TODO : IDF-6251
 #define MMU_INVALID_MASK                MMU_MSPI_VALID
 #define MMU_INVALID                     MMU_MSPI_INVALID
 

components/soc/esp32h2/include/soc/soc.h

@@ -156,9 +156,9 @@
  */
 
 #define SOC_IROM_LOW    0x42000000
-#define SOC_IROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
-#define SOC_DROM_LOW    SOC_IROM_HIGH
-#define SOC_DROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) // ESP32H2 MMU-TODO: IDF-6251
+#define SOC_IROM_HIGH   (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
+#define SOC_DROM_LOW    SOC_IROM_LOW
+#define SOC_DROM_HIGH   SOC_IROM_HIGH
 #define SOC_IROM_MASK_LOW  0x40000000
 #define SOC_IROM_MASK_HIGH 0x4001C400
 #define SOC_DROM_MASK_LOW  0x4001C400

components/soc/esp32h2/include/soc/soc_caps.h

@@ -124,10 +124,11 @@
 #define SOC_CPU_WATCHPOINTS_NUM         4
 #define SOC_CPU_WATCHPOINT_SIZE         0x80000000 // bytes
 
-// TODO: IDF-6370 (Copy from esp32c6, need check)
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
+#define SOC_MMU_PERIPH_NUM                    (1U)
 #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM     (1U)
+#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
 
 // TODO: IDF-6285 (Copy from esp32c6, need check)
 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/