feat(soc): rename mspi registers

components/soc/esp32p4/include/soc/dspi_mem_reg.h

@@ -1,2832 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_DSPI_MEM_REG_H_
-#define _SOC_DSPI_MEM_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define DSPI_MEM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x0)
-/* DSPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
-#define DSPI_MEM_USR    (BIT(18))
-#define DSPI_MEM_USR_M  (BIT(18))
-#define DSPI_MEM_USR_V  0x1
-#define DSPI_MEM_USR_S  18
-/* DSPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define DSPI_MEM_SLV_ST    0x0000000F
-#define DSPI_MEM_SLV_ST_M  ((DSPI_MEM_SLV_ST_V)<<(DSPI_MEM_SLV_ST_S))
-#define DSPI_MEM_SLV_ST_V  0xF
-#define DSPI_MEM_SLV_ST_S  4
-/* DSPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define DSPI_MEM_MST_ST    0x0000000F
-#define DSPI_MEM_MST_ST_M  ((DSPI_MEM_MST_ST_V)<<(DSPI_MEM_MST_ST_S))
-#define DSPI_MEM_MST_ST_V  0xF
-#define DSPI_MEM_MST_ST_S  0
-
-#define DSPI_MEM_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x8)
-/* DSPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
-lways 1. 0: Others..*/
-#define DSPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
-#define DSPI_MEM_DATA_IE_ALWAYS_ON_S  31
-/* DSPI_MEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
-s 1. 0: Others..*/
-#define DSPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
-#define DSPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/* DSPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define DSPI_MEM_FREAD_QIO    (BIT(24))
-#define DSPI_MEM_FREAD_QIO_M  (BIT(24))
-#define DSPI_MEM_FREAD_QIO_V  0x1
-#define DSPI_MEM_FREAD_QIO_S  24
-/* DSPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define DSPI_MEM_FREAD_DIO    (BIT(23))
-#define DSPI_MEM_FREAD_DIO_M  (BIT(23))
-#define DSPI_MEM_FREAD_DIO_V  0x1
-#define DSPI_MEM_FREAD_DIO_S  23
-/* DSPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define DSPI_MEM_WP_REG    (BIT(21))
-#define DSPI_MEM_WP_REG_M  (BIT(21))
-#define DSPI_MEM_WP_REG_V  0x1
-#define DSPI_MEM_WP_REG_S  21
-/* DSPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_FREAD_QUAD    (BIT(20))
-#define DSPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define DSPI_MEM_FREAD_QUAD_V  0x1
-#define DSPI_MEM_FREAD_QUAD_S  20
-/* DSPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define DSPI_MEM_D_POL    (BIT(19))
-#define DSPI_MEM_D_POL_M  (BIT(19))
-#define DSPI_MEM_D_POL_V  0x1
-#define DSPI_MEM_D_POL_S  19
-/* DSPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define DSPI_MEM_Q_POL    (BIT(18))
-#define DSPI_MEM_Q_POL_M  (BIT(18))
-#define DSPI_MEM_Q_POL_V  0x1
-#define DSPI_MEM_Q_POL_S  18
-/* DSPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_FREAD_DUAL    (BIT(14))
-#define DSPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define DSPI_MEM_FREAD_DUAL_V  0x1
-#define DSPI_MEM_FREAD_DUAL_S  14
-/* DSPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define DSPI_MEM_FASTRD_MODE    (BIT(13))
-#define DSPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define DSPI_MEM_FASTRD_MODE_V  0x1
-#define DSPI_MEM_FASTRD_MODE_S  13
-/* DSPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
-#define DSPI_MEM_FCMD_OCT    (BIT(9))
-#define DSPI_MEM_FCMD_OCT_M  (BIT(9))
-#define DSPI_MEM_FCMD_OCT_V  0x1
-#define DSPI_MEM_FCMD_OCT_S  9
-/* DSPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define DSPI_MEM_FCMD_QUAD    (BIT(8))
-#define DSPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define DSPI_MEM_FCMD_QUAD_V  0x1
-#define DSPI_MEM_FCMD_QUAD_S  8
-/* DSPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
-#define DSPI_MEM_FADDR_OCT    (BIT(6))
-#define DSPI_MEM_FADDR_OCT_M  (BIT(6))
-#define DSPI_MEM_FADDR_OCT_V  0x1
-#define DSPI_MEM_FADDR_OCT_S  6
-/* DSPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
-#define DSPI_MEM_FDIN_OCT    (BIT(5))
-#define DSPI_MEM_FDIN_OCT_M  (BIT(5))
-#define DSPI_MEM_FDIN_OCT_V  0x1
-#define DSPI_MEM_FDIN_OCT_S  5
-/* DSPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
-#define DSPI_MEM_FDOUT_OCT    (BIT(4))
-#define DSPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define DSPI_MEM_FDOUT_OCT_V  0x1
-#define DSPI_MEM_FDOUT_OCT_S  4
-/* DSPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
-is output by the MSPI controller in the second half part of dummy phase. It is u
-sed to pre-drive flash..*/
-#define DSPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define DSPI_MEM_FDUMMY_WOUT_M  (BIT(3))
-#define DSPI_MEM_FDUMMY_WOUT_V  0x1
-#define DSPI_MEM_FDUMMY_WOUT_S  3
-/* DSPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
-s output by the MSPI controller in the first half part of dummy phase. It is use
-d to mask invalid SPI_DQS in the half part of dummy phase..*/
-#define DSPI_MEM_FDUMMY_RIN    (BIT(2))
-#define DSPI_MEM_FDUMMY_RIN_M  (BIT(2))
-#define DSPI_MEM_FDUMMY_RIN_V  0x1
-#define DSPI_MEM_FDUMMY_RIN_S  2
-/* DSPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_IO[7:0] is output by the MSPI controller..*/
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/* DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_DQS is output by the MSPI controller..*/
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-
-#define DSPI_MEM_CTRL1_REG          (DR_REG_DSPI_MEM_BASE + 0xC)
-/* DSPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- send signals to AXI. Set this bit to reset these FIFO..*/
-#define DSPI_MEM_TXFIFO_RST    (BIT(31))
-#define DSPI_MEM_TXFIFO_RST_M  (BIT(31))
-#define DSPI_MEM_TXFIFO_RST_V  0x1
-#define DSPI_MEM_TXFIFO_RST_S  31
-/* DSPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- receive signals from AXI.  Set this bit to reset these FIFO..*/
-#define DSPI_MEM_RXFIFO_RST    (BIT(30))
-#define DSPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define DSPI_MEM_RXFIFO_RST_V  0x1
-#define DSPI_MEM_RXFIFO_RST_S  30
-/* DSPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
-in  tx_bus_fifo_l2..*/
-#define DSPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define DSPI_MEM_FAST_WRITE_EN_M  (BIT(29))
-#define DSPI_MEM_FAST_WRITE_EN_V  0x1
-#define DSPI_MEM_FAST_WRITE_EN_S  29
-/* DSPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
-the same time..*/
-#define DSPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define DSPI_MEM_DUAL_RAM_EN_M  (BIT(28))
-#define DSPI_MEM_DUAL_RAM_EN_V  0x1
-#define DSPI_MEM_DUAL_RAM_EN_S  28
-/* DSPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
-cessed at the same time..*/
-#define DSPI_MEM_RAM0_EN    (BIT(27))
-#define DSPI_MEM_RAM0_EN_M  (BIT(27))
-#define DSPI_MEM_RAM0_EN_V  0x1
-#define DSPI_MEM_RAM0_EN_S  27
-/* DSPI_MEM_AW_SPLICE_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Write Splice-transfer..*/
-#define DSPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define DSPI_MEM_AW_SPLICE_EN_M  (BIT(26))
-#define DSPI_MEM_AW_SPLICE_EN_V  0x1
-#define DSPI_MEM_AW_SPLICE_EN_S  26
-/* DSPI_MEM_AR_SPLICE_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Read Splice-transfer..*/
-#define DSPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define DSPI_MEM_AR_SPLICE_EN_M  (BIT(25))
-#define DSPI_MEM_AR_SPLICE_EN_V  0x1
-#define DSPI_MEM_AR_SPLICE_EN_S  25
-/* DSPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- when there is a ECC error in AXI read data. The ECC error information is record
-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
-#define DSPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define DSPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
-#define DSPI_MEM_RRESP_ECC_ERR_EN_V  0x1
-#define DSPI_MEM_RRESP_ECC_ERR_EN_S  24
-/* DSPI_MEM_SPI_AXI_RDATA_BACK_FAST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
-eply AXI read data to AXI bus when all the read data is available..*/
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_M  (BIT(23))
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_V  0x1
-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_S  23
-/* DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V  0x1
-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/* DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V  0x1
-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/* DSPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define DSPI_MEM_CLK_MODE    0x00000003
-#define DSPI_MEM_CLK_MODE_M  ((DSPI_MEM_CLK_MODE_V)<<(DSPI_MEM_CLK_MODE_S))
-#define DSPI_MEM_CLK_MODE_V  0x3
-#define DSPI_MEM_CLK_MODE_S  0
-
-#define DSPI_MEM_CTRL2_REG          (DR_REG_DSPI_MEM_BASE + 0x10)
-/* DSPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
-#define DSPI_MEM_SYNC_RESET    (BIT(31))
-#define DSPI_MEM_SYNC_RESET_M  (BIT(31))
-#define DSPI_MEM_SYNC_RESET_V  0x1
-#define DSPI_MEM_SYNC_RESET_S  31
-/* DSPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define DSPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define DSPI_MEM_CS_HOLD_DELAY_M  ((DSPI_MEM_CS_HOLD_DELAY_V)<<(DSPI_MEM_CS_HOLD_DELAY_S))
-#define DSPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define DSPI_MEM_CS_HOLD_DELAY_S  25
-/* DSPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
-whether there is an ECC region or not..*/
-#define DSPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define DSPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
-#define DSPI_MEM_SPLIT_TRANS_EN_V  0x1
-#define DSPI_MEM_SPLIT_TRANS_EN_S  24
-/* DSPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
-#define DSPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define DSPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* DSPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
-hen accesses flash..*/
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* DSPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- mode when accessed flash..*/
-#define DSPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define DSPI_MEM_ECC_CS_HOLD_TIME_M  ((DSPI_MEM_ECC_CS_HOLD_TIME_V)<<(DSPI_MEM_ECC_CS_HOLD_TIME_S))
-#define DSPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define DSPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* DSPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
-th SPI_MEM_CS_HOLD bit..*/
-#define DSPI_MEM_CS_HOLD_TIME    0x0000001F
-#define DSPI_MEM_CS_HOLD_TIME_M  ((DSPI_MEM_CS_HOLD_TIME_V)<<(DSPI_MEM_CS_HOLD_TIME_S))
-#define DSPI_MEM_CS_HOLD_TIME_V  0x1F
-#define DSPI_MEM_CS_HOLD_TIME_S  5
-/* DSPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
-M_CS_SETUP bit..*/
-#define DSPI_MEM_CS_SETUP_TIME    0x0000001F
-#define DSPI_MEM_CS_SETUP_TIME_M  ((DSPI_MEM_CS_SETUP_TIME_V)<<(DSPI_MEM_CS_SETUP_TIME_S))
-#define DSPI_MEM_CS_SETUP_TIME_V  0x1F
-#define DSPI_MEM_CS_SETUP_TIME_S  0
-
-#define DSPI_MEM_CLOCK_REG          (DR_REG_DSPI_MEM_BASE + 0x14)
-/* DSPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- clock..*/
-#define DSPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define DSPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define DSPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define DSPI_MEM_CLK_EQU_SYSCLK_S  31
-/* DSPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define DSPI_MEM_CLKCNT_N    0x000000FF
-#define DSPI_MEM_CLKCNT_N_M  ((DSPI_MEM_CLKCNT_N_V)<<(DSPI_MEM_CLKCNT_N_S))
-#define DSPI_MEM_CLKCNT_N_V  0xFF
-#define DSPI_MEM_CLKCNT_N_S  16
-/* DSPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define DSPI_MEM_CLKCNT_H    0x000000FF
-#define DSPI_MEM_CLKCNT_H_M  ((DSPI_MEM_CLKCNT_H_V)<<(DSPI_MEM_CLKCNT_H_S))
-#define DSPI_MEM_CLKCNT_H_V  0xFF
-#define DSPI_MEM_CLKCNT_H_S  8
-/* DSPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define DSPI_MEM_CLKCNT_L    0x000000FF
-#define DSPI_MEM_CLKCNT_L_M  ((DSPI_MEM_CLKCNT_L_V)<<(DSPI_MEM_CLKCNT_L_S))
-#define DSPI_MEM_CLKCNT_L_V  0xFF
-#define DSPI_MEM_CLKCNT_L_S  0
-
-#define DSPI_MEM_USER_REG          (DR_REG_DSPI_MEM_BASE + 0x18)
-/* DSPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define DSPI_MEM_USR_DUMMY    (BIT(29))
-#define DSPI_MEM_USR_DUMMY_M  (BIT(29))
-#define DSPI_MEM_USR_DUMMY_V  0x1
-#define DSPI_MEM_USR_DUMMY_S  29
-/* DSPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define DSPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define DSPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define DSPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define DSPI_MEM_USR_DUMMY_IDLE_S  26
-/* DSPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
-#define DSPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define DSPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define DSPI_MEM_CK_OUT_EDGE_V  0x1
-#define DSPI_MEM_CK_OUT_EDGE_S  9
-/* DSPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define DSPI_MEM_CS_SETUP    (BIT(7))
-#define DSPI_MEM_CS_SETUP_M  (BIT(7))
-#define DSPI_MEM_CS_SETUP_V  0x1
-#define DSPI_MEM_CS_SETUP_S  7
-/* DSPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define DSPI_MEM_CS_HOLD    (BIT(6))
-#define DSPI_MEM_CS_HOLD_M  (BIT(6))
-#define DSPI_MEM_CS_HOLD_V  0x1
-#define DSPI_MEM_CS_HOLD_S  6
-
-#define DSPI_MEM_USER1_REG          (DR_REG_DSPI_MEM_BASE + 0x1C)
-/* DSPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define DSPI_MEM_USR_ADDR_BITLEN_M  ((DSPI_MEM_USR_ADDR_BITLEN_V)<<(DSPI_MEM_USR_ADDR_BITLEN_S))
-#define DSPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define DSPI_MEM_USR_ADDR_BITLEN_S  26
-/* DSPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
-/*description: SPI0 USR_CMD read or write data byte length -1.*/
-#define DSPI_MEM_USR_DBYTELEN    0x00000007
-#define DSPI_MEM_USR_DBYTELEN_M  ((DSPI_MEM_USR_DBYTELEN_V)<<(DSPI_MEM_USR_DBYTELEN_S))
-#define DSPI_MEM_USR_DBYTELEN_V  0x7
-#define DSPI_MEM_USR_DBYTELEN_S  6
-/* DSPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define DSPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_M  ((DSPI_MEM_USR_DUMMY_CYCLELEN_V)<<(DSPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define DSPI_MEM_USER2_REG          (DR_REG_DSPI_MEM_BASE + 0x20)
-/* DSPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define DSPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define DSPI_MEM_USR_COMMAND_BITLEN_M  ((DSPI_MEM_USR_COMMAND_BITLEN_V)<<(DSPI_MEM_USR_COMMAND_BITLEN_S))
-#define DSPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define DSPI_MEM_USR_COMMAND_BITLEN_S  28
-/* DSPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define DSPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define DSPI_MEM_USR_COMMAND_VALUE_M  ((DSPI_MEM_USR_COMMAND_VALUE_V)<<(DSPI_MEM_USR_COMMAND_VALUE_S))
-#define DSPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define DSPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define DSPI_MEM_RD_STATUS_REG          (DR_REG_DSPI_MEM_BASE + 0x2C)
-/* DSPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define DSPI_MEM_WB_MODE    0x000000FF
-#define DSPI_MEM_WB_MODE_M  ((DSPI_MEM_WB_MODE_V)<<(DSPI_MEM_WB_MODE_S))
-#define DSPI_MEM_WB_MODE_V  0xFF
-#define DSPI_MEM_WB_MODE_S  16
-
-#define DSPI_MEM_MISC_REG          (DR_REG_DSPI_MEM_BASE + 0x34)
-/* DSPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define DSPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define DSPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define DSPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define DSPI_MEM_CS_KEEP_ACTIVE_S  10
-/* DSPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
-#define DSPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define DSPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define DSPI_MEM_CK_IDLE_EDGE_V  0x1
-#define DSPI_MEM_CK_IDLE_EDGE_S  9
-/* DSPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0,  sram is connected to SUBPINs..*/
-#define DSPI_MEM_SSUB_PIN    (BIT(8))
-#define DSPI_MEM_SSUB_PIN_M  (BIT(8))
-#define DSPI_MEM_SSUB_PIN_V  0x1
-#define DSPI_MEM_SSUB_PIN_S  8
-/* DSPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0,  flash is connected to SUBPINs..*/
-#define DSPI_MEM_FSUB_PIN    (BIT(7))
-#define DSPI_MEM_FSUB_PIN_M  (BIT(7))
-#define DSPI_MEM_FSUB_PIN_V  0x1
-#define DSPI_MEM_FSUB_PIN_S  7
-
-#define DSPI_MEM_CACHE_FCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x3C)
-/* DSPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
-_ERR will be replied to BRESP/RRESP..*/
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_M  (BIT(31))
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_V  0x1
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_S  31
-/* DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: Set this bit to check AXI read/write the same address region..*/
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x1
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/* DSPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FADDR_QUAD    (BIT(8))
-#define DSPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define DSPI_MEM_FADDR_QUAD_V  0x1
-#define DSPI_MEM_FADDR_QUAD_S  8
-/* DSPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FDOUT_QUAD    (BIT(7))
-#define DSPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define DSPI_MEM_FDOUT_QUAD_V  0x1
-#define DSPI_MEM_FDOUT_QUAD_S  7
-/* DSPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define DSPI_MEM_FDIN_QUAD    (BIT(6))
-#define DSPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define DSPI_MEM_FDIN_QUAD_V  0x1
-#define DSPI_MEM_FDIN_QUAD_S  6
-/* DSPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FADDR_DUAL    (BIT(5))
-#define DSPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define DSPI_MEM_FADDR_DUAL_V  0x1
-#define DSPI_MEM_FADDR_DUAL_S  5
-/* DSPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FDOUT_DUAL    (BIT(4))
-#define DSPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define DSPI_MEM_FDOUT_DUAL_V  0x1
-#define DSPI_MEM_FDOUT_DUAL_S  4
-/* DSPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define DSPI_MEM_FDIN_DUAL    (BIT(3))
-#define DSPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define DSPI_MEM_FDIN_DUAL_V  0x1
-#define DSPI_MEM_FDIN_DUAL_S  3
-/* DSPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define DSPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define DSPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* DSPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* DSPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
-#define DSPI_MEM_AXI_REQ_EN    (BIT(0))
-#define DSPI_MEM_AXI_REQ_EN_M  (BIT(0))
-#define DSPI_MEM_AXI_REQ_EN_V  0x1
-#define DSPI_MEM_AXI_REQ_EN_S  0
-
-#define DSPI_MEM_CACHE_SCTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x40)
-/* DSPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
-e. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* DSPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: reserved.*/
-#define DSPI_MEM_SRAM_OCT    (BIT(21))
-#define DSPI_MEM_SRAM_OCT_M  (BIT(21))
-#define DSPI_MEM_SRAM_OCT_V  0x1
-#define DSPI_MEM_SRAM_OCT_S  21
-/* DSPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* DSPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
-he register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define DSPI_MEM_SRAM_ADDR_BITLEN_M  ((DSPI_MEM_SRAM_ADDR_BITLEN_V)<<(DSPI_MEM_SRAM_ADDR_BITLEN_S))
-#define DSPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define DSPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* DSPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
-. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* DSPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* DSPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
- operations..*/
-#define DSPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* DSPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
-e operations..*/
-#define DSPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* DSPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
-le.*/
-#define DSPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define DSPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define DSPI_MEM_USR_SRAM_QIO_V  0x1
-#define DSPI_MEM_USR_SRAM_QIO_S  2
-/* DSPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
-le.*/
-#define DSPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define DSPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define DSPI_MEM_USR_SRAM_DIO_V  0x1
-#define DSPI_MEM_USR_SRAM_DIO_S  1
-/* DSPI_MEM_CACHE_USR_SADDR_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
-able, 0:disable..*/
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
-
-#define DSPI_MEM_SRAM_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x44)
-/* DSPI_SMEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
-] are always 1. 0: Others..*/
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_V  0x1
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_S  31
-/* DSPI_SMEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
-e always 1. 0: Others..*/
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_V  0x1
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/* DSPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDOUT_HEX    (BIT(27))
-#define DSPI_MEM_SDOUT_HEX_M  (BIT(27))
-#define DSPI_MEM_SDOUT_HEX_V  0x1
-#define DSPI_MEM_SDOUT_HEX_S  27
-/* DSPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDIN_HEX    (BIT(26))
-#define DSPI_MEM_SDIN_HEX_M  (BIT(26))
-#define DSPI_MEM_SDIN_HEX_V  0x1
-#define DSPI_MEM_SDIN_HEX_S  26
-/* DSPI_SMEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/* DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_DQS is output by the MSPI controller..*/
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/* DSPI_MEM_SDUMMY_WOUT : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
-the signal level of SPI bus is output by the MSPI controller..*/
-#define DSPI_MEM_SDUMMY_WOUT    (BIT(23))
-#define DSPI_MEM_SDUMMY_WOUT_M  (BIT(23))
-#define DSPI_MEM_SDUMMY_WOUT_V  0x1
-#define DSPI_MEM_SDUMMY_WOUT_S  23
-/* DSPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
-he signal level of SPI bus is output by the MSPI controller..*/
-#define DSPI_MEM_SDUMMY_RIN    (BIT(22))
-#define DSPI_MEM_SDUMMY_RIN_M  (BIT(22))
-#define DSPI_MEM_SDUMMY_RIN_V  0x1
-#define DSPI_MEM_SDUMMY_RIN_S  22
-/* DSPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SCMD_OCT    (BIT(21))
-#define DSPI_MEM_SCMD_OCT_M  (BIT(21))
-#define DSPI_MEM_SCMD_OCT_V  0x1
-#define DSPI_MEM_SCMD_OCT_S  21
-/* DSPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SADDR_OCT    (BIT(20))
-#define DSPI_MEM_SADDR_OCT_M  (BIT(20))
-#define DSPI_MEM_SADDR_OCT_V  0x1
-#define DSPI_MEM_SADDR_OCT_S  20
-/* DSPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDOUT_OCT    (BIT(19))
-#define DSPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define DSPI_MEM_SDOUT_OCT_V  0x1
-#define DSPI_MEM_SDOUT_OCT_S  19
-/* DSPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
-#define DSPI_MEM_SDIN_OCT    (BIT(18))
-#define DSPI_MEM_SDIN_OCT_M  (BIT(18))
-#define DSPI_MEM_SDIN_OCT_V  0x1
-#define DSPI_MEM_SDIN_OCT_S  18
-/* DSPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SCMD_QUAD    (BIT(17))
-#define DSPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define DSPI_MEM_SCMD_QUAD_V  0x1
-#define DSPI_MEM_SCMD_QUAD_S  17
-/* DSPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SADDR_QUAD    (BIT(16))
-#define DSPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define DSPI_MEM_SADDR_QUAD_V  0x1
-#define DSPI_MEM_SADDR_QUAD_S  16
-/* DSPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SDOUT_QUAD    (BIT(15))
-#define DSPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define DSPI_MEM_SDOUT_QUAD_V  0x1
-#define DSPI_MEM_SDOUT_QUAD_S  15
-/* DSPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define DSPI_MEM_SDIN_QUAD    (BIT(14))
-#define DSPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define DSPI_MEM_SDIN_QUAD_V  0x1
-#define DSPI_MEM_SDIN_QUAD_S  14
-/* DSPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SADDR_DUAL    (BIT(12))
-#define DSPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define DSPI_MEM_SADDR_DUAL_V  0x1
-#define DSPI_MEM_SADDR_DUAL_S  12
-/* DSPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SDOUT_DUAL    (BIT(11))
-#define DSPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define DSPI_MEM_SDOUT_DUAL_V  0x1
-#define DSPI_MEM_SDOUT_DUAL_S  11
-/* DSPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_dio..*/
-#define DSPI_MEM_SDIN_DUAL    (BIT(10))
-#define DSPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define DSPI_MEM_SDIN_DUAL_V  0x1
-#define DSPI_MEM_SDIN_DUAL_S  10
-/* DSPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
-_mode bit..*/
-#define DSPI_MEM_SWB_MODE    0x000000FF
-#define DSPI_MEM_SWB_MODE_M  ((DSPI_MEM_SWB_MODE_V)<<(DSPI_MEM_SWB_MODE_S))
-#define DSPI_MEM_SWB_MODE_V  0xFF
-#define DSPI_MEM_SWB_MODE_S  2
-/* DSPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is always on..*/
-#define DSPI_MEM_SCLK_MODE    0x00000003
-#define DSPI_MEM_SCLK_MODE_M  ((DSPI_MEM_SCLK_MODE_V)<<(DSPI_MEM_SCLK_MODE_S))
-#define DSPI_MEM_SCLK_MODE_V  0x3
-#define DSPI_MEM_SCLK_MODE_S  0
-
-#define DSPI_MEM_SRAM_DRD_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x48)
-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
- sram. The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
- for sram..*/
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define DSPI_MEM_SRAM_DWR_CMD_REG          (DR_REG_DSPI_MEM_BASE + 0x4C)
-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
- The register value shall be (bit_num-1)..*/
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
-e for sram..*/
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define DSPI_MEM_SRAM_CLK_REG          (DR_REG_DSPI_MEM_BASE + 0x50)
-/* DSPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
-lk is divided from system clock..*/
-#define DSPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define DSPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define DSPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define DSPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* DSPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
-lk frequency is system/(spi_mem_clkcnt_N+1).*/
-#define DSPI_MEM_SCLKCNT_N    0x000000FF
-#define DSPI_MEM_SCLKCNT_N_M  ((DSPI_MEM_SCLKCNT_N_V)<<(DSPI_MEM_SCLKCNT_N_S))
-#define DSPI_MEM_SCLKCNT_N_V  0xFF
-#define DSPI_MEM_SCLKCNT_N_S  16
-/* DSPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define DSPI_MEM_SCLKCNT_H    0x000000FF
-#define DSPI_MEM_SCLKCNT_H_M  ((DSPI_MEM_SCLKCNT_H_V)<<(DSPI_MEM_SCLKCNT_H_S))
-#define DSPI_MEM_SCLKCNT_H_V  0xFF
-#define DSPI_MEM_SCLKCNT_H_S  8
-/* DSPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
-#define DSPI_MEM_SCLKCNT_L    0x000000FF
-#define DSPI_MEM_SCLKCNT_L_M  ((DSPI_MEM_SCLKCNT_L_V)<<(DSPI_MEM_SCLKCNT_L_S))
-#define DSPI_MEM_SCLKCNT_L_V  0xFF
-#define DSPI_MEM_SCLKCNT_L_S  0
-
-#define DSPI_MEM_FSM_REG          (DR_REG_DSPI_MEM_BASE + 0x54)
-/* DSPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define DSPI_MEM_LOCK_DELAY_TIME    0x0000001F
-#define DSPI_MEM_LOCK_DELAY_TIME_M  ((DSPI_MEM_LOCK_DELAY_TIME_V)<<(DSPI_MEM_LOCK_DELAY_TIME_S))
-#define DSPI_MEM_LOCK_DELAY_TIME_V  0x1F
-#define DSPI_MEM_LOCK_DELAY_TIME_S  7
-
-#define DSPI_MEM_INT_ENA_REG          (DR_REG_DSPI_MEM_BASE + 0xC0)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/* DSPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ENA_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_ENA_S  6
-/* DSPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_ENA_S  5
-/* DSPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_ENA_S  4
-/* DSPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_ENA_S  3
-
-#define DSPI_MEM_INT_CLR_REG          (DR_REG_DSPI_MEM_BASE + 0xC4)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/* DSPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_CLR_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_CLR_S  6
-/* DSPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_CLR_S  5
-/* DSPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_CLR_S  4
-/* DSPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_CLR_S  3
-
-#define DSPI_MEM_INT_RAW_REG          (DR_REG_DSPI_MEM_BASE + 0xC8)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO
- is underflow..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO
- is underflow..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
-O connected to SPI_DQS is overflow..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
-O connected to SPI_DQS1 is overflow..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- address is invalid by compared to MMU configuration. 0: Others..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
-ite flash request is received. 0: Others..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
-address is invalid by compared to MMU configuration. 0: Others..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/* DSPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
-is rejected. 0: Others..*/
-#define DSPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_RAW_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_RAW_S  6
-/* DSPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
-et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
-#define DSPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_RAW_S  5
-/* DSPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define DSPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_RAW_S  4
-/* DSPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define DSPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_RAW_S  3
-
-#define DSPI_MEM_INT_ST_REG          (DR_REG_DSPI_MEM_BASE + 0xCC)
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST    (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_M  (BIT(31))
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_V  0x1
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_S  31
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST    (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_M  (BIT(30))
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_V  0x1
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_S  30
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST    (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_M  (BIT(29))
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_V  0x1
-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_S  29
-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST    (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_M  (BIT(28))
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_V  0x1
-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_S  28
-/* DSPI_MEM_AXI_WADDR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/* DSPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/* DSPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define DSPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
-#define DSPI_MEM_PMS_REJECT_INT_ST_V  0x1
-#define DSPI_MEM_PMS_REJECT_INT_ST_S  6
-/* DSPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define DSPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
-#define DSPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define DSPI_MEM_ECC_ERR_INT_ST_S  5
-/* DSPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define DSPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define DSPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define DSPI_MEM_MST_ST_END_INT_ST_S  4
-/* DSPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define DSPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define DSPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define DSPI_MEM_SLV_ST_END_INT_ST_S  3
-
-#define DSPI_MEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD4)
-/* DSPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define DSPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define DSPI_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define DSPI_FMEM_HYPERBUS_CA_V  0x1
-#define DSPI_FMEM_HYPERBUS_CA_S  30
-/* DSPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define DSPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define DSPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define DSPI_FMEM_OCTA_RAM_ADDR_V  0x1
-#define DSPI_FMEM_OCTA_RAM_ADDR_S  29
-/* DSPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define DSPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define DSPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define DSPI_FMEM_CLK_DIFF_INV_V  0x1
-#define DSPI_FMEM_CLK_DIFF_INV_S  28
-/* DSPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* DSPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define DSPI_FMEM_DQS_CA_IN    (BIT(26))
-#define DSPI_FMEM_DQS_CA_IN_M  (BIT(26))
-#define DSPI_FMEM_DQS_CA_IN_V  0x1
-#define DSPI_FMEM_DQS_CA_IN_S  26
-/* DSPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define DSPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define DSPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define DSPI_FMEM_CLK_DIFF_EN_V  0x1
-#define DSPI_FMEM_CLK_DIFF_EN_S  24
-/* DSPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define DSPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define DSPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define DSPI_FMEM_DDR_DQS_LOOP_V  0x1
-#define DSPI_FMEM_DDR_DQS_LOOP_S  21
-/* DSPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define DSPI_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define DSPI_FMEM_USR_DDR_DQS_THD_M  ((DSPI_FMEM_USR_DDR_DQS_THD_V)<<(DSPI_FMEM_USR_DDR_DQS_THD_S))
-#define DSPI_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define DSPI_FMEM_USR_DDR_DQS_THD_S  14
-/* DSPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to flash..*/
-#define DSPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define DSPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define DSPI_FMEM_RX_DDR_MSK_EN_V  0x1
-#define DSPI_FMEM_RX_DDR_MSK_EN_S  13
-/* DSPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to flash..*/
-#define DSPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define DSPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define DSPI_FMEM_TX_DDR_MSK_EN_V  0x1
-#define DSPI_FMEM_TX_DDR_MSK_EN_S  12
-/* DSPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define DSPI_FMEM_OUTMINBYTELEN    0x0000007F
-#define DSPI_FMEM_OUTMINBYTELEN_M  ((DSPI_FMEM_OUTMINBYTELEN_V)<<(DSPI_FMEM_OUTMINBYTELEN_S))
-#define DSPI_FMEM_OUTMINBYTELEN_V  0x7F
-#define DSPI_FMEM_OUTMINBYTELEN_S  5
-/* DSPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define DSPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define DSPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define DSPI_FMEM_DDR_CMD_DIS_V  0x1
-#define DSPI_FMEM_DDR_CMD_DIS_S  4
-/* DSPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define DSPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define DSPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define DSPI_FMEM_DDR_WDAT_SWP_V  0x1
-#define DSPI_FMEM_DDR_WDAT_SWP_S  3
-/* DSPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define DSPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define DSPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define DSPI_FMEM_DDR_RDAT_SWP_V  0x1
-#define DSPI_FMEM_DDR_RDAT_SWP_S  2
-/* DSPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define DSPI_FMEM_VAR_DUMMY    (BIT(1))
-#define DSPI_FMEM_VAR_DUMMY_M  (BIT(1))
-#define DSPI_FMEM_VAR_DUMMY_V  0x1
-#define DSPI_FMEM_VAR_DUMMY_S  1
-/* DSPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define DSPI_FMEM_DDR_EN    (BIT(0))
-#define DSPI_FMEM_DDR_EN_M  (BIT(0))
-#define DSPI_FMEM_DDR_EN_V  0x1
-#define DSPI_FMEM_DDR_EN_S  0
-
-#define DSPI_SMEM_DDR_REG          (DR_REG_DSPI_MEM_BASE + 0xD8)
-/* DSPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define DSPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define DSPI_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define DSPI_SMEM_HYPERBUS_CA_V  0x1
-#define DSPI_SMEM_HYPERBUS_CA_S  30
-/* DSPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define DSPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define DSPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define DSPI_SMEM_OCTA_RAM_ADDR_V  0x1
-#define DSPI_SMEM_OCTA_RAM_ADDR_S  29
-/* DSPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define DSPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define DSPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define DSPI_SMEM_CLK_DIFF_INV_V  0x1
-#define DSPI_SMEM_CLK_DIFF_INV_S  28
-/* DSPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* DSPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define DSPI_SMEM_DQS_CA_IN    (BIT(26))
-#define DSPI_SMEM_DQS_CA_IN_M  (BIT(26))
-#define DSPI_SMEM_DQS_CA_IN_V  0x1
-#define DSPI_SMEM_DQS_CA_IN_S  26
-/* DSPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define DSPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define DSPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define DSPI_SMEM_CLK_DIFF_EN_V  0x1
-#define DSPI_SMEM_CLK_DIFF_EN_S  24
-/* DSPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define DSPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define DSPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define DSPI_SMEM_DDR_DQS_LOOP_V  0x1
-#define DSPI_SMEM_DDR_DQS_LOOP_S  21
-/* DSPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define DSPI_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define DSPI_SMEM_USR_DDR_DQS_THD_M  ((DSPI_SMEM_USR_DDR_DQS_THD_V)<<(DSPI_SMEM_USR_DDR_DQS_THD_S))
-#define DSPI_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define DSPI_SMEM_USR_DDR_DQS_THD_S  14
-/* DSPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to external RAM..*/
-#define DSPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define DSPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define DSPI_SMEM_RX_DDR_MSK_EN_V  0x1
-#define DSPI_SMEM_RX_DDR_MSK_EN_S  13
-/* DSPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to external RAM..*/
-#define DSPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define DSPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define DSPI_SMEM_TX_DDR_MSK_EN_V  0x1
-#define DSPI_SMEM_TX_DDR_MSK_EN_S  12
-/* DSPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the DDR psram..*/
-#define DSPI_SMEM_OUTMINBYTELEN    0x0000007F
-#define DSPI_SMEM_OUTMINBYTELEN_M  ((DSPI_SMEM_OUTMINBYTELEN_V)<<(DSPI_SMEM_OUTMINBYTELEN_S))
-#define DSPI_SMEM_OUTMINBYTELEN_V  0x7F
-#define DSPI_SMEM_OUTMINBYTELEN_S  5
-/* DSPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define DSPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define DSPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define DSPI_SMEM_DDR_CMD_DIS_V  0x1
-#define DSPI_SMEM_DDR_CMD_DIS_S  4
-/* DSPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define DSPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define DSPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define DSPI_SMEM_DDR_WDAT_SWP_V  0x1
-#define DSPI_SMEM_DDR_WDAT_SWP_S  3
-/* DSPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define DSPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define DSPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define DSPI_SMEM_DDR_RDAT_SWP_V  0x1
-#define DSPI_SMEM_DDR_RDAT_SWP_S  2
-/* DSPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define DSPI_SMEM_VAR_DUMMY    (BIT(1))
-#define DSPI_SMEM_VAR_DUMMY_M  (BIT(1))
-#define DSPI_SMEM_VAR_DUMMY_V  0x1
-#define DSPI_SMEM_VAR_DUMMY_S  1
-/* DSPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define DSPI_SMEM_DDR_EN    (BIT(0))
-#define DSPI_SMEM_DDR_EN_M  (BIT(0))
-#define DSPI_SMEM_DDR_EN_V  0x1
-#define DSPI_SMEM_DDR_EN_S  0
-
-#define DSPI_FMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x100)
-/* DSPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS0_ECC    (BIT(2))
-#define DSPI_FMEM_PMS0_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS0_ECC_V  0x1
-#define DSPI_FMEM_PMS0_ECC_S  2
-/* DSPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS0_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS0_WR_ATTR_S  1
-/* DSPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS0_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS0_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x104)
-/* DSPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS1_ECC    (BIT(2))
-#define DSPI_FMEM_PMS1_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS1_ECC_V  0x1
-#define DSPI_FMEM_PMS1_ECC_S  2
-/* DSPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS1_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS1_WR_ATTR_S  1
-/* DSPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS1_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS1_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x108)
-/* DSPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS2_ECC    (BIT(2))
-#define DSPI_FMEM_PMS2_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS2_ECC_V  0x1
-#define DSPI_FMEM_PMS2_ECC_S  2
-/* DSPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS2_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS2_WR_ATTR_S  1
-/* DSPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS2_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS2_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x10C)
-/* DSPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define DSPI_FMEM_PMS3_ECC    (BIT(2))
-#define DSPI_FMEM_PMS3_ECC_M  (BIT(2))
-#define DSPI_FMEM_PMS3_ECC_V  0x1
-#define DSPI_FMEM_PMS3_ECC_S  2
-/* DSPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define DSPI_FMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define DSPI_FMEM_PMS3_WR_ATTR_V  0x1
-#define DSPI_FMEM_PMS3_WR_ATTR_S  1
-/* DSPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define DSPI_FMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define DSPI_FMEM_PMS3_RD_ATTR_V  0x1
-#define DSPI_FMEM_PMS3_RD_ATTR_S  0
-
-#define DSPI_FMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x110)
-/* DSPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS0_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS0_ADDR_S_M  ((DSPI_FMEM_PMS0_ADDR_S_V)<<(DSPI_FMEM_PMS0_ADDR_S_S))
-#define DSPI_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS0_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x114)
-/* DSPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS1_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS1_ADDR_S_M  ((DSPI_FMEM_PMS1_ADDR_S_V)<<(DSPI_FMEM_PMS1_ADDR_S_S))
-#define DSPI_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS1_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x118)
-/* DSPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS2_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS2_ADDR_S_M  ((DSPI_FMEM_PMS2_ADDR_S_V)<<(DSPI_FMEM_PMS2_ADDR_S_S))
-#define DSPI_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS2_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x11C)
-/* DSPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 flash PMS section $n start address value.*/
-#define DSPI_FMEM_PMS3_ADDR_S    0x03FFFFFF
-#define DSPI_FMEM_PMS3_ADDR_S_M  ((DSPI_FMEM_PMS3_ADDR_S_V)<<(DSPI_FMEM_PMS3_ADDR_S_S))
-#define DSPI_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define DSPI_FMEM_PMS3_ADDR_S_S  0
-
-#define DSPI_FMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x120)
-/* DSPI_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS0_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS0_SIZE_M  ((DSPI_FMEM_PMS0_SIZE_V)<<(DSPI_FMEM_PMS0_SIZE_S))
-#define DSPI_FMEM_PMS0_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS0_SIZE_S  0
-
-#define DSPI_FMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x124)
-/* DSPI_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS1_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS1_SIZE_M  ((DSPI_FMEM_PMS1_SIZE_V)<<(DSPI_FMEM_PMS1_SIZE_S))
-#define DSPI_FMEM_PMS1_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS1_SIZE_S  0
-
-#define DSPI_FMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x128)
-/* DSPI_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS2_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS2_SIZE_M  ((DSPI_FMEM_PMS2_SIZE_V)<<(DSPI_FMEM_PMS2_SIZE_S))
-#define DSPI_FMEM_PMS2_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS2_SIZE_S  0
-
-#define DSPI_FMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x12C)
-/* DSPI_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define DSPI_FMEM_PMS3_SIZE    0x00003FFF
-#define DSPI_FMEM_PMS3_SIZE_M  ((DSPI_FMEM_PMS3_SIZE_V)<<(DSPI_FMEM_PMS3_SIZE_S))
-#define DSPI_FMEM_PMS3_SIZE_V  0x3FFF
-#define DSPI_FMEM_PMS3_SIZE_S  0
-
-#define DSPI_SMEM_PMS0_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x130)
-/* DSPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS0_ECC    (BIT(2))
-#define DSPI_SMEM_PMS0_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS0_ECC_V  0x1
-#define DSPI_SMEM_PMS0_ECC_S  2
-/* DSPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS0_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS0_WR_ATTR_S  1
-/* DSPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS0_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS0_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS1_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x134)
-/* DSPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS1_ECC    (BIT(2))
-#define DSPI_SMEM_PMS1_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS1_ECC_V  0x1
-#define DSPI_SMEM_PMS1_ECC_S  2
-/* DSPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS1_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS1_WR_ATTR_S  1
-/* DSPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS1_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS1_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS2_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x138)
-/* DSPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS2_ECC    (BIT(2))
-#define DSPI_SMEM_PMS2_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS2_ECC_V  0x1
-#define DSPI_SMEM_PMS2_ECC_S  2
-/* DSPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS2_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS2_WR_ATTR_S  1
-/* DSPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS2_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS2_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS3_ATTR_REG          (DR_REG_DSPI_MEM_BASE + 0x13C)
-/* DSPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define DSPI_SMEM_PMS3_ECC    (BIT(2))
-#define DSPI_SMEM_PMS3_ECC_M  (BIT(2))
-#define DSPI_SMEM_PMS3_ECC_V  0x1
-#define DSPI_SMEM_PMS3_ECC_S  2
-/* DSPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define DSPI_SMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define DSPI_SMEM_PMS3_WR_ATTR_V  0x1
-#define DSPI_SMEM_PMS3_WR_ATTR_S  1
-/* DSPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
-#define DSPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define DSPI_SMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define DSPI_SMEM_PMS3_RD_ATTR_V  0x1
-#define DSPI_SMEM_PMS3_RD_ATTR_S  0
-
-#define DSPI_SMEM_PMS0_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x140)
-/* DSPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS0_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS0_ADDR_S_M  ((DSPI_SMEM_PMS0_ADDR_S_V)<<(DSPI_SMEM_PMS0_ADDR_S_S))
-#define DSPI_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS0_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS1_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x144)
-/* DSPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS1_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS1_ADDR_S_M  ((DSPI_SMEM_PMS1_ADDR_S_V)<<(DSPI_SMEM_PMS1_ADDR_S_S))
-#define DSPI_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS1_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS2_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x148)
-/* DSPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS2_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS2_ADDR_S_M  ((DSPI_SMEM_PMS2_ADDR_S_V)<<(DSPI_SMEM_PMS2_ADDR_S_S))
-#define DSPI_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS2_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS3_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x14C)
-/* DSPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 external RAM PMS section $n start address value.*/
-#define DSPI_SMEM_PMS3_ADDR_S    0x03FFFFFF
-#define DSPI_SMEM_PMS3_ADDR_S_M  ((DSPI_SMEM_PMS3_ADDR_S_V)<<(DSPI_SMEM_PMS3_ADDR_S_S))
-#define DSPI_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define DSPI_SMEM_PMS3_ADDR_S_S  0
-
-#define DSPI_SMEM_PMS0_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x150)
-/* DSPI_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS0_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS0_SIZE_M  ((DSPI_SMEM_PMS0_SIZE_V)<<(DSPI_SMEM_PMS0_SIZE_S))
-#define DSPI_SMEM_PMS0_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS0_SIZE_S  0
-
-#define DSPI_SMEM_PMS1_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x154)
-/* DSPI_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS1_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS1_SIZE_M  ((DSPI_SMEM_PMS1_SIZE_V)<<(DSPI_SMEM_PMS1_SIZE_S))
-#define DSPI_SMEM_PMS1_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS1_SIZE_S  0
-
-#define DSPI_SMEM_PMS2_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x158)
-/* DSPI_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS2_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS2_SIZE_M  ((DSPI_SMEM_PMS2_SIZE_V)<<(DSPI_SMEM_PMS2_SIZE_S))
-#define DSPI_SMEM_PMS2_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS2_SIZE_S  0
-
-#define DSPI_SMEM_PMS3_SIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x15C)
-/* DSPI_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define DSPI_SMEM_PMS3_SIZE    0x00003FFF
-#define DSPI_SMEM_PMS3_SIZE_M  ((DSPI_SMEM_PMS3_SIZE_V)<<(DSPI_SMEM_PMS3_SIZE_S))
-#define DSPI_SMEM_PMS3_SIZE_V  0x3FFF
-#define DSPI_SMEM_PMS3_SIZE_S  0
-
-#define DSPI_MEM_PMS_REJECT_REG          (DR_REG_DSPI_MEM_BASE + 0x164)
-/* DSPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_IVD    (BIT(31))
-#define DSPI_MEM_PMS_IVD_M  (BIT(31))
-#define DSPI_MEM_PMS_IVD_V  0x1
-#define DSPI_MEM_PMS_IVD_S  31
-/* DSPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
- is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define DSPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
-#define DSPI_MEM_PMS_MULTI_HIT_V  0x1
-#define DSPI_MEM_PMS_MULTI_HIT_S  30
-/* DSPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_ST    (BIT(29))
-#define DSPI_MEM_PMS_ST_M  (BIT(29))
-#define DSPI_MEM_PMS_ST_V  0x1
-#define DSPI_MEM_PMS_ST_S  29
-/* DSPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_PMS_LD    (BIT(28))
-#define DSPI_MEM_PMS_LD_M  (BIT(28))
-#define DSPI_MEM_PMS_LD_V  0x1
-#define DSPI_MEM_PMS_LD_S  28
-/* DSPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
-#define DSPI_MEM_PM_EN    (BIT(26))
-#define DSPI_MEM_PM_EN_M  (BIT(26))
-#define DSPI_MEM_PM_EN_V  0x1
-#define DSPI_MEM_PM_EN_S  26
-/* DSPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define DSPI_MEM_REJECT_ADDR    0x03FFFFFF
-#define DSPI_MEM_REJECT_ADDR_M  ((DSPI_MEM_REJECT_ADDR_V)<<(DSPI_MEM_REJECT_ADDR_S))
-#define DSPI_MEM_REJECT_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_REJECT_ADDR_S  0
-
-#define DSPI_MEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x168)
-/* DSPI_MEM_ECC_ERR_BITS : R/SS/WTC ;bitpos:[31:25] ;default: 7'd0 ; */
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
- to byte 0 bit 0 to byte 15 bit 7).*/
-#define DSPI_MEM_ECC_ERR_BITS    0x0000007F
-#define DSPI_MEM_ECC_ERR_BITS_M  ((DSPI_MEM_ECC_ERR_BITS_V)<<(DSPI_MEM_ECC_ERR_BITS_S))
-#define DSPI_MEM_ECC_ERR_BITS_V  0x7F
-#define DSPI_MEM_ECC_ERR_BITS_S  25
-/* DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
-R record the first ECC error information..*/
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/* DSPI_MEM_USR_ECC_ADDR_EN : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
-#define DSPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define DSPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
-#define DSPI_MEM_USR_ECC_ADDR_EN_V  0x1
-#define DSPI_MEM_USR_ECC_ADDR_EN_S  21
-/* DSPI_FMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
-is bit should be 0. Otherwise, this bit should be 1..*/
-#define DSPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define DSPI_FMEM_ECC_ADDR_EN_M  (BIT(20))
-#define DSPI_FMEM_ECC_ADDR_EN_V  0x1
-#define DSPI_FMEM_ECC_ADDR_EN_S  20
-/* DSPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define DSPI_FMEM_PAGE_SIZE    0x00000003
-#define DSPI_FMEM_PAGE_SIZE_M  ((DSPI_FMEM_PAGE_SIZE_V)<<(DSPI_FMEM_PAGE_SIZE_S))
-#define DSPI_FMEM_PAGE_SIZE_V  0x3
-#define DSPI_FMEM_PAGE_SIZE_S  18
-/* DSPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define DSPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define DSPI_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define DSPI_FMEM_ECC_ERR_INT_EN_V  0x1
-#define DSPI_FMEM_ECC_ERR_INT_EN_S  17
-/* DSPI_FMEM_ECC_ERR_INT_NUM : R/W ;bitpos:[16:11] ;default: 6'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define DSPI_FMEM_ECC_ERR_INT_NUM    0x0000003F
-#define DSPI_FMEM_ECC_ERR_INT_NUM_M  ((DSPI_FMEM_ECC_ERR_INT_NUM_V)<<(DSPI_FMEM_ECC_ERR_INT_NUM_S))
-#define DSPI_FMEM_ECC_ERR_INT_NUM_V  0x3F
-#define DSPI_FMEM_ECC_ERR_INT_NUM_S  11
-
-#define DSPI_MEM_ECC_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x16C)
-/* DSPI_MEM_ECC_ERR_CNT : R/SS/WTC ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define DSPI_MEM_ECC_ERR_CNT    0x0000003F
-#define DSPI_MEM_ECC_ERR_CNT_M  ((DSPI_MEM_ECC_ERR_CNT_V)<<(DSPI_MEM_ECC_ERR_CNT_S))
-#define DSPI_MEM_ECC_ERR_CNT_V  0x3F
-#define DSPI_MEM_ECC_ERR_CNT_S  26
-/* DSPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define DSPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
-#define DSPI_MEM_ECC_ERR_ADDR_M  ((DSPI_MEM_ECC_ERR_ADDR_V)<<(DSPI_MEM_ECC_ERR_ADDR_S))
-#define DSPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_ECC_ERR_ADDR_S  0
-
-#define DSPI_MEM_AXI_ERR_ADDR_REG          (DR_REG_DSPI_MEM_BASE + 0x170)
-/* DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-/* DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M  (BIT(30))
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S  30
-/* DSPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_M  (BIT(29))
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_S  29
-/* DSPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_M  (BIT(28))
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_S  28
-/* DSPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_M  (BIT(27))
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_V  0x1
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_S  27
-/* DSPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- and SPI0 transfers are done. 0: Others..*/
-#define DSPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define DSPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
-#define DSPI_MEM_ALL_FIFO_EMPTY_V  0x1
-#define DSPI_MEM_ALL_FIFO_EMPTY_S  26
-/* DSPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
-#define DSPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
-#define DSPI_MEM_AXI_ERR_ADDR_M  ((DSPI_MEM_AXI_ERR_ADDR_V)<<(DSPI_MEM_AXI_ERR_ADDR_S))
-#define DSPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
-#define DSPI_MEM_AXI_ERR_ADDR_S  0
-
-#define DSPI_SMEM_ECC_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x174)
-/* DSPI_SMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
-#define DSPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define DSPI_SMEM_ECC_ADDR_EN_M  (BIT(20))
-#define DSPI_SMEM_ECC_ADDR_EN_V  0x1
-#define DSPI_SMEM_ECC_ADDR_EN_S  20
-/* DSPI_SMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd2 ; */
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
-es. 2: 1024 bytes. 3: 2048 bytes..*/
-#define DSPI_SMEM_PAGE_SIZE    0x00000003
-#define DSPI_SMEM_PAGE_SIZE_M  ((DSPI_SMEM_PAGE_SIZE_V)<<(DSPI_SMEM_PAGE_SIZE_S))
-#define DSPI_SMEM_PAGE_SIZE_V  0x3
-#define DSPI_SMEM_PAGE_SIZE_S  18
-/* DSPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define DSPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define DSPI_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define DSPI_SMEM_ECC_ERR_INT_EN_V  0x1
-#define DSPI_SMEM_ECC_ERR_INT_EN_S  17
-
-#define DSPI_MEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x180)
-/* DSPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
-#define DSPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define DSPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
-#define DSPI_MEM_TIMING_CALI_UPDATE_V  0x1
-#define DSPI_MEM_TIMING_CALI_UPDATE_S  6
-/* DSPI_MEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
-lash..*/
-#define DSPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define DSPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
-#define DSPI_MEM_DLL_TIMING_CALI_V  0x1
-#define DSPI_MEM_DLL_TIMING_CALI_S  5
-/* DSPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* DSPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define DSPI_MEM_TIMING_CALI    (BIT(1))
-#define DSPI_MEM_TIMING_CALI_M  (BIT(1))
-#define DSPI_MEM_TIMING_CALI_V  0x1
-#define DSPI_MEM_TIMING_CALI_S  1
-/* DSPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define DSPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define DSPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define DSPI_MEM_TIMING_CLK_ENA_V  0x1
-#define DSPI_MEM_TIMING_CLK_ENA_S  0
-
-#define DSPI_MEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x184)
-/* DSPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DINS_MODE    0x00000007
-#define DSPI_MEM_DINS_MODE_M  ((DSPI_MEM_DINS_MODE_V)<<(DSPI_MEM_DINS_MODE_S))
-#define DSPI_MEM_DINS_MODE_V  0x7
-#define DSPI_MEM_DINS_MODE_S  24
-/* DSPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN7_MODE    0x00000007
-#define DSPI_MEM_DIN7_MODE_M  ((DSPI_MEM_DIN7_MODE_V)<<(DSPI_MEM_DIN7_MODE_S))
-#define DSPI_MEM_DIN7_MODE_V  0x7
-#define DSPI_MEM_DIN7_MODE_S  21
-/* DSPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN6_MODE    0x00000007
-#define DSPI_MEM_DIN6_MODE_M  ((DSPI_MEM_DIN6_MODE_V)<<(DSPI_MEM_DIN6_MODE_S))
-#define DSPI_MEM_DIN6_MODE_V  0x7
-#define DSPI_MEM_DIN6_MODE_S  18
-/* DSPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN5_MODE    0x00000007
-#define DSPI_MEM_DIN5_MODE_M  ((DSPI_MEM_DIN5_MODE_V)<<(DSPI_MEM_DIN5_MODE_S))
-#define DSPI_MEM_DIN5_MODE_V  0x7
-#define DSPI_MEM_DIN5_MODE_S  15
-/* DSPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define DSPI_MEM_DIN4_MODE    0x00000007
-#define DSPI_MEM_DIN4_MODE_M  ((DSPI_MEM_DIN4_MODE_V)<<(DSPI_MEM_DIN4_MODE_S))
-#define DSPI_MEM_DIN4_MODE_V  0x7
-#define DSPI_MEM_DIN4_MODE_S  12
-/* DSPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN3_MODE    0x00000007
-#define DSPI_MEM_DIN3_MODE_M  ((DSPI_MEM_DIN3_MODE_V)<<(DSPI_MEM_DIN3_MODE_S))
-#define DSPI_MEM_DIN3_MODE_V  0x7
-#define DSPI_MEM_DIN3_MODE_S  9
-/* DSPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN2_MODE    0x00000007
-#define DSPI_MEM_DIN2_MODE_M  ((DSPI_MEM_DIN2_MODE_V)<<(DSPI_MEM_DIN2_MODE_S))
-#define DSPI_MEM_DIN2_MODE_V  0x7
-#define DSPI_MEM_DIN2_MODE_S  6
-/* DSPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN1_MODE    0x00000007
-#define DSPI_MEM_DIN1_MODE_M  ((DSPI_MEM_DIN1_MODE_V)<<(DSPI_MEM_DIN1_MODE_S))
-#define DSPI_MEM_DIN1_MODE_V  0x7
-#define DSPI_MEM_DIN1_MODE_S  3
-/* DSPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_MEM_DIN0_MODE    0x00000007
-#define DSPI_MEM_DIN0_MODE_M  ((DSPI_MEM_DIN0_MODE_V)<<(DSPI_MEM_DIN0_MODE_S))
-#define DSPI_MEM_DIN0_MODE_V  0x7
-#define DSPI_MEM_DIN0_MODE_S  0
-
-#define DSPI_MEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x188)
-/* DSPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DINS_NUM    0x00000003
-#define DSPI_MEM_DINS_NUM_M  ((DSPI_MEM_DINS_NUM_V)<<(DSPI_MEM_DINS_NUM_S))
-#define DSPI_MEM_DINS_NUM_V  0x3
-#define DSPI_MEM_DINS_NUM_S  16
-/* DSPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN7_NUM    0x00000003
-#define DSPI_MEM_DIN7_NUM_M  ((DSPI_MEM_DIN7_NUM_V)<<(DSPI_MEM_DIN7_NUM_S))
-#define DSPI_MEM_DIN7_NUM_V  0x3
-#define DSPI_MEM_DIN7_NUM_S  14
-/* DSPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN6_NUM    0x00000003
-#define DSPI_MEM_DIN6_NUM_M  ((DSPI_MEM_DIN6_NUM_V)<<(DSPI_MEM_DIN6_NUM_S))
-#define DSPI_MEM_DIN6_NUM_V  0x3
-#define DSPI_MEM_DIN6_NUM_S  12
-/* DSPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN5_NUM    0x00000003
-#define DSPI_MEM_DIN5_NUM_M  ((DSPI_MEM_DIN5_NUM_V)<<(DSPI_MEM_DIN5_NUM_S))
-#define DSPI_MEM_DIN5_NUM_V  0x3
-#define DSPI_MEM_DIN5_NUM_S  10
-/* DSPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN4_NUM    0x00000003
-#define DSPI_MEM_DIN4_NUM_M  ((DSPI_MEM_DIN4_NUM_V)<<(DSPI_MEM_DIN4_NUM_S))
-#define DSPI_MEM_DIN4_NUM_V  0x3
-#define DSPI_MEM_DIN4_NUM_S  8
-/* DSPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN3_NUM    0x00000003
-#define DSPI_MEM_DIN3_NUM_M  ((DSPI_MEM_DIN3_NUM_V)<<(DSPI_MEM_DIN3_NUM_S))
-#define DSPI_MEM_DIN3_NUM_V  0x3
-#define DSPI_MEM_DIN3_NUM_S  6
-/* DSPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN2_NUM    0x00000003
-#define DSPI_MEM_DIN2_NUM_M  ((DSPI_MEM_DIN2_NUM_V)<<(DSPI_MEM_DIN2_NUM_S))
-#define DSPI_MEM_DIN2_NUM_V  0x3
-#define DSPI_MEM_DIN2_NUM_S  4
-/* DSPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN1_NUM    0x00000003
-#define DSPI_MEM_DIN1_NUM_M  ((DSPI_MEM_DIN1_NUM_V)<<(DSPI_MEM_DIN1_NUM_S))
-#define DSPI_MEM_DIN1_NUM_V  0x3
-#define DSPI_MEM_DIN1_NUM_S  2
-/* DSPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_MEM_DIN0_NUM    0x00000003
-#define DSPI_MEM_DIN0_NUM_M  ((DSPI_MEM_DIN0_NUM_V)<<(DSPI_MEM_DIN0_NUM_S))
-#define DSPI_MEM_DIN0_NUM_V  0x3
-#define DSPI_MEM_DIN0_NUM_S  0
-
-#define DSPI_MEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x18C)
-/* DSPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUTS_MODE    (BIT(8))
-#define DSPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define DSPI_MEM_DOUTS_MODE_V  0x1
-#define DSPI_MEM_DOUTS_MODE_S  8
-/* DSPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT7_MODE    (BIT(7))
-#define DSPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define DSPI_MEM_DOUT7_MODE_V  0x1
-#define DSPI_MEM_DOUT7_MODE_S  7
-/* DSPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT6_MODE    (BIT(6))
-#define DSPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define DSPI_MEM_DOUT6_MODE_V  0x1
-#define DSPI_MEM_DOUT6_MODE_S  6
-/* DSPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT5_MODE    (BIT(5))
-#define DSPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define DSPI_MEM_DOUT5_MODE_V  0x1
-#define DSPI_MEM_DOUT5_MODE_S  5
-/* DSPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define DSPI_MEM_DOUT4_MODE    (BIT(4))
-#define DSPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define DSPI_MEM_DOUT4_MODE_V  0x1
-#define DSPI_MEM_DOUT4_MODE_S  4
-/* DSPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT3_MODE    (BIT(3))
-#define DSPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define DSPI_MEM_DOUT3_MODE_V  0x1
-#define DSPI_MEM_DOUT3_MODE_S  3
-/* DSPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT2_MODE    (BIT(2))
-#define DSPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define DSPI_MEM_DOUT2_MODE_V  0x1
-#define DSPI_MEM_DOUT2_MODE_S  2
-/* DSPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT1_MODE    (BIT(1))
-#define DSPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define DSPI_MEM_DOUT1_MODE_V  0x1
-#define DSPI_MEM_DOUT1_MODE_S  1
-/* DSPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_MEM_DOUT0_MODE    (BIT(0))
-#define DSPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define DSPI_MEM_DOUT0_MODE_V  0x1
-#define DSPI_MEM_DOUT0_MODE_S  0
-
-#define DSPI_SMEM_TIMING_CALI_REG          (DR_REG_DSPI_MEM_BASE + 0x190)
-/* DSPI_SMEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
-XT_RAM..*/
-#define DSPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define DSPI_SMEM_DLL_TIMING_CALI_M  (BIT(5))
-#define DSPI_SMEM_DLL_TIMING_CALI_V  0x1
-#define DSPI_SMEM_DLL_TIMING_CALI_S  5
-/* DSPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* DSPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
-ations..*/
-#define DSPI_SMEM_TIMING_CALI    (BIT(1))
-#define DSPI_SMEM_TIMING_CALI_M  (BIT(1))
-#define DSPI_SMEM_TIMING_CALI_V  0x1
-#define DSPI_SMEM_TIMING_CALI_S  1
-/* DSPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
-ns..*/
-#define DSPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define DSPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define DSPI_SMEM_TIMING_CLK_ENA_V  0x1
-#define DSPI_SMEM_TIMING_CLK_ENA_S  0
-
-#define DSPI_SMEM_DIN_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x194)
-/* DSPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DINS_MODE    0x00000007
-#define DSPI_SMEM_DINS_MODE_M  ((DSPI_SMEM_DINS_MODE_V)<<(DSPI_SMEM_DINS_MODE_S))
-#define DSPI_SMEM_DINS_MODE_V  0x7
-#define DSPI_SMEM_DINS_MODE_S  24
-/* DSPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN7_MODE    0x00000007
-#define DSPI_SMEM_DIN7_MODE_M  ((DSPI_SMEM_DIN7_MODE_V)<<(DSPI_SMEM_DIN7_MODE_S))
-#define DSPI_SMEM_DIN7_MODE_V  0x7
-#define DSPI_SMEM_DIN7_MODE_S  21
-/* DSPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN6_MODE    0x00000007
-#define DSPI_SMEM_DIN6_MODE_M  ((DSPI_SMEM_DIN6_MODE_V)<<(DSPI_SMEM_DIN6_MODE_S))
-#define DSPI_SMEM_DIN6_MODE_V  0x7
-#define DSPI_SMEM_DIN6_MODE_S  18
-/* DSPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN5_MODE    0x00000007
-#define DSPI_SMEM_DIN5_MODE_M  ((DSPI_SMEM_DIN5_MODE_V)<<(DSPI_SMEM_DIN5_MODE_S))
-#define DSPI_SMEM_DIN5_MODE_V  0x7
-#define DSPI_SMEM_DIN5_MODE_S  15
-/* DSPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN4_MODE    0x00000007
-#define DSPI_SMEM_DIN4_MODE_M  ((DSPI_SMEM_DIN4_MODE_V)<<(DSPI_SMEM_DIN4_MODE_S))
-#define DSPI_SMEM_DIN4_MODE_V  0x7
-#define DSPI_SMEM_DIN4_MODE_S  12
-/* DSPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN3_MODE    0x00000007
-#define DSPI_SMEM_DIN3_MODE_M  ((DSPI_SMEM_DIN3_MODE_V)<<(DSPI_SMEM_DIN3_MODE_S))
-#define DSPI_SMEM_DIN3_MODE_V  0x7
-#define DSPI_SMEM_DIN3_MODE_S  9
-/* DSPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN2_MODE    0x00000007
-#define DSPI_SMEM_DIN2_MODE_M  ((DSPI_SMEM_DIN2_MODE_V)<<(DSPI_SMEM_DIN2_MODE_S))
-#define DSPI_SMEM_DIN2_MODE_V  0x7
-#define DSPI_SMEM_DIN2_MODE_S  6
-/* DSPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN1_MODE    0x00000007
-#define DSPI_SMEM_DIN1_MODE_M  ((DSPI_SMEM_DIN1_MODE_V)<<(DSPI_SMEM_DIN1_MODE_S))
-#define DSPI_SMEM_DIN1_MODE_V  0x7
-#define DSPI_SMEM_DIN1_MODE_S  3
-/* DSPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN0_MODE    0x00000007
-#define DSPI_SMEM_DIN0_MODE_M  ((DSPI_SMEM_DIN0_MODE_V)<<(DSPI_SMEM_DIN0_MODE_S))
-#define DSPI_SMEM_DIN0_MODE_V  0x7
-#define DSPI_SMEM_DIN0_MODE_S  0
-
-#define DSPI_SMEM_DIN_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x198)
-/* DSPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DINS_NUM    0x00000003
-#define DSPI_SMEM_DINS_NUM_M  ((DSPI_SMEM_DINS_NUM_V)<<(DSPI_SMEM_DINS_NUM_S))
-#define DSPI_SMEM_DINS_NUM_V  0x3
-#define DSPI_SMEM_DINS_NUM_S  16
-/* DSPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN7_NUM    0x00000003
-#define DSPI_SMEM_DIN7_NUM_M  ((DSPI_SMEM_DIN7_NUM_V)<<(DSPI_SMEM_DIN7_NUM_S))
-#define DSPI_SMEM_DIN7_NUM_V  0x3
-#define DSPI_SMEM_DIN7_NUM_S  14
-/* DSPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN6_NUM    0x00000003
-#define DSPI_SMEM_DIN6_NUM_M  ((DSPI_SMEM_DIN6_NUM_V)<<(DSPI_SMEM_DIN6_NUM_S))
-#define DSPI_SMEM_DIN6_NUM_V  0x3
-#define DSPI_SMEM_DIN6_NUM_S  12
-/* DSPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN5_NUM    0x00000003
-#define DSPI_SMEM_DIN5_NUM_M  ((DSPI_SMEM_DIN5_NUM_V)<<(DSPI_SMEM_DIN5_NUM_S))
-#define DSPI_SMEM_DIN5_NUM_V  0x3
-#define DSPI_SMEM_DIN5_NUM_S  10
-/* DSPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN4_NUM    0x00000003
-#define DSPI_SMEM_DIN4_NUM_M  ((DSPI_SMEM_DIN4_NUM_V)<<(DSPI_SMEM_DIN4_NUM_S))
-#define DSPI_SMEM_DIN4_NUM_V  0x3
-#define DSPI_SMEM_DIN4_NUM_S  8
-/* DSPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN3_NUM    0x00000003
-#define DSPI_SMEM_DIN3_NUM_M  ((DSPI_SMEM_DIN3_NUM_V)<<(DSPI_SMEM_DIN3_NUM_S))
-#define DSPI_SMEM_DIN3_NUM_V  0x3
-#define DSPI_SMEM_DIN3_NUM_S  6
-/* DSPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN2_NUM    0x00000003
-#define DSPI_SMEM_DIN2_NUM_M  ((DSPI_SMEM_DIN2_NUM_V)<<(DSPI_SMEM_DIN2_NUM_S))
-#define DSPI_SMEM_DIN2_NUM_V  0x3
-#define DSPI_SMEM_DIN2_NUM_S  4
-/* DSPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN1_NUM    0x00000003
-#define DSPI_SMEM_DIN1_NUM_M  ((DSPI_SMEM_DIN1_NUM_V)<<(DSPI_SMEM_DIN1_NUM_S))
-#define DSPI_SMEM_DIN1_NUM_V  0x3
-#define DSPI_SMEM_DIN1_NUM_S  2
-/* DSPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN0_NUM    0x00000003
-#define DSPI_SMEM_DIN0_NUM_M  ((DSPI_SMEM_DIN0_NUM_V)<<(DSPI_SMEM_DIN0_NUM_S))
-#define DSPI_SMEM_DIN0_NUM_V  0x3
-#define DSPI_SMEM_DIN0_NUM_S  0
-
-#define DSPI_SMEM_DOUT_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x19C)
-/* DSPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUTS_MODE    (BIT(8))
-#define DSPI_SMEM_DOUTS_MODE_M  (BIT(8))
-#define DSPI_SMEM_DOUTS_MODE_V  0x1
-#define DSPI_SMEM_DOUTS_MODE_S  8
-/* DSPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT7_MODE    (BIT(7))
-#define DSPI_SMEM_DOUT7_MODE_M  (BIT(7))
-#define DSPI_SMEM_DOUT7_MODE_V  0x1
-#define DSPI_SMEM_DOUT7_MODE_S  7
-/* DSPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT6_MODE    (BIT(6))
-#define DSPI_SMEM_DOUT6_MODE_M  (BIT(6))
-#define DSPI_SMEM_DOUT6_MODE_V  0x1
-#define DSPI_SMEM_DOUT6_MODE_S  6
-/* DSPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT5_MODE    (BIT(5))
-#define DSPI_SMEM_DOUT5_MODE_M  (BIT(5))
-#define DSPI_SMEM_DOUT5_MODE_V  0x1
-#define DSPI_SMEM_DOUT5_MODE_S  5
-/* DSPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT4_MODE    (BIT(4))
-#define DSPI_SMEM_DOUT4_MODE_M  (BIT(4))
-#define DSPI_SMEM_DOUT4_MODE_V  0x1
-#define DSPI_SMEM_DOUT4_MODE_S  4
-/* DSPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT3_MODE    (BIT(3))
-#define DSPI_SMEM_DOUT3_MODE_M  (BIT(3))
-#define DSPI_SMEM_DOUT3_MODE_V  0x1
-#define DSPI_SMEM_DOUT3_MODE_S  3
-/* DSPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT2_MODE    (BIT(2))
-#define DSPI_SMEM_DOUT2_MODE_M  (BIT(2))
-#define DSPI_SMEM_DOUT2_MODE_V  0x1
-#define DSPI_SMEM_DOUT2_MODE_S  2
-/* DSPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT1_MODE    (BIT(1))
-#define DSPI_SMEM_DOUT1_MODE_M  (BIT(1))
-#define DSPI_SMEM_DOUT1_MODE_V  0x1
-#define DSPI_SMEM_DOUT1_MODE_S  1
-/* DSPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT0_MODE    (BIT(0))
-#define DSPI_SMEM_DOUT0_MODE_M  (BIT(0))
-#define DSPI_SMEM_DOUT0_MODE_V  0x1
-#define DSPI_SMEM_DOUT0_MODE_S  0
-
-#define DSPI_SMEM_AC_REG          (DR_REG_DSPI_MEM_BASE + 0x1A0)
-/* DSPI_SMEM_SPLIT_TRANS_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
-er whether there is an ECC region or not..*/
-#define DSPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define DSPI_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
-#define DSPI_SMEM_SPLIT_TRANS_EN_V  0x1
-#define DSPI_SMEM_SPLIT_TRANS_EN_S  31
-/* DSPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define DSPI_SMEM_CS_HOLD_DELAY    0x0000003F
-#define DSPI_SMEM_CS_HOLD_DELAY_M  ((DSPI_SMEM_CS_HOLD_DELAY_V)<<(DSPI_SMEM_CS_HOLD_DELAY_S))
-#define DSPI_SMEM_CS_HOLD_DELAY_V  0x3F
-#define DSPI_SMEM_CS_HOLD_DELAY_S  25
-/* DSPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* DSPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
-en accesses external RAM..*/
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* DSPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
-ycles in ECC mode when accessed external RAM..*/
-#define DSPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_M  ((DSPI_SMEM_ECC_CS_HOLD_TIME_V)<<(DSPI_SMEM_ECC_CS_HOLD_TIME_S))
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/* DSPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
-re combined with spi_mem_cs_hold bit..*/
-#define DSPI_SMEM_CS_HOLD_TIME    0x0000001F
-#define DSPI_SMEM_CS_HOLD_TIME_M  ((DSPI_SMEM_CS_HOLD_TIME_V)<<(DSPI_SMEM_CS_HOLD_TIME_S))
-#define DSPI_SMEM_CS_HOLD_TIME_V  0x1F
-#define DSPI_SMEM_CS_HOLD_TIME_S  7
-/* DSPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
-pi_mem_cs_setup bit..*/
-#define DSPI_SMEM_CS_SETUP_TIME    0x0000001F
-#define DSPI_SMEM_CS_SETUP_TIME_M  ((DSPI_SMEM_CS_SETUP_TIME_V)<<(DSPI_SMEM_CS_SETUP_TIME_S))
-#define DSPI_SMEM_CS_SETUP_TIME_V  0x1F
-#define DSPI_SMEM_CS_SETUP_TIME_S  2
-/* DSPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
-le..*/
-#define DSPI_SMEM_CS_HOLD    (BIT(1))
-#define DSPI_SMEM_CS_HOLD_M  (BIT(1))
-#define DSPI_SMEM_CS_HOLD_V  0x1
-#define DSPI_SMEM_CS_HOLD_S  1
-/* DSPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
-isable..*/
-#define DSPI_SMEM_CS_SETUP    (BIT(0))
-#define DSPI_SMEM_CS_SETUP_M  (BIT(0))
-#define DSPI_SMEM_CS_SETUP_V  0x1
-#define DSPI_SMEM_CS_SETUP_S  0
-
-#define DSPI_SMEM_DIN_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1A4)
-/* DSPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DINS_HEX_MODE    0x00000007
-#define DSPI_SMEM_DINS_HEX_MODE_M  ((DSPI_SMEM_DINS_HEX_MODE_V)<<(DSPI_SMEM_DINS_HEX_MODE_S))
-#define DSPI_SMEM_DINS_HEX_MODE_V  0x7
-#define DSPI_SMEM_DINS_HEX_MODE_S  24
-/* DSPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN15_MODE    0x00000007
-#define DSPI_SMEM_DIN15_MODE_M  ((DSPI_SMEM_DIN15_MODE_V)<<(DSPI_SMEM_DIN15_MODE_S))
-#define DSPI_SMEM_DIN15_MODE_V  0x7
-#define DSPI_SMEM_DIN15_MODE_S  21
-/* DSPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN14_MODE    0x00000007
-#define DSPI_SMEM_DIN14_MODE_M  ((DSPI_SMEM_DIN14_MODE_V)<<(DSPI_SMEM_DIN14_MODE_S))
-#define DSPI_SMEM_DIN14_MODE_V  0x7
-#define DSPI_SMEM_DIN14_MODE_S  18
-/* DSPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN13_MODE    0x00000007
-#define DSPI_SMEM_DIN13_MODE_M  ((DSPI_SMEM_DIN13_MODE_V)<<(DSPI_SMEM_DIN13_MODE_S))
-#define DSPI_SMEM_DIN13_MODE_V  0x7
-#define DSPI_SMEM_DIN13_MODE_S  15
-/* DSPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN12_MODE    0x00000007
-#define DSPI_SMEM_DIN12_MODE_M  ((DSPI_SMEM_DIN12_MODE_V)<<(DSPI_SMEM_DIN12_MODE_S))
-#define DSPI_SMEM_DIN12_MODE_V  0x7
-#define DSPI_SMEM_DIN12_MODE_S  12
-/* DSPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN11_MODE    0x00000007
-#define DSPI_SMEM_DIN11_MODE_M  ((DSPI_SMEM_DIN11_MODE_V)<<(DSPI_SMEM_DIN11_MODE_S))
-#define DSPI_SMEM_DIN11_MODE_V  0x7
-#define DSPI_SMEM_DIN11_MODE_S  9
-/* DSPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN10_MODE    0x00000007
-#define DSPI_SMEM_DIN10_MODE_M  ((DSPI_SMEM_DIN10_MODE_V)<<(DSPI_SMEM_DIN10_MODE_S))
-#define DSPI_SMEM_DIN10_MODE_V  0x7
-#define DSPI_SMEM_DIN10_MODE_S  6
-/* DSPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN09_MODE    0x00000007
-#define DSPI_SMEM_DIN09_MODE_M  ((DSPI_SMEM_DIN09_MODE_V)<<(DSPI_SMEM_DIN09_MODE_S))
-#define DSPI_SMEM_DIN09_MODE_V  0x7
-#define DSPI_SMEM_DIN09_MODE_S  3
-/* DSPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define DSPI_SMEM_DIN08_MODE    0x00000007
-#define DSPI_SMEM_DIN08_MODE_M  ((DSPI_SMEM_DIN08_MODE_V)<<(DSPI_SMEM_DIN08_MODE_S))
-#define DSPI_SMEM_DIN08_MODE_V  0x7
-#define DSPI_SMEM_DIN08_MODE_S  0
-
-#define DSPI_SMEM_DIN_HEX_NUM_REG          (DR_REG_DSPI_MEM_BASE + 0x1A8)
-/* DSPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DINS_HEX_NUM    0x00000003
-#define DSPI_SMEM_DINS_HEX_NUM_M  ((DSPI_SMEM_DINS_HEX_NUM_V)<<(DSPI_SMEM_DINS_HEX_NUM_S))
-#define DSPI_SMEM_DINS_HEX_NUM_V  0x3
-#define DSPI_SMEM_DINS_HEX_NUM_S  16
-/* DSPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN15_NUM    0x00000003
-#define DSPI_SMEM_DIN15_NUM_M  ((DSPI_SMEM_DIN15_NUM_V)<<(DSPI_SMEM_DIN15_NUM_S))
-#define DSPI_SMEM_DIN15_NUM_V  0x3
-#define DSPI_SMEM_DIN15_NUM_S  14
-/* DSPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN14_NUM    0x00000003
-#define DSPI_SMEM_DIN14_NUM_M  ((DSPI_SMEM_DIN14_NUM_V)<<(DSPI_SMEM_DIN14_NUM_S))
-#define DSPI_SMEM_DIN14_NUM_V  0x3
-#define DSPI_SMEM_DIN14_NUM_S  12
-/* DSPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN13_NUM    0x00000003
-#define DSPI_SMEM_DIN13_NUM_M  ((DSPI_SMEM_DIN13_NUM_V)<<(DSPI_SMEM_DIN13_NUM_S))
-#define DSPI_SMEM_DIN13_NUM_V  0x3
-#define DSPI_SMEM_DIN13_NUM_S  10
-/* DSPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN12_NUM    0x00000003
-#define DSPI_SMEM_DIN12_NUM_M  ((DSPI_SMEM_DIN12_NUM_V)<<(DSPI_SMEM_DIN12_NUM_S))
-#define DSPI_SMEM_DIN12_NUM_V  0x3
-#define DSPI_SMEM_DIN12_NUM_S  8
-/* DSPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN11_NUM    0x00000003
-#define DSPI_SMEM_DIN11_NUM_M  ((DSPI_SMEM_DIN11_NUM_V)<<(DSPI_SMEM_DIN11_NUM_S))
-#define DSPI_SMEM_DIN11_NUM_V  0x3
-#define DSPI_SMEM_DIN11_NUM_S  6
-/* DSPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN10_NUM    0x00000003
-#define DSPI_SMEM_DIN10_NUM_M  ((DSPI_SMEM_DIN10_NUM_V)<<(DSPI_SMEM_DIN10_NUM_S))
-#define DSPI_SMEM_DIN10_NUM_V  0x3
-#define DSPI_SMEM_DIN10_NUM_S  4
-/* DSPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN09_NUM    0x00000003
-#define DSPI_SMEM_DIN09_NUM_M  ((DSPI_SMEM_DIN09_NUM_V)<<(DSPI_SMEM_DIN09_NUM_S))
-#define DSPI_SMEM_DIN09_NUM_V  0x3
-#define DSPI_SMEM_DIN09_NUM_S  2
-/* DSPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define DSPI_SMEM_DIN08_NUM    0x00000003
-#define DSPI_SMEM_DIN08_NUM_M  ((DSPI_SMEM_DIN08_NUM_V)<<(DSPI_SMEM_DIN08_NUM_S))
-#define DSPI_SMEM_DIN08_NUM_V  0x3
-#define DSPI_SMEM_DIN08_NUM_S  0
-
-#define DSPI_SMEM_DOUT_HEX_MODE_REG          (DR_REG_DSPI_MEM_BASE + 0x1AC)
-/* DSPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUTS_HEX_MODE    (BIT(8))
-#define DSPI_SMEM_DOUTS_HEX_MODE_M  (BIT(8))
-#define DSPI_SMEM_DOUTS_HEX_MODE_V  0x1
-#define DSPI_SMEM_DOUTS_HEX_MODE_S  8
-/* DSPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT15_MODE    (BIT(7))
-#define DSPI_SMEM_DOUT15_MODE_M  (BIT(7))
-#define DSPI_SMEM_DOUT15_MODE_V  0x1
-#define DSPI_SMEM_DOUT15_MODE_S  7
-/* DSPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT14_MODE    (BIT(6))
-#define DSPI_SMEM_DOUT14_MODE_M  (BIT(6))
-#define DSPI_SMEM_DOUT14_MODE_V  0x1
-#define DSPI_SMEM_DOUT14_MODE_S  6
-/* DSPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT13_MODE    (BIT(5))
-#define DSPI_SMEM_DOUT13_MODE_M  (BIT(5))
-#define DSPI_SMEM_DOUT13_MODE_V  0x1
-#define DSPI_SMEM_DOUT13_MODE_S  5
-/* DSPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT12_MODE    (BIT(4))
-#define DSPI_SMEM_DOUT12_MODE_M  (BIT(4))
-#define DSPI_SMEM_DOUT12_MODE_V  0x1
-#define DSPI_SMEM_DOUT12_MODE_S  4
-/* DSPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT11_MODE    (BIT(3))
-#define DSPI_SMEM_DOUT11_MODE_M  (BIT(3))
-#define DSPI_SMEM_DOUT11_MODE_V  0x1
-#define DSPI_SMEM_DOUT11_MODE_S  3
-/* DSPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT10_MODE    (BIT(2))
-#define DSPI_SMEM_DOUT10_MODE_M  (BIT(2))
-#define DSPI_SMEM_DOUT10_MODE_V  0x1
-#define DSPI_SMEM_DOUT10_MODE_S  2
-/* DSPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT09_MODE    (BIT(1))
-#define DSPI_SMEM_DOUT09_MODE_M  (BIT(1))
-#define DSPI_SMEM_DOUT09_MODE_V  0x1
-#define DSPI_SMEM_DOUT09_MODE_S  1
-/* DSPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define DSPI_SMEM_DOUT08_MODE    (BIT(0))
-#define DSPI_SMEM_DOUT08_MODE_M  (BIT(0))
-#define DSPI_SMEM_DOUT08_MODE_V  0x1
-#define DSPI_SMEM_DOUT08_MODE_S  0
-
-#define DSPI_MEM_CLOCK_GATE_REG          (DR_REG_DSPI_MEM_BASE + 0x200)
-/* DSPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define DSPI_MEM_SPI_CLK_EN    (BIT(0))
-#define DSPI_MEM_SPI_CLK_EN_M  (BIT(0))
-#define DSPI_MEM_SPI_CLK_EN_V  0x1
-#define DSPI_MEM_SPI_CLK_EN_S  0
-
-#define DSPI_MEM_XTS_PLAIN_BASE_REG          (DR_REG_DSPI_MEM_BASE + 0x300)
-/* DSPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define DSPI_MEM_SPI_XTS_PLAIN    0xFFFFFFFF
-#define DSPI_MEM_SPI_XTS_PLAIN_M  ((DSPI_MEM_SPI_XTS_PLAIN_V)<<(DSPI_MEM_SPI_XTS_PLAIN_S))
-#define DSPI_MEM_SPI_XTS_PLAIN_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_XTS_PLAIN_S  0
-
-#define DSPI_MEM_XTS_LINESIZE_REG          (DR_REG_DSPI_MEM_BASE + 0x340)
-/* DSPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define DSPI_MEM_SPI_XTS_LINESIZE    0x00000003
-#define DSPI_MEM_SPI_XTS_LINESIZE_M  ((DSPI_MEM_SPI_XTS_LINESIZE_V)<<(DSPI_MEM_SPI_XTS_LINESIZE_S))
-#define DSPI_MEM_SPI_XTS_LINESIZE_V  0x3
-#define DSPI_MEM_SPI_XTS_LINESIZE_S  0
-
-#define DSPI_MEM_XTS_DESTINATION_REG          (DR_REG_DSPI_MEM_BASE + 0x344)
-/* DSPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define DSPI_MEM_SPI_XTS_DESTINATION    (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTINATION_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTINATION_V  0x1
-#define DSPI_MEM_SPI_XTS_DESTINATION_S  0
-
-#define DSPI_MEM_XTS_PHYSICAL_ADDRESS_REG          (DR_REG_DSPI_MEM_BASE + 0x348)
-/* DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFF
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M  ((DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S  0
-
-#define DSPI_MEM_XTS_TRIGGER_REG          (DR_REG_DSPI_MEM_BASE + 0x34C)
-/* DSPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define DSPI_MEM_SPI_XTS_TRIGGER    (BIT(0))
-#define DSPI_MEM_SPI_XTS_TRIGGER_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_TRIGGER_V  0x1
-#define DSPI_MEM_SPI_XTS_TRIGGER_S  0
-
-#define DSPI_MEM_XTS_RELEASE_REG          (DR_REG_DSPI_MEM_BASE + 0x350)
-/* DSPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define DSPI_MEM_SPI_XTS_RELEASE    (BIT(0))
-#define DSPI_MEM_SPI_XTS_RELEASE_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_RELEASE_V  0x1
-#define DSPI_MEM_SPI_XTS_RELEASE_S  0
-
-#define DSPI_MEM_XTS_DESTROY_REG          (DR_REG_DSPI_MEM_BASE + 0x354)
-/* DSPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define DSPI_MEM_SPI_XTS_DESTROY    (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTROY_M  (BIT(0))
-#define DSPI_MEM_SPI_XTS_DESTROY_V  0x1
-#define DSPI_MEM_SPI_XTS_DESTROY_S  0
-
-#define DSPI_MEM_XTS_STATE_REG          (DR_REG_DSPI_MEM_BASE + 0x358)
-/* DSPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define DSPI_MEM_SPI_XTS_STATE    0x00000003
-#define DSPI_MEM_SPI_XTS_STATE_M  ((DSPI_MEM_SPI_XTS_STATE_V)<<(DSPI_MEM_SPI_XTS_STATE_S))
-#define DSPI_MEM_SPI_XTS_STATE_V  0x3
-#define DSPI_MEM_SPI_XTS_STATE_S  0
-
-#define DSPI_MEM_XTS_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x35C)
-/* DSPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define DSPI_MEM_SPI_XTS_DATE    0x3FFFFFFF
-#define DSPI_MEM_SPI_XTS_DATE_M  ((DSPI_MEM_SPI_XTS_DATE_V)<<(DSPI_MEM_SPI_XTS_DATE_S))
-#define DSPI_MEM_SPI_XTS_DATE_V  0x3FFFFFFF
-#define DSPI_MEM_SPI_XTS_DATE_S  0
-
-#define DSPI_MEM_MMU_ITEM_CONTENT_REG          (DR_REG_DSPI_MEM_BASE + 0x37C)
-/* DSPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: MSPI-MMU item content.*/
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT    0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_M  ((DSPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(DSPI_MEM_SPI_MMU_ITEM_CONTENT_S))
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_S  0
-
-#define DSPI_MEM_MMU_ITEM_INDEX_REG          (DR_REG_DSPI_MEM_BASE + 0x380)
-/* DSPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: MSPI-MMU item index.*/
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX    0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_M  ((DSPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(DSPI_MEM_SPI_MMU_ITEM_INDEX_S))
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_V  0xFFFFFFFF
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_S  0
-
-#define DSPI_MEM_MMU_POWER_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x384)
-/* DSPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
-#define DSPI_MEM_RDN_RESULT    (BIT(31))
-#define DSPI_MEM_RDN_RESULT_M  (BIT(31))
-#define DSPI_MEM_RDN_RESULT_V  0x1
-#define DSPI_MEM_RDN_RESULT_S  31
-/* DSPI_MEM_RDN_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: ECO register enable bit.*/
-#define DSPI_MEM_RDN_ENA    (BIT(30))
-#define DSPI_MEM_RDN_ENA_M  (BIT(30))
-#define DSPI_MEM_RDN_ENA_V  0x1
-#define DSPI_MEM_RDN_ENA_S  30
-/* DSPI_MEM_AUX_CTRL : R/W ;bitpos:[29:16] ;default: 14'h1320 ; */
-/*description: MMU PSRAM aux control register.*/
-#define DSPI_MEM_AUX_CTRL    0x00003FFF
-#define DSPI_MEM_AUX_CTRL_M  ((DSPI_MEM_AUX_CTRL_V)<<(DSPI_MEM_AUX_CTRL_S))
-#define DSPI_MEM_AUX_CTRL_V  0x3FFF
-#define DSPI_MEM_AUX_CTRL_S  16
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
- controlled by rtc..*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_S  2
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to force mmu-memory powerdown.*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_S  1
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable mmu-memory clock force on.*/
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_V  0x1
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_S  0
-
-#define DSPI_MEM_DPA_CTRL_REG          (DR_REG_DSPI_MEM_BASE + 0x388)
-/* DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S  4
-/* DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V  0x1
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S  3
-/* DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL    0x00000007
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M  ((DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V  0x7
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S  0
-
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_REG          (DR_REG_DSPI_MEM_BASE + 0x3F0)
-/* DSPI_MEM_REGISTERRND_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO high register.*/
-#define DSPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_M  ((DSPI_MEM_REGISTERRND_ECO_HIGH_V)<<(DSPI_MEM_REGISTERRND_ECO_HIGH_S))
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_S  0
-
-#define DSPI_MEM_REGISTERRND_ECO_LOW_REG          (DR_REG_DSPI_MEM_BASE + 0x3F4)
-/* DSPI_MEM_REGISTERRND_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO low register.*/
-#define DSPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_LOW_M  ((DSPI_MEM_REGISTERRND_ECO_LOW_V)<<(DSPI_MEM_REGISTERRND_ECO_LOW_S))
-#define DSPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
-#define DSPI_MEM_REGISTERRND_ECO_LOW_S  0
-
-#define DSPI_MEM_DATE_REG          (DR_REG_DSPI_MEM_BASE + 0x3FC)
-/* DSPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2211210 ; */
-/*description: SPI0 register version..*/
-#define DSPI_MEM_DATE    0x0FFFFFFF
-#define DSPI_MEM_DATE_M  ((DSPI_MEM_DATE_V)<<(DSPI_MEM_DATE_S))
-#define DSPI_MEM_DATE_V  0xFFFFFFF
-#define DSPI_MEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_DSPI_MEM_REG_H_ */

components/soc/esp32p4/include/soc/reg_base.h

@@ -54,8 +54,8 @@
 #define DR_REG_DMA2D_BASE             (DR_REG_HPPERIPH0_BASE + 0x88000)
 #define DR_REG_KEY_MANAGER_BASE       (DR_REG_HPPERIPH0_BASE + 0x89000)
 #define DR_REG_AXI_DMA_BASE           (DR_REG_HPPERIPH0_BASE + 0x8A000)
-#define DR_REG_SPI0_BASE              (DR_REG_HPPERIPH0_BASE + 0x8C000)
-#define DR_REG_SPI1_BASE              (DR_REG_HPPERIPH0_BASE + 0x8D000)
+#define DR_REG_FLASH_SPI0_BASE        (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define DR_REG_FLASH_SPI1_BASE        (DR_REG_HPPERIPH0_BASE + 0x8D000)
 #define DR_REG_PSRAM_MSPI0_BASE       (DR_REG_HPPERIPH0_BASE + 0x8E000)
 #define DR_REG_PSRAM_MSPI1_BASE       (DR_REG_HPPERIPH0_BASE + 0x8F000)
 #define DR_REG_CRYPTO_BASE            (DR_REG_HPPERIPH0_BASE + 0x90000)

components/soc/esp32p4/include/soc/soc.h

@@ -21,7 +21,7 @@
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_BASE(i) + 0x0)
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)         // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
-#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
+#define REG_SPI_MEM_BASE(i)                     (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000)  // SPIMEM0 and SPIMEM1
 #define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i) * 0x1000)        // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)                         (DR_REG_I2C0_BASE + (i) * 0x1000)
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE + (i) * 0x1000)

components/soc/esp32p4/include/soc/spi1_mem_c_reg.h

@@ -11,1470 +11,1470 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI1_MEM_C_CMD_REG register
  *  SPI1 memory command register
  */
-#define SPI_MEM_CMD_REG (DR_REG_SPI1_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI1_MEM_C_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0x0)
+/** SPI1_MEM_C_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI1 master FSM.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI1_MEM_C_MST_ST    0x0000000FU
+#define SPI1_MEM_C_MST_ST_M  (SPI1_MEM_C_MST_ST_V << SPI1_MEM_C_MST_ST_S)
+#define SPI1_MEM_C_MST_ST_V  0x0000000FU
+#define SPI1_MEM_C_MST_ST_S  0
+/** SPI1_MEM_C_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+#define SPI1_MEM_C_SLV_ST    0x0000000FU
+#define SPI1_MEM_C_SLV_ST_M  (SPI1_MEM_C_SLV_ST_V << SPI1_MEM_C_SLV_ST_S)
+#define SPI1_MEM_C_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_C_SLV_ST_S  4
+/** SPI1_MEM_C_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
  *  In user mode, it is set to indicate that program/erase operation will be triggered.
- *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+ *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
  *  operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S)
-#define SPI_MEM_FLASH_PE_V  0x00000001U
-#define SPI_MEM_FLASH_PE_S  17
-/** SPI_MEM_USR : R/W/SC; bitpos: [18]; default: 0;
+#define SPI1_MEM_C_FLASH_PE    (BIT(17))
+#define SPI1_MEM_C_FLASH_PE_M  (SPI1_MEM_C_FLASH_PE_V << SPI1_MEM_C_FLASH_PE_S)
+#define SPI1_MEM_C_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PE_S  17
+/** SPI1_MEM_C_USR : R/W/SC; bitpos: [18]; default: 0;
  *  User define command enable.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
-/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+#define SPI1_MEM_C_USR    (BIT(18))
+#define SPI1_MEM_C_USR_M  (SPI1_MEM_C_USR_V << SPI1_MEM_C_USR_S)
+#define SPI1_MEM_C_USR_V  0x00000001U
+#define SPI1_MEM_C_USR_S  18
+/** SPI1_MEM_C_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
  *  Drive Flash into high performance mode.  The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S)
-#define SPI_MEM_FLASH_HPM_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_S  19
-/** SPI_MEM_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+#define SPI1_MEM_C_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_C_FLASH_HPM_M  (SPI1_MEM_C_FLASH_HPM_V << SPI1_MEM_C_FLASH_HPM_S)
+#define SPI1_MEM_C_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_S  19
+/** SPI1_MEM_C_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
  *  This bit combined with reg_resandres bit releases Flash from the power-down state
  *  or high performance mode and obtains the devices ID. The bit will be cleared once
  *  the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S)
-#define SPI_MEM_FLASH_RES_V  0x00000001U
-#define SPI_MEM_FLASH_RES_S  20
-/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+#define SPI1_MEM_C_FLASH_RES    (BIT(20))
+#define SPI1_MEM_C_FLASH_RES_M  (SPI1_MEM_C_FLASH_RES_V << SPI1_MEM_C_FLASH_RES_S)
+#define SPI1_MEM_C_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_S  20
+/** SPI1_MEM_C_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
  *  Drive Flash into power down.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S)
-#define SPI_MEM_FLASH_DP_V  0x00000001U
-#define SPI_MEM_FLASH_DP_S  21
-/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_FLASH_DP    (BIT(21))
+#define SPI1_MEM_C_FLASH_DP_M  (SPI1_MEM_C_FLASH_DP_V << SPI1_MEM_C_FLASH_DP_S)
+#define SPI1_MEM_C_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_S  21
+/** SPI1_MEM_C_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
  *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S)
-#define SPI_MEM_FLASH_CE_V  0x00000001U
-#define SPI_MEM_FLASH_CE_S  22
-/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_FLASH_CE    (BIT(22))
+#define SPI1_MEM_C_FLASH_CE_M  (SPI1_MEM_C_FLASH_CE_V << SPI1_MEM_C_FLASH_CE_S)
+#define SPI1_MEM_C_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_CE_S  22
+/** SPI1_MEM_C_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
  *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S)
-#define SPI_MEM_FLASH_BE_V  0x00000001U
-#define SPI_MEM_FLASH_BE_S  23
-/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FLASH_BE    (BIT(23))
+#define SPI1_MEM_C_FLASH_BE_M  (SPI1_MEM_C_FLASH_BE_V << SPI1_MEM_C_FLASH_BE_S)
+#define SPI1_MEM_C_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_BE_S  23
+/** SPI1_MEM_C_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
  *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S)
-#define SPI_MEM_FLASH_SE_V  0x00000001U
-#define SPI_MEM_FLASH_SE_S  24
-/** SPI_MEM_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+#define SPI1_MEM_C_FLASH_SE    (BIT(24))
+#define SPI1_MEM_C_FLASH_SE_M  (SPI1_MEM_C_FLASH_SE_V << SPI1_MEM_C_FLASH_SE_S)
+#define SPI1_MEM_C_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SE_S  24
+/** SPI1_MEM_C_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
  *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
  *  operation  will be triggered when the bit is set. The bit will be cleared once the
  *  operation done .1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S)
-#define SPI_MEM_FLASH_PP_V  0x00000001U
-#define SPI_MEM_FLASH_PP_S  25
-/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_FLASH_PP    (BIT(25))
+#define SPI1_MEM_C_FLASH_PP_M  (SPI1_MEM_C_FLASH_PP_V << SPI1_MEM_C_FLASH_PP_S)
+#define SPI1_MEM_C_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PP_S  25
+/** SPI1_MEM_C_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
  *  Write status register enable.   Write status operation  will be triggered when the
  *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S)
-#define SPI_MEM_FLASH_WRSR_V  0x00000001U
-#define SPI_MEM_FLASH_WRSR_S  26
-/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_C_FLASH_WRSR_M  (SPI1_MEM_C_FLASH_WRSR_V << SPI1_MEM_C_FLASH_WRSR_S)
+#define SPI1_MEM_C_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRSR_S  26
+/** SPI1_MEM_C_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
  *  Read status register-1.  Read status operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S)
-#define SPI_MEM_FLASH_RDSR_V  0x00000001U
-#define SPI_MEM_FLASH_RDSR_S  27
-/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_C_FLASH_RDSR_M  (SPI1_MEM_C_FLASH_RDSR_V << SPI1_MEM_C_FLASH_RDSR_S)
+#define SPI1_MEM_C_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDSR_S  27
+/** SPI1_MEM_C_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
  *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
  *  cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S)
-#define SPI_MEM_FLASH_RDID_V  0x00000001U
-#define SPI_MEM_FLASH_RDID_S  28
-/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_C_FLASH_RDID_M  (SPI1_MEM_C_FLASH_RDID_V << SPI1_MEM_C_FLASH_RDID_S)
+#define SPI1_MEM_C_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RDID_S  28
+/** SPI1_MEM_C_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
  *  Write flash disable. Write disable command will be sent when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S)
-#define SPI_MEM_FLASH_WRDI_V  0x00000001U
-#define SPI_MEM_FLASH_WRDI_S  29
-/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_C_FLASH_WRDI_M  (SPI1_MEM_C_FLASH_WRDI_V << SPI1_MEM_C_FLASH_WRDI_S)
+#define SPI1_MEM_C_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WRDI_S  29
+/** SPI1_MEM_C_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
  *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
  *  will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S)
-#define SPI_MEM_FLASH_WREN_V  0x00000001U
-#define SPI_MEM_FLASH_WREN_S  30
-/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_C_FLASH_WREN_M  (SPI1_MEM_C_FLASH_WREN_V << SPI1_MEM_C_FLASH_WREN_S)
+#define SPI1_MEM_C_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_WREN_S  30
+/** SPI1_MEM_C_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
  *  Read flash enable. Read flash operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S)
-#define SPI_MEM_FLASH_READ_V  0x00000001U
-#define SPI_MEM_FLASH_READ_S  31
+#define SPI1_MEM_C_FLASH_READ    (BIT(31))
+#define SPI1_MEM_C_FLASH_READ_M  (SPI1_MEM_C_FLASH_READ_V << SPI1_MEM_C_FLASH_READ_S)
+#define SPI1_MEM_C_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_C_FLASH_READ_S  31
 
-/** SPI_MEM_ADDR_REG register
+/** SPI1_MEM_C_ADDR_REG register
  *  SPI1 address register
  */
-#define SPI_MEM_ADDR_REG (DR_REG_SPI1_BASE + 0x4)
-/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_ADDR_REG (DR_REG_FLASH_SPI1_BASE + 0x4)
+/** SPI1_MEM_C_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
  *  address, the bit24-bit31 are the byte length of a transfer.
  */
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_M  (SPI_MEM_USR_ADDR_VALUE_V << SPI_MEM_USR_ADDR_VALUE_S)
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_S  0
+#define SPI1_MEM_C_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_M  (SPI1_MEM_C_USR_ADDR_VALUE_V << SPI1_MEM_C_USR_ADDR_VALUE_S)
+#define SPI1_MEM_C_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_C_USR_ADDR_VALUE_S  0
 
-/** SPI_MEM_CTRL_REG register
+/** SPI1_MEM_C_CTRL_REG register
  *  SPI1 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_SPI1_BASE + 0x8)
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI1_MEM_C_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x8)
+/** SPI1_MEM_C_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI1_MEM_C_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_C_FDUMMY_RIN_M  (SPI1_MEM_C_FDUMMY_RIN_V << SPI1_MEM_C_FDUMMY_RIN_S)
+#define SPI1_MEM_C_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_RIN_S  2
+/** SPI1_MEM_C_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_C_FDUMMY_WOUT_M  (SPI1_MEM_C_FDUMMY_WOUT_V << SPI1_MEM_C_FDUMMY_WOUT_S)
+#define SPI1_MEM_C_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_C_FDUMMY_WOUT_S  3
+/** SPI1_MEM_C_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_C_FDOUT_OCT_M  (SPI1_MEM_C_FDOUT_OCT_V << SPI1_MEM_C_FDOUT_OCT_S)
+#define SPI1_MEM_C_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_OCT_S  4
+/** SPI1_MEM_C_FDIN_OCT : HRO; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0;
+#define SPI1_MEM_C_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_C_FDIN_OCT_M  (SPI1_MEM_C_FDIN_OCT_V << SPI1_MEM_C_FDIN_OCT_S)
+#define SPI1_MEM_C_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_C_FDIN_OCT_S  5
+/** SPI1_MEM_C_FADDR_OCT : HRO; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_C_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_C_FADDR_OCT_M  (SPI1_MEM_C_FADDR_OCT_V << SPI1_MEM_C_FADDR_OCT_S)
+#define SPI1_MEM_C_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_C_FADDR_OCT_S  6
+/** SPI1_MEM_C_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_C_FCMD_QUAD_M  (SPI1_MEM_C_FCMD_QUAD_V << SPI1_MEM_C_FCMD_QUAD_S)
+#define SPI1_MEM_C_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FCMD_QUAD_S  8
+/** SPI1_MEM_C_FCMD_OCT : HRO; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
+#define SPI1_MEM_C_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_C_FCMD_OCT_M  (SPI1_MEM_C_FCMD_OCT_V << SPI1_MEM_C_FCMD_OCT_S)
+#define SPI1_MEM_C_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_C_FCMD_OCT_S  9
+/** SPI1_MEM_C_FCS_CRC_EN : HRO; bitpos: [10]; default: 0;
  *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
  *  low.
  */
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S)
-#define SPI_MEM_FCS_CRC_EN_V  0x00000001U
-#define SPI_MEM_FCS_CRC_EN_S  10
-/** SPI_MEM_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
+#define SPI1_MEM_C_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_C_FCS_CRC_EN_M  (SPI1_MEM_C_FCS_CRC_EN_V << SPI1_MEM_C_FCS_CRC_EN_S)
+#define SPI1_MEM_C_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_FCS_CRC_EN_S  10
+/** SPI1_MEM_C_TX_CRC_EN : HRO; bitpos: [11]; default: 0;
  *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
  */
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S)
-#define SPI_MEM_TX_CRC_EN_V  0x00000001U
-#define SPI_MEM_TX_CRC_EN_S  11
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
- *  and spi_mem_fread_dout. 1: enable 0: disable.
- */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_C_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_C_TX_CRC_EN_M  (SPI1_MEM_C_TX_CRC_EN_V << SPI1_MEM_C_TX_CRC_EN_S)
+#define SPI1_MEM_C_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_C_TX_CRC_EN_S  11
+/** SPI1_MEM_C_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+ *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_C_FASTRD_MODE_M  (SPI1_MEM_C_FASTRD_MODE_V << SPI1_MEM_C_FASTRD_MODE_S)
+#define SPI1_MEM_C_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_C_FASTRD_MODE_S  13
+/** SPI1_MEM_C_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1;
- *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
- *  spi_mem_flash_res bit. 1: enable 0: disable.
- */
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S)
-#define SPI_MEM_RESANDRES_V  0x00000001U
-#define SPI_MEM_RESANDRES_S  15
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI1_MEM_C_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_C_FREAD_DUAL_M  (SPI1_MEM_C_FREAD_DUAL_V << SPI1_MEM_C_FREAD_DUAL_S)
+#define SPI1_MEM_C_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DUAL_S  14
+/** SPI1_MEM_C_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+ *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
+ */
+#define SPI1_MEM_C_RESANDRES    (BIT(15))
+#define SPI1_MEM_C_RESANDRES_M  (SPI1_MEM_C_RESANDRES_V << SPI1_MEM_C_RESANDRES_S)
+#define SPI1_MEM_C_RESANDRES_V  0x00000001U
+#define SPI1_MEM_C_RESANDRES_S  15
+/** SPI1_MEM_C_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI1_MEM_C_Q_POL    (BIT(18))
+#define SPI1_MEM_C_Q_POL_M  (SPI1_MEM_C_Q_POL_V << SPI1_MEM_C_Q_POL_S)
+#define SPI1_MEM_C_Q_POL_V  0x00000001U
+#define SPI1_MEM_C_Q_POL_S  18
+/** SPI1_MEM_C_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI1_MEM_C_D_POL    (BIT(19))
+#define SPI1_MEM_C_D_POL_M  (SPI1_MEM_C_D_POL_V << SPI1_MEM_C_D_POL_S)
+#define SPI1_MEM_C_D_POL_V  0x00000001U
+#define SPI1_MEM_C_D_POL_S  19
+/** SPI1_MEM_C_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI1_MEM_C_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_C_FREAD_QUAD_M  (SPI1_MEM_C_FREAD_QUAD_V << SPI1_MEM_C_FREAD_QUAD_S)
+#define SPI1_MEM_C_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QUAD_S  20
+/** SPI1_MEM_C_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_WP_REG    (BIT(21))
+#define SPI1_MEM_C_WP_REG_M  (SPI1_MEM_C_WP_REG_V << SPI1_MEM_C_WP_REG_S)
+#define SPI1_MEM_C_WP_REG_V  0x00000001U
+#define SPI1_MEM_C_WP_REG_S  21
+/** SPI1_MEM_C_WRSR_2B : R/W; bitpos: [22]; default: 0;
  *  two bytes data will be written to status register when it is set. 1: enable 0:
  *  disable.
  */
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S)
-#define SPI_MEM_WRSR_2B_V  0x00000001U
-#define SPI_MEM_WRSR_2B_S  22
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_WRSR_2B    (BIT(22))
+#define SPI1_MEM_C_WRSR_2B_M  (SPI1_MEM_C_WRSR_2B_V << SPI1_MEM_C_WRSR_2B_S)
+#define SPI1_MEM_C_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_C_WRSR_2B_S  22
+/** SPI1_MEM_C_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_C_FREAD_DIO_M  (SPI1_MEM_C_FREAD_DIO_V << SPI1_MEM_C_FREAD_DIO_S)
+#define SPI1_MEM_C_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_DIO_S  23
+/** SPI1_MEM_C_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
+#define SPI1_MEM_C_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_C_FREAD_QIO_M  (SPI1_MEM_C_FREAD_QIO_V << SPI1_MEM_C_FREAD_QIO_S)
+#define SPI1_MEM_C_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_C_FREAD_QIO_S  24
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI1_MEM_C_CTRL1_REG register
  *  SPI1 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_SPI1_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI1_MEM_C_CTRL1_REG (DR_REG_FLASH_SPI1_BASE + 0xc)
+/** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
- *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+#define SPI1_MEM_C_CLK_MODE    0x00000003U
+#define SPI1_MEM_C_CLK_MODE_M  (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S)
+#define SPI1_MEM_C_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_C_CLK_MODE_S  0
+/** SPI1_MEM_C_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
  *  SPI_CLK cycles.
  */
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_M  (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+#define SPI1_MEM_C_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_M  (SPI1_MEM_C_CS_HOLD_DLY_RES_V << SPI1_MEM_C_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_C_CS_HOLD_DLY_RES_S  2
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI1_MEM_C_CTRL2_REG register
  *  SPI1 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_SPI1_BASE + 0x10)
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_CTRL2_REG (DR_REG_FLASH_SPI1_BASE + 0x10)
+/** SPI1_MEM_C_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The FSM will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI1_MEM_C_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_C_SYNC_RESET_M  (SPI1_MEM_C_SYNC_RESET_V << SPI1_MEM_C_SYNC_RESET_S)
+#define SPI1_MEM_C_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_C_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI1_MEM_C_CLOCK_REG register
  *  SPI1 clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_SPI1_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
- */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
- */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
- */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI1_MEM_C_CLOCK_REG (DR_REG_FLASH_SPI1_BASE + 0x14)
+/** SPI1_MEM_C_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
+ */
+#define SPI1_MEM_C_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_M  (SPI1_MEM_C_CLKCNT_L_V << SPI1_MEM_C_CLKCNT_L_S)
+#define SPI1_MEM_C_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_L_S  0
+/** SPI1_MEM_C_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
+ */
+#define SPI1_MEM_C_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_M  (SPI1_MEM_C_CLKCNT_H_V << SPI1_MEM_C_CLKCNT_H_S)
+#define SPI1_MEM_C_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_H_S  8
+/** SPI1_MEM_C_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+ *  system/(spi1_mem_c_clkcnt_N+1)
+ */
+#define SPI1_MEM_C_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_M  (SPI1_MEM_C_CLKCNT_N_V << SPI1_MEM_C_CLKCNT_N_S)
+#define SPI1_MEM_C_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_C_CLKCNT_N_S  16
+/** SPI1_MEM_C_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  reserved
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI1_MEM_C_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_M  (SPI1_MEM_C_CLK_EQU_SYSCLK_V << SPI1_MEM_C_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_C_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI1_MEM_C_USER_REG register
  *  SPI1 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_SPI1_BASE + 0x18)
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+#define SPI1_MEM_C_USER_REG (DR_REG_FLASH_SPI1_BASE + 0x18)
+/** SPI1_MEM_C_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+#define SPI1_MEM_C_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_OUT_EDGE_M  (SPI1_MEM_C_CK_OUT_EDGE_V << SPI1_MEM_C_CK_OUT_EDGE_S)
+#define SPI1_MEM_C_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_OUT_EDGE_S  9
+/** SPI1_MEM_C_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
  *  In the write operations read-data phase apply 2 signals
  */
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (SPI_MEM_FWRITE_DUAL_V << SPI_MEM_FWRITE_DUAL_S)
-#define SPI_MEM_FWRITE_DUAL_V  0x00000001U
-#define SPI_MEM_FWRITE_DUAL_S  12
-/** SPI_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+#define SPI1_MEM_C_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_C_FWRITE_DUAL_M  (SPI1_MEM_C_FWRITE_DUAL_V << SPI1_MEM_C_FWRITE_DUAL_S)
+#define SPI1_MEM_C_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DUAL_S  12
+/** SPI1_MEM_C_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
  *  In the write operations read-data phase apply 4 signals
  */
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (SPI_MEM_FWRITE_QUAD_V << SPI_MEM_FWRITE_QUAD_S)
-#define SPI_MEM_FWRITE_QUAD_V  0x00000001U
-#define SPI_MEM_FWRITE_QUAD_S  13
-/** SPI_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_C_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_C_FWRITE_QUAD_M  (SPI1_MEM_C_FWRITE_QUAD_V << SPI1_MEM_C_FWRITE_QUAD_S)
+#define SPI1_MEM_C_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QUAD_S  13
+/** SPI1_MEM_C_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
  *  In the write operations address phase and read-data phase apply 2 signals.
  */
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (SPI_MEM_FWRITE_DIO_V << SPI_MEM_FWRITE_DIO_S)
-#define SPI_MEM_FWRITE_DIO_V  0x00000001U
-#define SPI_MEM_FWRITE_DIO_S  14
-/** SPI_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_C_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_C_FWRITE_DIO_M  (SPI1_MEM_C_FWRITE_DIO_V << SPI1_MEM_C_FWRITE_DIO_S)
+#define SPI1_MEM_C_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_DIO_S  14
+/** SPI1_MEM_C_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
  *  In the write operations address phase and read-data phase apply 4 signals.
  */
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (SPI_MEM_FWRITE_QIO_V << SPI_MEM_FWRITE_QIO_S)
-#define SPI_MEM_FWRITE_QIO_V  0x00000001U
-#define SPI_MEM_FWRITE_QIO_S  15
-/** SPI_MEM_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_C_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_C_FWRITE_QIO_M  (SPI1_MEM_C_FWRITE_QIO_V << SPI1_MEM_C_FWRITE_QIO_S)
+#define SPI1_MEM_C_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_C_FWRITE_QIO_S  15
+/** SPI1_MEM_C_USR_MISO_HIGHPART : HRO; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (SPI_MEM_USR_MISO_HIGHPART_V << SPI_MEM_USR_MISO_HIGHPART_S)
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/** SPI_MEM_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_C_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_C_USR_MISO_HIGHPART_M  (SPI1_MEM_C_USR_MISO_HIGHPART_V << SPI1_MEM_C_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_C_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_C_USR_MOSI_HIGHPART : HRO; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (SPI_MEM_USR_MOSI_HIGHPART_V << SPI_MEM_USR_MOSI_HIGHPART_S)
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_M  (SPI1_MEM_C_USR_MOSI_HIGHPART_V << SPI1_MEM_C_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_C_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  SPI clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_C_USR_DUMMY_IDLE_M  (SPI1_MEM_C_USR_DUMMY_IDLE_V << SPI1_MEM_C_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_C_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_C_USR_MOSI : R/W; bitpos: [27]; default: 0;
  *  This bit enable the write-data phase of an operation.
  */
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (SPI_MEM_USR_MOSI_V << SPI_MEM_USR_MOSI_S)
-#define SPI_MEM_USR_MOSI_V  0x00000001U
-#define SPI_MEM_USR_MOSI_S  27
-/** SPI_MEM_USR_MISO : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_USR_MOSI    (BIT(27))
+#define SPI1_MEM_C_USR_MOSI_M  (SPI1_MEM_C_USR_MOSI_V << SPI1_MEM_C_USR_MOSI_S)
+#define SPI1_MEM_C_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_C_USR_MOSI_S  27
+/** SPI1_MEM_C_USR_MISO : R/W; bitpos: [28]; default: 0;
  *  This bit enable the read-data phase of an operation.
  */
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (SPI_MEM_USR_MISO_V << SPI_MEM_USR_MISO_S)
-#define SPI_MEM_USR_MISO_V  0x00000001U
-#define SPI_MEM_USR_MISO_S  28
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_USR_MISO    (BIT(28))
+#define SPI1_MEM_C_USR_MISO_M  (SPI1_MEM_C_USR_MISO_V << SPI1_MEM_C_USR_MISO_S)
+#define SPI1_MEM_C_USR_MISO_V  0x00000001U
+#define SPI1_MEM_C_USR_MISO_S  28
+/** SPI1_MEM_C_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
-/** SPI_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_C_USR_DUMMY_M  (SPI1_MEM_C_USR_DUMMY_V << SPI1_MEM_C_USR_DUMMY_S)
+#define SPI1_MEM_C_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_USR_DUMMY_S  29
+/** SPI1_MEM_C_USR_ADDR : R/W; bitpos: [30]; default: 0;
  *  This bit enable the address phase of an operation.
  */
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (SPI_MEM_USR_ADDR_V << SPI_MEM_USR_ADDR_S)
-#define SPI_MEM_USR_ADDR_V  0x00000001U
-#define SPI_MEM_USR_ADDR_S  30
-/** SPI_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+#define SPI1_MEM_C_USR_ADDR    (BIT(30))
+#define SPI1_MEM_C_USR_ADDR_M  (SPI1_MEM_C_USR_ADDR_V << SPI1_MEM_C_USR_ADDR_S)
+#define SPI1_MEM_C_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_C_USR_ADDR_S  30
+/** SPI1_MEM_C_USR_COMMAND : R/W; bitpos: [31]; default: 1;
  *  This bit enable the command phase of an operation.
  */
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (SPI_MEM_USR_COMMAND_V << SPI_MEM_USR_COMMAND_S)
-#define SPI_MEM_USR_COMMAND_V  0x00000001U
-#define SPI_MEM_USR_COMMAND_S  31
+#define SPI1_MEM_C_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_C_USR_COMMAND_M  (SPI1_MEM_C_USR_COMMAND_V << SPI1_MEM_C_USR_COMMAND_S)
+#define SPI1_MEM_C_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_C_USR_COMMAND_S  31
 
-/** SPI_MEM_USER1_REG register
+/** SPI1_MEM_C_USER1_REG register
  *  SPI1 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_SPI1_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+#define SPI1_MEM_C_USER1_REG (DR_REG_FLASH_SPI1_BASE + 0x1c)
+/** SPI1_MEM_C_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_C_USR_DUMMY_CYCLELEN_V << SPI1_MEM_C_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_C_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI1_MEM_C_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_M  (SPI1_MEM_C_USR_ADDR_BITLEN_V << SPI1_MEM_C_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_C_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_C_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI1_MEM_C_USER2_REG register
  *  SPI1 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_SPI1_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI1_MEM_C_USER2_REG (DR_REG_FLASH_SPI1_BASE + 0x20)
+/** SPI1_MEM_C_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI1_MEM_C_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_M  (SPI1_MEM_C_USR_COMMAND_VALUE_V << SPI1_MEM_C_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_C_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_C_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_C_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI1_MEM_C_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_M  (SPI1_MEM_C_USR_COMMAND_BITLEN_V << SPI1_MEM_C_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_C_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MOSI_DLEN_REG register
+/** SPI1_MEM_C_MOSI_DLEN_REG register
  *  SPI1 send data bit length control register.
  */
-#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI1_BASE + 0x24)
-/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_C_MOSI_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x24)
+/** SPI1_MEM_C_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of write-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_M  (SPI_MEM_USR_MOSI_DBITLEN_V << SPI_MEM_USR_MOSI_DBITLEN_S)
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+#define SPI1_MEM_C_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_M  (SPI1_MEM_C_USR_MOSI_DBITLEN_V << SPI1_MEM_C_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MOSI_DBITLEN_S  0
 
-/** SPI_MEM_MISO_DLEN_REG register
+/** SPI1_MEM_C_MISO_DLEN_REG register
  *  SPI1 receive data bit length control register.
  */
-#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI1_BASE + 0x28)
-/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_C_MISO_DLEN_REG (DR_REG_FLASH_SPI1_BASE + 0x28)
+/** SPI1_MEM_C_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of  read-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_M  (SPI_MEM_USR_MISO_DBITLEN_V << SPI_MEM_USR_MISO_DBITLEN_S)
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
+#define SPI1_MEM_C_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_M  (SPI1_MEM_C_USR_MISO_DBITLEN_V << SPI1_MEM_C_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_C_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_C_USR_MISO_DBITLEN_S  0
 
-/** SPI_MEM_RD_STATUS_REG register
+/** SPI1_MEM_C_RD_STATUS_REG register
  *  SPI1 status register.
  */
-#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI1_BASE + 0x2c)
-/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
- *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
- */
-#define SPI_MEM_STATUS    0x0000FFFFU
-#define SPI_MEM_STATUS_M  (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
-#define SPI_MEM_STATUS_V  0x0000FFFFU
-#define SPI_MEM_STATUS_S  0
-/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
- *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
- */
-#define SPI_MEM_WB_MODE    0x000000FFU
-#define SPI_MEM_WB_MODE_M  (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
-#define SPI_MEM_WB_MODE_V  0x000000FFU
-#define SPI_MEM_WB_MODE_S  16
+#define SPI1_MEM_C_RD_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0x2c)
+/** SPI1_MEM_C_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
+ */
+#define SPI1_MEM_C_STATUS    0x0000FFFFU
+#define SPI1_MEM_C_STATUS_M  (SPI1_MEM_C_STATUS_V << SPI1_MEM_C_STATUS_S)
+#define SPI1_MEM_C_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_C_STATUS_S  0
+/** SPI1_MEM_C_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
+ */
+#define SPI1_MEM_C_WB_MODE    0x000000FFU
+#define SPI1_MEM_C_WB_MODE_M  (SPI1_MEM_C_WB_MODE_V << SPI1_MEM_C_WB_MODE_S)
+#define SPI1_MEM_C_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_C_WB_MODE_S  16
 
-/** SPI_MEM_MISC_REG register
+/** SPI1_MEM_C_MISC_REG register
  *  SPI1 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_SPI1_BASE + 0x34)
-/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_MISC_REG (DR_REG_FLASH_SPI1_BASE + 0x34)
+/** SPI1_MEM_C_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (SPI_MEM_CS0_DIS_V << SPI_MEM_CS0_DIS_S)
-#define SPI_MEM_CS0_DIS_V  0x00000001U
-#define SPI_MEM_CS0_DIS_S  0
-/** SPI_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1;
+#define SPI1_MEM_C_CS0_DIS    (BIT(0))
+#define SPI1_MEM_C_CS0_DIS_M  (SPI1_MEM_C_CS0_DIS_V << SPI1_MEM_C_CS0_DIS_S)
+#define SPI1_MEM_C_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS0_DIS_S  0
+/** SPI1_MEM_C_CS1_DIS : R/W; bitpos: [1]; default: 1;
  *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (SPI_MEM_CS1_DIS_V << SPI_MEM_CS1_DIS_S)
-#define SPI_MEM_CS1_DIS_V  0x00000001U
-#define SPI_MEM_CS1_DIS_S  1
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_CS1_DIS    (BIT(1))
+#define SPI1_MEM_C_CS1_DIS_M  (SPI1_MEM_C_CS1_DIS_V << SPI1_MEM_C_CS1_DIS_S)
+#define SPI1_MEM_C_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_C_CS1_DIS_S  1
+/** SPI1_MEM_C_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: spi clk line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_C_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_C_CK_IDLE_EDGE_M  (SPI1_MEM_C_CK_IDLE_EDGE_V << SPI1_MEM_C_CK_IDLE_EDGE_S)
+#define SPI1_MEM_C_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_C_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_C_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  spi cs line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI1_MEM_C_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_M  (SPI1_MEM_C_CS_KEEP_ACTIVE_V << SPI1_MEM_C_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_C_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_TX_CRC_REG register
+/** SPI1_MEM_C_TX_CRC_REG register
  *  SPI1 TX CRC data register.
  */
-#define SPI_MEM_TX_CRC_REG (DR_REG_SPI1_BASE + 0x38)
-/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+#define SPI1_MEM_C_TX_CRC_REG (DR_REG_FLASH_SPI1_BASE + 0x38)
+/** SPI1_MEM_C_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
  *  For SPI1, the value of crc32.
  */
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_M  (SPI_MEM_TX_CRC_DATA_V << SPI_MEM_TX_CRC_DATA_S)
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_S  0
+#define SPI1_MEM_C_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_M  (SPI1_MEM_C_TX_CRC_DATA_V << SPI1_MEM_C_TX_CRC_DATA_S)
+#define SPI1_MEM_C_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_C_TX_CRC_DATA_S  0
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI1_MEM_C_CACHE_FCTRL_REG register
  *  SPI1 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI1_BASE + 0x3c)
-/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_CACHE_FCTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x3c)
+/** SPI1_MEM_C_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
  *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
  */
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S)
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x00000001U
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_C_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_C_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
  *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
- *  spi_mem_fread_dio.
+ *  spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S)
-#define SPI_MEM_FDIN_DUAL_V  0x00000001U
-#define SPI_MEM_FDIN_DUAL_S  3
-/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_C_FDIN_DUAL_M  (SPI1_MEM_C_FDIN_DUAL_V << SPI1_MEM_C_FDIN_DUAL_S)
+#define SPI1_MEM_C_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDIN_DUAL_S  3
+/** SPI1_MEM_C_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
  *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S)
-#define SPI_MEM_FDOUT_DUAL_V  0x00000001U
-#define SPI_MEM_FDOUT_DUAL_S  4
-/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_C_FDOUT_DUAL_M  (SPI1_MEM_C_FDOUT_DUAL_V << SPI1_MEM_C_FDOUT_DUAL_S)
+#define SPI1_MEM_C_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_DUAL_S  4
+/** SPI1_MEM_C_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
  *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_c_fread_dio.
  */
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S)
-#define SPI_MEM_FADDR_DUAL_V  0x00000001U
-#define SPI_MEM_FADDR_DUAL_S  5
-/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_C_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_C_FADDR_DUAL_M  (SPI1_MEM_C_FADDR_DUAL_V << SPI1_MEM_C_FADDR_DUAL_S)
+#define SPI1_MEM_C_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_C_FADDR_DUAL_S  5
+/** SPI1_MEM_C_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
  *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S)
-#define SPI_MEM_FDIN_QUAD_V  0x00000001U
-#define SPI_MEM_FDIN_QUAD_S  6
-/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_C_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_C_FDIN_QUAD_M  (SPI1_MEM_C_FDIN_QUAD_V << SPI1_MEM_C_FDIN_QUAD_S)
+#define SPI1_MEM_C_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDIN_QUAD_S  6
+/** SPI1_MEM_C_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
  *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S)
-#define SPI_MEM_FDOUT_QUAD_V  0x00000001U
-#define SPI_MEM_FDOUT_QUAD_S  7
-/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_C_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_C_FDOUT_QUAD_M  (SPI1_MEM_C_FDOUT_QUAD_V << SPI1_MEM_C_FDOUT_QUAD_S)
+#define SPI1_MEM_C_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FDOUT_QUAD_S  7
+/** SPI1_MEM_C_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
  *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_c_fread_qio.
  */
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S)
-#define SPI_MEM_FADDR_QUAD_V  0x00000001U
-#define SPI_MEM_FADDR_QUAD_S  8
+#define SPI1_MEM_C_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_C_FADDR_QUAD_M  (SPI1_MEM_C_FADDR_QUAD_V << SPI1_MEM_C_FADDR_QUAD_S)
+#define SPI1_MEM_C_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_C_FADDR_QUAD_S  8
 
-/** SPI_MEM_W0_REG register
+/** SPI1_MEM_C_W0_REG register
  *  SPI1 memory data buffer0
  */
-#define SPI_MEM_W0_REG (DR_REG_SPI1_BASE + 0x58)
-/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W0_REG (DR_REG_FLASH_SPI1_BASE + 0x58)
+/** SPI1_MEM_C_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF0    0xFFFFFFFFU
-#define SPI_MEM_BUF0_M  (SPI_MEM_BUF0_V << SPI_MEM_BUF0_S)
-#define SPI_MEM_BUF0_V  0xFFFFFFFFU
-#define SPI_MEM_BUF0_S  0
+#define SPI1_MEM_C_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_M  (SPI1_MEM_C_BUF0_V << SPI1_MEM_C_BUF0_S)
+#define SPI1_MEM_C_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF0_S  0
 
-/** SPI_MEM_W1_REG register
+/** SPI1_MEM_C_W1_REG register
  *  SPI1 memory data buffer1
  */
-#define SPI_MEM_W1_REG (DR_REG_SPI1_BASE + 0x5c)
-/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W1_REG (DR_REG_FLASH_SPI1_BASE + 0x5c)
+/** SPI1_MEM_C_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF1    0xFFFFFFFFU
-#define SPI_MEM_BUF1_M  (SPI_MEM_BUF1_V << SPI_MEM_BUF1_S)
-#define SPI_MEM_BUF1_V  0xFFFFFFFFU
-#define SPI_MEM_BUF1_S  0
+#define SPI1_MEM_C_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_M  (SPI1_MEM_C_BUF1_V << SPI1_MEM_C_BUF1_S)
+#define SPI1_MEM_C_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF1_S  0
 
-/** SPI_MEM_W2_REG register
+/** SPI1_MEM_C_W2_REG register
  *  SPI1 memory data buffer2
  */
-#define SPI_MEM_W2_REG (DR_REG_SPI1_BASE + 0x60)
-/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W2_REG (DR_REG_FLASH_SPI1_BASE + 0x60)
+/** SPI1_MEM_C_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF2    0xFFFFFFFFU
-#define SPI_MEM_BUF2_M  (SPI_MEM_BUF2_V << SPI_MEM_BUF2_S)
-#define SPI_MEM_BUF2_V  0xFFFFFFFFU
-#define SPI_MEM_BUF2_S  0
+#define SPI1_MEM_C_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_M  (SPI1_MEM_C_BUF2_V << SPI1_MEM_C_BUF2_S)
+#define SPI1_MEM_C_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF2_S  0
 
-/** SPI_MEM_W3_REG register
+/** SPI1_MEM_C_W3_REG register
  *  SPI1 memory data buffer3
  */
-#define SPI_MEM_W3_REG (DR_REG_SPI1_BASE + 0x64)
-/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W3_REG (DR_REG_FLASH_SPI1_BASE + 0x64)
+/** SPI1_MEM_C_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF3    0xFFFFFFFFU
-#define SPI_MEM_BUF3_M  (SPI_MEM_BUF3_V << SPI_MEM_BUF3_S)
-#define SPI_MEM_BUF3_V  0xFFFFFFFFU
-#define SPI_MEM_BUF3_S  0
+#define SPI1_MEM_C_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_M  (SPI1_MEM_C_BUF3_V << SPI1_MEM_C_BUF3_S)
+#define SPI1_MEM_C_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF3_S  0
 
-/** SPI_MEM_W4_REG register
+/** SPI1_MEM_C_W4_REG register
  *  SPI1 memory data buffer4
  */
-#define SPI_MEM_W4_REG (DR_REG_SPI1_BASE + 0x68)
-/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W4_REG (DR_REG_FLASH_SPI1_BASE + 0x68)
+/** SPI1_MEM_C_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF4    0xFFFFFFFFU
-#define SPI_MEM_BUF4_M  (SPI_MEM_BUF4_V << SPI_MEM_BUF4_S)
-#define SPI_MEM_BUF4_V  0xFFFFFFFFU
-#define SPI_MEM_BUF4_S  0
+#define SPI1_MEM_C_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_M  (SPI1_MEM_C_BUF4_V << SPI1_MEM_C_BUF4_S)
+#define SPI1_MEM_C_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF4_S  0
 
-/** SPI_MEM_W5_REG register
+/** SPI1_MEM_C_W5_REG register
  *  SPI1 memory data buffer5
  */
-#define SPI_MEM_W5_REG (DR_REG_SPI1_BASE + 0x6c)
-/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W5_REG (DR_REG_FLASH_SPI1_BASE + 0x6c)
+/** SPI1_MEM_C_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF5    0xFFFFFFFFU
-#define SPI_MEM_BUF5_M  (SPI_MEM_BUF5_V << SPI_MEM_BUF5_S)
-#define SPI_MEM_BUF5_V  0xFFFFFFFFU
-#define SPI_MEM_BUF5_S  0
+#define SPI1_MEM_C_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_M  (SPI1_MEM_C_BUF5_V << SPI1_MEM_C_BUF5_S)
+#define SPI1_MEM_C_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF5_S  0
 
-/** SPI_MEM_W6_REG register
+/** SPI1_MEM_C_W6_REG register
  *  SPI1 memory data buffer6
  */
-#define SPI_MEM_W6_REG (DR_REG_SPI1_BASE + 0x70)
-/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W6_REG (DR_REG_FLASH_SPI1_BASE + 0x70)
+/** SPI1_MEM_C_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF6    0xFFFFFFFFU
-#define SPI_MEM_BUF6_M  (SPI_MEM_BUF6_V << SPI_MEM_BUF6_S)
-#define SPI_MEM_BUF6_V  0xFFFFFFFFU
-#define SPI_MEM_BUF6_S  0
+#define SPI1_MEM_C_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_M  (SPI1_MEM_C_BUF6_V << SPI1_MEM_C_BUF6_S)
+#define SPI1_MEM_C_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF6_S  0
 
-/** SPI_MEM_W7_REG register
+/** SPI1_MEM_C_W7_REG register
  *  SPI1 memory data buffer7
  */
-#define SPI_MEM_W7_REG (DR_REG_SPI1_BASE + 0x74)
-/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W7_REG (DR_REG_FLASH_SPI1_BASE + 0x74)
+/** SPI1_MEM_C_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF7    0xFFFFFFFFU
-#define SPI_MEM_BUF7_M  (SPI_MEM_BUF7_V << SPI_MEM_BUF7_S)
-#define SPI_MEM_BUF7_V  0xFFFFFFFFU
-#define SPI_MEM_BUF7_S  0
+#define SPI1_MEM_C_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_M  (SPI1_MEM_C_BUF7_V << SPI1_MEM_C_BUF7_S)
+#define SPI1_MEM_C_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF7_S  0
 
-/** SPI_MEM_W8_REG register
+/** SPI1_MEM_C_W8_REG register
  *  SPI1 memory data buffer8
  */
-#define SPI_MEM_W8_REG (DR_REG_SPI1_BASE + 0x78)
-/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W8_REG (DR_REG_FLASH_SPI1_BASE + 0x78)
+/** SPI1_MEM_C_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF8    0xFFFFFFFFU
-#define SPI_MEM_BUF8_M  (SPI_MEM_BUF8_V << SPI_MEM_BUF8_S)
-#define SPI_MEM_BUF8_V  0xFFFFFFFFU
-#define SPI_MEM_BUF8_S  0
+#define SPI1_MEM_C_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_M  (SPI1_MEM_C_BUF8_V << SPI1_MEM_C_BUF8_S)
+#define SPI1_MEM_C_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF8_S  0
 
-/** SPI_MEM_W9_REG register
+/** SPI1_MEM_C_W9_REG register
  *  SPI1 memory data buffer9
  */
-#define SPI_MEM_W9_REG (DR_REG_SPI1_BASE + 0x7c)
-/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W9_REG (DR_REG_FLASH_SPI1_BASE + 0x7c)
+/** SPI1_MEM_C_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF9    0xFFFFFFFFU
-#define SPI_MEM_BUF9_M  (SPI_MEM_BUF9_V << SPI_MEM_BUF9_S)
-#define SPI_MEM_BUF9_V  0xFFFFFFFFU
-#define SPI_MEM_BUF9_S  0
+#define SPI1_MEM_C_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_M  (SPI1_MEM_C_BUF9_V << SPI1_MEM_C_BUF9_S)
+#define SPI1_MEM_C_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF9_S  0
 
-/** SPI_MEM_W10_REG register
+/** SPI1_MEM_C_W10_REG register
  *  SPI1 memory data buffer10
  */
-#define SPI_MEM_W10_REG (DR_REG_SPI1_BASE + 0x80)
-/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W10_REG (DR_REG_FLASH_SPI1_BASE + 0x80)
+/** SPI1_MEM_C_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF10    0xFFFFFFFFU
-#define SPI_MEM_BUF10_M  (SPI_MEM_BUF10_V << SPI_MEM_BUF10_S)
-#define SPI_MEM_BUF10_V  0xFFFFFFFFU
-#define SPI_MEM_BUF10_S  0
+#define SPI1_MEM_C_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_M  (SPI1_MEM_C_BUF10_V << SPI1_MEM_C_BUF10_S)
+#define SPI1_MEM_C_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF10_S  0
 
-/** SPI_MEM_W11_REG register
+/** SPI1_MEM_C_W11_REG register
  *  SPI1 memory data buffer11
  */
-#define SPI_MEM_W11_REG (DR_REG_SPI1_BASE + 0x84)
-/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W11_REG (DR_REG_FLASH_SPI1_BASE + 0x84)
+/** SPI1_MEM_C_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF11    0xFFFFFFFFU
-#define SPI_MEM_BUF11_M  (SPI_MEM_BUF11_V << SPI_MEM_BUF11_S)
-#define SPI_MEM_BUF11_V  0xFFFFFFFFU
-#define SPI_MEM_BUF11_S  0
+#define SPI1_MEM_C_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_M  (SPI1_MEM_C_BUF11_V << SPI1_MEM_C_BUF11_S)
+#define SPI1_MEM_C_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF11_S  0
 
-/** SPI_MEM_W12_REG register
+/** SPI1_MEM_C_W12_REG register
  *  SPI1 memory data buffer12
  */
-#define SPI_MEM_W12_REG (DR_REG_SPI1_BASE + 0x88)
-/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W12_REG (DR_REG_FLASH_SPI1_BASE + 0x88)
+/** SPI1_MEM_C_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF12    0xFFFFFFFFU
-#define SPI_MEM_BUF12_M  (SPI_MEM_BUF12_V << SPI_MEM_BUF12_S)
-#define SPI_MEM_BUF12_V  0xFFFFFFFFU
-#define SPI_MEM_BUF12_S  0
+#define SPI1_MEM_C_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_M  (SPI1_MEM_C_BUF12_V << SPI1_MEM_C_BUF12_S)
+#define SPI1_MEM_C_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF12_S  0
 
-/** SPI_MEM_W13_REG register
+/** SPI1_MEM_C_W13_REG register
  *  SPI1 memory data buffer13
  */
-#define SPI_MEM_W13_REG (DR_REG_SPI1_BASE + 0x8c)
-/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W13_REG (DR_REG_FLASH_SPI1_BASE + 0x8c)
+/** SPI1_MEM_C_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF13    0xFFFFFFFFU
-#define SPI_MEM_BUF13_M  (SPI_MEM_BUF13_V << SPI_MEM_BUF13_S)
-#define SPI_MEM_BUF13_V  0xFFFFFFFFU
-#define SPI_MEM_BUF13_S  0
+#define SPI1_MEM_C_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_M  (SPI1_MEM_C_BUF13_V << SPI1_MEM_C_BUF13_S)
+#define SPI1_MEM_C_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF13_S  0
 
-/** SPI_MEM_W14_REG register
+/** SPI1_MEM_C_W14_REG register
  *  SPI1 memory data buffer14
  */
-#define SPI_MEM_W14_REG (DR_REG_SPI1_BASE + 0x90)
-/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W14_REG (DR_REG_FLASH_SPI1_BASE + 0x90)
+/** SPI1_MEM_C_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF14    0xFFFFFFFFU
-#define SPI_MEM_BUF14_M  (SPI_MEM_BUF14_V << SPI_MEM_BUF14_S)
-#define SPI_MEM_BUF14_V  0xFFFFFFFFU
-#define SPI_MEM_BUF14_S  0
+#define SPI1_MEM_C_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_M  (SPI1_MEM_C_BUF14_V << SPI1_MEM_C_BUF14_S)
+#define SPI1_MEM_C_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF14_S  0
 
-/** SPI_MEM_W15_REG register
+/** SPI1_MEM_C_W15_REG register
  *  SPI1 memory data buffer15
  */
-#define SPI_MEM_W15_REG (DR_REG_SPI1_BASE + 0x94)
-/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_C_W15_REG (DR_REG_FLASH_SPI1_BASE + 0x94)
+/** SPI1_MEM_C_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF15    0xFFFFFFFFU
-#define SPI_MEM_BUF15_M  (SPI_MEM_BUF15_V << SPI_MEM_BUF15_S)
-#define SPI_MEM_BUF15_V  0xFFFFFFFFU
-#define SPI_MEM_BUF15_S  0
+#define SPI1_MEM_C_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_M  (SPI1_MEM_C_BUF15_V << SPI1_MEM_C_BUF15_S)
+#define SPI1_MEM_C_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_C_BUF15_S  0
 
-/** SPI_MEM_FLASH_WAITI_CTRL_REG register
+/** SPI1_MEM_C_FLASH_WAITI_CTRL_REG register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI1_BASE + 0x98)
-/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_C_FLASH_WAITI_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x98)
+/** SPI1_MEM_C_WAITI_EN : R/W; bitpos: [0]; default: 1;
  *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
  *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
  *  Suspend/Resume are not supported.
  */
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (SPI_MEM_WAITI_EN_V << SPI_MEM_WAITI_EN_S)
-#define SPI_MEM_WAITI_EN_V  0x00000001U
-#define SPI_MEM_WAITI_EN_S  0
-/** SPI_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_WAITI_EN    (BIT(0))
+#define SPI1_MEM_C_WAITI_EN_M  (SPI1_MEM_C_WAITI_EN_V << SPI1_MEM_C_WAITI_EN_S)
+#define SPI1_MEM_C_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_EN_S  0
+/** SPI1_MEM_C_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
  *  The dummy phase enable when wait flash idle (RDSR)
  */
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (SPI_MEM_WAITI_DUMMY_V << SPI_MEM_WAITI_DUMMY_S)
-#define SPI_MEM_WAITI_DUMMY_V  0x00000001U
-#define SPI_MEM_WAITI_DUMMY_S  1
-/** SPI_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_C_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_C_WAITI_DUMMY_M  (SPI1_MEM_C_WAITI_DUMMY_V << SPI1_MEM_C_WAITI_DUMMY_S)
+#define SPI1_MEM_C_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_WAITI_DUMMY_S  1
+/** SPI1_MEM_C_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
  *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
  *  address in RDSR or read SUS command transfer.
  */
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (SPI_MEM_WAITI_ADDR_EN_V << SPI_MEM_WAITI_ADDR_EN_S)
-#define SPI_MEM_WAITI_ADDR_EN_V  0x00000001U
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/** SPI_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
- *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
- *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
- *  SPI_MEM_WAITI_ADDR_EN is cleared.
- */
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  (SPI_MEM_WAITI_ADDR_CYCLELEN_V << SPI_MEM_WAITI_ADDR_CYCLELEN_S)
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/** SPI_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_C_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_C_WAITI_ADDR_EN_M  (SPI1_MEM_C_WAITI_ADDR_EN_V << SPI1_MEM_C_WAITI_ADDR_EN_S)
+#define SPI1_MEM_C_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_C_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_C_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
+ */
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_C_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_C_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
  *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  */
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (SPI_MEM_WAITI_CMD_2B_V << SPI_MEM_WAITI_CMD_2B_S)
-#define SPI_MEM_WAITI_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/** SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+#define SPI1_MEM_C_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_C_WAITI_CMD_2B_M  (SPI1_MEM_C_WAITI_CMD_2B_V << SPI1_MEM_C_WAITI_CMD_2B_S)
+#define SPI1_MEM_C_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAITI_CMD_2B_S  9
+/** SPI1_MEM_C_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
  *  The dummy cycle length when wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  (SPI_MEM_WAITI_DUMMY_CYCLELEN_V << SPI_MEM_WAITI_DUMMY_CYCLELEN_S)
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/** SPI_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_C_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_C_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
  *  The command value to wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_CMD    0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_M  (SPI_MEM_WAITI_CMD_V << SPI_MEM_WAITI_CMD_S)
-#define SPI_MEM_WAITI_CMD_V  0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_S  16
+#define SPI1_MEM_C_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_M  (SPI1_MEM_C_WAITI_CMD_V << SPI1_MEM_C_WAITI_CMD_S)
+#define SPI1_MEM_C_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_C_WAITI_CMD_S  16
 
-/** SPI_MEM_FLASH_SUS_CTRL_REG register
+/** SPI1_MEM_C_FLASH_SUS_CTRL_REG register
  *  SPI1 flash suspend control register
  */
-#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI1_BASE + 0x9c)
-/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_FLASH_SUS_CTRL_REG (DR_REG_FLASH_SPI1_BASE + 0x9c)
+/** SPI1_MEM_C_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
  *  program erase resume bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (SPI_MEM_FLASH_PER_V << SPI_MEM_FLASH_PER_S)
-#define SPI_MEM_FLASH_PER_V  0x00000001U
-#define SPI_MEM_FLASH_PER_S  0
-/** SPI_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_FLASH_PER    (BIT(0))
+#define SPI1_MEM_C_FLASH_PER_M  (SPI1_MEM_C_FLASH_PER_V << SPI1_MEM_C_FLASH_PER_S)
+#define SPI1_MEM_C_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_S  0
+/** SPI1_MEM_C_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
  *  program erase suspend bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (SPI_MEM_FLASH_PES_V << SPI_MEM_FLASH_PES_S)
-#define SPI_MEM_FLASH_PES_V  0x00000001U
-#define SPI_MEM_FLASH_PES_S  1
-/** SPI_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_C_FLASH_PES    (BIT(1))
+#define SPI1_MEM_C_FLASH_PES_M  (SPI1_MEM_C_FLASH_PES_V << SPI1_MEM_C_FLASH_PES_S)
+#define SPI1_MEM_C_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_S  1
+/** SPI1_MEM_C_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase resume command is sent. 0: SPI1 does not wait after program erase
  *  resume command is sent.
  */
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (SPI_MEM_FLASH_PER_WAIT_EN_V << SPI_MEM_FLASH_PER_WAIT_EN_S)
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/** SPI_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_M  (SPI1_MEM_C_FLASH_PER_WAIT_EN_V << SPI1_MEM_C_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_C_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
  *  suspend command is sent.
  */
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (SPI_MEM_FLASH_PES_WAIT_EN_V << SPI_MEM_FLASH_PES_WAIT_EN_S)
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/** SPI_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_M  (SPI1_MEM_C_FLASH_PES_WAIT_EN_V << SPI1_MEM_C_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_C_PES_PER_EN : R/W; bitpos: [4]; default: 0;
  *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
  *  application should send PER after PES is done.
  */
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (SPI_MEM_PES_PER_EN_V << SPI_MEM_PES_PER_EN_S)
-#define SPI_MEM_PES_PER_EN_V  0x00000001U
-#define SPI_MEM_PES_PER_EN_S  4
-/** SPI_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_C_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_C_PES_PER_EN_M  (SPI1_MEM_C_PES_PER_EN_V << SPI1_MEM_C_PES_PER_EN_S)
+#define SPI1_MEM_C_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_PER_EN_S  4
+/** SPI1_MEM_C_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable Auto-suspending function.
  */
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (SPI_MEM_FLASH_PES_EN_V << SPI_MEM_FLASH_PES_EN_S)
-#define SPI_MEM_FLASH_PES_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_EN_S  5
-/** SPI_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+#define SPI1_MEM_C_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_C_FLASH_PES_EN_M  (SPI1_MEM_C_FLASH_PES_EN_V << SPI1_MEM_C_FLASH_PES_EN_S)
+#define SPI1_MEM_C_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_EN_S  5
+/** SPI1_MEM_C_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
  *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
  *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
  *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
- *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+ *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
  */
-#define SPI_MEM_PESR_END_MSK    0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_M  (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S)
-#define SPI_MEM_PESR_END_MSK_V  0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_S  6
-/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_C_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_M  (SPI1_MEM_C_PESR_END_MSK_V << SPI1_MEM_C_PESR_END_MSK_S)
+#define SPI1_MEM_C_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_C_PESR_END_MSK_S  6
+/** SPI1_MEM_C_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
  *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
  *  check flash SUS/SUS1/SUS2 status bit
  */
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S)
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x00000001U
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_C_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_M  (SPI1_MEM_C_FMEM_RD_SUS_2B_V << SPI1_MEM_C_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_C_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_C_PER_END_EN : R/W; bitpos: [23]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
  *  flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (SPI_MEM_PER_END_EN_V << SPI_MEM_PER_END_EN_S)
-#define SPI_MEM_PER_END_EN_V  0x00000001U
-#define SPI_MEM_PER_END_EN_S  23
-/** SPI_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_PER_END_EN    (BIT(23))
+#define SPI1_MEM_C_PER_END_EN_M  (SPI1_MEM_C_PER_END_EN_V << SPI1_MEM_C_PER_END_EN_S)
+#define SPI1_MEM_C_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PER_END_EN_S  23
+/** SPI1_MEM_C_PES_END_EN : R/W; bitpos: [24]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
  *  of flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (SPI_MEM_PES_END_EN_V << SPI_MEM_PES_END_EN_S)
-#define SPI_MEM_PES_END_EN_V  0x00000001U
-#define SPI_MEM_PES_END_EN_S  24
-/** SPI_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
- *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+#define SPI1_MEM_C_PES_END_EN    (BIT(24))
+#define SPI1_MEM_C_PES_END_EN_M  (SPI1_MEM_C_PES_END_EN_V << SPI1_MEM_C_PES_END_EN_S)
+#define SPI1_MEM_C_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_C_PES_END_EN_S  24
+/** SPI1_MEM_C_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
  *  will be treated as check pass.
  */
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  (SPI_MEM_SUS_TIMEOUT_CNT_V << SPI_MEM_SUS_TIMEOUT_CNT_S)
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_M  (SPI1_MEM_C_SUS_TIMEOUT_CNT_V << SPI1_MEM_C_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_C_SUS_TIMEOUT_CNT_S  25
 
-/** SPI_MEM_FLASH_SUS_CMD_REG register
+/** SPI1_MEM_C_FLASH_SUS_CMD_REG register
  *  SPI1 flash suspend command register
  */
-#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI1_BASE + 0xa0)
-/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+#define SPI1_MEM_C_FLASH_SUS_CMD_REG (DR_REG_FLASH_SPI1_BASE + 0xa0)
+/** SPI1_MEM_C_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
  *  Program/Erase suspend command.
  */
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_M  (SPI_MEM_FLASH_PES_COMMAND_V << SPI_MEM_FLASH_PES_COMMAND_S)
-#define SPI_MEM_FLASH_PES_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-/** SPI_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_C_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_M  (SPI1_MEM_C_FLASH_PES_COMMAND_V << SPI1_MEM_C_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_C_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
  *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
  *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
  */
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_M  (SPI_MEM_WAIT_PESR_COMMAND_V << SPI_MEM_WAIT_PESR_COMMAND_S)
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+#define SPI1_MEM_C_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_M  (SPI1_MEM_C_WAIT_PESR_COMMAND_V << SPI1_MEM_C_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_WAIT_PESR_COMMAND_S  16
 
-/** SPI_MEM_SUS_STATUS_REG register
+/** SPI1_MEM_C_SUS_STATUS_REG register
  *  SPI1 flash suspend status register
  */
-#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI1_BASE + 0xa4)
-/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_SUS_STATUS_REG (DR_REG_FLASH_SPI1_BASE + 0xa4)
+/** SPI1_MEM_C_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
  *  The status of flash suspend, only used in SPI1.
  */
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (SPI_MEM_FLASH_SUS_V << SPI_MEM_FLASH_SUS_S)
-#define SPI_MEM_FLASH_SUS_V  0x00000001U
-#define SPI_MEM_FLASH_SUS_S  0
-/** SPI_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
- *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
- */
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (SPI_MEM_WAIT_PESR_CMD_2B_V << SPI_MEM_WAIT_PESR_CMD_2B_S)
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/** SPI_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_C_FLASH_SUS_M  (SPI1_MEM_C_FLASH_SUS_V << SPI1_MEM_C_FLASH_SUS_S)
+#define SPI1_MEM_C_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_C_FLASH_SUS_S  0
+/** SPI1_MEM_C_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+ */
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_M  (SPI1_MEM_C_WAIT_PESR_CMD_2B_V << SPI1_MEM_C_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_C_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after HPM command is sent.
  */
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (SPI_MEM_FLASH_HPM_DLY_128_V << SPI_MEM_FLASH_HPM_DLY_128_S)
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/** SPI_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_M  (SPI1_MEM_C_FLASH_HPM_DLY_128_V << SPI1_MEM_C_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_C_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after RES command is sent.
  */
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (SPI_MEM_FLASH_RES_DLY_128_V << SPI_MEM_FLASH_RES_DLY_128_S)
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/** SPI_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_C_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_C_FLASH_RES_DLY_128_M  (SPI1_MEM_C_FLASH_RES_DLY_128_V << SPI1_MEM_C_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_C_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after DP command is sent.
  */
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (SPI_MEM_FLASH_DP_DLY_128_V << SPI_MEM_FLASH_DP_DLY_128_S)
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/** SPI_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
- *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+#define SPI1_MEM_C_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_C_FLASH_DP_DLY_128_M  (SPI1_MEM_C_FLASH_DP_DLY_128_V << SPI1_MEM_C_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_C_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_C_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (SPI_MEM_FLASH_PER_DLY_128_V << SPI_MEM_FLASH_PER_DLY_128_S)
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/** SPI_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
- *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+#define SPI1_MEM_C_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_C_FLASH_PER_DLY_128_M  (SPI1_MEM_C_FLASH_PER_DLY_128_V << SPI1_MEM_C_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_C_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (SPI_MEM_FLASH_PES_DLY_128_V << SPI_MEM_FLASH_PES_DLY_128_S)
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/** SPI_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_C_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_C_FLASH_PES_DLY_128_M  (SPI1_MEM_C_FLASH_PES_DLY_128_V << SPI1_MEM_C_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_C_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_C_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
  *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
  */
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (SPI_MEM_SPI0_LOCK_EN_V << SPI_MEM_SPI0_LOCK_EN_S)
-#define SPI_MEM_SPI0_LOCK_EN_V  0x00000001U
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/** SPI_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_C_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_C_SPI0_LOCK_EN_M  (SPI1_MEM_C_SPI0_LOCK_EN_V << SPI1_MEM_C_SPI0_LOCK_EN_S)
+#define SPI1_MEM_C_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_C_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_C_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
  *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
  *  of Program/Erase Suspend/Resume command is 8.
  */
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (SPI_MEM_FLASH_PESR_CMD_2B_V << SPI_MEM_FLASH_PESR_CMD_2B_S)
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/** SPI_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_M  (SPI1_MEM_C_FLASH_PESR_CMD_2B_V << SPI1_MEM_C_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_C_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_C_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
  *  Program/Erase resume command.
  */
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_M  (SPI_MEM_FLASH_PER_COMMAND_V << SPI_MEM_FLASH_PER_COMMAND_S)
-#define SPI_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
+#define SPI1_MEM_C_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_M  (SPI1_MEM_C_FLASH_PER_COMMAND_V << SPI1_MEM_C_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_C_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_C_FLASH_PER_COMMAND_S  16
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI1_MEM_C_INT_ENA_REG register
  *  SPI1 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_SPI1_BASE + 0xc0)
-/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (SPI_MEM_PER_END_INT_ENA_V << SPI_MEM_PER_END_INT_ENA_S)
-#define SPI_MEM_PER_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ENA_S  0
-/** SPI_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (SPI_MEM_PES_END_INT_ENA_V << SPI_MEM_PES_END_INT_ENA_S)
-#define SPI_MEM_PES_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/** SPI_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (SPI_MEM_WPE_END_INT_ENA_V << SPI_MEM_WPE_END_INT_ENA_S)
-#define SPI_MEM_WPE_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (SPI_MEM_BROWN_OUT_INT_ENA_V << SPI_MEM_BROWN_OUT_INT_ENA_S)
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+#define SPI1_MEM_C_INT_ENA_REG (DR_REG_FLASH_SPI1_BASE + 0xc0)
+/** SPI1_MEM_C_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ENA_M  (SPI1_MEM_C_PER_END_INT_ENA_V << SPI1_MEM_C_PER_END_INT_ENA_S)
+#define SPI1_MEM_C_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ENA_S  0
+/** SPI1_MEM_C_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ENA_M  (SPI1_MEM_C_PES_END_INT_ENA_V << SPI1_MEM_C_PES_END_INT_ENA_S)
+#define SPI1_MEM_C_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ENA_S  1
+/** SPI1_MEM_C_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ENA_M  (SPI1_MEM_C_WPE_END_INT_ENA_V << SPI1_MEM_C_WPE_END_INT_ENA_S)
+#define SPI1_MEM_C_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_M  (SPI1_MEM_C_SLV_ST_END_INT_ENA_V << SPI1_MEM_C_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_M  (SPI1_MEM_C_MST_ST_END_INT_ENA_V << SPI1_MEM_C_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_M  (SPI1_MEM_C_BROWN_OUT_INT_ENA_V << SPI1_MEM_C_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ENA_S  10
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI1_MEM_C_INT_CLR_REG register
  *  SPI1 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_SPI1_BASE + 0xc4)
-/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (SPI_MEM_PER_END_INT_CLR_V << SPI_MEM_PER_END_INT_CLR_S)
-#define SPI_MEM_PER_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PER_END_INT_CLR_S  0
-/** SPI_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (SPI_MEM_PES_END_INT_CLR_V << SPI_MEM_PES_END_INT_CLR_S)
-#define SPI_MEM_PES_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/** SPI_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (SPI_MEM_WPE_END_INT_CLR_V << SPI_MEM_WPE_END_INT_CLR_S)
-#define SPI_MEM_WPE_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (SPI_MEM_BROWN_OUT_INT_CLR_V << SPI_MEM_BROWN_OUT_INT_CLR_S)
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+#define SPI1_MEM_C_INT_CLR_REG (DR_REG_FLASH_SPI1_BASE + 0xc4)
+/** SPI1_MEM_C_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_CLR_M  (SPI1_MEM_C_PER_END_INT_CLR_V << SPI1_MEM_C_PER_END_INT_CLR_S)
+#define SPI1_MEM_C_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_CLR_S  0
+/** SPI1_MEM_C_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_CLR_M  (SPI1_MEM_C_PES_END_INT_CLR_V << SPI1_MEM_C_PES_END_INT_CLR_S)
+#define SPI1_MEM_C_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_CLR_S  1
+/** SPI1_MEM_C_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_CLR_M  (SPI1_MEM_C_WPE_END_INT_CLR_V << SPI1_MEM_C_WPE_END_INT_CLR_S)
+#define SPI1_MEM_C_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_M  (SPI1_MEM_C_SLV_ST_END_INT_CLR_V << SPI1_MEM_C_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_M  (SPI1_MEM_C_MST_ST_END_INT_CLR_V << SPI1_MEM_C_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_M  (SPI1_MEM_C_BROWN_OUT_INT_CLR_V << SPI1_MEM_C_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_CLR_S  10
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI1_MEM_C_INT_RAW_REG register
  *  SPI1 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_SPI1_BASE + 0xc8)
-/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+#define SPI1_MEM_C_INT_RAW_REG (DR_REG_FLASH_SPI1_BASE + 0xc8)
+/** SPI1_MEM_C_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
  *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
  */
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (SPI_MEM_PER_END_INT_RAW_V << SPI_MEM_PER_END_INT_RAW_S)
-#define SPI_MEM_PER_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PER_END_INT_RAW_S  0
-/** SPI_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+#define SPI1_MEM_C_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_RAW_M  (SPI1_MEM_C_PER_END_INT_RAW_V << SPI1_MEM_C_PER_END_INT_RAW_S)
+#define SPI1_MEM_C_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_RAW_S  0
+/** SPI1_MEM_C_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
  *  command (0x75) is sent and flash is suspended successfully. 0: Others.
  */
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (SPI_MEM_PES_END_INT_RAW_V << SPI_MEM_PES_END_INT_RAW_S)
-#define SPI_MEM_PES_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/** SPI_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+#define SPI1_MEM_C_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_RAW_M  (SPI1_MEM_C_PES_END_INT_RAW_V << SPI1_MEM_C_PES_END_INT_RAW_S)
+#define SPI1_MEM_C_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_RAW_S  1
+/** SPI1_MEM_C_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
  *  is sent and flash is already idle. 0: Others.
  */
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (SPI_MEM_WPE_END_INT_RAW_V << SPI_MEM_WPE_END_INT_RAW_S)
-#define SPI_MEM_WPE_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+#define SPI1_MEM_C_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_RAW_M  (SPI1_MEM_C_WPE_END_INT_RAW_V << SPI1_MEM_C_WPE_END_INT_RAW_S)
+#define SPI1_MEM_C_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_M  (SPI1_MEM_C_SLV_ST_END_INT_RAW_V << SPI1_MEM_C_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+#define SPI1_MEM_C_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_M  (SPI1_MEM_C_MST_ST_END_INT_RAW_V << SPI1_MEM_C_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
  *  chip is loosing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (SPI_MEM_BROWN_OUT_INT_RAW_V << SPI_MEM_BROWN_OUT_INT_RAW_S)
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_M  (SPI1_MEM_C_BROWN_OUT_INT_RAW_V << SPI1_MEM_C_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_RAW_S  10
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI1_MEM_C_INT_ST_REG register
  *  SPI1 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_SPI1_BASE + 0xcc)
-/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (SPI_MEM_PER_END_INT_ST_V << SPI_MEM_PER_END_INT_ST_S)
-#define SPI_MEM_PER_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ST_S  0
-/** SPI_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (SPI_MEM_PES_END_INT_ST_V << SPI_MEM_PES_END_INT_ST_S)
-#define SPI_MEM_PES_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ST_S  1
-/** SPI_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (SPI_MEM_WPE_END_INT_ST_V << SPI_MEM_WPE_END_INT_ST_S)
-#define SPI_MEM_WPE_END_INT_ST_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (SPI_MEM_BROWN_OUT_INT_ST_V << SPI_MEM_BROWN_OUT_INT_ST_S)
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+#define SPI1_MEM_C_INT_ST_REG (DR_REG_FLASH_SPI1_BASE + 0xcc)
+/** SPI1_MEM_C_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_C_PER_END_INT_ST_M  (SPI1_MEM_C_PER_END_INT_ST_V << SPI1_MEM_C_PER_END_INT_ST_S)
+#define SPI1_MEM_C_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PER_END_INT_ST_S  0
+/** SPI1_MEM_C_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_C_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_C_PES_END_INT_ST_M  (SPI1_MEM_C_PES_END_INT_ST_V << SPI1_MEM_C_PES_END_INT_ST_S)
+#define SPI1_MEM_C_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_PES_END_INT_ST_S  1
+/** SPI1_MEM_C_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_C_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_C_WPE_END_INT_ST_M  (SPI1_MEM_C_WPE_END_INT_ST_V << SPI1_MEM_C_WPE_END_INT_ST_S)
+#define SPI1_MEM_C_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_WPE_END_INT_ST_S  2
+/** SPI1_MEM_C_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_M  (SPI1_MEM_C_SLV_ST_END_INT_ST_V << SPI1_MEM_C_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_C_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_C_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_C_MST_ST_END_INT_ST_M  (SPI1_MEM_C_MST_ST_END_INT_ST_V << SPI1_MEM_C_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_C_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_C_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_C_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_M  (SPI1_MEM_C_BROWN_OUT_INT_ST_V << SPI1_MEM_C_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_C_BROWN_OUT_INT_ST_S  10
 
-/** SPI_MEM_DDR_REG register
+/** SPI1_MEM_C_DDR_REG register
  *  SPI1 DDR control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_SPI1_BASE + 0xd4)
-/** SPI_MEM_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
+#define SPI1_MEM_C_DDR_REG (DR_REG_FLASH_SPI1_BASE + 0xd4)
+/** SPI1_MEM_C_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
  *  1: in ddr mode,  0 in sdr mode
  */
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S)
-#define SPI_MEM_FMEM_DDR_EN_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_EN_S  0
-/** SPI_MEM_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_C_FMEM_DDR_EN_M  (SPI1_MEM_C_FMEM_DDR_EN_V << SPI1_MEM_C_FMEM_DDR_EN_S)
+#define SPI1_MEM_C_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_EN_S  0
+/** SPI1_MEM_C_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi ddr mode.
  */
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S)
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/** SPI_MEM_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
+#define SPI1_MEM_C_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_M  (SPI1_MEM_C_FMEM_VAR_DUMMY_V << SPI1_MEM_C_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_C_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_C_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_MEM_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_C_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_MEM_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_C_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S)
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/** SPI_MEM_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_C_FMEM_DDR_CMD_DIS_V << SPI1_MEM_C_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_C_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S)
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/** SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_C_FMEM_OUTMINBYTELEN_V << SPI1_MEM_C_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_C_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_MEM_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_C_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_C_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S)
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_MEM_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_C_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S)
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/** SPI_MEM_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_C_FMEM_CLK_DIFF_EN_V << SPI1_MEM_C_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_C_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S)
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
+#define SPI1_MEM_C_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_M  (SPI1_MEM_C_FMEM_DQS_CA_IN_V << SPI1_MEM_C_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_C_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_MEM_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_C_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S)
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/** SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_C_FMEM_CLK_DIFF_INV_V << SPI1_MEM_C_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_C_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_C_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_MEM_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_C_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_C_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S)
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_M  (SPI1_MEM_C_FMEM_HYPERBUS_CA_V << SPI1_MEM_C_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_C_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI1_MEM_C_TIMING_CALI_REG register
  *  SPI1 timing control register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI1_BASE + 0x180)
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_C_TIMING_CALI_REG (DR_REG_FLASH_SPI1_BASE + 0x180)
+/** SPI1_MEM_C_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI1_MEM_C_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_C_TIMING_CALI_M  (SPI1_MEM_C_TIMING_CALI_V << SPI1_MEM_C_TIMING_CALI_S)
+#define SPI1_MEM_C_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_C_TIMING_CALI_S  1
+/** SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_C_EXTRA_DUMMY_CYCLELEN_S  2
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI1_MEM_C_CLOCK_GATE_REG register
  *  SPI1 clk_gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI1_BASE + 0x200)
-/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_C_CLOCK_GATE_REG (DR_REG_FLASH_SPI1_BASE + 0x200)
+/** SPI1_MEM_C_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (SPI_MEM_CLK_EN_V << SPI_MEM_CLK_EN_S)
-#define SPI_MEM_CLK_EN_V  0x00000001U
-#define SPI_MEM_CLK_EN_S  0
+#define SPI1_MEM_C_CLK_EN    (BIT(0))
+#define SPI1_MEM_C_CLK_EN_M  (SPI1_MEM_C_CLK_EN_V << SPI1_MEM_C_CLK_EN_S)
+#define SPI1_MEM_C_CLK_EN_V  0x00000001U
+#define SPI1_MEM_C_CLK_EN_S  0
 
-/** SPI_MEM_DATE_REG register
+/** SPI1_MEM_C_DATE_REG register
  *  Version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_SPI1_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128;
+#define SPI1_MEM_C_DATE_REG (DR_REG_FLASH_SPI1_BASE + 0x3fc)
+/** SPI1_MEM_C_DATE : R/W; bitpos: [27:0]; default: 35660128;
  *  Version control register
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI1_MEM_C_DATE    0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_M  (SPI1_MEM_C_DATE_V << SPI1_MEM_C_DATE_S)
+#define SPI1_MEM_C_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_C_DATE_S  0
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/spi1_mem_c_struct.h

@@ -29,7 +29,7 @@ typedef union {
         uint32_t reserved_8:9;
         /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
          *  In user mode, it is set to indicate that program/erase operation will be triggered.
-         *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+         *  The bit is combined with spi1_mem_c_usr bit. The bit will be cleared once the
          *  operation done.1: enable 0: disable.
          */
         uint32_t flash_pe:1;
@@ -107,7 +107,7 @@ typedef union {
         uint32_t flash_read:1;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi1_mem_c_cmd_reg_t;
 
 /** Type of addr register
  *  SPI1 address register
@@ -121,7 +121,7 @@ typedef union {
         uint32_t usr_addr_value:32;
     };
     uint32_t val;
-} spi_mem_addr_reg_t;
+} spi1_mem_c_addr_reg_t;
 
 /** Type of user register
  *  SPI1 user register.
@@ -130,7 +130,7 @@ typedef union {
     struct {
         uint32_t reserved_0:9;
         /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+         *  the bit combined with spi1_mem_c_mosi_delay_mode bits to set mosi signal delay mode.
          */
         uint32_t ck_out_edge:1;
         uint32_t reserved_10:2;
@@ -152,12 +152,12 @@ typedef union {
         uint32_t fwrite_qio:1;
         uint32_t reserved_16:8;
         /** usr_miso_highpart : HRO; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  read-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_miso_highpart:1;
         /** usr_mosi_highpart : HRO; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  write-data phase only access to high-part of the buffer spi1_mem_c_w8~spi1_mem_c_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_mosi_highpart:1;
@@ -187,7 +187,7 @@ typedef union {
         uint32_t usr_command:1;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi1_mem_c_user_reg_t;
 
 /** Type of user1 register
  *  SPI1 user1 register.
@@ -195,7 +195,7 @@ typedef union {
 typedef union {
     struct {
         /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi1_mem_c_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t usr_dummy_cyclelen:6;
@@ -206,7 +206,7 @@ typedef union {
         uint32_t usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi1_mem_c_user1_reg_t;
 
 /** Type of user2 register
  *  SPI1 user2 register.
@@ -224,7 +224,7 @@ typedef union {
         uint32_t usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi1_mem_c_user2_reg_t;
 
 
 /** Group: Control and configuration registers */
@@ -276,8 +276,8 @@ typedef union {
         uint32_t tx_crc_en:1;
         uint32_t reserved_12:1;
         /** fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
-         *  and spi_mem_fread_dout. 1: enable 0: disable.
+         *  This bit enable the bits: spi1_mem_c_fread_qio, spi1_mem_c_fread_dio, spi1_mem_c_fread_qout
+         *  and spi1_mem_c_fread_dout. 1: enable 0: disable.
          */
         uint32_t fastrd_mode:1;
         /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -285,8 +285,8 @@ typedef union {
          */
         uint32_t fread_dual:1;
         /** resandres : R/W; bitpos: [15]; default: 1;
-         *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-         *  spi_mem_flash_res bit. 1: enable 0: disable.
+         *  The Device ID is read out to SPI1_MEM_C_RD_STATUS register,  this bit combine with
+         *  spi1_mem_c_flash_res bit. 1: enable 0: disable.
          */
         uint32_t resandres:1;
         uint32_t reserved_16:2;
@@ -324,7 +324,7 @@ typedef union {
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi1_mem_c_ctrl_reg_t;
 
 /** Type of ctrl1 register
  *  SPI1 control1 register.
@@ -338,14 +338,14 @@ typedef union {
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
-         *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 512)
          *  SPI_CLK cycles.
          */
         uint32_t cs_hold_dly_res:10;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi1_mem_c_ctrl1_reg_t;
 
 /** Type of ctrl2 register
  *  SPI1 control2 register.
@@ -359,7 +359,7 @@ typedef union {
         uint32_t sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi1_mem_c_ctrl2_reg_t;
 
 /** Type of clock register
  *  SPI1 clock division control register.
@@ -367,16 +367,16 @@ typedef union {
 typedef union {
     struct {
         /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi1_mem_c_clkcnt_N.
          */
         uint32_t clkcnt_l:8;
         /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi1_mem_c_clkcnt_N+1)/2-1).
          */
         uint32_t clkcnt_h:8;
         /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi1_mem_c_clk. So spi1_mem_c_clk frequency is
+         *  system/(spi1_mem_c_clkcnt_N+1)
          */
         uint32_t clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -386,7 +386,7 @@ typedef union {
         uint32_t clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi1_mem_c_clock_reg_t;
 
 /** Type of mosi_dlen register
  *  SPI1 send data bit length control register.
@@ -400,7 +400,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_mosi_dlen_reg_t;
+} spi1_mem_c_mosi_dlen_reg_t;
 
 /** Type of miso_dlen register
  *  SPI1 receive data bit length control register.
@@ -414,7 +414,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_miso_dlen_reg_t;
+} spi1_mem_c_miso_dlen_reg_t;
 
 /** Type of rd_status register
  *  SPI1 status register.
@@ -422,17 +422,17 @@ typedef union {
 typedef union {
     struct {
         /** status : R/W/SS; bitpos: [15:0]; default: 0;
-         *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+         *  The value is stored when set spi1_mem_c_flash_rdsr bit and spi1_mem_c_flash_res bit.
          */
         uint32_t status:16;
         /** wb_mode : R/W; bitpos: [23:16]; default: 0;
-         *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_c_fastrd_mode bit.
          */
         uint32_t wb_mode:8;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} spi_mem_rd_status_reg_t;
+} spi1_mem_c_rd_status_reg_t;
 
 /** Type of misc register
  *  SPI1 misc register
@@ -461,7 +461,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi1_mem_c_misc_reg_t;
 
 /** Type of cache_fctrl register
  *  SPI1 bit mode control register.
@@ -476,38 +476,38 @@ typedef union {
         uint32_t reserved_2:1;
         /** fdin_dual : R/W; bitpos: [3]; default: 0;
          *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
-         *  spi_mem_fread_dio.
+         *  spi1_mem_c_fread_dio.
          */
         uint32_t fdin_dual:1;
         /** fdout_dual : R/W; bitpos: [4]; default: 0;
          *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_c_fread_dio.
          */
         uint32_t fdout_dual:1;
         /** faddr_dual : R/W; bitpos: [5]; default: 0;
          *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_c_fread_dio.
          */
         uint32_t faddr_dual:1;
         /** fdin_quad : R/W; bitpos: [6]; default: 0;
          *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t fdin_quad:1;
         /** fdout_quad : R/W; bitpos: [7]; default: 0;
          *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t fdout_quad:1;
         /** faddr_quad : R/W; bitpos: [8]; default: 0;
          *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_c_fread_qio.
          */
         uint32_t faddr_quad:1;
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi1_mem_c_cache_fctrl_reg_t;
 
 /** Type of flash_waiti_ctrl register
  *  SPI1 wait idle control register
@@ -530,9 +530,9 @@ typedef union {
          */
         uint32_t waiti_addr_en:1;
         /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
-         *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
-         *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-         *  SPI_MEM_WAITI_ADDR_EN is cleared.
+         *  When SPI1_MEM_C_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_C_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_C_WAITI_ADDR_EN is cleared.
          */
         uint32_t waiti_addr_cyclelen:2;
         uint32_t reserved_5:4;
@@ -550,7 +550,7 @@ typedef union {
         uint32_t waiti_cmd:16;
     };
     uint32_t val;
-} spi_mem_flash_waiti_ctrl_reg_t;
+} spi1_mem_c_flash_waiti_ctrl_reg_t;
 
 /** Type of flash_sus_ctrl register
  *  SPI1 flash suspend control register
@@ -570,13 +570,13 @@ typedef union {
          */
         uint32_t flash_pes:1;
         /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase resume command is sent. 0: SPI1 does not wait after program erase
          *  resume command is sent.
          */
         uint32_t flash_per_wait_en:1;
         /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
          *  suspend command is sent.
          */
@@ -594,7 +594,7 @@ typedef union {
          *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
          *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
          *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
-         *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+         *  status_in[15:0]^ SPI1_MEM_C_PESR_END_MSK[15:0].
          */
         uint32_t pesr_end_msk:16;
         /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
@@ -613,13 +613,13 @@ typedef union {
          */
         uint32_t pes_end_en:1;
         /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
-         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_C_SUS_TIMEOUT_CNT[6:0] times, it
          *  will be treated as check pass.
          */
         uint32_t sus_timeout_cnt:7;
     };
     uint32_t val;
-} spi_mem_flash_sus_ctrl_reg_t;
+} spi1_mem_c_flash_sus_ctrl_reg_t;
 
 /** Type of flash_sus_cmd register
  *  SPI1 flash suspend command register
@@ -637,7 +637,7 @@ typedef union {
         uint32_t wait_pesr_command:16;
     };
     uint32_t val;
-} spi_mem_flash_sus_cmd_reg_t;
+} spi1_mem_c_flash_sus_cmd_reg_t;
 
 /** Type of sus_status register
  *  SPI1 flash suspend status register
@@ -649,39 +649,39 @@ typedef union {
          */
         uint32_t flash_sus:1;
         /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
-         *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-         *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         *  1: SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_C_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
          */
         uint32_t wait_pesr_cmd_2b:1;
         /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after HPM command is sent.
          */
         uint32_t flash_hpm_dly_128:1;
         /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after RES command is sent.
          */
         uint32_t flash_res_dly_128:1;
         /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after DP command is sent.
          */
         uint32_t flash_dp_dly_128:1;
         /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  Valid when SPI1_MEM_C_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
          *  sent.
          */
         uint32_t flash_per_dly_128:1;
         /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  Valid when SPI1_MEM_C_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_C_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
          *  sent.
          */
         uint32_t flash_pes_dly_128:1;
@@ -701,7 +701,7 @@ typedef union {
         uint32_t flash_per_command:16;
     };
     uint32_t val;
-} spi_mem_sus_status_reg_t;
+} spi1_mem_c_sus_status_reg_t;
 
 /** Type of ddr register
  *  SPI1 DDR control register
@@ -739,7 +739,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI1_MEM_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -776,7 +776,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi1_mem_c_ddr_reg_t;
 
 /** Type of clock_gate register
  *  SPI1 clk_gate register
@@ -790,7 +790,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi1_mem_c_clock_gate_reg_t;
 
 
 /** Group: Status register */
@@ -805,7 +805,7 @@ typedef union {
         uint32_t tx_crc_data:32;
     };
     uint32_t val;
-} spi_mem_tx_crc_reg_t;
+} spi1_mem_c_tx_crc_reg_t;
 
 
 /** Group: Memory data buffer register */
@@ -820,7 +820,7 @@ typedef union {
         uint32_t buf0:32;
     };
     uint32_t val;
-} spi_mem_w0_reg_t;
+} spi1_mem_c_w0_reg_t;
 
 /** Type of w1 register
  *  SPI1 memory data buffer1
@@ -833,7 +833,7 @@ typedef union {
         uint32_t buf1:32;
     };
     uint32_t val;
-} spi_mem_w1_reg_t;
+} spi1_mem_c_w1_reg_t;
 
 /** Type of w2 register
  *  SPI1 memory data buffer2
@@ -846,7 +846,7 @@ typedef union {
         uint32_t buf2:32;
     };
     uint32_t val;
-} spi_mem_w2_reg_t;
+} spi1_mem_c_w2_reg_t;
 
 /** Type of w3 register
  *  SPI1 memory data buffer3
@@ -859,7 +859,7 @@ typedef union {
         uint32_t buf3:32;
     };
     uint32_t val;
-} spi_mem_w3_reg_t;
+} spi1_mem_c_w3_reg_t;
 
 /** Type of w4 register
  *  SPI1 memory data buffer4
@@ -872,7 +872,7 @@ typedef union {
         uint32_t buf4:32;
     };
     uint32_t val;
-} spi_mem_w4_reg_t;
+} spi1_mem_c_w4_reg_t;
 
 /** Type of w5 register
  *  SPI1 memory data buffer5
@@ -885,7 +885,7 @@ typedef union {
         uint32_t buf5:32;
     };
     uint32_t val;
-} spi_mem_w5_reg_t;
+} spi1_mem_c_w5_reg_t;
 
 /** Type of w6 register
  *  SPI1 memory data buffer6
@@ -898,7 +898,7 @@ typedef union {
         uint32_t buf6:32;
     };
     uint32_t val;
-} spi_mem_w6_reg_t;
+} spi1_mem_c_w6_reg_t;
 
 /** Type of w7 register
  *  SPI1 memory data buffer7
@@ -911,7 +911,7 @@ typedef union {
         uint32_t buf7:32;
     };
     uint32_t val;
-} spi_mem_w7_reg_t;
+} spi1_mem_c_w7_reg_t;
 
 /** Type of w8 register
  *  SPI1 memory data buffer8
@@ -924,7 +924,7 @@ typedef union {
         uint32_t buf8:32;
     };
     uint32_t val;
-} spi_mem_w8_reg_t;
+} spi1_mem_c_w8_reg_t;
 
 /** Type of w9 register
  *  SPI1 memory data buffer9
@@ -937,7 +937,7 @@ typedef union {
         uint32_t buf9:32;
     };
     uint32_t val;
-} spi_mem_w9_reg_t;
+} spi1_mem_c_w9_reg_t;
 
 /** Type of w10 register
  *  SPI1 memory data buffer10
@@ -950,7 +950,7 @@ typedef union {
         uint32_t buf10:32;
     };
     uint32_t val;
-} spi_mem_w10_reg_t;
+} spi1_mem_c_w10_reg_t;
 
 /** Type of w11 register
  *  SPI1 memory data buffer11
@@ -963,7 +963,7 @@ typedef union {
         uint32_t buf11:32;
     };
     uint32_t val;
-} spi_mem_w11_reg_t;
+} spi1_mem_c_w11_reg_t;
 
 /** Type of w12 register
  *  SPI1 memory data buffer12
@@ -976,7 +976,7 @@ typedef union {
         uint32_t buf12:32;
     };
     uint32_t val;
-} spi_mem_w12_reg_t;
+} spi1_mem_c_w12_reg_t;
 
 /** Type of w13 register
  *  SPI1 memory data buffer13
@@ -989,7 +989,7 @@ typedef union {
         uint32_t buf13:32;
     };
     uint32_t val;
-} spi_mem_w13_reg_t;
+} spi1_mem_c_w13_reg_t;
 
 /** Type of w14 register
  *  SPI1 memory data buffer14
@@ -1002,7 +1002,7 @@ typedef union {
         uint32_t buf14:32;
     };
     uint32_t val;
-} spi_mem_w14_reg_t;
+} spi1_mem_c_w14_reg_t;
 
 /** Type of w15 register
  *  SPI1 memory data buffer15
@@ -1015,7 +1015,7 @@ typedef union {
         uint32_t buf15:32;
     };
     uint32_t val;
-} spi_mem_w15_reg_t;
+} spi1_mem_c_w15_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -1025,34 +1025,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_ena:1;
         /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_ena:1;
         /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_ena:1;
         /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_ena:1;
         /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_ena:1;
         uint32_t reserved_5:5;
         /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The enable bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_ena:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi1_mem_c_int_ena_reg_t;
 
 /** Type of int_clr register
  *  SPI1 interrupt clear register
@@ -1060,34 +1060,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_clr:1;
         /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_clr:1;
         /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_clr:1;
         /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_clr:1;
         /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_clr:1;
         uint32_t reserved_5:5;
         /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_clr:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi1_mem_c_int_clr_reg_t;
 
 /** Type of int_raw register
  *  SPI1 interrupt raw register
@@ -1095,34 +1095,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  The raw bit for SPI1_MEM_C_PER_END_INT interrupt. 1: Triggered when Auto Resume
          *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
          */
         uint32_t per_end_int_raw:1;
         /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  The raw bit for SPI1_MEM_C_PES_END_INT interrupt.1: Triggered when Auto Suspend
          *  command (0x75) is sent and flash is suspended successfully. 0: Others.
          */
         uint32_t pes_end_int_raw:1;
         /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  The raw bit for SPI1_MEM_C_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
          *  is sent and flash is already idle. 0: Others.
          */
         uint32_t wpe_end_int_raw:1;
         /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  The raw bit for SPI1_MEM_C_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t slv_st_end_int_raw:1;
         /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  The raw bit for SPI1_MEM_C_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mst_st_end_int_raw:1;
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
          *  chip is loosing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
@@ -1131,7 +1131,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi1_mem_c_int_raw_reg_t;
 
 /** Type of int_st register
  *  SPI1 interrupt status register
@@ -1139,34 +1139,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_MEM_PER_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_PER_END_INT interrupt.
          */
         uint32_t per_end_int_st:1;
         /** pes_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_MEM_PES_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_st:1;
         /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_st:1;
         /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_st:1;
         /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_C_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_st:1;
         uint32_t reserved_5:5;
         /** brown_out_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_C_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_st:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi1_mem_c_int_st_reg_t;
 
 
 /** Group: Timing registers */
@@ -1187,7 +1187,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi1_mem_c_timing_cali_reg_t;
 
 
 /** Group: Version register */
@@ -1203,65 +1203,65 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi1_mem_c_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t cmd;
-    volatile spi_mem_addr_reg_t addr;
-    volatile spi_mem_ctrl_reg_t ctrl;
-    volatile spi_mem_ctrl1_reg_t ctrl1;
-    volatile spi_mem_ctrl2_reg_t ctrl2;
-    volatile spi_mem_clock_reg_t clock;
-    volatile spi_mem_user_reg_t user;
-    volatile spi_mem_user1_reg_t user1;
-    volatile spi_mem_user2_reg_t user2;
-    volatile spi_mem_mosi_dlen_reg_t mosi_dlen;
-    volatile spi_mem_miso_dlen_reg_t miso_dlen;
-    volatile spi_mem_rd_status_reg_t rd_status;
+typedef struct spi1_mem_c_dev_s {
+    volatile spi1_mem_c_cmd_reg_t cmd;
+    volatile spi1_mem_c_addr_reg_t addr;
+    volatile spi1_mem_c_ctrl_reg_t ctrl;
+    volatile spi1_mem_c_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_c_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_c_clock_reg_t clock;
+    volatile spi1_mem_c_user_reg_t user;
+    volatile spi1_mem_c_user1_reg_t user1;
+    volatile spi1_mem_c_user2_reg_t user2;
+    volatile spi1_mem_c_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_c_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_c_rd_status_reg_t rd_status;
     uint32_t reserved_030;
-    volatile spi_mem_misc_reg_t misc;
-    volatile spi_mem_tx_crc_reg_t tx_crc;
-    volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
+    volatile spi1_mem_c_misc_reg_t misc;
+    volatile spi1_mem_c_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040[6];
-    volatile spi_mem_w0_reg_t w0;
-    volatile spi_mem_w1_reg_t w1;
-    volatile spi_mem_w2_reg_t w2;
-    volatile spi_mem_w3_reg_t w3;
-    volatile spi_mem_w4_reg_t w4;
-    volatile spi_mem_w5_reg_t w5;
-    volatile spi_mem_w6_reg_t w6;
-    volatile spi_mem_w7_reg_t w7;
-    volatile spi_mem_w8_reg_t w8;
-    volatile spi_mem_w9_reg_t w9;
-    volatile spi_mem_w10_reg_t w10;
-    volatile spi_mem_w11_reg_t w11;
-    volatile spi_mem_w12_reg_t w12;
-    volatile spi_mem_w13_reg_t w13;
-    volatile spi_mem_w14_reg_t w14;
-    volatile spi_mem_w15_reg_t w15;
-    volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
-    volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
-    volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
-    volatile spi_mem_sus_status_reg_t sus_status;
+    volatile spi1_mem_c_w0_reg_t w0;
+    volatile spi1_mem_c_w1_reg_t w1;
+    volatile spi1_mem_c_w2_reg_t w2;
+    volatile spi1_mem_c_w3_reg_t w3;
+    volatile spi1_mem_c_w4_reg_t w4;
+    volatile spi1_mem_c_w5_reg_t w5;
+    volatile spi1_mem_c_w6_reg_t w6;
+    volatile spi1_mem_c_w7_reg_t w7;
+    volatile spi1_mem_c_w8_reg_t w8;
+    volatile spi1_mem_c_w9_reg_t w9;
+    volatile spi1_mem_c_w10_reg_t w10;
+    volatile spi1_mem_c_w11_reg_t w11;
+    volatile spi1_mem_c_w12_reg_t w12;
+    volatile spi1_mem_c_w13_reg_t w13;
+    volatile spi1_mem_c_w14_reg_t w14;
+    volatile spi1_mem_c_w15_reg_t w15;
+    volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_c_sus_status_reg_t sus_status;
     uint32_t reserved_0a8[6];
-    volatile spi_mem_int_ena_reg_t int_ena;
-    volatile spi_mem_int_clr_reg_t int_clr;
-    volatile spi_mem_int_raw_reg_t int_raw;
-    volatile spi_mem_int_st_reg_t int_st;
+    volatile spi1_mem_c_int_ena_reg_t int_ena;
+    volatile spi1_mem_c_int_clr_reg_t int_clr;
+    volatile spi1_mem_c_int_raw_reg_t int_raw;
+    volatile spi1_mem_c_int_st_reg_t int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t ddr;
+    volatile spi1_mem_c_ddr_reg_t ddr;
     uint32_t reserved_0d8[42];
-    volatile spi_mem_timing_cali_reg_t timing_cali;
+    volatile spi1_mem_c_timing_cali_reg_t timing_cali;
     uint32_t reserved_184[31];
-    volatile spi_mem_clock_gate_reg_t clock_gate;
+    volatile spi1_mem_c_clock_gate_reg_t clock_gate;
     uint32_t reserved_204[126];
-    volatile spi_mem_date_reg_t date;
+    volatile spi1_mem_c_date_reg_t date;
 } spi1_mem_c_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+_Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/spi1_mem_s_reg.h

@@ -11,1470 +11,1470 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI1_MEM_S_CMD_REG register
  *  SPI1 memory command register
  */
-#define SPI_MEM_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
+#define SPI1_MEM_S_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0x0)
+/** SPI1_MEM_S_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI1 master FSM.
  */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
+#define SPI1_MEM_S_MST_ST    0x0000000FU
+#define SPI1_MEM_S_MST_ST_M  (SPI1_MEM_S_MST_ST_V << SPI1_MEM_S_MST_ST_S)
+#define SPI1_MEM_S_MST_ST_V  0x0000000FU
+#define SPI1_MEM_S_MST_ST_S  0
+/** SPI1_MEM_S_SLV_ST : RO; bitpos: [7:4]; default: 0;
  *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
  *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
  *  6:write data state, 7: done state, 8: read data end state.
  */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
+#define SPI1_MEM_S_SLV_ST    0x0000000FU
+#define SPI1_MEM_S_SLV_ST_M  (SPI1_MEM_S_SLV_ST_V << SPI1_MEM_S_SLV_ST_S)
+#define SPI1_MEM_S_SLV_ST_V  0x0000000FU
+#define SPI1_MEM_S_SLV_ST_S  4
+/** SPI1_MEM_S_FLASH_PE : R/W/SC; bitpos: [17]; default: 0;
  *  In user mode, it is set to indicate that program/erase operation will be triggered.
- *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+ *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
  *  operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S)
-#define SPI_MEM_FLASH_PE_V  0x00000001U
-#define SPI_MEM_FLASH_PE_S  17
-/** SPI_MEM_USR : R/W/SC; bitpos: [18]; default: 0;
+#define SPI1_MEM_S_FLASH_PE    (BIT(17))
+#define SPI1_MEM_S_FLASH_PE_M  (SPI1_MEM_S_FLASH_PE_V << SPI1_MEM_S_FLASH_PE_S)
+#define SPI1_MEM_S_FLASH_PE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PE_S  17
+/** SPI1_MEM_S_USR : R/W/SC; bitpos: [18]; default: 0;
  *  User define command enable.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
-/** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
+#define SPI1_MEM_S_USR    (BIT(18))
+#define SPI1_MEM_S_USR_M  (SPI1_MEM_S_USR_V << SPI1_MEM_S_USR_S)
+#define SPI1_MEM_S_USR_V  0x00000001U
+#define SPI1_MEM_S_USR_S  18
+/** SPI1_MEM_S_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0;
  *  Drive Flash into high performance mode.  The bit will be cleared once the operation
  *  done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S)
-#define SPI_MEM_FLASH_HPM_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_S  19
-/** SPI_MEM_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
+#define SPI1_MEM_S_FLASH_HPM    (BIT(19))
+#define SPI1_MEM_S_FLASH_HPM_M  (SPI1_MEM_S_FLASH_HPM_V << SPI1_MEM_S_FLASH_HPM_S)
+#define SPI1_MEM_S_FLASH_HPM_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_S  19
+/** SPI1_MEM_S_FLASH_RES : R/W/SC; bitpos: [20]; default: 0;
  *  This bit combined with reg_resandres bit releases Flash from the power-down state
  *  or high performance mode and obtains the devices ID. The bit will be cleared once
  *  the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S)
-#define SPI_MEM_FLASH_RES_V  0x00000001U
-#define SPI_MEM_FLASH_RES_S  20
-/** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
+#define SPI1_MEM_S_FLASH_RES    (BIT(20))
+#define SPI1_MEM_S_FLASH_RES_M  (SPI1_MEM_S_FLASH_RES_V << SPI1_MEM_S_FLASH_RES_S)
+#define SPI1_MEM_S_FLASH_RES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_S  20
+/** SPI1_MEM_S_FLASH_DP : R/W/SC; bitpos: [21]; default: 0;
  *  Drive Flash into power down.  An operation will be triggered when the bit is set.
  *  The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S)
-#define SPI_MEM_FLASH_DP_V  0x00000001U
-#define SPI_MEM_FLASH_DP_S  21
-/** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_FLASH_DP    (BIT(21))
+#define SPI1_MEM_S_FLASH_DP_M  (SPI1_MEM_S_FLASH_DP_V << SPI1_MEM_S_FLASH_DP_S)
+#define SPI1_MEM_S_FLASH_DP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_S  21
+/** SPI1_MEM_S_FLASH_CE : R/W/SC; bitpos: [22]; default: 0;
  *  Chip erase enable. Chip erase operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S)
-#define SPI_MEM_FLASH_CE_V  0x00000001U
-#define SPI_MEM_FLASH_CE_S  22
-/** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_FLASH_CE    (BIT(22))
+#define SPI1_MEM_S_FLASH_CE_M  (SPI1_MEM_S_FLASH_CE_V << SPI1_MEM_S_FLASH_CE_S)
+#define SPI1_MEM_S_FLASH_CE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_CE_S  22
+/** SPI1_MEM_S_FLASH_BE : R/W/SC; bitpos: [23]; default: 0;
  *  Block erase enable(32KB) .  Block erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S)
-#define SPI_MEM_FLASH_BE_V  0x00000001U
-#define SPI_MEM_FLASH_BE_S  23
-/** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FLASH_BE    (BIT(23))
+#define SPI1_MEM_S_FLASH_BE_M  (SPI1_MEM_S_FLASH_BE_V << SPI1_MEM_S_FLASH_BE_S)
+#define SPI1_MEM_S_FLASH_BE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_BE_S  23
+/** SPI1_MEM_S_FLASH_SE : R/W/SC; bitpos: [24]; default: 0;
  *  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S)
-#define SPI_MEM_FLASH_SE_V  0x00000001U
-#define SPI_MEM_FLASH_SE_S  24
-/** SPI_MEM_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
+#define SPI1_MEM_S_FLASH_SE    (BIT(24))
+#define SPI1_MEM_S_FLASH_SE_M  (SPI1_MEM_S_FLASH_SE_V << SPI1_MEM_S_FLASH_SE_S)
+#define SPI1_MEM_S_FLASH_SE_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SE_S  24
+/** SPI1_MEM_S_FLASH_PP : R/W/SC; bitpos: [25]; default: 0;
  *  Page program enable(1 byte ~256 bytes data to be programmed). Page program
  *  operation  will be triggered when the bit is set. The bit will be cleared once the
  *  operation done .1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S)
-#define SPI_MEM_FLASH_PP_V  0x00000001U
-#define SPI_MEM_FLASH_PP_S  25
-/** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_FLASH_PP    (BIT(25))
+#define SPI1_MEM_S_FLASH_PP_M  (SPI1_MEM_S_FLASH_PP_V << SPI1_MEM_S_FLASH_PP_S)
+#define SPI1_MEM_S_FLASH_PP_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PP_S  25
+/** SPI1_MEM_S_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0;
  *  Write status register enable.   Write status operation  will be triggered when the
  *  bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S)
-#define SPI_MEM_FLASH_WRSR_V  0x00000001U
-#define SPI_MEM_FLASH_WRSR_S  26
-/** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_FLASH_WRSR    (BIT(26))
+#define SPI1_MEM_S_FLASH_WRSR_M  (SPI1_MEM_S_FLASH_WRSR_V << SPI1_MEM_S_FLASH_WRSR_S)
+#define SPI1_MEM_S_FLASH_WRSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRSR_S  26
+/** SPI1_MEM_S_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0;
  *  Read status register-1.  Read status operation will be triggered when the bit is
  *  set. The bit will be cleared once the operation done.1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S)
-#define SPI_MEM_FLASH_RDSR_V  0x00000001U
-#define SPI_MEM_FLASH_RDSR_S  27
-/** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_FLASH_RDSR    (BIT(27))
+#define SPI1_MEM_S_FLASH_RDSR_M  (SPI1_MEM_S_FLASH_RDSR_V << SPI1_MEM_S_FLASH_RDSR_S)
+#define SPI1_MEM_S_FLASH_RDSR_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDSR_S  27
+/** SPI1_MEM_S_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0;
  *  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be
  *  cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S)
-#define SPI_MEM_FLASH_RDID_V  0x00000001U
-#define SPI_MEM_FLASH_RDID_S  28
-/** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_FLASH_RDID    (BIT(28))
+#define SPI1_MEM_S_FLASH_RDID_M  (SPI1_MEM_S_FLASH_RDID_V << SPI1_MEM_S_FLASH_RDID_S)
+#define SPI1_MEM_S_FLASH_RDID_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RDID_S  28
+/** SPI1_MEM_S_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0;
  *  Write flash disable. Write disable command will be sent when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S)
-#define SPI_MEM_FLASH_WRDI_V  0x00000001U
-#define SPI_MEM_FLASH_WRDI_S  29
-/** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_FLASH_WRDI    (BIT(29))
+#define SPI1_MEM_S_FLASH_WRDI_M  (SPI1_MEM_S_FLASH_WRDI_V << SPI1_MEM_S_FLASH_WRDI_S)
+#define SPI1_MEM_S_FLASH_WRDI_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WRDI_S  29
+/** SPI1_MEM_S_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0;
  *  Write flash enable.  Write enable command will be sent when the bit is set. The bit
  *  will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S)
-#define SPI_MEM_FLASH_WREN_V  0x00000001U
-#define SPI_MEM_FLASH_WREN_S  30
-/** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_FLASH_WREN    (BIT(30))
+#define SPI1_MEM_S_FLASH_WREN_M  (SPI1_MEM_S_FLASH_WREN_V << SPI1_MEM_S_FLASH_WREN_S)
+#define SPI1_MEM_S_FLASH_WREN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_WREN_S  30
+/** SPI1_MEM_S_FLASH_READ : R/W/SC; bitpos: [31]; default: 0;
  *  Read flash enable. Read flash operation will be triggered when the bit is set. The
  *  bit will be cleared once the operation done. 1: enable 0: disable.
  */
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S)
-#define SPI_MEM_FLASH_READ_V  0x00000001U
-#define SPI_MEM_FLASH_READ_S  31
+#define SPI1_MEM_S_FLASH_READ    (BIT(31))
+#define SPI1_MEM_S_FLASH_READ_M  (SPI1_MEM_S_FLASH_READ_V << SPI1_MEM_S_FLASH_READ_S)
+#define SPI1_MEM_S_FLASH_READ_V  0x00000001U
+#define SPI1_MEM_S_FLASH_READ_S  31
 
-/** SPI_MEM_ADDR_REG register
+/** SPI1_MEM_S_ADDR_REG register
  *  SPI1 address register
  */
-#define SPI_MEM_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4)
-/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_ADDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0x4)
+/** SPI1_MEM_S_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
  *  address, the bit24-bit31 are the byte length of a transfer.
  */
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_M  (SPI_MEM_USR_ADDR_VALUE_V << SPI_MEM_USR_ADDR_VALUE_S)
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_MEM_USR_ADDR_VALUE_S  0
+#define SPI1_MEM_S_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_M  (SPI1_MEM_S_USR_ADDR_VALUE_V << SPI1_MEM_S_USR_ADDR_VALUE_S)
+#define SPI1_MEM_S_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI1_MEM_S_USR_ADDR_VALUE_S  0
 
-/** SPI_MEM_CTRL_REG register
+/** SPI1_MEM_S_CTRL_REG register
  *  SPI1 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8)
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
+#define SPI1_MEM_S_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8)
+/** SPI1_MEM_S_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
+#define SPI1_MEM_S_FDUMMY_RIN    (BIT(2))
+#define SPI1_MEM_S_FDUMMY_RIN_M  (SPI1_MEM_S_FDUMMY_RIN_V << SPI1_MEM_S_FDUMMY_RIN_S)
+#define SPI1_MEM_S_FDUMMY_RIN_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_RIN_S  2
+/** SPI1_MEM_S_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
  *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
  */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FDUMMY_WOUT    (BIT(3))
+#define SPI1_MEM_S_FDUMMY_WOUT_M  (SPI1_MEM_S_FDUMMY_WOUT_V << SPI1_MEM_S_FDUMMY_WOUT_S)
+#define SPI1_MEM_S_FDUMMY_WOUT_V  0x00000001U
+#define SPI1_MEM_S_FDUMMY_WOUT_S  3
+/** SPI1_MEM_S_FDOUT_OCT : R/W; bitpos: [4]; default: 0;
  *  Apply 8 signals during write-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_FDOUT_OCT    (BIT(4))
+#define SPI1_MEM_S_FDOUT_OCT_M  (SPI1_MEM_S_FDOUT_OCT_V << SPI1_MEM_S_FDOUT_OCT_S)
+#define SPI1_MEM_S_FDOUT_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_OCT_S  4
+/** SPI1_MEM_S_FDIN_OCT : R/W; bitpos: [5]; default: 0;
  *  Apply 8 signals during read-data phase 1:enable 0: disable
  */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_S_FDIN_OCT    (BIT(5))
+#define SPI1_MEM_S_FDIN_OCT_M  (SPI1_MEM_S_FDIN_OCT_V << SPI1_MEM_S_FDIN_OCT_S)
+#define SPI1_MEM_S_FDIN_OCT_V  0x00000001U
+#define SPI1_MEM_S_FDIN_OCT_S  5
+/** SPI1_MEM_S_FADDR_OCT : R/W; bitpos: [6]; default: 0;
  *  Apply 8 signals during address phase 1:enable 0: disable
  */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_S_FADDR_OCT    (BIT(6))
+#define SPI1_MEM_S_FADDR_OCT_M  (SPI1_MEM_S_FADDR_OCT_V << SPI1_MEM_S_FADDR_OCT_S)
+#define SPI1_MEM_S_FADDR_OCT_V  0x00000001U
+#define SPI1_MEM_S_FADDR_OCT_S  6
+/** SPI1_MEM_S_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
  *  Apply 4 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_FCMD_QUAD    (BIT(8))
+#define SPI1_MEM_S_FCMD_QUAD_M  (SPI1_MEM_S_FCMD_QUAD_V << SPI1_MEM_S_FCMD_QUAD_S)
+#define SPI1_MEM_S_FCMD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FCMD_QUAD_S  8
+/** SPI1_MEM_S_FCMD_OCT : R/W; bitpos: [9]; default: 0;
  *  Apply 8 signals during command phase 1:enable 0: disable
  */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_S_FCMD_OCT    (BIT(9))
+#define SPI1_MEM_S_FCMD_OCT_M  (SPI1_MEM_S_FCMD_OCT_V << SPI1_MEM_S_FCMD_OCT_S)
+#define SPI1_MEM_S_FCMD_OCT_V  0x00000001U
+#define SPI1_MEM_S_FCMD_OCT_S  9
+/** SPI1_MEM_S_FCS_CRC_EN : R/W; bitpos: [10]; default: 0;
  *  For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
  *  low.
  */
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S)
-#define SPI_MEM_FCS_CRC_EN_V  0x00000001U
-#define SPI_MEM_FCS_CRC_EN_S  10
-/** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
+#define SPI1_MEM_S_FCS_CRC_EN    (BIT(10))
+#define SPI1_MEM_S_FCS_CRC_EN_M  (SPI1_MEM_S_FCS_CRC_EN_V << SPI1_MEM_S_FCS_CRC_EN_S)
+#define SPI1_MEM_S_FCS_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_FCS_CRC_EN_S  10
+/** SPI1_MEM_S_TX_CRC_EN : R/W; bitpos: [11]; default: 0;
  *  For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
  */
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S)
-#define SPI_MEM_TX_CRC_EN_V  0x00000001U
-#define SPI_MEM_TX_CRC_EN_S  11
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
- *  and spi_mem_fread_dout. 1: enable 0: disable.
- */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_S_TX_CRC_EN    (BIT(11))
+#define SPI1_MEM_S_TX_CRC_EN_M  (SPI1_MEM_S_TX_CRC_EN_V << SPI1_MEM_S_TX_CRC_EN_S)
+#define SPI1_MEM_S_TX_CRC_EN_V  0x00000001U
+#define SPI1_MEM_S_TX_CRC_EN_S  11
+/** SPI1_MEM_S_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
+ *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+ *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_FASTRD_MODE    (BIT(13))
+#define SPI1_MEM_S_FASTRD_MODE_M  (SPI1_MEM_S_FASTRD_MODE_V << SPI1_MEM_S_FASTRD_MODE_S)
+#define SPI1_MEM_S_FASTRD_MODE_V  0x00000001U
+#define SPI1_MEM_S_FASTRD_MODE_S  13
+/** SPI1_MEM_S_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
  *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1;
- *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
- *  spi_mem_flash_res bit. 1: enable 0: disable.
- */
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S)
-#define SPI_MEM_RESANDRES_V  0x00000001U
-#define SPI_MEM_RESANDRES_S  15
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
+#define SPI1_MEM_S_FREAD_DUAL    (BIT(14))
+#define SPI1_MEM_S_FREAD_DUAL_M  (SPI1_MEM_S_FREAD_DUAL_V << SPI1_MEM_S_FREAD_DUAL_S)
+#define SPI1_MEM_S_FREAD_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DUAL_S  14
+/** SPI1_MEM_S_RESANDRES : R/W; bitpos: [15]; default: 1;
+ *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+ *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
+ */
+#define SPI1_MEM_S_RESANDRES    (BIT(15))
+#define SPI1_MEM_S_RESANDRES_M  (SPI1_MEM_S_RESANDRES_V << SPI1_MEM_S_RESANDRES_S)
+#define SPI1_MEM_S_RESANDRES_V  0x00000001U
+#define SPI1_MEM_S_RESANDRES_S  15
+/** SPI1_MEM_S_Q_POL : R/W; bitpos: [18]; default: 1;
  *  The bit is used to set MISO line polarity, 1: high 0, low
  */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
+#define SPI1_MEM_S_Q_POL    (BIT(18))
+#define SPI1_MEM_S_Q_POL_M  (SPI1_MEM_S_Q_POL_V << SPI1_MEM_S_Q_POL_S)
+#define SPI1_MEM_S_Q_POL_V  0x00000001U
+#define SPI1_MEM_S_Q_POL_S  18
+/** SPI1_MEM_S_D_POL : R/W; bitpos: [19]; default: 1;
  *  The bit is used to set MOSI line polarity, 1: high 0, low
  */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
+#define SPI1_MEM_S_D_POL    (BIT(19))
+#define SPI1_MEM_S_D_POL_M  (SPI1_MEM_S_D_POL_V << SPI1_MEM_S_D_POL_S)
+#define SPI1_MEM_S_D_POL_V  0x00000001U
+#define SPI1_MEM_S_D_POL_S  19
+/** SPI1_MEM_S_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
  *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
+#define SPI1_MEM_S_FREAD_QUAD    (BIT(20))
+#define SPI1_MEM_S_FREAD_QUAD_M  (SPI1_MEM_S_FREAD_QUAD_V << SPI1_MEM_S_FREAD_QUAD_S)
+#define SPI1_MEM_S_FREAD_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QUAD_S  20
+/** SPI1_MEM_S_WP_REG : R/W; bitpos: [21]; default: 1;
  *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
  */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_WP_REG    (BIT(21))
+#define SPI1_MEM_S_WP_REG_M  (SPI1_MEM_S_WP_REG_V << SPI1_MEM_S_WP_REG_S)
+#define SPI1_MEM_S_WP_REG_V  0x00000001U
+#define SPI1_MEM_S_WP_REG_S  21
+/** SPI1_MEM_S_WRSR_2B : R/W; bitpos: [22]; default: 0;
  *  two bytes data will be written to status register when it is set. 1: enable 0:
  *  disable.
  */
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S)
-#define SPI_MEM_WRSR_2B_V  0x00000001U
-#define SPI_MEM_WRSR_2B_S  22
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_WRSR_2B    (BIT(22))
+#define SPI1_MEM_S_WRSR_2B_M  (SPI1_MEM_S_WRSR_2B_V << SPI1_MEM_S_WRSR_2B_S)
+#define SPI1_MEM_S_WRSR_2B_V  0x00000001U
+#define SPI1_MEM_S_WRSR_2B_S  22
+/** SPI1_MEM_S_FREAD_DIO : R/W; bitpos: [23]; default: 0;
  *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FREAD_DIO    (BIT(23))
+#define SPI1_MEM_S_FREAD_DIO_M  (SPI1_MEM_S_FREAD_DIO_V << SPI1_MEM_S_FREAD_DIO_S)
+#define SPI1_MEM_S_FREAD_DIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_DIO_S  23
+/** SPI1_MEM_S_FREAD_QIO : R/W; bitpos: [24]; default: 0;
  *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
  *  0: disable.
  */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
+#define SPI1_MEM_S_FREAD_QIO    (BIT(24))
+#define SPI1_MEM_S_FREAD_QIO_M  (SPI1_MEM_S_FREAD_QIO_V << SPI1_MEM_S_FREAD_QIO_S)
+#define SPI1_MEM_S_FREAD_QIO_V  0x00000001U
+#define SPI1_MEM_S_FREAD_QIO_S  24
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI1_MEM_S_CTRL1_REG register
  *  SPI1 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+#define SPI1_MEM_S_CTRL1_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc)
+/** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
  *  SPI clock is alwasy on.
  */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
- *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+#define SPI1_MEM_S_CLK_MODE    0x00000003U
+#define SPI1_MEM_S_CLK_MODE_M  (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S)
+#define SPI1_MEM_S_CLK_MODE_V  0x00000003U
+#define SPI1_MEM_S_CLK_MODE_S  0
+/** SPI1_MEM_S_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023;
+ *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
  *  SPI_CLK cycles.
  */
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_M  (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S)
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x000003FFU
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+#define SPI1_MEM_S_CS_HOLD_DLY_RES    0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_M  (SPI1_MEM_S_CS_HOLD_DLY_RES_V << SPI1_MEM_S_CS_HOLD_DLY_RES_S)
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_V  0x000003FFU
+#define SPI1_MEM_S_CS_HOLD_DLY_RES_S  2
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI1_MEM_S_CTRL2_REG register
  *  SPI1 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10)
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_CTRL2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x10)
+/** SPI1_MEM_S_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The FSM will be reset.
  */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
+#define SPI1_MEM_S_SYNC_RESET    (BIT(31))
+#define SPI1_MEM_S_SYNC_RESET_M  (SPI1_MEM_S_SYNC_RESET_V << SPI1_MEM_S_SYNC_RESET_S)
+#define SPI1_MEM_S_SYNC_RESET_V  0x00000001U
+#define SPI1_MEM_S_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI1_MEM_S_CLOCK_REG register
  *  SPI1 clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
- */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
- */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
- */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
+#define SPI1_MEM_S_CLOCK_REG (DR_REG_PSRAM_MSPI1_BASE + 0x14)
+/** SPI1_MEM_S_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
+ *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
+ */
+#define SPI1_MEM_S_CLKCNT_L    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_M  (SPI1_MEM_S_CLKCNT_L_V << SPI1_MEM_S_CLKCNT_L_S)
+#define SPI1_MEM_S_CLKCNT_L_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_L_S  0
+/** SPI1_MEM_S_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
+ *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
+ */
+#define SPI1_MEM_S_CLKCNT_H    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_M  (SPI1_MEM_S_CLKCNT_H_V << SPI1_MEM_S_CLKCNT_H_S)
+#define SPI1_MEM_S_CLKCNT_H_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_H_S  8
+/** SPI1_MEM_S_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
+ *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+ *  system/(spi1_mem_s_clkcnt_N+1)
+ */
+#define SPI1_MEM_S_CLKCNT_N    0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_M  (SPI1_MEM_S_CLKCNT_N_V << SPI1_MEM_S_CLKCNT_N_S)
+#define SPI1_MEM_S_CLKCNT_N_V  0x000000FFU
+#define SPI1_MEM_S_CLKCNT_N_S  16
+/** SPI1_MEM_S_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
  *  reserved
  */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+#define SPI1_MEM_S_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_M  (SPI1_MEM_S_CLK_EQU_SYSCLK_V << SPI1_MEM_S_CLK_EQU_SYSCLK_S)
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI1_MEM_S_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI1_MEM_S_USER_REG register
  *  SPI1 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+#define SPI1_MEM_S_USER_REG (DR_REG_PSRAM_MSPI1_BASE + 0x18)
+/** SPI1_MEM_S_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
  */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+#define SPI1_MEM_S_CK_OUT_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_OUT_EDGE_M  (SPI1_MEM_S_CK_OUT_EDGE_V << SPI1_MEM_S_CK_OUT_EDGE_S)
+#define SPI1_MEM_S_CK_OUT_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_OUT_EDGE_S  9
+/** SPI1_MEM_S_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
  *  In the write operations read-data phase apply 2 signals
  */
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (SPI_MEM_FWRITE_DUAL_V << SPI_MEM_FWRITE_DUAL_S)
-#define SPI_MEM_FWRITE_DUAL_V  0x00000001U
-#define SPI_MEM_FWRITE_DUAL_S  12
-/** SPI_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+#define SPI1_MEM_S_FWRITE_DUAL    (BIT(12))
+#define SPI1_MEM_S_FWRITE_DUAL_M  (SPI1_MEM_S_FWRITE_DUAL_V << SPI1_MEM_S_FWRITE_DUAL_S)
+#define SPI1_MEM_S_FWRITE_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DUAL_S  12
+/** SPI1_MEM_S_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
  *  In the write operations read-data phase apply 4 signals
  */
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (SPI_MEM_FWRITE_QUAD_V << SPI_MEM_FWRITE_QUAD_S)
-#define SPI_MEM_FWRITE_QUAD_V  0x00000001U
-#define SPI_MEM_FWRITE_QUAD_S  13
-/** SPI_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
+#define SPI1_MEM_S_FWRITE_QUAD    (BIT(13))
+#define SPI1_MEM_S_FWRITE_QUAD_M  (SPI1_MEM_S_FWRITE_QUAD_V << SPI1_MEM_S_FWRITE_QUAD_S)
+#define SPI1_MEM_S_FWRITE_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QUAD_S  13
+/** SPI1_MEM_S_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
  *  In the write operations address phase and read-data phase apply 2 signals.
  */
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (SPI_MEM_FWRITE_DIO_V << SPI_MEM_FWRITE_DIO_S)
-#define SPI_MEM_FWRITE_DIO_V  0x00000001U
-#define SPI_MEM_FWRITE_DIO_S  14
-/** SPI_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_S_FWRITE_DIO    (BIT(14))
+#define SPI1_MEM_S_FWRITE_DIO_M  (SPI1_MEM_S_FWRITE_DIO_V << SPI1_MEM_S_FWRITE_DIO_S)
+#define SPI1_MEM_S_FWRITE_DIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_DIO_S  14
+/** SPI1_MEM_S_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
  *  In the write operations address phase and read-data phase apply 4 signals.
  */
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (SPI_MEM_FWRITE_QIO_V << SPI_MEM_FWRITE_QIO_S)
-#define SPI_MEM_FWRITE_QIO_V  0x00000001U
-#define SPI_MEM_FWRITE_QIO_S  15
-/** SPI_MEM_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_S_FWRITE_QIO    (BIT(15))
+#define SPI1_MEM_S_FWRITE_QIO_M  (SPI1_MEM_S_FWRITE_QIO_V << SPI1_MEM_S_FWRITE_QIO_S)
+#define SPI1_MEM_S_FWRITE_QIO_V  0x00000001U
+#define SPI1_MEM_S_FWRITE_QIO_S  15
+/** SPI1_MEM_S_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (SPI_MEM_USR_MISO_HIGHPART_V << SPI_MEM_USR_MISO_HIGHPART_S)
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/** SPI_MEM_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+#define SPI1_MEM_S_USR_MISO_HIGHPART    (BIT(24))
+#define SPI1_MEM_S_USR_MISO_HIGHPART_M  (SPI1_MEM_S_USR_MISO_HIGHPART_V << SPI1_MEM_S_USR_MISO_HIGHPART_S)
+#define SPI1_MEM_S_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_HIGHPART_S  24
+/** SPI1_MEM_S_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
  *  enable 0: disable.
  */
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (SPI_MEM_USR_MOSI_HIGHPART_V << SPI_MEM_USR_MOSI_HIGHPART_S)
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_M  (SPI1_MEM_S_USR_MOSI_HIGHPART_V << SPI1_MEM_S_USR_MOSI_HIGHPART_S)
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_HIGHPART_S  25
+/** SPI1_MEM_S_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
  *  SPI clock is disable in dummy phase when the bit is enable.
  */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_USR_DUMMY_IDLE    (BIT(26))
+#define SPI1_MEM_S_USR_DUMMY_IDLE_M  (SPI1_MEM_S_USR_DUMMY_IDLE_V << SPI1_MEM_S_USR_DUMMY_IDLE_S)
+#define SPI1_MEM_S_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_IDLE_S  26
+/** SPI1_MEM_S_USR_MOSI : R/W; bitpos: [27]; default: 0;
  *  This bit enable the write-data phase of an operation.
  */
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (SPI_MEM_USR_MOSI_V << SPI_MEM_USR_MOSI_S)
-#define SPI_MEM_USR_MOSI_V  0x00000001U
-#define SPI_MEM_USR_MOSI_S  27
-/** SPI_MEM_USR_MISO : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_USR_MOSI    (BIT(27))
+#define SPI1_MEM_S_USR_MOSI_M  (SPI1_MEM_S_USR_MOSI_V << SPI1_MEM_S_USR_MOSI_S)
+#define SPI1_MEM_S_USR_MOSI_V  0x00000001U
+#define SPI1_MEM_S_USR_MOSI_S  27
+/** SPI1_MEM_S_USR_MISO : R/W; bitpos: [28]; default: 0;
  *  This bit enable the read-data phase of an operation.
  */
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (SPI_MEM_USR_MISO_V << SPI_MEM_USR_MISO_S)
-#define SPI_MEM_USR_MISO_V  0x00000001U
-#define SPI_MEM_USR_MISO_S  28
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_USR_MISO    (BIT(28))
+#define SPI1_MEM_S_USR_MISO_M  (SPI1_MEM_S_USR_MISO_V << SPI1_MEM_S_USR_MISO_S)
+#define SPI1_MEM_S_USR_MISO_V  0x00000001U
+#define SPI1_MEM_S_USR_MISO_S  28
+/** SPI1_MEM_S_USR_DUMMY : R/W; bitpos: [29]; default: 0;
  *  This bit enable the dummy phase of an operation.
  */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
-/** SPI_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_USR_DUMMY    (BIT(29))
+#define SPI1_MEM_S_USR_DUMMY_M  (SPI1_MEM_S_USR_DUMMY_V << SPI1_MEM_S_USR_DUMMY_S)
+#define SPI1_MEM_S_USR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_USR_DUMMY_S  29
+/** SPI1_MEM_S_USR_ADDR : R/W; bitpos: [30]; default: 0;
  *  This bit enable the address phase of an operation.
  */
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (SPI_MEM_USR_ADDR_V << SPI_MEM_USR_ADDR_S)
-#define SPI_MEM_USR_ADDR_V  0x00000001U
-#define SPI_MEM_USR_ADDR_S  30
-/** SPI_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+#define SPI1_MEM_S_USR_ADDR    (BIT(30))
+#define SPI1_MEM_S_USR_ADDR_M  (SPI1_MEM_S_USR_ADDR_V << SPI1_MEM_S_USR_ADDR_S)
+#define SPI1_MEM_S_USR_ADDR_V  0x00000001U
+#define SPI1_MEM_S_USR_ADDR_S  30
+/** SPI1_MEM_S_USR_COMMAND : R/W; bitpos: [31]; default: 1;
  *  This bit enable the command phase of an operation.
  */
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (SPI_MEM_USR_COMMAND_V << SPI_MEM_USR_COMMAND_S)
-#define SPI_MEM_USR_COMMAND_V  0x00000001U
-#define SPI_MEM_USR_COMMAND_S  31
+#define SPI1_MEM_S_USR_COMMAND    (BIT(31))
+#define SPI1_MEM_S_USR_COMMAND_M  (SPI1_MEM_S_USR_COMMAND_V << SPI1_MEM_S_USR_COMMAND_S)
+#define SPI1_MEM_S_USR_COMMAND_V  0x00000001U
+#define SPI1_MEM_S_USR_COMMAND_S  31
 
-/** SPI_MEM_USER1_REG register
+/** SPI1_MEM_S_USER1_REG register
  *  SPI1 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+#define SPI1_MEM_S_USER1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x1c)
+/** SPI1_MEM_S_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
+ *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
  */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_S_USR_DUMMY_CYCLELEN_V << SPI1_MEM_S_USR_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_DUMMY_CYCLELEN_S  0
+/** SPI1_MEM_S_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
  *  The length in bits of address phase. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
+#define SPI1_MEM_S_USR_ADDR_BITLEN    0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_M  (SPI1_MEM_S_USR_ADDR_BITLEN_V << SPI1_MEM_S_USR_ADDR_BITLEN_S)
+#define SPI1_MEM_S_USR_ADDR_BITLEN_V  0x0000003FU
+#define SPI1_MEM_S_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI1_MEM_S_USER2_REG register
  *  SPI1 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+#define SPI1_MEM_S_USER2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x20)
+/** SPI1_MEM_S_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+#define SPI1_MEM_S_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_M  (SPI1_MEM_S_USR_COMMAND_VALUE_V << SPI1_MEM_S_USR_COMMAND_VALUE_S)
+#define SPI1_MEM_S_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI1_MEM_S_USR_COMMAND_VALUE_S  0
+/** SPI1_MEM_S_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
  *  The length in bits of command phase. The register value shall be (bit_num-1)
  */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+#define SPI1_MEM_S_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_M  (SPI1_MEM_S_USR_COMMAND_BITLEN_V << SPI1_MEM_S_USR_COMMAND_BITLEN_S)
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI1_MEM_S_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MOSI_DLEN_REG register
+/** SPI1_MEM_S_MOSI_DLEN_REG register
  *  SPI1 send data bit length control register.
  */
-#define SPI_MEM_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24)
-/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_S_MOSI_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x24)
+/** SPI1_MEM_S_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of write-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_M  (SPI_MEM_USR_MOSI_DBITLEN_V << SPI_MEM_USR_MOSI_DBITLEN_S)
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+#define SPI1_MEM_S_USR_MOSI_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_M  (SPI1_MEM_S_USR_MOSI_DBITLEN_V << SPI1_MEM_S_USR_MOSI_DBITLEN_S)
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MOSI_DBITLEN_S  0
 
-/** SPI_MEM_MISO_DLEN_REG register
+/** SPI1_MEM_S_MISO_DLEN_REG register
  *  SPI1 receive data bit length control register.
  */
-#define SPI_MEM_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28)
-/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
+#define SPI1_MEM_S_MISO_DLEN_REG (DR_REG_PSRAM_MSPI1_BASE + 0x28)
+/** SPI1_MEM_S_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of  read-data. The register value shall be (bit_num-1).
  */
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_M  (SPI_MEM_USR_MISO_DBITLEN_V << SPI_MEM_USR_MISO_DBITLEN_S)
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x000003FFU
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
+#define SPI1_MEM_S_USR_MISO_DBITLEN    0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_M  (SPI1_MEM_S_USR_MISO_DBITLEN_V << SPI1_MEM_S_USR_MISO_DBITLEN_S)
+#define SPI1_MEM_S_USR_MISO_DBITLEN_V  0x000003FFU
+#define SPI1_MEM_S_USR_MISO_DBITLEN_S  0
 
-/** SPI_MEM_RD_STATUS_REG register
+/** SPI1_MEM_S_RD_STATUS_REG register
  *  SPI1 status register.
  */
-#define SPI_MEM_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
-/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
- *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
- */
-#define SPI_MEM_STATUS    0x0000FFFFU
-#define SPI_MEM_STATUS_M  (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
-#define SPI_MEM_STATUS_V  0x0000FFFFU
-#define SPI_MEM_STATUS_S  0
-/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
- *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
- */
-#define SPI_MEM_WB_MODE    0x000000FFU
-#define SPI_MEM_WB_MODE_M  (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
-#define SPI_MEM_WB_MODE_V  0x000000FFU
-#define SPI_MEM_WB_MODE_S  16
+#define SPI1_MEM_S_RD_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0x2c)
+/** SPI1_MEM_S_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
+ *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
+ */
+#define SPI1_MEM_S_STATUS    0x0000FFFFU
+#define SPI1_MEM_S_STATUS_M  (SPI1_MEM_S_STATUS_V << SPI1_MEM_S_STATUS_S)
+#define SPI1_MEM_S_STATUS_V  0x0000FFFFU
+#define SPI1_MEM_S_STATUS_S  0
+/** SPI1_MEM_S_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
+ */
+#define SPI1_MEM_S_WB_MODE    0x000000FFU
+#define SPI1_MEM_S_WB_MODE_M  (SPI1_MEM_S_WB_MODE_V << SPI1_MEM_S_WB_MODE_S)
+#define SPI1_MEM_S_WB_MODE_V  0x000000FFU
+#define SPI1_MEM_S_WB_MODE_S  16
 
-/** SPI_MEM_MISC_REG register
+/** SPI1_MEM_S_MISC_REG register
  *  SPI1 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34)
-/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_MISC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x34)
+/** SPI1_MEM_S_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (SPI_MEM_CS0_DIS_V << SPI_MEM_CS0_DIS_S)
-#define SPI_MEM_CS0_DIS_V  0x00000001U
-#define SPI_MEM_CS0_DIS_S  0
-/** SPI_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1;
+#define SPI1_MEM_S_CS0_DIS    (BIT(0))
+#define SPI1_MEM_S_CS0_DIS_M  (SPI1_MEM_S_CS0_DIS_V << SPI1_MEM_S_CS0_DIS_S)
+#define SPI1_MEM_S_CS0_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS0_DIS_S  0
+/** SPI1_MEM_S_CS1_DIS : R/W; bitpos: [1]; default: 1;
  *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
  */
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (SPI_MEM_CS1_DIS_V << SPI_MEM_CS1_DIS_S)
-#define SPI_MEM_CS1_DIS_V  0x00000001U
-#define SPI_MEM_CS1_DIS_S  1
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_CS1_DIS    (BIT(1))
+#define SPI1_MEM_S_CS1_DIS_M  (SPI1_MEM_S_CS1_DIS_V << SPI1_MEM_S_CS1_DIS_S)
+#define SPI1_MEM_S_CS1_DIS_V  0x00000001U
+#define SPI1_MEM_S_CS1_DIS_S  1
+/** SPI1_MEM_S_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
  *  1: spi clk line is high when idle     0: spi clk line is low when idle
  */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
+#define SPI1_MEM_S_CK_IDLE_EDGE    (BIT(9))
+#define SPI1_MEM_S_CK_IDLE_EDGE_M  (SPI1_MEM_S_CK_IDLE_EDGE_V << SPI1_MEM_S_CK_IDLE_EDGE_S)
+#define SPI1_MEM_S_CK_IDLE_EDGE_V  0x00000001U
+#define SPI1_MEM_S_CK_IDLE_EDGE_S  9
+/** SPI1_MEM_S_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
  *  spi cs line keep low when the bit is set.
  */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+#define SPI1_MEM_S_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_M  (SPI1_MEM_S_CS_KEEP_ACTIVE_V << SPI1_MEM_S_CS_KEEP_ACTIVE_S)
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI1_MEM_S_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_TX_CRC_REG register
+/** SPI1_MEM_S_TX_CRC_REG register
  *  SPI1 TX CRC data register.
  */
-#define SPI_MEM_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38)
-/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
+#define SPI1_MEM_S_TX_CRC_REG (DR_REG_PSRAM_MSPI1_BASE + 0x38)
+/** SPI1_MEM_S_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
  *  For SPI1, the value of crc32.
  */
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_M  (SPI_MEM_TX_CRC_DATA_V << SPI_MEM_TX_CRC_DATA_S)
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFFU
-#define SPI_MEM_TX_CRC_DATA_S  0
+#define SPI1_MEM_S_TX_CRC_DATA    0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_M  (SPI1_MEM_S_TX_CRC_DATA_V << SPI1_MEM_S_TX_CRC_DATA_S)
+#define SPI1_MEM_S_TX_CRC_DATA_V  0xFFFFFFFFU
+#define SPI1_MEM_S_TX_CRC_DATA_S  0
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI1_MEM_S_CACHE_FCTRL_REG register
  *  SPI1 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
-/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_CACHE_FCTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3c)
+/** SPI1_MEM_S_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
  *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
  */
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S)
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x00000001U
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_M  (SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V << SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S)
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_V  0x00000001U
+#define SPI1_MEM_S_CACHE_USR_ADDR_4BYTE_S  1
+/** SPI1_MEM_S_FDIN_DUAL : R/W; bitpos: [3]; default: 0;
  *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
- *  spi_mem_fread_dio.
+ *  spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S)
-#define SPI_MEM_FDIN_DUAL_V  0x00000001U
-#define SPI_MEM_FDIN_DUAL_S  3
-/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FDIN_DUAL    (BIT(3))
+#define SPI1_MEM_S_FDIN_DUAL_M  (SPI1_MEM_S_FDIN_DUAL_V << SPI1_MEM_S_FDIN_DUAL_S)
+#define SPI1_MEM_S_FDIN_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDIN_DUAL_S  3
+/** SPI1_MEM_S_FDOUT_DUAL : R/W; bitpos: [4]; default: 0;
  *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S)
-#define SPI_MEM_FDOUT_DUAL_V  0x00000001U
-#define SPI_MEM_FDOUT_DUAL_S  4
-/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_FDOUT_DUAL    (BIT(4))
+#define SPI1_MEM_S_FDOUT_DUAL_M  (SPI1_MEM_S_FDOUT_DUAL_V << SPI1_MEM_S_FDOUT_DUAL_S)
+#define SPI1_MEM_S_FDOUT_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_DUAL_S  4
+/** SPI1_MEM_S_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
  *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_dio.
+ *  with spi1_mem_s_fread_dio.
  */
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S)
-#define SPI_MEM_FADDR_DUAL_V  0x00000001U
-#define SPI_MEM_FADDR_DUAL_S  5
-/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
+#define SPI1_MEM_S_FADDR_DUAL    (BIT(5))
+#define SPI1_MEM_S_FADDR_DUAL_M  (SPI1_MEM_S_FADDR_DUAL_V << SPI1_MEM_S_FADDR_DUAL_S)
+#define SPI1_MEM_S_FADDR_DUAL_V  0x00000001U
+#define SPI1_MEM_S_FADDR_DUAL_S  5
+/** SPI1_MEM_S_FDIN_QUAD : R/W; bitpos: [6]; default: 0;
  *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S)
-#define SPI_MEM_FDIN_QUAD_V  0x00000001U
-#define SPI_MEM_FDIN_QUAD_S  6
-/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_S_FDIN_QUAD    (BIT(6))
+#define SPI1_MEM_S_FDIN_QUAD_M  (SPI1_MEM_S_FDIN_QUAD_V << SPI1_MEM_S_FDIN_QUAD_S)
+#define SPI1_MEM_S_FDIN_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDIN_QUAD_S  6
+/** SPI1_MEM_S_FDOUT_QUAD : R/W; bitpos: [7]; default: 0;
  *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S)
-#define SPI_MEM_FDOUT_QUAD_V  0x00000001U
-#define SPI_MEM_FDOUT_QUAD_S  7
-/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
+#define SPI1_MEM_S_FDOUT_QUAD    (BIT(7))
+#define SPI1_MEM_S_FDOUT_QUAD_M  (SPI1_MEM_S_FDOUT_QUAD_V << SPI1_MEM_S_FDOUT_QUAD_S)
+#define SPI1_MEM_S_FDOUT_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FDOUT_QUAD_S  7
+/** SPI1_MEM_S_FADDR_QUAD : R/W; bitpos: [8]; default: 0;
  *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
- *  with spi_mem_fread_qio.
+ *  with spi1_mem_s_fread_qio.
  */
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S)
-#define SPI_MEM_FADDR_QUAD_V  0x00000001U
-#define SPI_MEM_FADDR_QUAD_S  8
+#define SPI1_MEM_S_FADDR_QUAD    (BIT(8))
+#define SPI1_MEM_S_FADDR_QUAD_M  (SPI1_MEM_S_FADDR_QUAD_V << SPI1_MEM_S_FADDR_QUAD_S)
+#define SPI1_MEM_S_FADDR_QUAD_V  0x00000001U
+#define SPI1_MEM_S_FADDR_QUAD_S  8
 
-/** SPI_MEM_W0_REG register
+/** SPI1_MEM_S_W0_REG register
  *  SPI1 memory data buffer0
  */
-#define SPI_MEM_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58)
-/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W0_REG (DR_REG_PSRAM_MSPI1_BASE + 0x58)
+/** SPI1_MEM_S_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF0    0xFFFFFFFFU
-#define SPI_MEM_BUF0_M  (SPI_MEM_BUF0_V << SPI_MEM_BUF0_S)
-#define SPI_MEM_BUF0_V  0xFFFFFFFFU
-#define SPI_MEM_BUF0_S  0
+#define SPI1_MEM_S_BUF0    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_M  (SPI1_MEM_S_BUF0_V << SPI1_MEM_S_BUF0_S)
+#define SPI1_MEM_S_BUF0_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF0_S  0
 
-/** SPI_MEM_W1_REG register
+/** SPI1_MEM_S_W1_REG register
  *  SPI1 memory data buffer1
  */
-#define SPI_MEM_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c)
-/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W1_REG (DR_REG_PSRAM_MSPI1_BASE + 0x5c)
+/** SPI1_MEM_S_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF1    0xFFFFFFFFU
-#define SPI_MEM_BUF1_M  (SPI_MEM_BUF1_V << SPI_MEM_BUF1_S)
-#define SPI_MEM_BUF1_V  0xFFFFFFFFU
-#define SPI_MEM_BUF1_S  0
+#define SPI1_MEM_S_BUF1    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_M  (SPI1_MEM_S_BUF1_V << SPI1_MEM_S_BUF1_S)
+#define SPI1_MEM_S_BUF1_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF1_S  0
 
-/** SPI_MEM_W2_REG register
+/** SPI1_MEM_S_W2_REG register
  *  SPI1 memory data buffer2
  */
-#define SPI_MEM_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60)
-/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W2_REG (DR_REG_PSRAM_MSPI1_BASE + 0x60)
+/** SPI1_MEM_S_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF2    0xFFFFFFFFU
-#define SPI_MEM_BUF2_M  (SPI_MEM_BUF2_V << SPI_MEM_BUF2_S)
-#define SPI_MEM_BUF2_V  0xFFFFFFFFU
-#define SPI_MEM_BUF2_S  0
+#define SPI1_MEM_S_BUF2    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_M  (SPI1_MEM_S_BUF2_V << SPI1_MEM_S_BUF2_S)
+#define SPI1_MEM_S_BUF2_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF2_S  0
 
-/** SPI_MEM_W3_REG register
+/** SPI1_MEM_S_W3_REG register
  *  SPI1 memory data buffer3
  */
-#define SPI_MEM_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64)
-/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W3_REG (DR_REG_PSRAM_MSPI1_BASE + 0x64)
+/** SPI1_MEM_S_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF3    0xFFFFFFFFU
-#define SPI_MEM_BUF3_M  (SPI_MEM_BUF3_V << SPI_MEM_BUF3_S)
-#define SPI_MEM_BUF3_V  0xFFFFFFFFU
-#define SPI_MEM_BUF3_S  0
+#define SPI1_MEM_S_BUF3    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_M  (SPI1_MEM_S_BUF3_V << SPI1_MEM_S_BUF3_S)
+#define SPI1_MEM_S_BUF3_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF3_S  0
 
-/** SPI_MEM_W4_REG register
+/** SPI1_MEM_S_W4_REG register
  *  SPI1 memory data buffer4
  */
-#define SPI_MEM_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68)
-/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W4_REG (DR_REG_PSRAM_MSPI1_BASE + 0x68)
+/** SPI1_MEM_S_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF4    0xFFFFFFFFU
-#define SPI_MEM_BUF4_M  (SPI_MEM_BUF4_V << SPI_MEM_BUF4_S)
-#define SPI_MEM_BUF4_V  0xFFFFFFFFU
-#define SPI_MEM_BUF4_S  0
+#define SPI1_MEM_S_BUF4    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_M  (SPI1_MEM_S_BUF4_V << SPI1_MEM_S_BUF4_S)
+#define SPI1_MEM_S_BUF4_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF4_S  0
 
-/** SPI_MEM_W5_REG register
+/** SPI1_MEM_S_W5_REG register
  *  SPI1 memory data buffer5
  */
-#define SPI_MEM_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c)
-/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W5_REG (DR_REG_PSRAM_MSPI1_BASE + 0x6c)
+/** SPI1_MEM_S_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF5    0xFFFFFFFFU
-#define SPI_MEM_BUF5_M  (SPI_MEM_BUF5_V << SPI_MEM_BUF5_S)
-#define SPI_MEM_BUF5_V  0xFFFFFFFFU
-#define SPI_MEM_BUF5_S  0
+#define SPI1_MEM_S_BUF5    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_M  (SPI1_MEM_S_BUF5_V << SPI1_MEM_S_BUF5_S)
+#define SPI1_MEM_S_BUF5_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF5_S  0
 
-/** SPI_MEM_W6_REG register
+/** SPI1_MEM_S_W6_REG register
  *  SPI1 memory data buffer6
  */
-#define SPI_MEM_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70)
-/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W6_REG (DR_REG_PSRAM_MSPI1_BASE + 0x70)
+/** SPI1_MEM_S_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF6    0xFFFFFFFFU
-#define SPI_MEM_BUF6_M  (SPI_MEM_BUF6_V << SPI_MEM_BUF6_S)
-#define SPI_MEM_BUF6_V  0xFFFFFFFFU
-#define SPI_MEM_BUF6_S  0
+#define SPI1_MEM_S_BUF6    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_M  (SPI1_MEM_S_BUF6_V << SPI1_MEM_S_BUF6_S)
+#define SPI1_MEM_S_BUF6_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF6_S  0
 
-/** SPI_MEM_W7_REG register
+/** SPI1_MEM_S_W7_REG register
  *  SPI1 memory data buffer7
  */
-#define SPI_MEM_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74)
-/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W7_REG (DR_REG_PSRAM_MSPI1_BASE + 0x74)
+/** SPI1_MEM_S_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF7    0xFFFFFFFFU
-#define SPI_MEM_BUF7_M  (SPI_MEM_BUF7_V << SPI_MEM_BUF7_S)
-#define SPI_MEM_BUF7_V  0xFFFFFFFFU
-#define SPI_MEM_BUF7_S  0
+#define SPI1_MEM_S_BUF7    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_M  (SPI1_MEM_S_BUF7_V << SPI1_MEM_S_BUF7_S)
+#define SPI1_MEM_S_BUF7_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF7_S  0
 
-/** SPI_MEM_W8_REG register
+/** SPI1_MEM_S_W8_REG register
  *  SPI1 memory data buffer8
  */
-#define SPI_MEM_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78)
-/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W8_REG (DR_REG_PSRAM_MSPI1_BASE + 0x78)
+/** SPI1_MEM_S_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF8    0xFFFFFFFFU
-#define SPI_MEM_BUF8_M  (SPI_MEM_BUF8_V << SPI_MEM_BUF8_S)
-#define SPI_MEM_BUF8_V  0xFFFFFFFFU
-#define SPI_MEM_BUF8_S  0
+#define SPI1_MEM_S_BUF8    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_M  (SPI1_MEM_S_BUF8_V << SPI1_MEM_S_BUF8_S)
+#define SPI1_MEM_S_BUF8_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF8_S  0
 
-/** SPI_MEM_W9_REG register
+/** SPI1_MEM_S_W9_REG register
  *  SPI1 memory data buffer9
  */
-#define SPI_MEM_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c)
-/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W9_REG (DR_REG_PSRAM_MSPI1_BASE + 0x7c)
+/** SPI1_MEM_S_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF9    0xFFFFFFFFU
-#define SPI_MEM_BUF9_M  (SPI_MEM_BUF9_V << SPI_MEM_BUF9_S)
-#define SPI_MEM_BUF9_V  0xFFFFFFFFU
-#define SPI_MEM_BUF9_S  0
+#define SPI1_MEM_S_BUF9    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_M  (SPI1_MEM_S_BUF9_V << SPI1_MEM_S_BUF9_S)
+#define SPI1_MEM_S_BUF9_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF9_S  0
 
-/** SPI_MEM_W10_REG register
+/** SPI1_MEM_S_W10_REG register
  *  SPI1 memory data buffer10
  */
-#define SPI_MEM_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80)
-/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W10_REG (DR_REG_PSRAM_MSPI1_BASE + 0x80)
+/** SPI1_MEM_S_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF10    0xFFFFFFFFU
-#define SPI_MEM_BUF10_M  (SPI_MEM_BUF10_V << SPI_MEM_BUF10_S)
-#define SPI_MEM_BUF10_V  0xFFFFFFFFU
-#define SPI_MEM_BUF10_S  0
+#define SPI1_MEM_S_BUF10    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_M  (SPI1_MEM_S_BUF10_V << SPI1_MEM_S_BUF10_S)
+#define SPI1_MEM_S_BUF10_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF10_S  0
 
-/** SPI_MEM_W11_REG register
+/** SPI1_MEM_S_W11_REG register
  *  SPI1 memory data buffer11
  */
-#define SPI_MEM_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84)
-/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W11_REG (DR_REG_PSRAM_MSPI1_BASE + 0x84)
+/** SPI1_MEM_S_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF11    0xFFFFFFFFU
-#define SPI_MEM_BUF11_M  (SPI_MEM_BUF11_V << SPI_MEM_BUF11_S)
-#define SPI_MEM_BUF11_V  0xFFFFFFFFU
-#define SPI_MEM_BUF11_S  0
+#define SPI1_MEM_S_BUF11    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_M  (SPI1_MEM_S_BUF11_V << SPI1_MEM_S_BUF11_S)
+#define SPI1_MEM_S_BUF11_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF11_S  0
 
-/** SPI_MEM_W12_REG register
+/** SPI1_MEM_S_W12_REG register
  *  SPI1 memory data buffer12
  */
-#define SPI_MEM_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88)
-/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W12_REG (DR_REG_PSRAM_MSPI1_BASE + 0x88)
+/** SPI1_MEM_S_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF12    0xFFFFFFFFU
-#define SPI_MEM_BUF12_M  (SPI_MEM_BUF12_V << SPI_MEM_BUF12_S)
-#define SPI_MEM_BUF12_V  0xFFFFFFFFU
-#define SPI_MEM_BUF12_S  0
+#define SPI1_MEM_S_BUF12    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_M  (SPI1_MEM_S_BUF12_V << SPI1_MEM_S_BUF12_S)
+#define SPI1_MEM_S_BUF12_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF12_S  0
 
-/** SPI_MEM_W13_REG register
+/** SPI1_MEM_S_W13_REG register
  *  SPI1 memory data buffer13
  */
-#define SPI_MEM_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c)
-/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W13_REG (DR_REG_PSRAM_MSPI1_BASE + 0x8c)
+/** SPI1_MEM_S_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF13    0xFFFFFFFFU
-#define SPI_MEM_BUF13_M  (SPI_MEM_BUF13_V << SPI_MEM_BUF13_S)
-#define SPI_MEM_BUF13_V  0xFFFFFFFFU
-#define SPI_MEM_BUF13_S  0
+#define SPI1_MEM_S_BUF13    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_M  (SPI1_MEM_S_BUF13_V << SPI1_MEM_S_BUF13_S)
+#define SPI1_MEM_S_BUF13_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF13_S  0
 
-/** SPI_MEM_W14_REG register
+/** SPI1_MEM_S_W14_REG register
  *  SPI1 memory data buffer14
  */
-#define SPI_MEM_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90)
-/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W14_REG (DR_REG_PSRAM_MSPI1_BASE + 0x90)
+/** SPI1_MEM_S_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF14    0xFFFFFFFFU
-#define SPI_MEM_BUF14_M  (SPI_MEM_BUF14_V << SPI_MEM_BUF14_S)
-#define SPI_MEM_BUF14_V  0xFFFFFFFFU
-#define SPI_MEM_BUF14_S  0
+#define SPI1_MEM_S_BUF14    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_M  (SPI1_MEM_S_BUF14_V << SPI1_MEM_S_BUF14_S)
+#define SPI1_MEM_S_BUF14_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF14_S  0
 
-/** SPI_MEM_W15_REG register
+/** SPI1_MEM_S_W15_REG register
  *  SPI1 memory data buffer15
  */
-#define SPI_MEM_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94)
-/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+#define SPI1_MEM_S_W15_REG (DR_REG_PSRAM_MSPI1_BASE + 0x94)
+/** SPI1_MEM_S_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
-#define SPI_MEM_BUF15    0xFFFFFFFFU
-#define SPI_MEM_BUF15_M  (SPI_MEM_BUF15_V << SPI_MEM_BUF15_S)
-#define SPI_MEM_BUF15_V  0xFFFFFFFFU
-#define SPI_MEM_BUF15_S  0
+#define SPI1_MEM_S_BUF15    0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_M  (SPI1_MEM_S_BUF15_V << SPI1_MEM_S_BUF15_S)
+#define SPI1_MEM_S_BUF15_V  0xFFFFFFFFU
+#define SPI1_MEM_S_BUF15_S  0
 
-/** SPI_MEM_FLASH_WAITI_CTRL_REG register
+/** SPI1_MEM_S_FLASH_WAITI_CTRL_REG register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98)
-/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_S_FLASH_WAITI_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x98)
+/** SPI1_MEM_S_WAITI_EN : R/W; bitpos: [0]; default: 1;
  *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
  *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
  *  Suspend/Resume are not supported.
  */
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (SPI_MEM_WAITI_EN_V << SPI_MEM_WAITI_EN_S)
-#define SPI_MEM_WAITI_EN_V  0x00000001U
-#define SPI_MEM_WAITI_EN_S  0
-/** SPI_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_WAITI_EN    (BIT(0))
+#define SPI1_MEM_S_WAITI_EN_M  (SPI1_MEM_S_WAITI_EN_V << SPI1_MEM_S_WAITI_EN_S)
+#define SPI1_MEM_S_WAITI_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_EN_S  0
+/** SPI1_MEM_S_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
  *  The dummy phase enable when wait flash idle (RDSR)
  */
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (SPI_MEM_WAITI_DUMMY_V << SPI_MEM_WAITI_DUMMY_S)
-#define SPI_MEM_WAITI_DUMMY_V  0x00000001U
-#define SPI_MEM_WAITI_DUMMY_S  1
-/** SPI_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_S_WAITI_DUMMY    (BIT(1))
+#define SPI1_MEM_S_WAITI_DUMMY_M  (SPI1_MEM_S_WAITI_DUMMY_V << SPI1_MEM_S_WAITI_DUMMY_S)
+#define SPI1_MEM_S_WAITI_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_WAITI_DUMMY_S  1
+/** SPI1_MEM_S_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
  *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
  *  address in RDSR or read SUS command transfer.
  */
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (SPI_MEM_WAITI_ADDR_EN_V << SPI_MEM_WAITI_ADDR_EN_S)
-#define SPI_MEM_WAITI_ADDR_EN_V  0x00000001U
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/** SPI_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
- *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
- *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
- *  SPI_MEM_WAITI_ADDR_EN is cleared.
- */
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  (SPI_MEM_WAITI_ADDR_CYCLELEN_V << SPI_MEM_WAITI_ADDR_CYCLELEN_S)
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x00000003U
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/** SPI_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
+#define SPI1_MEM_S_WAITI_ADDR_EN    (BIT(2))
+#define SPI1_MEM_S_WAITI_ADDR_EN_M  (SPI1_MEM_S_WAITI_ADDR_EN_V << SPI1_MEM_S_WAITI_ADDR_EN_S)
+#define SPI1_MEM_S_WAITI_ADDR_EN_V  0x00000001U
+#define SPI1_MEM_S_WAITI_ADDR_EN_S  2
+/** SPI1_MEM_S_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
+ *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+ *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+ *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
+ */
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN    0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_V  0x00000003U
+#define SPI1_MEM_S_WAITI_ADDR_CYCLELEN_S  3
+/** SPI1_MEM_S_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
  *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  */
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (SPI_MEM_WAITI_CMD_2B_V << SPI_MEM_WAITI_CMD_2B_S)
-#define SPI_MEM_WAITI_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/** SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
+#define SPI1_MEM_S_WAITI_CMD_2B    (BIT(9))
+#define SPI1_MEM_S_WAITI_CMD_2B_M  (SPI1_MEM_S_WAITI_CMD_2B_V << SPI1_MEM_S_WAITI_CMD_2B_S)
+#define SPI1_MEM_S_WAITI_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAITI_CMD_2B_S  9
+/** SPI1_MEM_S_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
  *  The dummy cycle length when wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  (SPI_MEM_WAITI_DUMMY_CYCLELEN_V << SPI_MEM_WAITI_DUMMY_CYCLELEN_S)
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/** SPI_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN    0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
+#define SPI1_MEM_S_WAITI_DUMMY_CYCLELEN_S  10
+/** SPI1_MEM_S_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
  *  The command value to wait flash idle(RDSR).
  */
-#define SPI_MEM_WAITI_CMD    0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_M  (SPI_MEM_WAITI_CMD_V << SPI_MEM_WAITI_CMD_S)
-#define SPI_MEM_WAITI_CMD_V  0x0000FFFFU
-#define SPI_MEM_WAITI_CMD_S  16
+#define SPI1_MEM_S_WAITI_CMD    0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_M  (SPI1_MEM_S_WAITI_CMD_V << SPI1_MEM_S_WAITI_CMD_S)
+#define SPI1_MEM_S_WAITI_CMD_V  0x0000FFFFU
+#define SPI1_MEM_S_WAITI_CMD_S  16
 
-/** SPI_MEM_FLASH_SUS_CTRL_REG register
+/** SPI1_MEM_S_FLASH_SUS_CTRL_REG register
  *  SPI1 flash suspend control register
  */
-#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c)
-/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_FLASH_SUS_CTRL_REG (DR_REG_PSRAM_MSPI1_BASE + 0x9c)
+/** SPI1_MEM_S_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
  *  program erase resume bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (SPI_MEM_FLASH_PER_V << SPI_MEM_FLASH_PER_S)
-#define SPI_MEM_FLASH_PER_V  0x00000001U
-#define SPI_MEM_FLASH_PER_S  0
-/** SPI_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_FLASH_PER    (BIT(0))
+#define SPI1_MEM_S_FLASH_PER_M  (SPI1_MEM_S_FLASH_PER_V << SPI1_MEM_S_FLASH_PER_S)
+#define SPI1_MEM_S_FLASH_PER_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_S  0
+/** SPI1_MEM_S_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
  *  program erase suspend bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
  *  disable.
  */
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (SPI_MEM_FLASH_PES_V << SPI_MEM_FLASH_PES_S)
-#define SPI_MEM_FLASH_PES_V  0x00000001U
-#define SPI_MEM_FLASH_PES_S  1
-/** SPI_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_S_FLASH_PES    (BIT(1))
+#define SPI1_MEM_S_FLASH_PES_M  (SPI1_MEM_S_FLASH_PES_V << SPI1_MEM_S_FLASH_PES_S)
+#define SPI1_MEM_S_FLASH_PES_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_S  1
+/** SPI1_MEM_S_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase resume command is sent. 0: SPI1 does not wait after program erase
  *  resume command is sent.
  */
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (SPI_MEM_FLASH_PER_WAIT_EN_V << SPI_MEM_FLASH_PER_WAIT_EN_S)
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/** SPI_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_M  (SPI1_MEM_S_FLASH_PER_WAIT_EN_V << SPI1_MEM_S_FLASH_PER_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_WAIT_EN_S  2
+/** SPI1_MEM_S_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
  *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
  *  suspend command is sent.
  */
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (SPI_MEM_FLASH_PES_WAIT_EN_V << SPI_MEM_FLASH_PES_WAIT_EN_S)
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/** SPI_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_M  (SPI1_MEM_S_FLASH_PES_WAIT_EN_V << SPI1_MEM_S_FLASH_PES_WAIT_EN_S)
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_WAIT_EN_S  3
+/** SPI1_MEM_S_PES_PER_EN : R/W; bitpos: [4]; default: 0;
  *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
  *  application should send PER after PES is done.
  */
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (SPI_MEM_PES_PER_EN_V << SPI_MEM_PES_PER_EN_S)
-#define SPI_MEM_PES_PER_EN_V  0x00000001U
-#define SPI_MEM_PES_PER_EN_S  4
-/** SPI_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
+#define SPI1_MEM_S_PES_PER_EN    (BIT(4))
+#define SPI1_MEM_S_PES_PER_EN_M  (SPI1_MEM_S_PES_PER_EN_V << SPI1_MEM_S_PES_PER_EN_S)
+#define SPI1_MEM_S_PES_PER_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_PER_EN_S  4
+/** SPI1_MEM_S_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
  *  Set this bit to enable Auto-suspending function.
  */
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (SPI_MEM_FLASH_PES_EN_V << SPI_MEM_FLASH_PES_EN_S)
-#define SPI_MEM_FLASH_PES_EN_V  0x00000001U
-#define SPI_MEM_FLASH_PES_EN_S  5
-/** SPI_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
+#define SPI1_MEM_S_FLASH_PES_EN    (BIT(5))
+#define SPI1_MEM_S_FLASH_PES_EN_M  (SPI1_MEM_S_FLASH_PES_EN_V << SPI1_MEM_S_FLASH_PES_EN_S)
+#define SPI1_MEM_S_FLASH_PES_EN_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_EN_S  5
+/** SPI1_MEM_S_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
  *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
  *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
  *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
- *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+ *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
  */
-#define SPI_MEM_PESR_END_MSK    0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_M  (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S)
-#define SPI_MEM_PESR_END_MSK_V  0x0000FFFFU
-#define SPI_MEM_PESR_END_MSK_S  6
-/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
+#define SPI1_MEM_S_PESR_END_MSK    0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_M  (SPI1_MEM_S_PESR_END_MSK_V << SPI1_MEM_S_PESR_END_MSK_S)
+#define SPI1_MEM_S_PESR_END_MSK_V  0x0000FFFFU
+#define SPI1_MEM_S_PESR_END_MSK_S  6
+/** SPI1_MEM_S_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
  *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
  *  check flash SUS/SUS1/SUS2 status bit
  */
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S)
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x00000001U
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
+#define SPI1_MEM_S_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_M  (SPI1_MEM_S_FMEM_RD_SUS_2B_V << SPI1_MEM_S_FMEM_RD_SUS_2B_S)
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_V  0x00000001U
+#define SPI1_MEM_S_FMEM_RD_SUS_2B_S  22
+/** SPI1_MEM_S_PER_END_EN : R/W; bitpos: [23]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
  *  flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (SPI_MEM_PER_END_EN_V << SPI_MEM_PER_END_EN_S)
-#define SPI_MEM_PER_END_EN_V  0x00000001U
-#define SPI_MEM_PER_END_EN_S  23
-/** SPI_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_PER_END_EN    (BIT(23))
+#define SPI1_MEM_S_PER_END_EN_M  (SPI1_MEM_S_PER_END_EN_V << SPI1_MEM_S_PER_END_EN_S)
+#define SPI1_MEM_S_PER_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PER_END_EN_S  23
+/** SPI1_MEM_S_PES_END_EN : R/W; bitpos: [24]; default: 0;
  *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
  *  of flash. 0: Only need to check WIP is 0.
  */
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (SPI_MEM_PES_END_EN_V << SPI_MEM_PES_END_EN_S)
-#define SPI_MEM_PES_END_EN_V  0x00000001U
-#define SPI_MEM_PES_END_EN_S  24
-/** SPI_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
- *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+#define SPI1_MEM_S_PES_END_EN    (BIT(24))
+#define SPI1_MEM_S_PES_END_EN_M  (SPI1_MEM_S_PES_END_EN_V << SPI1_MEM_S_PES_END_EN_S)
+#define SPI1_MEM_S_PES_END_EN_V  0x00000001U
+#define SPI1_MEM_S_PES_END_EN_S  24
+/** SPI1_MEM_S_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
+ *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
  *  will be treated as check pass.
  */
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  (SPI_MEM_SUS_TIMEOUT_CNT_V << SPI_MEM_SUS_TIMEOUT_CNT_S)
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT    0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_M  (SPI1_MEM_S_SUS_TIMEOUT_CNT_V << SPI1_MEM_S_SUS_TIMEOUT_CNT_S)
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_V  0x0000007FU
+#define SPI1_MEM_S_SUS_TIMEOUT_CNT_S  25
 
-/** SPI_MEM_FLASH_SUS_CMD_REG register
+/** SPI1_MEM_S_FLASH_SUS_CMD_REG register
  *  SPI1 flash suspend command register
  */
-#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0)
-/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
+#define SPI1_MEM_S_FLASH_SUS_CMD_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa0)
+/** SPI1_MEM_S_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
  *  Program/Erase suspend command.
  */
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_M  (SPI_MEM_FLASH_PES_COMMAND_V << SPI_MEM_FLASH_PES_COMMAND_S)
-#define SPI_MEM_FLASH_PES_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-/** SPI_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
+#define SPI1_MEM_S_FLASH_PES_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_M  (SPI1_MEM_S_FLASH_PES_COMMAND_V << SPI1_MEM_S_FLASH_PES_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PES_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PES_COMMAND_S  0
+/** SPI1_MEM_S_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
  *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
  *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
  */
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_M  (SPI_MEM_WAIT_PESR_COMMAND_V << SPI_MEM_WAIT_PESR_COMMAND_S)
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+#define SPI1_MEM_S_WAIT_PESR_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_M  (SPI1_MEM_S_WAIT_PESR_COMMAND_V << SPI1_MEM_S_WAIT_PESR_COMMAND_S)
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_WAIT_PESR_COMMAND_S  16
 
-/** SPI_MEM_SUS_STATUS_REG register
+/** SPI1_MEM_S_SUS_STATUS_REG register
  *  SPI1 flash suspend status register
  */
-#define SPI_MEM_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4)
-/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_SUS_STATUS_REG (DR_REG_PSRAM_MSPI1_BASE + 0xa4)
+/** SPI1_MEM_S_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
  *  The status of flash suspend, only used in SPI1.
  */
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (SPI_MEM_FLASH_SUS_V << SPI_MEM_FLASH_SUS_S)
-#define SPI_MEM_FLASH_SUS_V  0x00000001U
-#define SPI_MEM_FLASH_SUS_S  0
-/** SPI_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
- *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
- */
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (SPI_MEM_WAIT_PESR_CMD_2B_V << SPI_MEM_WAIT_PESR_CMD_2B_S)
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/** SPI_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_FLASH_SUS    (BIT(0))
+#define SPI1_MEM_S_FLASH_SUS_M  (SPI1_MEM_S_FLASH_SUS_V << SPI1_MEM_S_FLASH_SUS_S)
+#define SPI1_MEM_S_FLASH_SUS_V  0x00000001U
+#define SPI1_MEM_S_FLASH_SUS_S  0
+/** SPI1_MEM_S_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
+ *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+ */
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_M  (SPI1_MEM_S_WAIT_PESR_CMD_2B_V << SPI1_MEM_S_WAIT_PESR_CMD_2B_S)
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_WAIT_PESR_CMD_2B_S  1
+/** SPI1_MEM_S_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after HPM command is sent.
  */
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (SPI_MEM_FLASH_HPM_DLY_128_V << SPI_MEM_FLASH_HPM_DLY_128_S)
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/** SPI_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_M  (SPI1_MEM_S_FLASH_HPM_DLY_128_V << SPI1_MEM_S_FLASH_HPM_DLY_128_S)
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_HPM_DLY_128_S  2
+/** SPI1_MEM_S_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after RES command is sent.
  */
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (SPI_MEM_FLASH_RES_DLY_128_V << SPI_MEM_FLASH_RES_DLY_128_S)
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/** SPI_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
- *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
- *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+#define SPI1_MEM_S_FLASH_RES_DLY_128    (BIT(3))
+#define SPI1_MEM_S_FLASH_RES_DLY_128_M  (SPI1_MEM_S_FLASH_RES_DLY_128_V << SPI1_MEM_S_FLASH_RES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_RES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_RES_DLY_128_S  3
+/** SPI1_MEM_S_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
+ *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+ *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
  *  after DP command is sent.
  */
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (SPI_MEM_FLASH_DP_DLY_128_V << SPI_MEM_FLASH_DP_DLY_128_S)
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/** SPI_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
- *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+#define SPI1_MEM_S_FLASH_DP_DLY_128    (BIT(4))
+#define SPI1_MEM_S_FLASH_DP_DLY_128_M  (SPI1_MEM_S_FLASH_DP_DLY_128_V << SPI1_MEM_S_FLASH_DP_DLY_128_S)
+#define SPI1_MEM_S_FLASH_DP_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_DP_DLY_128_S  4
+/** SPI1_MEM_S_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (SPI_MEM_FLASH_PER_DLY_128_V << SPI_MEM_FLASH_PER_DLY_128_S)
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/** SPI_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
- *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
- *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+#define SPI1_MEM_S_FLASH_PER_DLY_128    (BIT(5))
+#define SPI1_MEM_S_FLASH_PER_DLY_128_M  (SPI1_MEM_S_FLASH_PER_DLY_128_V << SPI1_MEM_S_FLASH_PER_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PER_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PER_DLY_128_S  5
+/** SPI1_MEM_S_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
+ *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+ *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+ *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
  *  sent.
  */
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (SPI_MEM_FLASH_PES_DLY_128_V << SPI_MEM_FLASH_PES_DLY_128_S)
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x00000001U
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/** SPI_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
+#define SPI1_MEM_S_FLASH_PES_DLY_128    (BIT(6))
+#define SPI1_MEM_S_FLASH_PES_DLY_128_M  (SPI1_MEM_S_FLASH_PES_DLY_128_V << SPI1_MEM_S_FLASH_PES_DLY_128_S)
+#define SPI1_MEM_S_FLASH_PES_DLY_128_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PES_DLY_128_S  6
+/** SPI1_MEM_S_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
  *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
  */
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (SPI_MEM_SPI0_LOCK_EN_V << SPI_MEM_SPI0_LOCK_EN_S)
-#define SPI_MEM_SPI0_LOCK_EN_V  0x00000001U
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/** SPI_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
+#define SPI1_MEM_S_SPI0_LOCK_EN    (BIT(7))
+#define SPI1_MEM_S_SPI0_LOCK_EN_M  (SPI1_MEM_S_SPI0_LOCK_EN_V << SPI1_MEM_S_SPI0_LOCK_EN_S)
+#define SPI1_MEM_S_SPI0_LOCK_EN_V  0x00000001U
+#define SPI1_MEM_S_SPI0_LOCK_EN_S  7
+/** SPI1_MEM_S_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
  *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
  *  of Program/Erase Suspend/Resume command is 8.
  */
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (SPI_MEM_FLASH_PESR_CMD_2B_V << SPI_MEM_FLASH_PESR_CMD_2B_S)
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x00000001U
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/** SPI_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_M  (SPI1_MEM_S_FLASH_PESR_CMD_2B_V << SPI1_MEM_S_FLASH_PESR_CMD_2B_S)
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_V  0x00000001U
+#define SPI1_MEM_S_FLASH_PESR_CMD_2B_S  15
+/** SPI1_MEM_S_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
  *  Program/Erase resume command.
  */
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_M  (SPI_MEM_FLASH_PER_COMMAND_V << SPI_MEM_FLASH_PER_COMMAND_S)
-#define SPI_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
+#define SPI1_MEM_S_FLASH_PER_COMMAND    0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_M  (SPI1_MEM_S_FLASH_PER_COMMAND_V << SPI1_MEM_S_FLASH_PER_COMMAND_S)
+#define SPI1_MEM_S_FLASH_PER_COMMAND_V  0x0000FFFFU
+#define SPI1_MEM_S_FLASH_PER_COMMAND_S  16
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI1_MEM_S_INT_ENA_REG register
  *  SPI1 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0)
-/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (SPI_MEM_PER_END_INT_ENA_V << SPI_MEM_PER_END_INT_ENA_S)
-#define SPI_MEM_PER_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ENA_S  0
-/** SPI_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (SPI_MEM_PES_END_INT_ENA_V << SPI_MEM_PES_END_INT_ENA_S)
-#define SPI_MEM_PES_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/** SPI_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (SPI_MEM_WPE_END_INT_ENA_V << SPI_MEM_WPE_END_INT_ENA_S)
-#define SPI_MEM_WPE_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (SPI_MEM_BROWN_OUT_INT_ENA_V << SPI_MEM_BROWN_OUT_INT_ENA_S)
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+#define SPI1_MEM_S_INT_ENA_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc0)
+/** SPI1_MEM_S_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_ENA    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ENA_M  (SPI1_MEM_S_PER_END_INT_ENA_V << SPI1_MEM_S_PER_END_INT_ENA_S)
+#define SPI1_MEM_S_PER_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ENA_S  0
+/** SPI1_MEM_S_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_ENA    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ENA_M  (SPI1_MEM_S_PES_END_INT_ENA_V << SPI1_MEM_S_PES_END_INT_ENA_S)
+#define SPI1_MEM_S_PES_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ENA_S  1
+/** SPI1_MEM_S_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_ENA    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ENA_M  (SPI1_MEM_S_WPE_END_INT_ENA_V << SPI1_MEM_S_WPE_END_INT_ENA_S)
+#define SPI1_MEM_S_WPE_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ENA_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_M  (SPI1_MEM_S_SLV_ST_END_INT_ENA_V << SPI1_MEM_S_SLV_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ENA_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_M  (SPI1_MEM_S_MST_ST_END_INT_ENA_V << SPI1_MEM_S_MST_ST_END_INT_ENA_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ENA_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_M  (SPI1_MEM_S_BROWN_OUT_INT_ENA_V << SPI1_MEM_S_BROWN_OUT_INT_ENA_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ENA_S  10
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI1_MEM_S_INT_CLR_REG register
  *  SPI1 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4)
-/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (SPI_MEM_PER_END_INT_CLR_V << SPI_MEM_PER_END_INT_CLR_S)
-#define SPI_MEM_PER_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PER_END_INT_CLR_S  0
-/** SPI_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (SPI_MEM_PES_END_INT_CLR_V << SPI_MEM_PES_END_INT_CLR_S)
-#define SPI_MEM_PES_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/** SPI_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (SPI_MEM_WPE_END_INT_CLR_V << SPI_MEM_WPE_END_INT_CLR_S)
-#define SPI_MEM_WPE_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (SPI_MEM_BROWN_OUT_INT_CLR_V << SPI_MEM_BROWN_OUT_INT_CLR_S)
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+#define SPI1_MEM_S_INT_CLR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc4)
+/** SPI1_MEM_S_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_CLR    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_CLR_M  (SPI1_MEM_S_PER_END_INT_CLR_V << SPI1_MEM_S_PER_END_INT_CLR_S)
+#define SPI1_MEM_S_PER_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_CLR_S  0
+/** SPI1_MEM_S_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_CLR    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_CLR_M  (SPI1_MEM_S_PES_END_INT_CLR_V << SPI1_MEM_S_PES_END_INT_CLR_S)
+#define SPI1_MEM_S_PES_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_CLR_S  1
+/** SPI1_MEM_S_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_CLR    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_CLR_M  (SPI1_MEM_S_WPE_END_INT_CLR_V << SPI1_MEM_S_WPE_END_INT_CLR_S)
+#define SPI1_MEM_S_WPE_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_CLR_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_M  (SPI1_MEM_S_SLV_ST_END_INT_CLR_V << SPI1_MEM_S_SLV_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_CLR_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_M  (SPI1_MEM_S_MST_ST_END_INT_CLR_V << SPI1_MEM_S_MST_ST_END_INT_CLR_S)
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_CLR_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_M  (SPI1_MEM_S_BROWN_OUT_INT_CLR_V << SPI1_MEM_S_BROWN_OUT_INT_CLR_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_CLR_S  10
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI1_MEM_S_INT_RAW_REG register
  *  SPI1 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8)
-/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+#define SPI1_MEM_S_INT_RAW_REG (DR_REG_PSRAM_MSPI1_BASE + 0xc8)
+/** SPI1_MEM_S_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
  *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
  */
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (SPI_MEM_PER_END_INT_RAW_V << SPI_MEM_PER_END_INT_RAW_S)
-#define SPI_MEM_PER_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PER_END_INT_RAW_S  0
-/** SPI_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+#define SPI1_MEM_S_PER_END_INT_RAW    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_RAW_M  (SPI1_MEM_S_PER_END_INT_RAW_V << SPI1_MEM_S_PER_END_INT_RAW_S)
+#define SPI1_MEM_S_PER_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_RAW_S  0
+/** SPI1_MEM_S_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
  *  command (0x75) is sent and flash is suspended successfully. 0: Others.
  */
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (SPI_MEM_PES_END_INT_RAW_V << SPI_MEM_PES_END_INT_RAW_S)
-#define SPI_MEM_PES_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/** SPI_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+#define SPI1_MEM_S_PES_END_INT_RAW    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_RAW_M  (SPI1_MEM_S_PES_END_INT_RAW_V << SPI1_MEM_S_PES_END_INT_RAW_S)
+#define SPI1_MEM_S_PES_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_RAW_S  1
+/** SPI1_MEM_S_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
  *  is sent and flash is already idle. 0: Others.
  */
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (SPI_MEM_WPE_END_INT_RAW_V << SPI_MEM_WPE_END_INT_RAW_S)
-#define SPI_MEM_WPE_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+#define SPI1_MEM_S_WPE_END_INT_RAW    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_RAW_M  (SPI1_MEM_S_WPE_END_INT_RAW_V << SPI1_MEM_S_WPE_END_INT_RAW_S)
+#define SPI1_MEM_S_WPE_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_RAW_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
  *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
  *  Others
  */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_M  (SPI1_MEM_S_SLV_ST_END_INT_RAW_V << SPI1_MEM_S_SLV_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_RAW_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
  *  changed from non idle state to idle state. 0: Others.
  */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+#define SPI1_MEM_S_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_M  (SPI1_MEM_S_MST_ST_END_INT_RAW_V << SPI1_MEM_S_MST_ST_END_INT_RAW_S)
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_RAW_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
  *  chip is loosing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (SPI_MEM_BROWN_OUT_INT_RAW_V << SPI_MEM_BROWN_OUT_INT_RAW_S)
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_M  (SPI1_MEM_S_BROWN_OUT_INT_RAW_V << SPI1_MEM_S_BROWN_OUT_INT_RAW_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_RAW_S  10
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI1_MEM_S_INT_ST_REG register
  *  SPI1 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc)
-/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_MEM_PER_END_INT interrupt.
- */
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (SPI_MEM_PER_END_INT_ST_V << SPI_MEM_PER_END_INT_ST_S)
-#define SPI_MEM_PER_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PER_END_INT_ST_S  0
-/** SPI_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_MEM_PES_END_INT interrupt.
- */
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (SPI_MEM_PES_END_INT_ST_V << SPI_MEM_PES_END_INT_ST_S)
-#define SPI_MEM_PES_END_INT_ST_V  0x00000001U
-#define SPI_MEM_PES_END_INT_ST_S  1
-/** SPI_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI_MEM_WPE_END_INT interrupt.
- */
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (SPI_MEM_WPE_END_INT_ST_V << SPI_MEM_WPE_END_INT_ST_S)
-#define SPI_MEM_WPE_END_INT_ST_V  0x00000001U
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (SPI_MEM_BROWN_OUT_INT_ST_V << SPI_MEM_BROWN_OUT_INT_ST_S)
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x00000001U
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+#define SPI1_MEM_S_INT_ST_REG (DR_REG_PSRAM_MSPI1_BASE + 0xcc)
+/** SPI1_MEM_S_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PER_END_INT_ST    (BIT(0))
+#define SPI1_MEM_S_PER_END_INT_ST_M  (SPI1_MEM_S_PER_END_INT_ST_V << SPI1_MEM_S_PER_END_INT_ST_S)
+#define SPI1_MEM_S_PER_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PER_END_INT_ST_S  0
+/** SPI1_MEM_S_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
+ */
+#define SPI1_MEM_S_PES_END_INT_ST    (BIT(1))
+#define SPI1_MEM_S_PES_END_INT_ST_M  (SPI1_MEM_S_PES_END_INT_ST_V << SPI1_MEM_S_PES_END_INT_ST_S)
+#define SPI1_MEM_S_PES_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_PES_END_INT_ST_S  1
+/** SPI1_MEM_S_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
+ */
+#define SPI1_MEM_S_WPE_END_INT_ST    (BIT(2))
+#define SPI1_MEM_S_WPE_END_INT_ST_M  (SPI1_MEM_S_WPE_END_INT_ST_V << SPI1_MEM_S_WPE_END_INT_ST_S)
+#define SPI1_MEM_S_WPE_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_WPE_END_INT_ST_S  2
+/** SPI1_MEM_S_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_M  (SPI1_MEM_S_SLV_ST_END_INT_ST_V << SPI1_MEM_S_SLV_ST_END_INT_ST_S)
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_SLV_ST_END_INT_ST_S  3
+/** SPI1_MEM_S_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
+ */
+#define SPI1_MEM_S_MST_ST_END_INT_ST    (BIT(4))
+#define SPI1_MEM_S_MST_ST_END_INT_ST_M  (SPI1_MEM_S_MST_ST_END_INT_ST_V << SPI1_MEM_S_MST_ST_END_INT_ST_S)
+#define SPI1_MEM_S_MST_ST_END_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_MST_ST_END_INT_ST_S  4
+/** SPI1_MEM_S_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
+ */
+#define SPI1_MEM_S_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_M  (SPI1_MEM_S_BROWN_OUT_INT_ST_V << SPI1_MEM_S_BROWN_OUT_INT_ST_S)
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_V  0x00000001U
+#define SPI1_MEM_S_BROWN_OUT_INT_ST_S  10
 
-/** SPI_MEM_DDR_REG register
+/** SPI1_MEM_S_DDR_REG register
  *  SPI1 DDR control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4)
-/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
+#define SPI1_MEM_S_DDR_REG (DR_REG_PSRAM_MSPI1_BASE + 0xd4)
+/** SPI1_MEM_S_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
  *  1: in ddr mode,  0 in sdr mode
  */
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S)
-#define SPI_MEM_FMEM_DDR_EN_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_EN_S  0
-/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_EN    (BIT(0))
+#define SPI1_MEM_S_FMEM_DDR_EN_M  (SPI1_MEM_S_FMEM_DDR_EN_V << SPI1_MEM_S_FMEM_DDR_EN_S)
+#define SPI1_MEM_S_FMEM_DDR_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_EN_S  0
+/** SPI1_MEM_S_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0;
  *  Set the bit to enable variable dummy cycle in spi ddr mode.
  */
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S)
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
+#define SPI1_MEM_S_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_M  (SPI1_MEM_S_FMEM_VAR_DUMMY_V << SPI1_MEM_S_FMEM_VAR_DUMMY_S)
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_V  0x00000001U
+#define SPI1_MEM_S_FMEM_VAR_DUMMY_S  1
+/** SPI1_MEM_S_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0;
  *  Set the bit to reorder rx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_RDAT_SWP_S  2
+/** SPI1_MEM_S_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0;
  *  Set the bit to reorder tx data of the word in spi ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S)
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_M  (SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V << SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S)
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_WDAT_SWP_S  3
+/** SPI1_MEM_S_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0;
  *  the bit is used to disable dual edge in command phase when ddr mode.
  */
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S)
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_M  (SPI1_MEM_S_FMEM_DDR_CMD_DIS_V << SPI1_MEM_S_FMEM_DDR_CMD_DIS_S)
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_CMD_DIS_S  4
+/** SPI1_MEM_S_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1;
  *  It is the minimum output data length in the panda device.
  */
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S)
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN    0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_M  (SPI1_MEM_S_FMEM_OUTMINBYTELEN_V << SPI1_MEM_S_FMEM_OUTMINBYTELEN_S)
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_OUTMINBYTELEN_S  5
+/** SPI1_MEM_S_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0;
  *  The delay number of data strobe which from memory based on SPI clock.
  */
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD    0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_M  (SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V << SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S)
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
+#define SPI1_MEM_S_FMEM_USR_DDR_DQS_THD_S  14
+/** SPI1_MEM_S_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0;
  *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+ *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
  *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
  *  negative edge of SPI_DQS.
  */
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S)
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_M  (SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V << SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S)
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DDR_DQS_LOOP_S  21
+/** SPI1_MEM_S_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0;
  *  Set this bit to enable the differential SPI_CLK#.
  */
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S)
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_M  (SPI1_MEM_S_FMEM_CLK_DIFF_EN_V << SPI1_MEM_S_FMEM_CLK_DIFF_EN_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_EN_S  24
+/** SPI1_MEM_S_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0;
  *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  */
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S)
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
+#define SPI1_MEM_S_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_M  (SPI1_MEM_S_FMEM_DQS_CA_IN_V << SPI1_MEM_S_FMEM_DQS_CA_IN_S)
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_V  0x00000001U
+#define SPI1_MEM_S_FMEM_DQS_CA_IN_S  26
+/** SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0;
  *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
  *  accesses flash or SPI1 accesses flash or sram.
  */
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V << SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_DUMMY_2X_S  27
+/** SPI1_MEM_S_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0;
  *  Set this bit to invert SPI_DIFF when accesses to flash. .
  */
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S)
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_M  (SPI1_MEM_S_FMEM_CLK_DIFF_INV_V << SPI1_MEM_S_FMEM_CLK_DIFF_INV_S)
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_V  0x00000001U
+#define SPI1_MEM_S_FMEM_CLK_DIFF_INV_S  28
+/** SPI1_MEM_S_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0;
  *  Set this bit to enable octa_ram address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
  */
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_M  (SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V << SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S)
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_V  0x00000001U
+#define SPI1_MEM_S_FMEM_OCTA_RAM_ADDR_S  29
+/** SPI1_MEM_S_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0;
  *  Set this bit to enable HyperRAM address out when accesses to flash, which means
  *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
  */
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S)
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_M  (SPI1_MEM_S_FMEM_HYPERBUS_CA_V << SPI1_MEM_S_FMEM_HYPERBUS_CA_S)
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_V  0x00000001U
+#define SPI1_MEM_S_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI1_MEM_S_TIMING_CALI_REG register
  *  SPI1 timing control register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180)
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
+#define SPI1_MEM_S_TIMING_CALI_REG (DR_REG_PSRAM_MSPI1_BASE + 0x180)
+/** SPI1_MEM_S_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
+#define SPI1_MEM_S_TIMING_CALI    (BIT(1))
+#define SPI1_MEM_S_TIMING_CALI_M  (SPI1_MEM_S_TIMING_CALI_V << SPI1_MEM_S_TIMING_CALI_S)
+#define SPI1_MEM_S_TIMING_CALI_V  0x00000001U
+#define SPI1_MEM_S_TIMING_CALI_S  1
+/** SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
  *  add extra dummy spi clock cycle length for spi clock calibration.
  */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN    0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S)
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
+#define SPI1_MEM_S_EXTRA_DUMMY_CYCLELEN_S  2
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI1_MEM_S_CLOCK_GATE_REG register
  *  SPI1 clk_gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200)
-/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+#define SPI1_MEM_S_CLOCK_GATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x200)
+/** SPI1_MEM_S_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (SPI_MEM_CLK_EN_V << SPI_MEM_CLK_EN_S)
-#define SPI_MEM_CLK_EN_V  0x00000001U
-#define SPI_MEM_CLK_EN_S  0
+#define SPI1_MEM_S_CLK_EN    (BIT(0))
+#define SPI1_MEM_S_CLK_EN_M  (SPI1_MEM_S_CLK_EN_V << SPI1_MEM_S_CLK_EN_S)
+#define SPI1_MEM_S_CLK_EN_V  0x00000001U
+#define SPI1_MEM_S_CLK_EN_S  0
 
-/** SPI_MEM_DATE_REG register
+/** SPI1_MEM_S_DATE_REG register
  *  Version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 34673216;
+#define SPI1_MEM_S_DATE_REG (DR_REG_PSRAM_MSPI1_BASE + 0x3fc)
+/** SPI1_MEM_S_DATE : R/W; bitpos: [27:0]; default: 34673216;
  *  Version control register
  */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
+#define SPI1_MEM_S_DATE    0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_M  (SPI1_MEM_S_DATE_V << SPI1_MEM_S_DATE_S)
+#define SPI1_MEM_S_DATE_V  0x0FFFFFFFU
+#define SPI1_MEM_S_DATE_S  0
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/spi1_mem_s_struct.h

@@ -29,7 +29,7 @@ typedef union {
         uint32_t reserved_8:9;
         /** flash_pe : R/W/SC; bitpos: [17]; default: 0;
          *  In user mode, it is set to indicate that program/erase operation will be triggered.
-         *  The bit is combined with spi_mem_usr bit. The bit will be cleared once the
+         *  The bit is combined with spi1_mem_s_usr bit. The bit will be cleared once the
          *  operation done.1: enable 0: disable.
          */
         uint32_t flash_pe:1;
@@ -107,7 +107,7 @@ typedef union {
         uint32_t flash_read:1;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi1_mem_s_cmd_reg_t;
 
 /** Type of addr register
  *  SPI1 address register
@@ -121,7 +121,7 @@ typedef union {
         uint32_t usr_addr_value:32;
     };
     uint32_t val;
-} spi_mem_addr_reg_t;
+} spi1_mem_s_addr_reg_t;
 
 /** Type of user register
  *  SPI1 user register.
@@ -130,7 +130,7 @@ typedef union {
     struct {
         uint32_t reserved_0:9;
         /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+         *  the bit combined with spi1_mem_s_mosi_delay_mode bits to set mosi signal delay mode.
          */
         uint32_t ck_out_edge:1;
         uint32_t reserved_10:2;
@@ -152,12 +152,12 @@ typedef union {
         uint32_t fwrite_qio:1;
         uint32_t reserved_16:8;
         /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  read-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_miso_highpart:1;
         /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1:
+         *  write-data phase only access to high-part of the buffer spi1_mem_s_w8~spi1_mem_s_w15. 1:
          *  enable 0: disable.
          */
         uint32_t usr_mosi_highpart:1;
@@ -187,7 +187,7 @@ typedef union {
         uint32_t usr_command:1;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi1_mem_s_user_reg_t;
 
 /** Type of user1 register
  *  SPI1 user1 register.
@@ -195,7 +195,7 @@ typedef union {
 typedef union {
     struct {
         /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi1_mem_s_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t usr_dummy_cyclelen:6;
@@ -206,7 +206,7 @@ typedef union {
         uint32_t usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi1_mem_s_user1_reg_t;
 
 /** Type of user2 register
  *  SPI1 user2 register.
@@ -224,7 +224,7 @@ typedef union {
         uint32_t usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi1_mem_s_user2_reg_t;
 
 
 /** Group: Control and configuration registers */
@@ -276,8 +276,8 @@ typedef union {
         uint32_t tx_crc_en:1;
         uint32_t reserved_12:1;
         /** fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
-         *  and spi_mem_fread_dout. 1: enable 0: disable.
+         *  This bit enable the bits: spi1_mem_s_fread_qio, spi1_mem_s_fread_dio, spi1_mem_s_fread_qout
+         *  and spi1_mem_s_fread_dout. 1: enable 0: disable.
          */
         uint32_t fastrd_mode:1;
         /** fread_dual : R/W; bitpos: [14]; default: 0;
@@ -285,8 +285,8 @@ typedef union {
          */
         uint32_t fread_dual:1;
         /** resandres : R/W; bitpos: [15]; default: 1;
-         *  The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-         *  spi_mem_flash_res bit. 1: enable 0: disable.
+         *  The Device ID is read out to SPI1_MEM_S_RD_STATUS register,  this bit combine with
+         *  spi1_mem_s_flash_res bit. 1: enable 0: disable.
          */
         uint32_t resandres:1;
         uint32_t reserved_16:2;
@@ -324,7 +324,7 @@ typedef union {
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi1_mem_s_ctrl_reg_t;
 
 /** Type of ctrl1 register
  *  SPI1 control1 register.
@@ -338,14 +338,14 @@ typedef union {
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
-         *  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512)
+         *  After RES/DP/HPM command is sent, SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 512)
          *  SPI_CLK cycles.
          */
         uint32_t cs_hold_dly_res:10;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi1_mem_s_ctrl1_reg_t;
 
 /** Type of ctrl2 register
  *  SPI1 control2 register.
@@ -359,7 +359,7 @@ typedef union {
         uint32_t sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi1_mem_s_ctrl2_reg_t;
 
 /** Type of clock register
  *  SPI1 clock division control register.
@@ -367,16 +367,16 @@ typedef union {
 typedef union {
     struct {
         /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi1_mem_s_clkcnt_N.
          */
         uint32_t clkcnt_l:8;
         /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi1_mem_s_clkcnt_N+1)/2-1).
          */
         uint32_t clkcnt_h:8;
         /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi1_mem_s_clk. So spi1_mem_s_clk frequency is
+         *  system/(spi1_mem_s_clkcnt_N+1)
          */
         uint32_t clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -386,7 +386,7 @@ typedef union {
         uint32_t clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi1_mem_s_clock_reg_t;
 
 /** Type of mosi_dlen register
  *  SPI1 send data bit length control register.
@@ -400,7 +400,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_mosi_dlen_reg_t;
+} spi1_mem_s_mosi_dlen_reg_t;
 
 /** Type of miso_dlen register
  *  SPI1 receive data bit length control register.
@@ -414,7 +414,7 @@ typedef union {
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_miso_dlen_reg_t;
+} spi1_mem_s_miso_dlen_reg_t;
 
 /** Type of rd_status register
  *  SPI1 status register.
@@ -422,17 +422,17 @@ typedef union {
 typedef union {
     struct {
         /** status : R/W/SS; bitpos: [15:0]; default: 0;
-         *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+         *  The value is stored when set spi1_mem_s_flash_rdsr bit and spi1_mem_s_flash_res bit.
          */
         uint32_t status:16;
         /** wb_mode : R/W; bitpos: [23:16]; default: 0;
-         *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+         *  Mode bits in the flash fast read mode  it is combined with spi1_mem_s_fastrd_mode bit.
          */
         uint32_t wb_mode:8;
         uint32_t reserved_24:8;
     };
     uint32_t val;
-} spi_mem_rd_status_reg_t;
+} spi1_mem_s_rd_status_reg_t;
 
 /** Type of misc register
  *  SPI1 misc register
@@ -461,7 +461,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi1_mem_s_misc_reg_t;
 
 /** Type of cache_fctrl register
  *  SPI1 bit mode control register.
@@ -476,38 +476,38 @@ typedef union {
         uint32_t reserved_2:1;
         /** fdin_dual : R/W; bitpos: [3]; default: 0;
          *  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with
-         *  spi_mem_fread_dio.
+         *  spi1_mem_s_fread_dio.
          */
         uint32_t fdin_dual:1;
         /** fdout_dual : R/W; bitpos: [4]; default: 0;
          *  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_s_fread_dio.
          */
         uint32_t fdout_dual:1;
         /** faddr_dual : R/W; bitpos: [5]; default: 0;
          *  For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_dio.
+         *  with spi1_mem_s_fread_dio.
          */
         uint32_t faddr_dual:1;
         /** fdin_quad : R/W; bitpos: [6]; default: 0;
          *  For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t fdin_quad:1;
         /** fdout_quad : R/W; bitpos: [7]; default: 0;
          *  For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t fdout_quad:1;
         /** faddr_quad : R/W; bitpos: [8]; default: 0;
          *  For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same
-         *  with spi_mem_fread_qio.
+         *  with spi1_mem_s_fread_qio.
          */
         uint32_t faddr_quad:1;
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi1_mem_s_cache_fctrl_reg_t;
 
 /** Type of flash_waiti_ctrl register
  *  SPI1 wait idle control register
@@ -530,9 +530,9 @@ typedef union {
          */
         uint32_t waiti_addr_en:1;
         /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
-         *  When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
-         *  (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-         *  SPI_MEM_WAITI_ADDR_EN is cleared.
+         *  When SPI1_MEM_S_WAITI_ADDR_EN is set, the  cycle length of sent out address is
+         *  (SPI1_MEM_S_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+         *  SPI1_MEM_S_WAITI_ADDR_EN is cleared.
          */
         uint32_t waiti_addr_cyclelen:2;
         uint32_t reserved_5:4;
@@ -550,7 +550,7 @@ typedef union {
         uint32_t waiti_cmd:16;
     };
     uint32_t val;
-} spi_mem_flash_waiti_ctrl_reg_t;
+} spi1_mem_s_flash_waiti_ctrl_reg_t;
 
 /** Type of flash_sus_ctrl register
  *  SPI1 flash suspend control register
@@ -570,13 +570,13 @@ typedef union {
          */
         uint32_t flash_pes:1;
         /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase resume command is sent. 0: SPI1 does not wait after program erase
          *  resume command is sent.
          */
         uint32_t flash_per_wait_en:1;
         /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
          *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
          *  suspend command is sent.
          */
@@ -594,7 +594,7 @@ typedef union {
          *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
          *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
          *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
-         *  status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+         *  status_in[15:0]^ SPI1_MEM_S_PESR_END_MSK[15:0].
          */
         uint32_t pesr_end_msk:16;
         /** fmem_rd_sus_2b : R/W; bitpos: [22]; default: 0;
@@ -613,13 +613,13 @@ typedef union {
          */
         uint32_t pes_end_en:1;
         /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
-         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it
+         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_S_SUS_TIMEOUT_CNT[6:0] times, it
          *  will be treated as check pass.
          */
         uint32_t sus_timeout_cnt:7;
     };
     uint32_t val;
-} spi_mem_flash_sus_ctrl_reg_t;
+} spi1_mem_s_flash_sus_ctrl_reg_t;
 
 /** Type of flash_sus_cmd register
  *  SPI1 flash suspend command register
@@ -637,7 +637,7 @@ typedef union {
         uint32_t wait_pesr_command:16;
     };
     uint32_t val;
-} spi_mem_flash_sus_cmd_reg_t;
+} spi1_mem_s_flash_sus_cmd_reg_t;
 
 /** Type of sus_status register
  *  SPI1 flash suspend status register
@@ -649,39 +649,39 @@ typedef union {
          */
         uint32_t flash_sus:1;
         /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
-         *  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-         *  SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+         *  1: SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+         *  SPI1 sends out SPI1_MEM_S_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
          */
         uint32_t wait_pesr_cmd_2b:1;
         /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after HPM command is sent.
          */
         uint32_t flash_hpm_dly_128:1;
         /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after RES command is sent.
          */
         uint32_t flash_res_dly_128:1;
         /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
-         *  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-         *  command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+         *  1: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+         *  command is sent. 0: SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
          *  after DP command is sent.
          */
         uint32_t flash_dp_dly_128:1;
         /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
+         *  Valid when SPI1_MEM_S_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is
          *  sent.
          */
         uint32_t flash_per_dly_128:1;
         /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
-         *  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
-         *  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
+         *  Valid when SPI1_MEM_S_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+         *  (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0:
+         *  SPI1 waits (SPI1_MEM_S_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is
          *  sent.
          */
         uint32_t flash_pes_dly_128:1;
@@ -701,7 +701,7 @@ typedef union {
         uint32_t flash_per_command:16;
     };
     uint32_t val;
-} spi_mem_sus_status_reg_t;
+} spi1_mem_s_sus_status_reg_t;
 
 /** Type of ddr register
  *  SPI1 DDR control register
@@ -739,7 +739,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in SPI1_MEM_S_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -776,7 +776,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi1_mem_s_ddr_reg_t;
 
 /** Type of clock_gate register
  *  SPI1 clk_gate register
@@ -790,7 +790,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi1_mem_s_clock_gate_reg_t;
 
 
 /** Group: Status register */
@@ -805,7 +805,7 @@ typedef union {
         uint32_t tx_crc_data:32;
     };
     uint32_t val;
-} spi_mem_tx_crc_reg_t;
+} spi1_mem_s_tx_crc_reg_t;
 
 
 /** Group: Memory data buffer register */
@@ -820,7 +820,7 @@ typedef union {
         uint32_t buf0:32;
     };
     uint32_t val;
-} spi_mem_w0_reg_t;
+} spi1_mem_s_w0_reg_t;
 
 /** Type of w1 register
  *  SPI1 memory data buffer1
@@ -833,7 +833,7 @@ typedef union {
         uint32_t buf1:32;
     };
     uint32_t val;
-} spi_mem_w1_reg_t;
+} spi1_mem_s_w1_reg_t;
 
 /** Type of w2 register
  *  SPI1 memory data buffer2
@@ -846,7 +846,7 @@ typedef union {
         uint32_t buf2:32;
     };
     uint32_t val;
-} spi_mem_w2_reg_t;
+} spi1_mem_s_w2_reg_t;
 
 /** Type of w3 register
  *  SPI1 memory data buffer3
@@ -859,7 +859,7 @@ typedef union {
         uint32_t buf3:32;
     };
     uint32_t val;
-} spi_mem_w3_reg_t;
+} spi1_mem_s_w3_reg_t;
 
 /** Type of w4 register
  *  SPI1 memory data buffer4
@@ -872,7 +872,7 @@ typedef union {
         uint32_t buf4:32;
     };
     uint32_t val;
-} spi_mem_w4_reg_t;
+} spi1_mem_s_w4_reg_t;
 
 /** Type of w5 register
  *  SPI1 memory data buffer5
@@ -885,7 +885,7 @@ typedef union {
         uint32_t buf5:32;
     };
     uint32_t val;
-} spi_mem_w5_reg_t;
+} spi1_mem_s_w5_reg_t;
 
 /** Type of w6 register
  *  SPI1 memory data buffer6
@@ -898,7 +898,7 @@ typedef union {
         uint32_t buf6:32;
     };
     uint32_t val;
-} spi_mem_w6_reg_t;
+} spi1_mem_s_w6_reg_t;
 
 /** Type of w7 register
  *  SPI1 memory data buffer7
@@ -911,7 +911,7 @@ typedef union {
         uint32_t buf7:32;
     };
     uint32_t val;
-} spi_mem_w7_reg_t;
+} spi1_mem_s_w7_reg_t;
 
 /** Type of w8 register
  *  SPI1 memory data buffer8
@@ -924,7 +924,7 @@ typedef union {
         uint32_t buf8:32;
     };
     uint32_t val;
-} spi_mem_w8_reg_t;
+} spi1_mem_s_w8_reg_t;
 
 /** Type of w9 register
  *  SPI1 memory data buffer9
@@ -937,7 +937,7 @@ typedef union {
         uint32_t buf9:32;
     };
     uint32_t val;
-} spi_mem_w9_reg_t;
+} spi1_mem_s_w9_reg_t;
 
 /** Type of w10 register
  *  SPI1 memory data buffer10
@@ -950,7 +950,7 @@ typedef union {
         uint32_t buf10:32;
     };
     uint32_t val;
-} spi_mem_w10_reg_t;
+} spi1_mem_s_w10_reg_t;
 
 /** Type of w11 register
  *  SPI1 memory data buffer11
@@ -963,7 +963,7 @@ typedef union {
         uint32_t buf11:32;
     };
     uint32_t val;
-} spi_mem_w11_reg_t;
+} spi1_mem_s_w11_reg_t;
 
 /** Type of w12 register
  *  SPI1 memory data buffer12
@@ -976,7 +976,7 @@ typedef union {
         uint32_t buf12:32;
     };
     uint32_t val;
-} spi_mem_w12_reg_t;
+} spi1_mem_s_w12_reg_t;
 
 /** Type of w13 register
  *  SPI1 memory data buffer13
@@ -989,7 +989,7 @@ typedef union {
         uint32_t buf13:32;
     };
     uint32_t val;
-} spi_mem_w13_reg_t;
+} spi1_mem_s_w13_reg_t;
 
 /** Type of w14 register
  *  SPI1 memory data buffer14
@@ -1002,7 +1002,7 @@ typedef union {
         uint32_t buf14:32;
     };
     uint32_t val;
-} spi_mem_w14_reg_t;
+} spi1_mem_s_w14_reg_t;
 
 /** Type of w15 register
  *  SPI1 memory data buffer15
@@ -1015,7 +1015,7 @@ typedef union {
         uint32_t buf15:32;
     };
     uint32_t val;
-} spi_mem_w15_reg_t;
+} spi1_mem_s_w15_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -1025,34 +1025,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_MEM_PER_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_ena:1;
         /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_MEM_PES_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_ena:1;
         /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_ena:1;
         /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_ena:1;
         /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_ena:1;
         uint32_t reserved_5:5;
         /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The enable bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_ena:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi1_mem_s_int_ena_reg_t;
 
 /** Type of int_clr register
  *  SPI1 interrupt clear register
@@ -1060,34 +1060,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_MEM_PER_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_clr:1;
         /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_MEM_PES_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_clr:1;
         /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_clr:1;
         /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_clr:1;
         /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_clr:1;
         uint32_t reserved_5:5;
         /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_clr:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi1_mem_s_int_clr_reg_t;
 
 /** Type of int_raw register
  *  SPI1 interrupt raw register
@@ -1095,34 +1095,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+         *  The raw bit for SPI1_MEM_S_PER_END_INT interrupt. 1: Triggered when Auto Resume
          *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
          */
         uint32_t per_end_int_raw:1;
         /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+         *  The raw bit for SPI1_MEM_S_PES_END_INT interrupt.1: Triggered when Auto Suspend
          *  command (0x75) is sent and flash is suspended successfully. 0: Others.
          */
         uint32_t pes_end_int_raw:1;
         /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
+         *  The raw bit for SPI1_MEM_S_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
          *  is sent and flash is already idle. 0: Others.
          */
         uint32_t wpe_end_int_raw:1;
         /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
+         *  The raw bit for SPI1_MEM_S_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t slv_st_end_int_raw:1;
         /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
+         *  The raw bit for SPI1_MEM_S_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mst_st_end_int_raw:1;
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+         *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
          *  chip is loosing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
@@ -1131,7 +1131,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi1_mem_s_int_raw_reg_t;
 
 /** Type of int_st register
  *  SPI1 interrupt status register
@@ -1139,34 +1139,34 @@ typedef union {
 typedef union {
     struct {
         /** per_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_MEM_PER_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_PER_END_INT interrupt.
          */
         uint32_t per_end_int_st:1;
         /** pes_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_MEM_PES_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_PES_END_INT interrupt.
          */
         uint32_t pes_end_int_st:1;
         /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI_MEM_WPE_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_WPE_END_INT interrupt.
          */
         uint32_t wpe_end_int_st:1;
         /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_SLV_ST_END_INT interrupt.
          */
         uint32_t slv_st_end_int_st:1;
         /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for SPI1_MEM_S_MST_ST_END_INT interrupt.
          */
         uint32_t mst_st_end_int_st:1;
         uint32_t reserved_5:5;
         /** brown_out_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
+         *  The status bit for SPI1_MEM_S_BROWN_OUT_INT interrupt.
          */
         uint32_t brown_out_int_st:1;
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi1_mem_s_int_st_reg_t;
 
 
 /** Group: Timing registers */
@@ -1187,7 +1187,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi1_mem_s_timing_cali_reg_t;
 
 
 /** Group: Version register */
@@ -1203,65 +1203,65 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi1_mem_s_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t cmd;
-    volatile spi_mem_addr_reg_t addr;
-    volatile spi_mem_ctrl_reg_t ctrl;
-    volatile spi_mem_ctrl1_reg_t ctrl1;
-    volatile spi_mem_ctrl2_reg_t ctrl2;
-    volatile spi_mem_clock_reg_t clock;
-    volatile spi_mem_user_reg_t user;
-    volatile spi_mem_user1_reg_t user1;
-    volatile spi_mem_user2_reg_t user2;
-    volatile spi_mem_mosi_dlen_reg_t mosi_dlen;
-    volatile spi_mem_miso_dlen_reg_t miso_dlen;
-    volatile spi_mem_rd_status_reg_t rd_status;
+typedef struct spi1_mem_s_dev_s {
+    volatile spi1_mem_s_cmd_reg_t cmd;
+    volatile spi1_mem_s_addr_reg_t addr;
+    volatile spi1_mem_s_ctrl_reg_t ctrl;
+    volatile spi1_mem_s_ctrl1_reg_t ctrl1;
+    volatile spi1_mem_s_ctrl2_reg_t ctrl2;
+    volatile spi1_mem_s_clock_reg_t clock;
+    volatile spi1_mem_s_user_reg_t user;
+    volatile spi1_mem_s_user1_reg_t user1;
+    volatile spi1_mem_s_user2_reg_t user2;
+    volatile spi1_mem_s_mosi_dlen_reg_t mosi_dlen;
+    volatile spi1_mem_s_miso_dlen_reg_t miso_dlen;
+    volatile spi1_mem_s_rd_status_reg_t rd_status;
     uint32_t reserved_030;
-    volatile spi_mem_misc_reg_t misc;
-    volatile spi_mem_tx_crc_reg_t tx_crc;
-    volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
+    volatile spi1_mem_s_misc_reg_t misc;
+    volatile spi1_mem_s_tx_crc_reg_t tx_crc;
+    volatile spi1_mem_s_cache_fctrl_reg_t cache_fctrl;
     uint32_t reserved_040[6];
-    volatile spi_mem_w0_reg_t w0;
-    volatile spi_mem_w1_reg_t w1;
-    volatile spi_mem_w2_reg_t w2;
-    volatile spi_mem_w3_reg_t w3;
-    volatile spi_mem_w4_reg_t w4;
-    volatile spi_mem_w5_reg_t w5;
-    volatile spi_mem_w6_reg_t w6;
-    volatile spi_mem_w7_reg_t w7;
-    volatile spi_mem_w8_reg_t w8;
-    volatile spi_mem_w9_reg_t w9;
-    volatile spi_mem_w10_reg_t w10;
-    volatile spi_mem_w11_reg_t w11;
-    volatile spi_mem_w12_reg_t w12;
-    volatile spi_mem_w13_reg_t w13;
-    volatile spi_mem_w14_reg_t w14;
-    volatile spi_mem_w15_reg_t w15;
-    volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
-    volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
-    volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
-    volatile spi_mem_sus_status_reg_t sus_status;
+    volatile spi1_mem_s_w0_reg_t w0;
+    volatile spi1_mem_s_w1_reg_t w1;
+    volatile spi1_mem_s_w2_reg_t w2;
+    volatile spi1_mem_s_w3_reg_t w3;
+    volatile spi1_mem_s_w4_reg_t w4;
+    volatile spi1_mem_s_w5_reg_t w5;
+    volatile spi1_mem_s_w6_reg_t w6;
+    volatile spi1_mem_s_w7_reg_t w7;
+    volatile spi1_mem_s_w8_reg_t w8;
+    volatile spi1_mem_s_w9_reg_t w9;
+    volatile spi1_mem_s_w10_reg_t w10;
+    volatile spi1_mem_s_w11_reg_t w11;
+    volatile spi1_mem_s_w12_reg_t w12;
+    volatile spi1_mem_s_w13_reg_t w13;
+    volatile spi1_mem_s_w14_reg_t w14;
+    volatile spi1_mem_s_w15_reg_t w15;
+    volatile spi1_mem_s_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
+    volatile spi1_mem_s_flash_sus_ctrl_reg_t flash_sus_ctrl;
+    volatile spi1_mem_s_flash_sus_cmd_reg_t flash_sus_cmd;
+    volatile spi1_mem_s_sus_status_reg_t sus_status;
     uint32_t reserved_0a8[6];
-    volatile spi_mem_int_ena_reg_t int_ena;
-    volatile spi_mem_int_clr_reg_t int_clr;
-    volatile spi_mem_int_raw_reg_t int_raw;
-    volatile spi_mem_int_st_reg_t int_st;
+    volatile spi1_mem_s_int_ena_reg_t int_ena;
+    volatile spi1_mem_s_int_clr_reg_t int_clr;
+    volatile spi1_mem_s_int_raw_reg_t int_raw;
+    volatile spi1_mem_s_int_st_reg_t int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t ddr;
+    volatile spi1_mem_s_ddr_reg_t ddr;
     uint32_t reserved_0d8[42];
-    volatile spi_mem_timing_cali_reg_t timing_cali;
+    volatile spi1_mem_s_timing_cali_reg_t timing_cali;
     uint32_t reserved_184[31];
-    volatile spi_mem_clock_gate_reg_t clock_gate;
+    volatile spi1_mem_s_clock_gate_reg_t clock_gate;
     uint32_t reserved_204[126];
-    volatile spi_mem_date_reg_t date;
+    volatile spi1_mem_s_date_reg_t date;
 } spi1_mem_s_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+_Static_assert(sizeof(spi1_mem_s_dev_t) == 0x400, "Invalid size of spi1_mem_s_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/spi_mem_c_struct.h

@@ -30,7 +30,7 @@ typedef union {
         uint32_t mem_slv_st:4;
         uint32_t reserved_8:10;
         /** mem_usr : HRO; bitpos: [18]; default: 0;
-         *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+         *  SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared.  An operation
          *  will be triggered when the bit is set. The bit will be cleared once the operation
          *  done.1: enable 0: disable.
          */
@@ -38,7 +38,7 @@ typedef union {
         uint32_t reserved_19:13;
     };
     uint32_t val;
-} spi_mem_cmd_reg_t;
+} spi_mem_c_cmd_reg_t;
 
 /** Type of mem_axi_err_addr register
  *  SPI0 AXI request error address.
@@ -47,14 +47,14 @@ typedef union {
     struct {
         /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first AXI write/read invalid error or AXI write flash error
-         *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
-         *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
+         *  address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR,
+         *  spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set.
          */
         uint32_t mem_axi_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_axi_err_addr_reg_t;
+} spi_mem_c_axi_err_addr_reg_t;
 
 
 /** Group: Flash Control and configuration registers */
@@ -108,8 +108,8 @@ typedef union {
         uint32_t mem_fcmd_oct:1;
         uint32_t reserved_10:3;
         /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
-         *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
+         *  This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT
+         *  and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable.
          */
         uint32_t mem_fastrd_mode:1;
         /** mem_fread_dual : R/W; bitpos: [14]; default: 0;
@@ -157,7 +157,7 @@ typedef union {
         uint32_t mem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_ctrl_reg_t;
+} spi_mem_c_ctrl_reg_t;
 
 /** Type of mem_ctrl1 register
  *  SPI0 control1 register.
@@ -188,7 +188,7 @@ typedef union {
         /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0;
          *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
          *  when there is a ECC error in AXI read data. The ECC error information is recorded
-         *  in SPI_MEM_ECC_ERR_ADDR_REG.
+         *  in spi_mem_c_C_ECC_ERR_ADDR_REG.
          */
         uint32_t mem_rresp_ecc_err_en:1;
         /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0;
@@ -200,9 +200,9 @@ typedef union {
          */
         uint32_t mem_aw_splice_en:1;
         /** mem_ram0_en : HRO; bitpos: [27]; default: 1;
-         *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
-         *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
-         *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
+         *  When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be
+         *  accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1
+         *  will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
          *  accessed at the same time.
          */
         uint32_t mem_ram0_en:1;
@@ -229,7 +229,7 @@ typedef union {
         uint32_t mem_txfifo_rst:1;
     };
     uint32_t val;
-} spi_mem_ctrl1_reg_t;
+} spi_mem_c_ctrl1_reg_t;
 
 /** Type of mem_ctrl2 register
  *  SPI0 control2 register.
@@ -238,16 +238,16 @@ typedef union {
     struct {
         /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1;
          *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
-         *  SPI_MEM_CS_SETUP bit.
+         *  spi_mem_c_C_CS_SETUP bit.
          */
         uint32_t mem_cs_setup_time:5;
         /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1;
          *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
-         *  SPI_MEM_CS_HOLD bit.
+         *  spi_mem_c_C_CS_HOLD bit.
          */
         uint32_t mem_cs_hold_time:5;
         /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3;
-         *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+         *  spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
          *  mode when accessed flash.
          */
         uint32_t mem_ecc_cs_hold_time:3;
@@ -270,7 +270,7 @@ typedef union {
         uint32_t mem_split_trans_en:1;
         /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+         *  transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI
          *  core clock cycles.
          */
         uint32_t mem_cs_hold_delay:6;
@@ -280,7 +280,7 @@ typedef union {
         uint32_t mem_sync_reset:1;
     };
     uint32_t val;
-} spi_mem_ctrl2_reg_t;
+} spi_mem_c_ctrl2_reg_t;
 
 /** Type of mem_misc register
  *  SPI0 misc register
@@ -307,7 +307,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} spi_mem_misc_reg_t;
+} spi_mem_c_misc_reg_t;
 
 /** Type of mem_cache_fctrl register
  *  SPI0 bit mode control register.
@@ -326,7 +326,7 @@ typedef union {
         uint32_t close_axi_inf_en:1;
     };
     uint32_t val;
-} spi_mem_cache_fctrl_reg_t;
+} spi_mem_c_cache_fctrl_reg_t;
 
 /** Type of mem_ddr register
  *  SPI0 flash DDR mode control register
@@ -373,7 +373,7 @@ typedef union {
         uint32_t fmem_usr_ddr_dqs_thd:7;
         /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -410,7 +410,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_mem_ddr_reg_t;
+} spi_mem_c_ddr_reg_t;
 
 
 /** Group: Clock control and configuration registers */
@@ -420,16 +420,16 @@ typedef union {
 typedef union {
     struct {
         /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
+         *  In the master mode it must be equal to spi_mem_c_clkcnt_N.
          */
         uint32_t mem_clkcnt_l:8;
         /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+         *  In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
          */
         uint32_t mem_clkcnt_h:8;
         /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
+         *  In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is
+         *  system/(spi_mem_c_clkcnt_N+1)
          */
         uint32_t mem_clkcnt_n:8;
         uint32_t reserved_24:7;
@@ -440,7 +440,7 @@ typedef union {
         uint32_t mem_clk_equ_sysclk:1;
     };
     uint32_t val;
-} spi_mem_clock_reg_t;
+} spi_mem_c_clock_reg_t;
 
 /** Type of mem_clock_gate register
  *  SPI0 clock gate register
@@ -454,7 +454,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_clock_gate_reg_t;
+} spi_mem_c_clock_gate_reg_t;
 
 
 /** Group: Flash User-defined control registers */
@@ -474,7 +474,7 @@ typedef union {
         uint32_t mem_cs_setup:1;
         uint32_t reserved_8:1;
         /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
+         *  The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
          */
         uint32_t mem_ck_out_edge:1;
         uint32_t reserved_10:16;
@@ -490,7 +490,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_user_reg_t;
+} spi_mem_c_user_reg_t;
 
 /** Type of mem_user1 register
  *  SPI0 user1 register.
@@ -498,7 +498,7 @@ typedef union {
 typedef union {
     struct {
         /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
+         *  The length in spi_mem_c_clk cycles of dummy phase. The register value shall be
          *  (cycle_num-1).
          */
         uint32_t mem_usr_dummy_cyclelen:6;
@@ -513,7 +513,7 @@ typedef union {
         uint32_t mem_usr_addr_bitlen:6;
     };
     uint32_t val;
-} spi_mem_user1_reg_t;
+} spi_mem_c_user1_reg_t;
 
 /** Type of mem_user2 register
  *  SPI0 user2 register.
@@ -531,7 +531,7 @@ typedef union {
         uint32_t mem_usr_command_bitlen:4;
     };
     uint32_t val;
-} spi_mem_user2_reg_t;
+} spi_mem_c_user2_reg_t;
 
 
 /** Group: External RAM Control and configuration registers */
@@ -564,7 +564,7 @@ typedef union {
         uint32_t smem_data_ie_always_on:1;
     };
     uint32_t val;
-} spi_mem_sram_cmd_reg_t;
+} spi_mem_c_sram_cmd_reg_t;
 
 /** Type of smem_ddr register
  *  SPI0 external RAM DDR mode control register
@@ -611,7 +611,7 @@ typedef union {
         uint32_t smem_usr_ddr_dqs_thd:7;
         /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
          *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+         *  spi0_slv_st is in spi_mem_c_C_DIN state. It is used when there is no SPI_DQS signal or
          *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
          *  negative edge of SPI_DQS.
          */
@@ -649,7 +649,7 @@ typedef union {
         uint32_t reserved_31:1;
     };
     uint32_t val;
-} spi_smem_ddr_reg_t;
+} spi_mem_c_smem_ddr_reg_t;
 
 /** Type of smem_ac register
  *  MSPI external RAM ECC and SPI CS timing control register
@@ -667,16 +667,16 @@ typedef union {
         uint32_t smem_cs_hold:1;
         /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1;
          *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
-         *  spi_mem_cs_setup bit.
+         *  spi_mem_c_cs_setup bit.
          */
         uint32_t smem_cs_setup_time:5;
         /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1;
          *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
-         *  combined with spi_mem_cs_hold bit.
+         *  combined with spi_mem_c_cs_hold bit.
          */
         uint32_t smem_cs_hold_time:5;
         /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3;
-         *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
+         *  SPI_MEM_C_SMEM_CS_HOLD_TIME + SPI_MEM_C_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
          *  cycles in ECC mode when accessed external RAM.
          */
         uint32_t smem_ecc_cs_hold_time:3;
@@ -693,7 +693,7 @@ typedef union {
         uint32_t reserved_17:8;
         /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0;
          *  These bits are used to set the minimum CS high time tSHSL between SPI burst
-         *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
+         *  transfer when accesses to external RAM. tSHSL is (SPI_MEM_C_SMEM_CS_HOLD_DELAY[5:0] + 1)
          *  MSPI core clock cycles.
          */
         uint32_t smem_cs_hold_delay:6;
@@ -705,7 +705,7 @@ typedef union {
         uint32_t smem_split_trans_en:1;
     };
     uint32_t val;
-} spi_smem_ac_reg_t;
+} spi_mem_c_smem_ac_reg_t;
 
 
 /** Group: State control register */
@@ -722,7 +722,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_fsm_reg_t;
+} spi_mem_c_fsm_reg_t;
 
 
 /** Group: Interrupt registers */
@@ -733,37 +733,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_ena:1;
         /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_ena:1;
         /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_ena:1;
         /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_ena:1;
         /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_ena:1;
         /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_ena:1;
         /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int__ena:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_ena_reg_t;
+} spi_mem_c_int_ena_reg_t;
 
 /** Type of mem_int_clr register
  *  SPI0 interrupt clear register
@@ -772,37 +772,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_clr:1;
         /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_clr:1;
         /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_clr:1;
         /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_clr:1;
         /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_clr:1;
         /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_clr:1;
         /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_clr:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_clr_reg_t;
+} spi_mem_c_int_clr_reg_t;
 
 /** Type of mem_int_raw register
  *  SPI0 interrupt raw register
@@ -811,53 +811,53 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
+         *  The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
          *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
          *  Others
          */
         uint32_t mem_slv_st_end_int_raw:1;
         /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
+         *  The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
          *  changed from non idle state to idle state. 0: Others.
          */
         uint32_t mem_mst_st_end_int_raw:1;
         /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0;
-         *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
-         *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
-         *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
-         *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
+         *  The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set
+         *  and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
+         *  of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When
+         *  SPI_MEM_C_FMEM__ECC_ERR_INT_EN is cleared and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN is set, this bit is
          *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
-         *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
-         *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+         *  than spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and
+         *  SPI_MEM_C_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
          *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
-         *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
+         *  spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and  SPI_MEM_C_SMEM_ECC_ERR_INT_EN
          *  are cleared, this bit will not be triggered.
          */
         uint32_t mem_ecc_err_int_raw:1;
         /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
+         *  The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
          *  rejected. 0: Others.
          */
         uint32_t mem_pms_reject_int_raw:1;
         /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+         *  The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_raddr_err_int_raw:1;
         /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
          *  flash request is received. 0: Others.
          */
         uint32_t mem_axi_wr_flash_err_int_raw:1;
         /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+         *  The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
          *  address is invalid by compared to MMU configuration. 0: Others.
          */
         uint32_t mem_axi_waddr_err_int_raw:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_raw_reg_t;
+} spi_mem_c_int_raw_reg_t;
 
 /** Type of mem_int_st register
  *  SPI0 interrupt status register
@@ -866,37 +866,37 @@ typedef union {
     struct {
         uint32_t reserved_0:3;
         /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+         *  The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt.
          */
         uint32_t mem_slv_st_end_int_st:1;
         /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+         *  The status bit for spi_mem_c_C_MST_ST_END_INT interrupt.
          */
         uint32_t mem_mst_st_end_int_st:1;
         /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0;
-         *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
+         *  The status bit for spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t mem_ecc_err_int_st:1;
         /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
+         *  The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt.
          */
         uint32_t mem_pms_reject_int_st:1;
         /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_raddr_err_int_st:1;
         /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt.
          */
         uint32_t mem_axi_wr_flash_err_int_st:1;
         /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
+         *  The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt.
          */
         uint32_t mem_axi_waddr_err_int_st:1;
         uint32_t reserved_10:22;
     };
     uint32_t val;
-} spi_mem_int_st_reg_t;
+} spi_mem_c_int_st_reg_t;
 
 
 /** Group: PMS control and configuration registers */
@@ -915,14 +915,14 @@ typedef union {
         uint32_t fmem_pmsn_wr_attr:1;
         /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
-         *  section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and
-         *  SPI_FMEM_PMSn_SIZE_REG.
+         *  section n is configured by registers SPI_MEM_C_FMEM__PMSn_ADDR_REG and
+         *  SPI_MEM_C_FMEM__PMSn_SIZE_REG.
          */
         uint32_t fmem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_fmem_pmsn_attr_reg_t;
+} spi_mem_c_fmem_pmsn_attr_reg_t;
 
 /** Type of fmem_pmsn_addr register
  *  SPI1 flash PMS section n start address register
@@ -936,7 +936,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_fmem_pmsn_addr_reg_t;
+} spi_mem_c_fmem_pmsn_addr_reg_t;
 
 /** Type of fmem_pmsn_size register
  *  SPI1 flash PMS section n start address register
@@ -944,14 +944,14 @@ typedef union {
 typedef union {
     struct {
         /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S,
-         *  SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE)
+         *  SPI1 flash PMS section n address region is (SPI_MEM_C_FMEM__PMSn_ADDR_S,
+         *  SPI_MEM_C_FMEM__PMSn_ADDR_S + SPI_MEM_C_FMEM__PMSn_SIZE)
          */
         uint32_t fmem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_fmem_pmsn_size_reg_t;
+} spi_mem_c_fmem_pmsn_size_reg_t;
 
 /** Type of smem_pmsn_attr register
  *  SPI1 flash PMS section n start address register
@@ -968,14 +968,14 @@ typedef union {
         uint32_t smem_pmsn_wr_attr:1;
         /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0;
          *  SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The
-         *  external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and
-         *  SPI_SMEM_PMSn_SIZE_REG.
+         *  external RAM PMS section n is configured by registers SPI_MEM_C_SMEM_PMSn_ADDR_REG and
+         *  SPI_MEM_C_SMEM_PMSn_SIZE_REG.
          */
         uint32_t smem_pmsn_ecc:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} spi_smem_pmsn_attr_reg_t;
+} spi_mem_c_smem_pmsn_attr_reg_t;
 
 /** Type of smem_pmsn_addr register
  *  SPI1 external RAM PMS section n start address register
@@ -989,7 +989,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_pmsn_addr_reg_t;
+} spi_mem_c_smem_pmsn_addr_reg_t;
 
 /** Type of smem_pmsn_size register
  *  SPI1 external RAM PMS section n start address register
@@ -997,14 +997,14 @@ typedef union {
 typedef union {
     struct {
         /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096;
-         *  SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S,
-         *  SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE)
+         *  SPI1 external RAM PMS section n address region is (SPI_MEM_C_SMEM_PMSn_ADDR_S,
+         *  SPI_MEM_C_SMEM_PMSn_ADDR_S + SPI_MEM_C_SMEM_PMSn_SIZE)
          */
         uint32_t smem_pmsn_size:15;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} spi_smem_pmsn_size_reg_t;
+} spi_mem_c_smem_pmsn_size_reg_t;
 
 /** Type of mem_pms_reject register
  *  SPI1 access reject register
@@ -1013,7 +1013,7 @@ typedef union {
     struct {
         /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0;
          *  This bits show the first SPI1 access error address. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_reject_addr:27;
         /** mem_pm_en : R/W; bitpos: [27]; default: 0;
@@ -1022,27 +1022,27 @@ typedef union {
         uint32_t mem_pm_en:1;
         /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0;
          *  1: SPI1 write access error. 0: No write access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ld:1;
         /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0;
          *  1: SPI1 read access error. 0: No read access error. It is cleared by when
-         *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_st:1;
         /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0;
          *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
-         *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_multi_hit:1;
         /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0;
          *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
-         *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
+         *  error. It is cleared by when  spi_mem_c_C_PMS_REJECT_INT_CLR bit is set.
          */
         uint32_t mem_pms_ivd:1;
     };
     uint32_t val;
-} spi_mem_pms_reject_reg_t;
+} spi_mem_c_pms_reject_reg_t;
 
 
 /** Group: MSPI ECC registers */
@@ -1054,11 +1054,11 @@ typedef union {
         uint32_t reserved_0:5;
         /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0;
          *  This bits show the error times of MSPI ECC read. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_cnt:6;
         /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10;
-         *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
+         *  Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt.
          */
         uint32_t fmem_ecc_err_int_num:6;
         /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0;
@@ -1082,9 +1082,9 @@ typedef union {
         uint32_t mem_usr_ecc_addr_en:1;
         uint32_t reserved_22:2;
         /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1;
-         *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
-         *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
-         *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
+         *  1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is
+         *  updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and
+         *  spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information.
          */
         uint32_t mem_ecc_continue_record_err_en:1;
         /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0;
@@ -1094,7 +1094,7 @@ typedef union {
         uint32_t mem_ecc_err_bits:7;
     };
     uint32_t val;
-} spi_mem_ecc_ctrl_reg_t;
+} spi_mem_c_ecc_ctrl_reg_t;
 
 /** Type of mem_ecc_err_addr register
  *  MSPI ECC error address register
@@ -1103,13 +1103,13 @@ typedef union {
     struct {
         /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0;
          *  This bits show the first MSPI ECC error address. It is cleared by when
-         *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
+         *  spi_mem_c_C_ECC_ERR_INT_CLR bit is set.
          */
         uint32_t mem_ecc_err_addr:27;
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_ecc_err_addr_reg_t;
+} spi_mem_c_ecc_err_addr_reg_t;
 
 /** Type of smem_ecc_ctrl register
  *  MSPI ECC control register
@@ -1136,7 +1136,7 @@ typedef union {
         uint32_t reserved_21:11;
     };
     uint32_t val;
-} spi_smem_ecc_ctrl_reg_t;
+} spi_mem_c_smem_ecc_ctrl_reg_t;
 
 
 /** Group: Status and state control registers */
@@ -1174,7 +1174,7 @@ typedef union {
         uint32_t all_axi_trans_afifo_empty:1;
     };
     uint32_t val;
-} spi_smem_axi_addr_ctrl_reg_t;
+} spi_mem_c_smem_axi_addr_ctrl_reg_t;
 
 /** Type of mem_axi_err_resp_en register
  *  SPI0 AXI error response enable register
@@ -1233,7 +1233,7 @@ typedef union {
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} spi_mem_axi_err_resp_en_reg_t;
+} spi_mem_c_axi_err_resp_en_reg_t;
 
 
 /** Group: Flash timing registers */
@@ -1266,7 +1266,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} spi_mem_timing_cali_reg_t;
+} spi_mem_c_timing_cali_reg_t;
 
 /** Type of mem_din_mode register
  *  MSPI flash input timing delay mode control register
@@ -1334,7 +1334,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_mem_din_mode_reg_t;
+} spi_mem_c_din_mode_reg_t;
 
 /** Type of mem_din_num register
  *  MSPI flash input timing delay number control register
@@ -1389,7 +1389,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_mem_din_num_reg_t;
+} spi_mem_c_din_num_reg_t;
 
 /** Type of mem_dout_mode register
  *  MSPI flash output timing adjustment control register
@@ -1457,7 +1457,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_mem_dout_mode_reg_t;
+} spi_mem_c_dout_mode_reg_t;
 
 
 /** Group: External RAM timing registers */
@@ -1487,7 +1487,7 @@ typedef union {
         uint32_t reserved_6:26;
     };
     uint32_t val;
-} spi_smem_timing_cali_reg_t;
+} spi_mem_c_smem_timing_cali_reg_t;
 
 /** Type of smem_din_mode register
  *  MSPI external RAM input timing delay mode control register
@@ -1560,7 +1560,7 @@ typedef union {
         uint32_t reserved_27:5;
     };
     uint32_t val;
-} spi_smem_din_mode_reg_t;
+} spi_mem_c_smem_din_mode_reg_t;
 
 /** Type of smem_din_num register
  *  MSPI external RAM input timing delay number control register
@@ -1615,7 +1615,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} spi_smem_din_num_reg_t;
+} spi_mem_c_smem_din_num_reg_t;
 
 /** Type of smem_dout_mode register
  *  MSPI external RAM output timing adjustment control register
@@ -1688,7 +1688,7 @@ typedef union {
         uint32_t reserved_9:23;
     };
     uint32_t val;
-} spi_smem_dout_mode_reg_t;
+} spi_mem_c_smem_dout_mode_reg_t;
 
 
 /** Group: Manual Encryption plaintext Memory */
@@ -1704,7 +1704,7 @@ typedef union {
         uint32_t xts_plain:32;
     };
     uint32_t val;
-} spi_mem_xts_plain_base_reg_t;
+} spi_mem_c_xts_plain_base_reg_t;
 
 
 /** Group: Manual Encryption configuration registers */
@@ -1722,7 +1722,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_linesize_reg_t;
+} spi_mem_c_xts_linesize_reg_t;
 
 /** Type of mem_xts_destination register
  *  Manual Encryption destination register
@@ -1737,7 +1737,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destination_reg_t;
+} spi_mem_c_xts_destination_reg_t;
 
 /** Type of mem_xts_physical_address register
  *  Manual Encryption physical address register
@@ -1753,7 +1753,7 @@ typedef union {
         uint32_t reserved_26:6;
     };
     uint32_t val;
-} spi_mem_xts_physical_address_reg_t;
+} spi_mem_c_xts_physical_address_reg_t;
 
 
 /** Group: Manual Encryption control and status registers */
@@ -1772,7 +1772,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_trigger_reg_t;
+} spi_mem_c_xts_trigger_reg_t;
 
 /** Type of mem_xts_release register
  *  Manual Encryption physical address register
@@ -1788,7 +1788,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_release_reg_t;
+} spi_mem_c_xts_release_reg_t;
 
 /** Type of mem_xts_destroy register
  *  Manual Encryption physical address register
@@ -1804,7 +1804,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} spi_mem_xts_destroy_reg_t;
+} spi_mem_c_xts_destroy_reg_t;
 
 /** Type of mem_xts_state register
  *  Manual Encryption physical address register
@@ -1820,7 +1820,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} spi_mem_xts_state_reg_t;
+} spi_mem_c_xts_state_reg_t;
 
 
 /** Group: Manual Encryption version control register */
@@ -1836,7 +1836,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_xts_date_reg_t;
+} spi_mem_c_xts_date_reg_t;
 
 
 /** Group: MMU access registers */
@@ -1851,7 +1851,7 @@ typedef union {
         uint32_t mmu_item_content:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_content_reg_t;
+} spi_mem_c_mmu_item_content_reg_t;
 
 /** Type of mem_mmu_item_index register
  *  MSPI-MMU item index register
@@ -1864,7 +1864,7 @@ typedef union {
         uint32_t mmu_item_index:32;
     };
     uint32_t val;
-} spi_mem_mmu_item_index_reg_t;
+} spi_mem_c_mmu_item_index_reg_t;
 
 
 /** Group: MMU power control and configuration registers */
@@ -1898,7 +1898,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} spi_mem_mmu_power_ctrl_reg_t;
+} spi_mem_c_mmu_power_ctrl_reg_t;
 
 
 /** Group: External mem cryption DPA registers */
@@ -1927,7 +1927,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} spi_mem_dpa_ctrl_reg_t;
+} spi_mem_c_dpa_ctrl_reg_t;
 
 
 /** Group: Version control register */
@@ -1943,84 +1943,84 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} spi_mem_date_reg_t;
+} spi_mem_c_date_reg_t;
 
 
-typedef struct {
-    volatile spi_mem_cmd_reg_t mem_cmd;
+typedef struct spi_mem_c_dev_s {
+    volatile spi_mem_c_cmd_reg_t mem_cmd;
     uint32_t reserved_004;
-    volatile spi_mem_ctrl_reg_t mem_ctrl;
-    volatile spi_mem_ctrl1_reg_t mem_ctrl1;
-    volatile spi_mem_ctrl2_reg_t mem_ctrl2;
-    volatile spi_mem_clock_reg_t mem_clock;
-    volatile spi_mem_user_reg_t mem_user;
-    volatile spi_mem_user1_reg_t mem_user1;
-    volatile spi_mem_user2_reg_t mem_user2;
+    volatile spi_mem_c_ctrl_reg_t mem_ctrl;
+    volatile spi_mem_c_ctrl1_reg_t mem_ctrl1;
+    volatile spi_mem_c_ctrl2_reg_t mem_ctrl2;
+    volatile spi_mem_c_clock_reg_t mem_clock;
+    volatile spi_mem_c_user_reg_t mem_user;
+    volatile spi_mem_c_user1_reg_t mem_user1;
+    volatile spi_mem_c_user2_reg_t mem_user2;
     uint32_t reserved_024[4];
-    volatile spi_mem_misc_reg_t mem_misc;
+    volatile spi_mem_c_misc_reg_t mem_misc;
     uint32_t reserved_038;
-    volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl;
+    volatile spi_mem_c_cache_fctrl_reg_t mem_cache_fctrl;
     uint32_t reserved_040;
-    volatile spi_mem_sram_cmd_reg_t mem_sram_cmd;
+    volatile spi_mem_c_sram_cmd_reg_t mem_sram_cmd;
     uint32_t reserved_048[3];
-    volatile spi_mem_fsm_reg_t mem_fsm;
+    volatile spi_mem_c_fsm_reg_t mem_fsm;
     uint32_t reserved_058[26];
-    volatile spi_mem_int_ena_reg_t mem_int_ena;
-    volatile spi_mem_int_clr_reg_t mem_int_clr;
-    volatile spi_mem_int_raw_reg_t mem_int_raw;
-    volatile spi_mem_int_st_reg_t mem_int_st;
+    volatile spi_mem_c_int_ena_reg_t mem_int_ena;
+    volatile spi_mem_c_int_clr_reg_t mem_int_clr;
+    volatile spi_mem_c_int_raw_reg_t mem_int_raw;
+    volatile spi_mem_c_int_st_reg_t mem_int_st;
     uint32_t reserved_0d0;
-    volatile spi_mem_ddr_reg_t mem_ddr;
-    volatile spi_smem_ddr_reg_t smem_ddr;
+    volatile spi_mem_c_ddr_reg_t mem_ddr;
+    volatile spi_mem_c_smem_ddr_reg_t smem_ddr;
     uint32_t reserved_0dc[9];
-    volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
-    volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
-    volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
-    volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
-    volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
-    volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4];
+    volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4];
+    volatile spi_mem_c_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4];
+    volatile spi_mem_c_fmem_pmsn_size_reg_t fmem_pmsn_size[4];
+    volatile spi_mem_c_smem_pmsn_attr_reg_t smem_pmsn_attr[4];
+    volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4];
+    volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4];
     uint32_t reserved_160;
-    volatile spi_mem_pms_reject_reg_t mem_pms_reject;
-    volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl;
-    volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr;
-    volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr;
-    volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
-    volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
-    volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en;
-    volatile spi_mem_timing_cali_reg_t mem_timing_cali;
-    volatile spi_mem_din_mode_reg_t mem_din_mode;
-    volatile spi_mem_din_num_reg_t mem_din_num;
-    volatile spi_mem_dout_mode_reg_t mem_dout_mode;
-    volatile spi_smem_timing_cali_reg_t smem_timing_cali;
-    volatile spi_smem_din_mode_reg_t smem_din_mode;
-    volatile spi_smem_din_num_reg_t smem_din_num;
-    volatile spi_smem_dout_mode_reg_t smem_dout_mode;
-    volatile spi_smem_ac_reg_t smem_ac;
+    volatile spi_mem_c_pms_reject_reg_t mem_pms_reject;
+    volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl;
+    volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr;
+    volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr;
+    volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl;
+    volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl;
+    volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en;
+    volatile spi_mem_c_timing_cali_reg_t mem_timing_cali;
+    volatile spi_mem_c_din_mode_reg_t mem_din_mode;
+    volatile spi_mem_c_din_num_reg_t mem_din_num;
+    volatile spi_mem_c_dout_mode_reg_t mem_dout_mode;
+    volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali;
+    volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode;
+    volatile spi_mem_c_smem_din_num_reg_t smem_din_num;
+    volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode;
+    volatile spi_mem_c_smem_ac_reg_t smem_ac;
     uint32_t reserved_1a4[23];
-    volatile spi_mem_clock_gate_reg_t mem_clock_gate;
+    volatile spi_mem_c_clock_gate_reg_t mem_clock_gate;
     uint32_t reserved_204[63];
-    volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base;
+    volatile spi_mem_c_xts_plain_base_reg_t mem_xts_plain_base;
     uint32_t reserved_304[15];
-    volatile spi_mem_xts_linesize_reg_t mem_xts_linesize;
-    volatile spi_mem_xts_destination_reg_t mem_xts_destination;
-    volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address;
-    volatile spi_mem_xts_trigger_reg_t mem_xts_trigger;
-    volatile spi_mem_xts_release_reg_t mem_xts_release;
-    volatile spi_mem_xts_destroy_reg_t mem_xts_destroy;
-    volatile spi_mem_xts_state_reg_t mem_xts_state;
-    volatile spi_mem_xts_date_reg_t mem_xts_date;
+    volatile spi_mem_c_xts_linesize_reg_t mem_xts_linesize;
+    volatile spi_mem_c_xts_destination_reg_t mem_xts_destination;
+    volatile spi_mem_c_xts_physical_address_reg_t mem_xts_physical_address;
+    volatile spi_mem_c_xts_trigger_reg_t mem_xts_trigger;
+    volatile spi_mem_c_xts_release_reg_t mem_xts_release;
+    volatile spi_mem_c_xts_destroy_reg_t mem_xts_destroy;
+    volatile spi_mem_c_xts_state_reg_t mem_xts_state;
+    volatile spi_mem_c_xts_date_reg_t mem_xts_date;
     uint32_t reserved_360[7];
-    volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content;
-    volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index;
-    volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
-    volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl;
+    volatile spi_mem_c_mmu_item_content_reg_t mem_mmu_item_content;
+    volatile spi_mem_c_mmu_item_index_reg_t mem_mmu_item_index;
+    volatile spi_mem_c_mmu_power_ctrl_reg_t mem_mmu_power_ctrl;
+    volatile spi_mem_c_dpa_ctrl_reg_t mem_dpa_ctrl;
     uint32_t reserved_38c[28];
-    volatile spi_mem_date_reg_t mem_date;
+    volatile spi_mem_c_date_reg_t mem_date;
 } spi_mem_c_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure");
+_Static_assert(sizeof(spi_mem_c_dev_t) == 0x400, "Invalid size of spi_mem_c_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/spi_mem_reg.h

@@ -1,16 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_SPI_MEM_REG_H_
-#define _SOC_SPI_MEM_REG_H_
+#pragma once
 
+#include <stdint.h>
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
 /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
@@ -3442,7 +3442,3 @@ formance of cryption will decrease together with this number increasing).*/
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_SPI_MEM_REG_H_ */