Rename Kconfig options (components/esp32)

Kconfig

@@ -4,6 +4,12 @@
 #
 mainmenu "Espressif IoT Development Framework Configuration"
 
+    # Hidden option to support checking for this specific target in C code and Kconfig files
+    config IDF_TARGET_ESP32
+        bool
+        default "y" if IDF_TARGET="esp32"
+        default "n"
+
     config IDF_CMAKE
         bool
         option env="IDF_CMAKE"

components/app_trace/Kconfig

@@ -16,8 +16,8 @@ menu "Application Level Tracing"
     config ESP32_APPTRACE_ENABLE
         bool
         depends on !ESP32_TRAX
-        select MEMMAP_TRACEMEM
-        select MEMMAP_TRACEMEM_TWOBANKS
+        select ESP32_MEMMAP_TRACEMEM
+        select ESP32_MEMMAP_TRACEMEM_TWOBANKS
         default n
         help
             Enables/disable application tracing module.

components/bootloader/Kconfig.projbuild

@@ -140,7 +140,7 @@ menu "Bootloader config"
             source for slow_clk - and ends calling app_main.
             Re-set timeout is needed due to WDT uses a SLOW_CLK clock source. After changing a frequency slow_clk a
             time of WDT needs to re-set for new frequency.
-            slow_clk depends on ESP32_RTC_CLOCK_SOURCE (INTERNAL_RC or EXTERNAL_CRYSTAL).
+            slow_clk depends on ESP32_RTC_CLC_SRC (INTERNAL_RC or EXTERNAL_CRYSTAL).
 
     config BOOTLOADER_WDT_DISABLE_IN_USER_CODE
         bool "Allows RTC watchdog disable in user code"

components/bootloader_support/src/bootloader_clock.c

@@ -53,7 +53,7 @@ void bootloader_clock_configure()
      * part of the start up time by enabling 32k XTAL early.
      * App startup code will wait until the oscillator has started up.
      */
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
     if (!rtc_clk_32k_enabled()) {
         rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
     }

components/bootloader_support/src/bootloader_init.c

@@ -412,11 +412,11 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
 
 static void uart_console_configure(void)
 {
-#if CONFIG_CONSOLE_UART_NONE
+#if CONFIG_ESP_CONSOLE_UART_NONE
     ets_install_putc1(NULL);
     ets_install_putc2(NULL);
-#else // CONFIG_CONSOLE_UART_NONE
-    const int uart_num = CONFIG_CONSOLE_UART_NUM;
+#else // CONFIG_ESP_CONSOLE_UART_NONE
+    const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
 
     uartAttach();
     ets_install_uart_printf();
@@ -424,10 +424,10 @@ static void uart_console_configure(void)
     // Wait for UART FIFO to be empty.
     uart_tx_wait_idle(0);
 
-#if CONFIG_CONSOLE_UART_CUSTOM
+#if CONFIG_ESP_CONSOLE_UART_CUSTOM
     // Some constants to make the following code less upper-case
-    const int uart_tx_gpio = CONFIG_CONSOLE_UART_TX_GPIO;
-    const int uart_rx_gpio = CONFIG_CONSOLE_UART_RX_GPIO;
+    const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
+    const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
     // Switch to the new UART (this just changes UART number used for
     // ets_printf in ROM code).
     uart_tx_switch(uart_num);
@@ -450,13 +450,13 @@ static void uart_console_configure(void)
         gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
         gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
     }
-#endif // CONFIG_CONSOLE_UART_CUSTOM
+#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
 
     // Set configured UART console baud rate
-    const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE;
+    const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
     uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
 
-#endif // CONFIG_CONSOLE_UART_NONE
+#endif // CONFIG_ESP_CONSOLE_UART_NONE
 }
 
 static void wdt_reset_cpu0_info_enable(void)

components/bt/Kconfig

@@ -173,7 +173,7 @@ menu Bluetooth
 
                 config BTDM_LPCLK_SEL_EXT_32K_XTAL
                     bool "External 32kHz crystal"
-                    depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+                    depends on ESP32_RTC_CLK_SRC_EXT_CRYS
             endchoice
 
         endmenu

components/driver/test/test_spi_master.c

@@ -544,7 +544,7 @@ static const uint8_t data_drom[320+3] = {
 
 TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
 {
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
     //test psram if enabled
     ESP_LOGI(TAG, "testing PSRAM...");
     uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_SPIRAM);

components/driver/test/test_spi_slave.c

@@ -11,7 +11,7 @@
 #include "sdkconfig.h"
 #include "test/test_common_spi.h"
 
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
 //This test should be removed once the timing test is merged.
 
 
@@ -140,4 +140,4 @@ TEST_CASE("test slave send unaligned","[spi]")
     ESP_LOGI(MASTER_TAG, "test passed.");
 }
 
-#endif // !CONFIG_SPIRAM_SUPPORT
+#endif // !CONFIG_ESP32_SPIRAM_SUPPORT

components/driver/uart.c

@@ -1452,7 +1452,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
     free(p_uart_obj[uart_num]);
     p_uart_obj[uart_num] = NULL;
 
-    if (uart_num != CONFIG_CONSOLE_UART_NUM ) {
+    if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) {
        if(uart_num == UART_NUM_0) {
            periph_module_disable(PERIPH_UART0_MODULE);
        } else if(uart_num == UART_NUM_1) {

components/esp32/Kconfig

@@ -1,11 +1,5 @@
 menu "ESP32-specific"
 
-    # Hidden option to support checking for this specific target in C code and Kconfig files
-    config IDF_TARGET_ESP32
-        bool
-        default "y" if IDF_TARGET="esp32"
-        default "n"
-
     choice ESP32_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
         default ESP32_DEFAULT_CPU_FREQ_160
@@ -26,7 +20,7 @@ menu "ESP32-specific"
         default 160 if ESP32_DEFAULT_CPU_FREQ_160
         default 240 if ESP32_DEFAULT_CPU_FREQ_240
 
-    config SPIRAM_SUPPORT
+    config ESP32_SPIRAM_SUPPORT
         bool "Support for external, SPI-connected RAM"
         default "n"
         help
@@ -34,7 +28,7 @@ menu "ESP32-specific"
             main SPI flash chip.
 
     menu "SPI RAM config"
-        depends on SPIRAM_SUPPORT
+        depends on ESP32_SPIRAM_SUPPORT
 
         config SPIRAM_BOOT_INIT
             bool "Initialize SPI RAM when booting the ESP32"
@@ -175,7 +169,7 @@ menu "ESP32-specific"
                 from the non-preferred region instead, so malloc() will not suddenly fail when either internal or
                 external memory is full.
 
-        config WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+        config SPIRAM_TRY_ALLOCATE_WIFI_LWIP
             bool "Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, allocate internal memory"
             depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
             default "n"
@@ -219,7 +213,7 @@ menu "ESP32-specific"
         config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
             bool "Allow .bss segment placed in external memory"
             default n
-            depends on SPIRAM_SUPPORT
+            depends on ESP32_SPIRAM_SUPPORT
             help
                 If enabled the option,and add EXT_RAM_ATTR defined your variable,then your variable will be placed in
                 PSRAM instead of internal memory, and placed most of variables of lwip,net802.11,pp,bluedroid library
@@ -239,9 +233,9 @@ menu "ESP32-specific"
                 bool "VSPI host (SPI3)"
         endchoice
 
-        config PICO_PSRAM_CS_IO
+        config SPIRAM_PICO_PSRAM_CS_IO
             int "PSRAM CS IO for ESP32-PICO chip"
-            depends on SPIRAM_SUPPORT
+            depends on ESP32_SPIRAM_SUPPORT
             range 0 33
             default 10
             help
@@ -250,18 +244,18 @@ menu "ESP32-specific"
 
     endmenu
 
-    config MEMMAP_TRACEMEM
+    config ESP32_MEMMAP_TRACEMEM
         bool
         default "n"
 
-    config MEMMAP_TRACEMEM_TWOBANKS
+    config ESP32_MEMMAP_TRACEMEM_TWOBANKS
         bool
         default "n"
 
     config ESP32_TRAX
         bool "Use TRAX tracing feature"
         default "n"
-        select MEMMAP_TRACEMEM
+        select ESP32_MEMMAP_TRACEMEM
         help
             The ESP32 contains a feature which allows you to trace the execution path the processor
             has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
@@ -272,7 +266,7 @@ menu "ESP32-specific"
         bool "Reserve memory for tracing both pro as well as app cpu execution"
         default "n"
         depends on ESP32_TRAX && !FREERTOS_UNICORE
-        select MEMMAP_TRACEMEM_TWOBANKS
+        select ESP32_MEMMAP_TRACEMEM_TWOBANKS
         help
             The ESP32 contains a feature which allows you to trace the execution path the processor
             has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
@@ -280,15 +274,15 @@ menu "ESP32-specific"
             what this is.
 
             # Memory to reverse for trace, used in linker script
-    config TRACEMEM_RESERVE_DRAM
+    config ESP32_TRACEMEM_RESERVE_DRAM
         hex
-        default 0x8000 if MEMMAP_TRACEMEM && MEMMAP_TRACEMEM_TWOBANKS
-        default 0x4000 if MEMMAP_TRACEMEM && !MEMMAP_TRACEMEM_TWOBANKS
+        default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
+        default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
         default 0x0
 
-    choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
+    choice ESP32_UNIVERSAL_MAC_ADDRESSES
         bool "Number of universally administered (by IEEE) MAC address"
-        default FOUR_UNIVERSAL_MAC_ADDRESS
+        default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
         help
             Configure the number of universally administered (by IEEE) MAC addresses.
             During initialisation, MAC addresses for each network interface are generated or derived from a
@@ -305,195 +299,19 @@ menu "ESP32-specific"
             a custom universal MAC address range, the correct setting will depend on the allocation of MAC
             addresses in this range (either 2 or 4 per device.)
 
-        config TWO_UNIVERSAL_MAC_ADDRESS
+        config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
             bool "Two"
-        config FOUR_UNIVERSAL_MAC_ADDRESS
+        config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
             bool "Four"
     endchoice
 
-    config NUMBER_OF_UNIVERSAL_MAC_ADDRESS
+    config ESP32_UNIVERSAL_MAC_ADDRESSES
         int
-        default 2 if TWO_UNIVERSAL_MAC_ADDRESS
-        default 4 if FOUR_UNIVERSAL_MAC_ADDRESS
-
-    config SYSTEM_EVENT_QUEUE_SIZE
-        int "System event queue size"
-        default 32
-        help
-            Config system event queue size in different application.
-
-    config SYSTEM_EVENT_TASK_STACK_SIZE
-        int "Event loop task stack size"
-        default 2304
-        help
-            Config system event task stack size in different application.
-
-    config MAIN_TASK_STACK_SIZE
-        int "Main task stack size"
-        default 3584
-        help
-            Configure the "main task" stack size. This is the stack of the task
-            which calls app_main(). If app_main() returns then this task is deleted
-            and its stack memory is freed.
-
-    config IPC_TASK_STACK_SIZE
-        int "Inter-Processor Call (IPC) task stack size"
-        default 1024
-        range 512 65536 if !ESP32_APPTRACE_ENABLE
-        range 2048 65536 if ESP32_APPTRACE_ENABLE
-        help
-            Configure the IPC tasks stack size. One IPC task runs on each core
-            (in dual core mode), and allows for cross-core function calls.
-
-            See IPC documentation for more details.
-
-            The default stack size should be enough for most common use cases.
-            It can be shrunk if you are sure that you do not use any custom
-            IPC functionality.
-
-    config TIMER_TASK_STACK_SIZE
-        int "High-resolution timer task stack size"
-        default 3584
-        range 2048 65536
-        help
-            Configure the stack size of esp_timer/ets_timer task. This task is used
-            to dispatch callbacks of timers created using ets_timer and esp_timer
-            APIs. If you are seing stack overflow errors in timer task, increase
-            this value.
-
-            Note that this is not the same as FreeRTOS timer task. To configure
-            FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
-            in "FreeRTOS" menu.
-
-    choice NEWLIB_STDOUT_LINE_ENDING
-        prompt "Line ending for UART output"
-        default NEWLIB_STDOUT_LINE_ENDING_CRLF
-        help
-            This option allows configuring the desired line endings sent to UART
-            when a newline ('\n', LF) appears on stdout.
-            Three options are possible:
-
-            CRLF: whenever LF is encountered, prepend it with CR
-
-            LF: no modification is applied, stdout is sent as is
-
-            CR: each occurence of LF is replaced with CR
-
-            This option doesn't affect behavior of the UART driver (drivers/uart.h).
-
-        config NEWLIB_STDOUT_LINE_ENDING_CRLF
-            bool "CRLF"
-        config NEWLIB_STDOUT_LINE_ENDING_LF
-            bool "LF"
-        config NEWLIB_STDOUT_LINE_ENDING_CR
-            bool "CR"
-    endchoice
-
-    choice NEWLIB_STDIN_LINE_ENDING
-        prompt "Line ending for UART input"
-        default NEWLIB_STDIN_LINE_ENDING_CR
-        help
-            This option allows configuring which input sequence on UART produces
-            a newline ('\n', LF) on stdin.
-            Three options are possible:
-
-            CRLF: CRLF is converted to LF
-
-            LF: no modification is applied, input is sent to stdin as is
-
-            CR: each occurence of CR is replaced with LF
-
-            This option doesn't affect behavior of the UART driver (drivers/uart.h).
-
-        config NEWLIB_STDIN_LINE_ENDING_CRLF
-            bool "CRLF"
-        config NEWLIB_STDIN_LINE_ENDING_LF
-            bool "LF"
-        config NEWLIB_STDIN_LINE_ENDING_CR
-            bool "CR"
-    endchoice
-
-    config NEWLIB_NANO_FORMAT
-        bool "Enable 'nano' formatting options for printf/scanf family"
-        default n
-        help
-            ESP32 ROM contains parts of newlib C library, including printf/scanf family
-            of functions. These functions have been compiled with so-called "nano"
-            formatting option. This option doesn't support 64-bit integer formats and C99
-            features, such as positional arguments.
-
-            For more details about "nano" formatting option, please see newlib readme file,
-            search for '--enable-newlib-nano-formatted-io':
-            https://sourceware.org/newlib/README
-
-            If this option is enabled, build system will use functions available in
-            ROM, reducing the application binary size. Functions available in ROM run
-            faster than functions which run from flash. Functions available in ROM can
-            also run when flash instruction cache is disabled.
-
-            If you need 64-bit integer formatting support or C99 features, keep this
-            option disabled.
-
-    choice CONSOLE_UART
-        prompt "UART for console output"
-        default CONSOLE_UART_DEFAULT
-        help
-            Select whether to use UART for console output (through stdout and stderr).
-
-            - Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
-            - If "Custom" is selected, UART0 or UART1 can be chosen,
-              and any pins can be selected.
-            - If "None" is selected, there will be no console output on any UART, except
-              for initial output from ROM bootloader. This output can be further suppressed by
-              bootstrapping GPIO13 pin to low logic level.
-
-        config CONSOLE_UART_DEFAULT
-            bool "Default: UART0, TX=GPIO1, RX=GPIO3"
-        config CONSOLE_UART_CUSTOM
-            bool "Custom"
-        config CONSOLE_UART_NONE
-            bool "None"
-    endchoice
+        default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
+        default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
 
-    choice CONSOLE_UART_NUM
-        prompt "UART peripheral to use for console output (0-1)"
-        depends on CONSOLE_UART_CUSTOM
-        default CONSOLE_UART_CUSTOM_NUM_0
-        help
-            Due of a ROM bug, UART2 is not supported for console output
-            via ets_printf.
-
-        config CONSOLE_UART_CUSTOM_NUM_0
-            bool "UART0"
-        config CONSOLE_UART_CUSTOM_NUM_1
-            bool "UART1"
-    endchoice
 
-    config CONSOLE_UART_NUM
-        int
-        default 0 if CONSOLE_UART_DEFAULT || CONSOLE_UART_NONE
-        default 0 if CONSOLE_UART_CUSTOM_NUM_0
-        default 1 if CONSOLE_UART_CUSTOM_NUM_1
-
-    config CONSOLE_UART_TX_GPIO
-        int "UART TX on GPIO#"
-        depends on CONSOLE_UART_CUSTOM
-        range 0 33
-        default 19
-
-    config CONSOLE_UART_RX_GPIO
-        int "UART RX on GPIO#"
-        depends on CONSOLE_UART_CUSTOM
-        range 0 39
-        default 21
-
-    config CONSOLE_UART_BAUDRATE
-        int "UART console baud rate"
-        depends on !CONSOLE_UART_NONE
-        default 115200
-        range 1200 4000000
-
-    config ULP_COPROC_ENABLED
+    config ESP32_ULP_COPROC_ENABLED
         bool "Enable Ultra Low Power (ULP) Coprocessor"
         default "n"
         help
@@ -501,13 +319,13 @@ menu "ESP32-specific"
 
             If this option is enabled, further coprocessor configuration will appear in the Components menu.
 
-    config ULP_COPROC_RESERVE_MEM
+    config ESP32_ULP_COPROC_RESERVE_MEM
         int
-        prompt "RTC slow memory reserved for coprocessor" if ULP_COPROC_ENABLED
-        default 512 if ULP_COPROC_ENABLED
-        range 32 8192 if ULP_COPROC_ENABLED
-        default 0 if !ULP_COPROC_ENABLED
-        range 0 0 if !ULP_COPROC_ENABLED
+        prompt "RTC slow memory reserved for coprocessor" if ESP32_ULP_COPROC_ENABLED
+        default 512 if ESP32_ULP_COPROC_ENABLED
+        range 32 8192 if ESP32_ULP_COPROC_ENABLED
+        default 0 if !ESP32_ULP_COPROC_ENABLED
+        range 0 0 if !ESP32_ULP_COPROC_ENABLED
         help
             Bytes of memory to reserve for ULP coprocessor firmware & data.
 
@@ -544,23 +362,6 @@ menu "ESP32-specific"
                 of the crash.
     endchoice
 
-    config GDBSTUB_SUPPORT_TASKS
-        bool "GDBStub: enable listing FreeRTOS tasks"
-        default y
-        depends on ESP32_PANIC_GDBSTUB
-        help
-            If enabled, GDBStub can supply the list of FreeRTOS tasks to GDB.
-            Thread list can be queried from GDB using 'info threads' command.
-            Note that if GDB task lists were corrupted, this feature may not work.
-            If GDBStub fails, try disabling this feature.
-
-    config GDBSTUB_MAX_TASKS
-        int "GDBStub: maximum number of tasks supported"
-        default 32
-        depends on GDBSTUB_SUPPORT_TASKS
-        help
-            Set the number of tasks which GDB Stub will support.
-
     config ESP32_DEBUG_OCDAWARE
         bool "Make exception and panic handlers JTAG/OCD aware"
         default y
@@ -576,78 +377,7 @@ menu "ESP32-specific"
             Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
             e.g. GCOV data dump.
 
-    config INT_WDT
-        bool "Interrupt watchdog"
-        default y
-        help
-            This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
-            either because a task turned off interrupts and did not turn them on for a long time, or because an
-            interrupt handler did not return. It will try to invoke the panic handler first and failing that
-            reset the SoC.
-
-    config INT_WDT_TIMEOUT_MS
-        int "Interrupt watchdog timeout (ms)"
-        depends on INT_WDT
-        default 300 if !SPIRAM_SUPPORT
-        default 800 if SPIRAM_SUPPORT
-        range 10 10000
-        help
-            The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
-
-    config INT_WDT_CHECK_CPU1
-        bool "Also watch CPU1 tick interrupt"
-        depends on INT_WDT && !FREERTOS_UNICORE
-        default y
-        help
-            Also detect if interrupts on CPU 1 are disabled for too long.
-
-    config TASK_WDT
-        bool "Initialize Task Watchdog Timer on startup"
-        default y
-        help
-            The Task Watchdog Timer can be used to make sure individual tasks are still
-            running. Enabling this option will cause the Task Watchdog Timer to be
-            initialized automatically at startup. The Task Watchdog timer can be
-            initialized after startup as well (see Task Watchdog Timer API Reference)
-
-    config TASK_WDT_PANIC
-        bool "Invoke panic handler on Task Watchdog timeout"
-        depends on TASK_WDT
-        default n
-        help
-            If this option is enabled, the Task Watchdog Timer will be configured to
-            trigger the panic handler when it times out. This can also be configured
-            at run time (see Task Watchdog Timer API Reference)
-
-    config TASK_WDT_TIMEOUT_S
-        int "Task Watchdog timeout period (seconds)"
-        depends on TASK_WDT
-        range 1 60
-        default 5
-        help
-            Timeout period configuration for the Task Watchdog Timer in seconds.
-            This is also configurable at run time (see Task Watchdog Timer API Reference)
-
-    config TASK_WDT_CHECK_IDLE_TASK_CPU0
-        bool "Watch CPU0 Idle Task"
-        depends on TASK_WDT
-        default y
-        help
-            If this option is enabled, the Task Watchdog Timer will watch the CPU0
-            Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
-            of CPU starvation as the Idle Task not being called is usually a symptom of
-            CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
-            tasks depend on the Idle Task getting some runtime every now and then.
-
-    config TASK_WDT_CHECK_IDLE_TASK_CPU1
-        bool "Watch CPU1 Idle Task"
-        depends on TASK_WDT && !FREERTOS_UNICORE
-        default y
-        help
-            If this option is enabled, the Task Wtachdog Timer will wach the CPU1
-            Idle Task.
-
-    config BROWNOUT_DET
+    config ESP32_BROWNOUT_DET
         #The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current
         #revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
         bool "Hardware brownout detect & reset"
@@ -657,9 +387,9 @@ menu "ESP32-specific"
             a specific value. If this happens, it will reset the chip in order to prevent unintended
             behaviour.
 
-    choice BROWNOUT_DET_LVL_SEL
+    choice ESP32_BROWNOUT_DET_LVL_SEL
         prompt "Brownout voltage level"
-        depends on BROWNOUT_DET
+        depends on ESP32_BROWNOUT_DET
         default BROWNOUT_DET_LVL_SEL_25
         help
             The brownout detector will reset the chip when the supply voltage is approximately
@@ -668,40 +398,40 @@ menu "ESP32-specific"
 
             #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
             #of the brownout threshold levels.
-        config BROWNOUT_DET_LVL_SEL_0
+        config ESP32_BROWNOUT_DET_LVL_SEL_0
             bool "2.43V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_1
+        config ESP32_BROWNOUT_DET_LVL_SEL_1
             bool "2.48V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_2
+        config ESP32_BROWNOUT_DET_LVL_SEL_2
             bool "2.58V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_3
+        config ESP32_BROWNOUT_DET_LVL_SEL_3
             bool "2.62V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_4
+        config ESP32_BROWNOUT_DET_LVL_SEL_4
             bool "2.67V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_5
+        config ESP32_BROWNOUT_DET_LVL_SEL_5
             bool "2.70V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_6
+        config ESP32_BROWNOUT_DET_LVL_SEL_6
             bool "2.77V +/- 0.05"
-        config BROWNOUT_DET_LVL_SEL_7
+        config ESP32_BROWNOUT_DET_LVL_SEL_7
             bool "2.80V +/- 0.05"
     endchoice
 
-    config BROWNOUT_DET_LVL
+    config ESP32_BROWNOUT_DET_LVL
         int
-        default 0 if BROWNOUT_DET_LVL_SEL_0
-        default 1 if BROWNOUT_DET_LVL_SEL_1
-        default 2 if BROWNOUT_DET_LVL_SEL_2
-        default 3 if BROWNOUT_DET_LVL_SEL_3
-        default 4 if BROWNOUT_DET_LVL_SEL_4
-        default 5 if BROWNOUT_DET_LVL_SEL_5
-        default 6 if BROWNOUT_DET_LVL_SEL_6
-        default 7 if BROWNOUT_DET_LVL_SEL_7
+        default 0 if ESP32_BROWNOUT_DET_LVL_SEL_0
+        default 1 if ESP32_BROWNOUT_DET_LVL_SEL_1
+        default 2 if ESP32_BROWNOUT_DET_LVL_SEL_2
+        default 3 if ESP32_BROWNOUT_DET_LVL_SEL_3
+        default 4 if ESP32_BROWNOUT_DET_LVL_SEL_4
+        default 5 if ESP32_BROWNOUT_DET_LVL_SEL_5
+        default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6
+        default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7
 
 
         #Reduce PHY TX power when brownout reset
-    config REDUCE_PHY_TX_POWER
+    config ESP32_REDUCE_PHY_TX_POWER
         bool "Reduce PHY TX power when brownout reset"
-        depends on BROWNOUT_DET
+        depends on ESP32_BROWNOUT_DET
         default y
         help
             When brownout reset occurs, reduce PHY TX power to keep the code running
@@ -742,9 +472,9 @@ menu "ESP32-specific"
             bool "None"
     endchoice
 
-    choice ESP32_RTC_CLOCK_SOURCE
+    choice ESP32_RTC_CLK_SRC
         prompt "RTC clock source"
-        default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
+        default ESP32_RTC_CLK_SRC_INT_RC
         help
             Choose which clock is used as RTC clock source.
 
@@ -765,19 +495,19 @@ menu "ESP32-specific"
               deep sleep current (by 5uA) but has better frequency stability than
               the internal 150kHz oscillator. It does not require external components.
 
-        config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
+        config ESP32_RTC_CLK_SRC_INT_RC
             bool "Internal 150kHz RC oscillator"
-        config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+        config ESP32_RTC_CLK_SRC_EXT_CRYS
             bool "External 32kHz crystal"
-        config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC
+        config ESP32_RTC_CLK_SRC_EXT_OSC
             bool "External 32kHz oscillator at 32K_XP pin"
-        config ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256
+        config ESP32_RTC_CLK_SRC_INT_8MD256
             bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
     endchoice
 
-    config ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+    config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
         bool "Additional current for external 32kHz crystal"
-        depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+        depends on ESP32_RTC_CLK_SRC_EXT_CRYS
         default "n"
         help
             Choose which additional current is used for rtc external crystal.
@@ -790,10 +520,10 @@ menu "ESP32-specific"
 
     config ESP32_RTC_CLK_CAL_CYCLES
         int "Number of cycles for RTC_SLOW_CLK calibration"
-        default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
-        default 1024 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
-        range 0 27000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL || ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC || ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256  # NOERROR
-        range 0 32766 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
+        default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS
+        default 1024 if ESP32_RTC_CLK_SRC_INT_RC
+        range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
+        range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC
         help
             When the startup code initializes RTC_SLOW_CLK, it can perform
             calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
@@ -812,7 +542,7 @@ menu "ESP32-specific"
 
     config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES
         int "Bootstrap cycles for external 32kHz crystal"
-        depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+        depends on ESP32_RTC_CLK_SRC_EXT_CRYS
         default 5
         range 0 32768
         help
@@ -875,7 +605,7 @@ menu "ESP32-specific"
         default 40 if ESP32_XTAL_FREQ_40
         default 26 if ESP32_XTAL_FREQ_26
 
-    config DISABLE_BASIC_ROM_CONSOLE
+    config ESP32_DISABLE_BASIC_ROM_CONSOLE
         bool "Permanently disable BASIC ROM Console"
         default n
         help
@@ -887,7 +617,7 @@ menu "ESP32-specific"
 
             (Enabling secure boot also disables the BASIC ROM Console by default.)
 
-    config NO_BLOBS
+    config ESP32_NO_BLOBS
         bool "No Binary Blobs"
         depends on !BT_ENABLED
         default n
@@ -895,18 +625,7 @@ menu "ESP32-specific"
             If enabled, this disables the linking of binary libraries in the application build. Note
             that after enabling this Wi-Fi/Bluetooth will not work.
 
-    config ESP_TIMER_PROFILING
-        bool "Enable esp_timer profiling features"
-        default n
-        help
-            If enabled, esp_timer_dump will dump information such as number of times
-            the timer was started, number of times the timer has triggered, and the
-            total time it took for the callback to run.
-            This option has some effect on timer performance and the amount of memory
-            used for timer storage, and should only be used for debugging/testing
-            purposes.
-
-    config COMPATIBLE_PRE_V2_1_BOOTLOADERS
+    config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
         bool "App compatible with bootloaders before IDF v2.1"
         default n
         help
@@ -922,16 +641,6 @@ menu "ESP32-specific"
 
             Enabling this setting adds approximately 1KB to the app's IRAM usage.
 
-    config ESP_ERR_TO_NAME_LOOKUP
-        bool "Enable lookup of error code strings"
-        default "y"
-        help
-            Functions esp_err_to_name() and esp_err_to_name_r() return string
-            representations of error codes from a pre-generated lookup table.
-            This option can be used to turn off the use of the look-up table in
-            order to save memory but this comes at the price of sacrificing
-            distinguishable (meaningful) output string representations.
-
     config ESP32_RTCDATA_IN_FAST_MEM
         bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
         default n

components/esp32/brownout.c

@@ -25,11 +25,11 @@
 #include "driver/rtc_cntl.h"
 #include "freertos/FreeRTOS.h"
 
-#ifdef CONFIG_BROWNOUT_DET_LVL
-#define BROWNOUT_DET_LVL CONFIG_BROWNOUT_DET_LVL
+#ifdef CONFIG_ESP32_BROWNOUT_DET_LVL
+#define BROWNOUT_DET_LVL CONFIG_ESP32_BROWNOUT_DET_LVL
 #else
 #define BROWNOUT_DET_LVL 0
-#endif //CONFIG_BROWNOUT_DET_LVL
+#endif //CONFIG_ESP32_BROWNOUT_DET_LVL
 
 static void rtc_brownout_isr_handler()
 {

components/esp32/clk.c

@@ -74,7 +74,7 @@ void esp_clk_init(void)
     rtc_config_t cfg = RTC_CONFIG_DEFAULT();
     rtc_init(cfg);
 
-#ifdef CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS
+#ifdef CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
     /* Check the bootloader set the XTAL frequency.
 
        Bootloaders pre-v2.1 don't do this.
@@ -85,7 +85,7 @@ void esp_clk_init(void)
         bootloader_clock_configure();
     }
 #else
-    /* If this assertion fails, either upgrade the bootloader or enable CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
+    /* If this assertion fails, either upgrade the bootloader or enable CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
     assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
 #endif
 
@@ -103,11 +103,11 @@ void esp_clk_init(void)
     rtc_wdt_protect_on();
 #endif
 
-#if defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL)
+#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
     select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
-#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC)
+#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
     select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
-#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256)
+#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
     select_rtc_slow_clk(SLOW_CLK_8MD256);
 #else
     select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -131,7 +131,7 @@ void esp_clk_init(void)
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 
     rtc_clk_cpu_freq_set_config(&new_config);
 
@@ -273,13 +273,13 @@ void esp_perip_clk_init(void)
 
     //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
     common_perip_clk |= DPORT_I2S0_CLK_EN |
-#if CONFIG_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
                         DPORT_UART_CLK_EN |
 #endif
-#if CONFIG_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
                         DPORT_UART1_CLK_EN |
 #endif
-#if CONFIG_CONSOLE_UART_NUM != 2
+#if CONFIG_ESP_CONSOLE_UART_NUM != 2
                         DPORT_UART2_CLK_EN |
 #endif
                         DPORT_SPI2_CLK_EN |

components/esp32/cpu_start.c

@@ -273,13 +273,13 @@ void IRAM_ATTR call_start_cpu1()
     cpu_configure_region_protection();
     cpu_init_memctl();
 
-#if CONFIG_CONSOLE_UART_NONE
+#if CONFIG_ESP_CONSOLE_UART_NONE
     ets_install_putc1(NULL);
     ets_install_putc2(NULL);
-#else // CONFIG_CONSOLE_UART_NONE
+#else // CONFIG_ESP_CONSOLE_UART_NONE
     uartAttach();
     ets_install_uart_printf();
-    uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
 #endif
 
     wdt_reset_cpu1_info_enable();
@@ -331,28 +331,28 @@ void start_cpu0_default(void)
     esp_perip_clk_init();
     intr_matrix_clear();
 
-#ifndef CONFIG_CONSOLE_UART_NONE
+#ifndef CONFIG_ESP_CONSOLE_UART_NONE
 #ifdef CONFIG_PM_ENABLE
     const int uart_clk_freq = REF_CLK_FREQ;
     /* When DFS is enabled, use REFTICK as UART clock source */
-    CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
+    CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
 #else
     const int uart_clk_freq = APB_CLK_FREQ;
 #endif // CONFIG_PM_DFS_ENABLE
-    uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
-#endif // CONFIG_CONSOLE_UART_NONE
+    uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
+#endif // CONFIG_ESP_CONSOLE_UART_NONE
 
-#if CONFIG_BROWNOUT_DET
+#if CONFIG_ESP32_BROWNOUT_DET
     esp_brownout_init();
 #endif
-#if CONFIG_DISABLE_BASIC_ROM_CONSOLE
+#if CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
     esp_efuse_disable_basic_rom_console();
 #endif
     rtc_gpio_force_hold_dis_all();
     esp_vfs_dev_uart_register();
     esp_reent_init(_GLOBAL_REENT);
-#ifndef CONFIG_CONSOLE_UART_NONE
-    const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
+#ifndef CONFIG_ESP_CONSOLE_UART_NONE
+    const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM);
     _GLOBAL_REENT->_stdin  = fopen(default_uart_dev, "r");
     _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
     _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
@@ -377,7 +377,7 @@ void start_cpu0_default(void)
     assert(err == ESP_OK && "Failed to init pthread module!");
 
     do_global_ctors();
-#if CONFIG_INT_WDT
+#if CONFIG_ESP_INT_WDT
     esp_int_wdt_init();
     //Initialize the interrupt watch dog for CPU0.
     esp_int_wdt_cpu_init();
@@ -438,7 +438,7 @@ void start_cpu1_default(void)
     esp_err_t err = esp_apptrace_init();
     assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
 #endif
-#if CONFIG_INT_WDT
+#if CONFIG_ESP_INT_WDT
     //Initialize the interrupt watch dog for CPU1.
     esp_int_wdt_cpu_init();
 #endif
@@ -495,21 +495,21 @@ static void main_task(void* args)
 #endif
 
     //Initialize task wdt if configured to do so
-#ifdef CONFIG_TASK_WDT_PANIC
-    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, true));
-#elif CONFIG_TASK_WDT
-    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, false));
+#ifdef CONFIG_ESP_TASK_WDT_PANIC
+    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
+#elif CONFIG_ESP_TASK_WDT
+    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
 #endif
 
     //Add IDLE 0 to task wdt
-#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0
+#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
     TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
     if(idle_0 != NULL){
         ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
     }
 #endif
     //Add IDLE 1 to task wdt
-#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1
+#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
     TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
     if(idle_1 != NULL){
         ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));

components/esp32/dport_panic_highint_hdl.S

@@ -86,7 +86,7 @@ xt_highint4:
     movi    a0, PANIC_RSN_CACHEERR
     j 9f
 1:
-#if CONFIG_INT_WDT_CHECK_CPU1
+#if CONFIG_ESP_INT_WDT_CHECK_CPU1
     /* Check if the cause is the app cpu failing to tick.*/
     movi    a0, int_wdt_app_cpu_ticked
     l32i    a0, a0, 0

components/esp32/esp_adapter.c

@@ -54,12 +54,12 @@ extern void esp_dport_access_stall_other_cpu_start_wrap(void);
 extern void esp_dport_access_stall_other_cpu_end_wrap(void);
 
 /*
- If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
+ If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
  If failed, try to allocate it in internal memory then.
  */
 IRAM_ATTR void *wifi_malloc( size_t size )
 {
-#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
     return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
 #else
     return malloc(size);
@@ -67,12 +67,12 @@ IRAM_ATTR void *wifi_malloc( size_t size )
 }
 
 /*
- If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
+ If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
  If failed, try to allocate it in internal memory then.
  */
 IRAM_ATTR void *wifi_realloc( void *ptr, size_t size )
 {
-#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
     return heap_caps_realloc_prefer(ptr, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
 #else
     return realloc(ptr, size);
@@ -80,12 +80,12 @@ IRAM_ATTR void *wifi_realloc( void *ptr, size_t size )
 }
 
 /*
- If CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
+ If CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is enabled. Prefer to allocate a chunk of memory in SPIRAM firstly.
  If failed, try to allocate it in internal memory then.
  */
 IRAM_ATTR void *wifi_calloc( size_t n, size_t size )
 {
-#if CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
     return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
 #else
     return calloc(n, size);

components/esp32/gdbstub.c

@@ -273,9 +273,9 @@ static int sendPacket(const char * text) {
 	return ST_OK;
 }
 
-#if CONFIG_GDBSTUB_SUPPORT_TASKS
+#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 
-#define STUB_TASKS_NUM  CONFIG_GDBSTUB_MAX_TASKS
+#define STUB_TASKS_NUM  CONFIG_ESP_GDBSTUB_MAX_TASKS
 
 //Remember the exception frame that caused panic since it's not saved in TCB
 static XtExcFrame paniced_frame;
@@ -365,7 +365,7 @@ static int findCurrentTaskIndex() {
 	return curTaskIndex;
 }
 
-#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
+#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 
 //Handle a command as received from GDB.
 static int gdbHandleCommand(unsigned char *cmd, int len) {
@@ -392,7 +392,7 @@ static int gdbHandleCommand(unsigned char *cmd, int len) {
 		gdbPacketEnd();
 	} else if (cmd[0]=='?') {	//Reply with stop reason
 		sendReason();
-#if CONFIG_GDBSTUB_SUPPORT_TASKS
+#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 	} else if (handlerState != HANDLER_TASK_SUPPORT_DISABLED) {
 		if (cmd[0]=='H') { //Continue with task
 			if (cmd[1]=='g' || cmd[1]=='c') {
@@ -473,7 +473,7 @@ static int gdbHandleCommand(unsigned char *cmd, int len) {
 			}
 			return sendPacket(NULL);
 		}
-#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
+#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 	} else {
 		//We don't recognize or support whatever GDB just sent us.
 		return sendPacket(NULL);
@@ -532,7 +532,7 @@ static int gdbReadCommand() {
 
 
 void esp_gdbstub_panic_handler(XtExcFrame *frame) {
-#if CONFIG_GDBSTUB_SUPPORT_TASKS
+#if CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 	if (handlerState == HANDLER_STARTED) {
 		//We have re-entered GDB Stub. Try disabling task support.
 		handlerState = HANDLER_TASK_SUPPORT_DISABLED;
@@ -542,9 +542,9 @@ void esp_gdbstub_panic_handler(XtExcFrame *frame) {
 		memcpy(&paniced_frame, frame, sizeof(paniced_frame));
 		dumpHwToRegfile(&paniced_frame);
 	}
-#else // CONFIG_GDBSTUB_SUPPORT_TASKS
+#else // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 	dumpHwToRegfile(frame);
-#endif // CONFIG_GDBSTUB_SUPPORT_TASKS
+#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
 
 	//Make sure txd/rxd are enabled
 	gpio_pullup_dis(1);

components/esp32/include/esp_sleep.h

@@ -95,7 +95,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
  *       source is used.
  * @return
  *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
+ *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
  *      - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
  */
 esp_err_t esp_sleep_enable_ulp_wakeup();
@@ -122,7 +122,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
  *
  * @return
  *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
+ *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
  *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
  */
 esp_err_t esp_sleep_enable_touchpad_wakeup();

components/esp32/int_wdt.c

@@ -32,14 +32,14 @@
 #include "driver/periph_ctrl.h"
 #include "esp_int_wdt.h"
 
-#if CONFIG_INT_WDT
+#if CONFIG_ESP_INT_WDT
 
 
 #define WDT_INT_NUM 24
 
 
 //Take care: the tick hook can also be called before esp_int_wdt_init() is called.
-#if CONFIG_INT_WDT_CHECK_CPU1
+#if CONFIG_ESP_INT_WDT_CHECK_CPU1
 //Not static; the ISR assembly checks this.
 bool int_wdt_app_cpu_ticked=false;
 
@@ -50,8 +50,8 @@ static void IRAM_ATTR tick_hook(void) {
         //Only feed wdt if app cpu also ticked.
         if (int_wdt_app_cpu_ticked) {
             TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
-            TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
-            TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
+            TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
+            TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
             TIMERG1.wdt_feed=1;
             TIMERG1.wdt_wprotect=0;
             int_wdt_app_cpu_ticked=false;
@@ -62,8 +62,8 @@ static void IRAM_ATTR tick_hook(void) {
 static void IRAM_ATTR tick_hook(void) {
     if (xPortGetCoreID()!=0) return;
     TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
-    TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
-    TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
+    TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
+    TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
     TIMERG1.wdt_feed=1;
     TIMERG1.wdt_wprotect=0;
 }

components/esp32/ld/esp32.ld

@@ -69,8 +69,8 @@ MEMORY
 
      Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
-  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
-                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
+  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
+                                     len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 
   /* external memory ,including data and text */
   extern_ram_seg(RWX)  :             org = 0x3F800000,
@@ -78,7 +78,7 @@ MEMORY
 }
 
 /* Heap ends at top of dram0_0_seg */
-_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
+_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
 
 _data_seg_org = ORIGIN(rtc_data_seg);
 

components/esp32/panic.c

@@ -67,8 +67,8 @@
 //printf may be broken, so we fix our own printing fns...
 static void panicPutChar(char c)
 {
-    while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
-    WRITE_PERI_REG(UART_FIFO_REG(CONFIG_CONSOLE_UART_NUM), c);
+    while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_ESP_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
+    WRITE_PERI_REG(UART_FIFO_REG(CONFIG_ESP_CONSOLE_UART_NUM), c);
 }
 
 static void panicPutStr(const char *c)
@@ -434,7 +434,7 @@ static void esp_panic_dig_reset() __attribute__((noreturn));
 static void esp_panic_dig_reset()
 {
     // make sure all the panic handler output is sent from UART FIFO
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     // switch to XTAL (otherwise we will keep running from the PLL)
     rtc_clk_cpu_freq_set_xtal();
     // reset the digital part

components/esp32/sdkconfig.rename

@@ -0,0 +1,38 @@
+# sdkconfig replacement configurations for deprecated options formatted as
+# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
+
+# ESP32-specific
+CONFIG_SPIRAM_SUPPORT                                   CONFIG_ESP32_SPIRAM_SUPPORT
+CONFIG_MEMMAP_TRACEMEM                                  CONFIG_ESP32_MEMMAP_TRACEMEM
+CONFIG_MEMMAP_TRACEMEM_TWOBANKS                         CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
+CONFIG_TRACEMEM_RESERVE_DRAM                            CONFIG_ESP32_TRACEMEM_RESERVE_DRAM
+CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS                  CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
+CONFIG_TWO_UNIVERSAL_MAC_ADDRESS                        CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
+CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS                       CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
+CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT    CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
+CONFIG_ESP32_RTC_CLOCK_SOURCE                           CONFIG_ESP32_RTC_CLK_SRC
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC               CONFIG_ESP32_RTC_CLK_SRC_INT_RC
+CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL          CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
+CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC              CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256           CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256
+CONFIG_DISABLE_BASIC_ROM_CONSOLE                        CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
+CONFIG_NO_BLOBS                                         CONFIG_ESP32_NO_BLOBS
+CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS                  CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
+CONFIG_ULP_COPROC_ENABLED                               CONFIG_ESP32_ULP_COPROC_ENABLED
+CONFIG_ULP_COPROC_RESERVE_MEM                           CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
+CONFIG_BROWNOUT_DET                                     CONFIG_ESP32_BROWNOUT_DET
+CONFIG_BROWNOUT_DET_LVL_SEL                             CONFIG_ESP32_BROWNOUT_DET_LVL_SEL
+CONFIG_BROWNOUT_DET_LVL_SEL_0                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0
+CONFIG_BROWNOUT_DET_LVL_SEL_1                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1
+CONFIG_BROWNOUT_DET_LVL_SEL_2                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2
+CONFIG_BROWNOUT_DET_LVL_SEL_3                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3
+CONFIG_BROWNOUT_DET_LVL_SEL_4                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4
+CONFIG_BROWNOUT_DET_LVL_SEL_5                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5
+CONFIG_BROWNOUT_DET_LVL_SEL_6                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6
+CONFIG_BROWNOUT_DET_LVL_SEL_7                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7
+CONFIG_BROWNOUT_DET_LVL                                 CONFIG_ESP32_BROWNOUT_DET_LVL
+CONFIG_REDUCE_PHY_TX_POWER                              CONFIG_ESP32_REDUCE_PHY_TX_POWER
+
+# SPI RAM config
+CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST           CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+CONFIG_PICO_PSRAM_CS_IO                                 CONFIG_SPIRAM_PICO_PSRAM_CS_IO

components/esp32/sleep_modes.c

@@ -48,13 +48,13 @@
 
 // Extra time it takes to enter and exit light sleep and deep sleep
 // For deep sleep, this is until the wake stub runs (not the app).
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
 #define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
 #define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
 #else
 #define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
 #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
-#endif // CONFIG_ESP32_RTC_CLOCK_SOURCE
+#endif // CONFIG_ESP32_RTC_CLK_SRC
 
 // Minimal amount of time we can sleep for
 #define LIGHT_SLEEP_MIN_TIME_US 200
@@ -305,7 +305,7 @@ esp_err_t esp_light_sleep_start()
     const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
                                           + CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
 
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
     const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
             flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US);
 
@@ -313,7 +313,7 @@ esp_err_t esp_light_sleep_start()
         pd_flags |= RTC_SLEEP_PD_VDDSDIO;
         s_config.sleep_time_adjustment += flash_enable_time_us;
     }
-#endif //CONFIG_SPIRAM_SUPPORT
+#endif //CONFIG_ESP32_SPIRAM_SUPPORT
 
     rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
 
@@ -390,7 +390,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
     } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
         s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
     }
-#ifdef CONFIG_ULP_COPROC_ENABLED
+#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
     else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
         s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
     }
@@ -404,10 +404,10 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
 
 esp_err_t esp_sleep_enable_ulp_wakeup()
 {
-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
     return ESP_ERR_NOT_SUPPORTED;
 #endif
-#ifdef CONFIG_ULP_COPROC_ENABLED
+#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
     if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
         ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
         return ESP_ERR_INVALID_STATE;
@@ -440,7 +440,7 @@ static void timer_wakeup_prepare()
 
 esp_err_t esp_sleep_enable_touchpad_wakeup()
 {
-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
     return ESP_ERR_NOT_SUPPORTED;
 #endif
     if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
@@ -705,7 +705,7 @@ static uint32_t get_power_down_flags()
 
     if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
     // If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
-#if ((defined CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL) && (defined CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT))
+#if ((defined CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT))
     pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
 #endif
     }

components/esp32/spiram.c

@@ -46,7 +46,7 @@ we add more types of external RAM memory, this can be made into a more intellige
 #endif
 #endif
 
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
 
 static const char* TAG = "spiram";
 

components/esp32/spiram_psram.c

@@ -36,7 +36,7 @@
 #include "driver/spi_common.h"
 #include "driver/periph_ctrl.h"
 
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
 #include "soc/rtc.h"
 
 //Commands for PSRAM chip
@@ -118,7 +118,7 @@ typedef enum {
 #define PICO_FLASH_SPIHD_SD2_IO         11
 
 #define PICO_PSRAM_CLK_IO                6
-#define PICO_PSRAM_CS_IO                CONFIG_PICO_PSRAM_CS_IO
+#define PICO_PSRAM_CS_IO                CONFIG_SPIRAM_PICO_PSRAM_CS_IO
 #define PICO_PSRAM_SPIQ_SD0_IO          17
 #define PICO_PSRAM_SPID_SD1_IO           8
 #define PICO_PSRAM_SPIWP_SD3_IO          7
@@ -836,4 +836,4 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
     CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
 }
 
-#endif // CONFIG_SPIRAM_SUPPORT
+#endif // CONFIG_ESP32_SPIRAM_SUPPORT

components/esp32/test/test_4mpsram.c

@@ -6,7 +6,7 @@
 
 static const char TAG[] = "test_psram";
 
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
 static void test_psram_content()
 {
     const int test_size = 2048;
@@ -40,7 +40,7 @@ static void test_psram_content()
 TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
 {
     spi_host_device_t host;
-#if !CONFIG_SPIRAM_SUPPORT || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
+#if !CONFIG_ESP32_SPIRAM_SUPPORT || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
     //currently all 8M psram don't need more SPI peripherals
     host = -1;
 #elif CONFIG_SPIRAM_OCCUPY_HSPI_HOST
@@ -66,7 +66,7 @@ TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
         TEST_ASSERT(claim_vspi==true);
     }
 
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
     test_psram_content();
 #endif
 }

components/esp32/test/test_dport.c

@@ -107,8 +107,8 @@ TEST_CASE("access DPORT and APB at same time", "[esp32]")
 
 void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
 {
-    const int uart_num = CONFIG_CONSOLE_UART_NUM;
-    const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE;
+    const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
+    const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
     dport_test_result = false;
     apb_test_result = false;
     rtc_cpu_freq_config_t old_config;

components/esp32/test/test_pm.c

@@ -122,7 +122,7 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
 
 TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
 
     /* Set up GPIO used to wake up RTC */
     const int ext1_wakeup_gpio = 25;

components/esp32/test/test_sleep.c

@@ -125,7 +125,7 @@ TEST_CASE("light sleep stress test with periodic esp_timer", "[deepsleep]")
 }
 
 
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
 #define MAX_SLEEP_TIME_ERROR_US 200
 #else
 #define MAX_SLEEP_TIME_ERROR_US 100
@@ -176,8 +176,8 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]")
 {
 #ifndef CONFIG_PM_ENABLE
     const int uart_clk_freq = REF_CLK_FREQ;
-    CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
-    uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
+    CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
+    uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 
     rtc_cpu_freq_config_t config_xtal, config_default;

components/esp32/test/test_spiram_cache_flush.c

@@ -23,7 +23,7 @@ This code tests the interaction between PSRAM and SPI flash routines.
 #include "esp_partition.h"
 #include "test_utils.h"
 
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
 
 #if CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC
 #define USE_CAPS_ALLOC 1
@@ -181,4 +181,4 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
 #endif
 }
 
-#endif // CONFIG_SPIRAM_SUPPORT
+#endif // CONFIG_ESP32_SPIRAM_SUPPORT

components/esp_common/Kconfig

@@ -0,0 +1,219 @@
+menu "Common ESP-related"
+
+    config ESP_TIMER_PROFILING
+        bool "Enable esp_timer profiling features"
+        default n
+        help
+            If enabled, esp_timer_dump will dump information such as number of times the timer was started, number of
+            times the timer has triggered, and the total time it took for the callback to run. This option has some
+            effect on timer performance and the amount of memory used for timer storage, and should only be used for
+            debugging/testing purposes.
+
+    config ESP_ERR_TO_NAME_LOOKUP
+        bool "Enable lookup of error code strings"
+        default "y"
+        help
+            Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a
+            pre-generated lookup table. This option can be used to turn off the use of the look-up table in order to
+            save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
+            representations.
+
+    config ESP_SYSTEM_EVENT_QUEUE_SIZE
+        int "System event queue size"
+        default 32
+        help
+            Config system event queue size in different application.
+
+    config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
+        int "Event loop task stack size"
+        default 2304
+        help
+            Config system event task stack size in different application.
+
+    config ESP_MAIN_TASK_STACK_SIZE
+        int "Main task stack size"
+        default 3584
+        help
+            Configure the "main task" stack size. This is the stack of the task
+            which calls app_main(). If app_main() returns then this task is deleted
+            and its stack memory is freed.
+
+    config ESP_IPC_TASK_STACK_SIZE
+        int "Inter-Processor Call (IPC) task stack size"
+        default 1024
+        range 512 65536 if !ESP32_APPTRACE_ENABLE
+        range 2048 65536 if ESP32_APPTRACE_ENABLE
+        help
+            Configure the IPC tasks stack size. One IPC task runs on each core
+            (in dual core mode), and allows for cross-core function calls.
+
+            See IPC documentation for more details.
+
+            The default stack size should be enough for most common use cases.
+            It can be shrunk if you are sure that you do not use any custom
+            IPC functionality.
+
+    config ESP_TIMER_TASK_STACK_SIZE
+        int "High-resolution timer task stack size"
+        default 3584
+        range 2048 65536
+        help
+            Configure the stack size of esp_timer/ets_timer task. This task is used
+            to dispatch callbacks of timers created using ets_timer and esp_timer
+            APIs. If you are seing stack overflow errors in timer task, increase
+            this value.
+
+            Note that this is not the same as FreeRTOS timer task. To configure
+            FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
+            in "FreeRTOS" menu.
+
+    choice ESP_CONSOLE_UART
+        prompt "UART for console output"
+        default ESP_CONSOLE_UART_DEFAULT
+        help
+            Select whether to use UART for console output (through stdout and stderr).
+
+            - Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
+            - If "Custom" is selected, UART0 or UART1 can be chosen,
+              and any pins can be selected.
+            - If "None" is selected, there will be no console output on any UART, except
+              for initial output from ROM bootloader. This output can be further suppressed by
+              bootstrapping GPIO13 pin to low logic level.
+
+        config ESP_CONSOLE_UART_DEFAULT
+            bool "Default: UART0, TX=GPIO1, RX=GPIO3"
+        config ESP_CONSOLE_UART_CUSTOM
+            bool "Custom"
+        config ESP_CONSOLE_UART_NONE
+            bool "None"
+    endchoice
+
+    choice ESP_CONSOLE_UART_NUM
+        prompt "UART peripheral to use for console output (0-1)"
+        depends on ESP_CONSOLE_UART_CUSTOM
+        default ESP_CONSOLE_UART_CUSTOM_NUM_0
+        help
+            Due of a ROM bug, UART2 is not supported for console output
+            via ets_printf.
+
+        config ESP_CONSOLE_UART_CUSTOM_NUM_0
+            bool "UART0"
+        config ESP_CONSOLE_UART_CUSTOM_NUM_1
+            bool "UART1"
+    endchoice
+
+    config ESP_CONSOLE_UART_NUM
+        int
+        default 0 if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_NONE
+        default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
+        default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
+
+    config ESP_CONSOLE_UART_TX_GPIO
+        int "UART TX on GPIO#"
+        depends on ESP_CONSOLE_UART_CUSTOM
+        range 0 33
+        default 19
+
+    config ESP_CONSOLE_UART_RX_GPIO
+        int "UART RX on GPIO#"
+        depends on ESP_CONSOLE_UART_CUSTOM
+        range 0 39
+        default 21
+
+    config ESP_CONSOLE_UART_BAUDRATE
+        int "UART console baud rate"
+        depends on !ESP_CONSOLE_UART_NONE
+        default 115200
+        range 1200 4000000
+
+
+    config ESP_GDBSTUB_SUPPORT_TASKS
+        bool "GDBStub: enable listing FreeRTOS tasks"
+        default y
+        depends on ESP32_PANIC_GDBSTUB
+        help
+            If enabled, GDBStub can supply the list of FreeRTOS tasks to GDB.
+            Thread list can be queried from GDB using 'info threads' command.
+            Note that if GDB task lists were corrupted, this feature may not work.
+            If GDBStub fails, try disabling this feature.
+
+    config ESP_GDBSTUB_MAX_TASKS
+        int "GDBStub: maximum number of tasks supported"
+        default 32
+        depends on ESP_GDBSTUB_SUPPORT_TASKS
+        help
+            Set the number of tasks which GDB Stub will support.
+
+
+    config ESP_INT_WDT
+        bool "Interrupt watchdog"
+        default y
+        help
+            This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
+            either because a task turned off interrupts and did not turn them on for a long time, or because an
+            interrupt handler did not return. It will try to invoke the panic handler first and failing that
+            reset the SoC.
+
+    config ESP_INT_WDT_TIMEOUT_MS
+        int "Interrupt watchdog timeout (ms)"
+        depends on ESP_INT_WDT
+        default 300 if !ESP32_SPIRAM_SUPPORT
+        default 800 if ESP32_SPIRAM_SUPPORT
+        range 10 10000
+        help
+            The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
+
+    config ESP_INT_WDT_CHECK_CPU1
+        bool "Also watch CPU1 tick interrupt"
+        depends on ESP_INT_WDT && !FREERTOS_UNICORE
+        default y
+        help
+            Also detect if interrupts on CPU 1 are disabled for too long.
+
+    config ESP_TASK_WDT
+        bool "Initialize Task Watchdog Timer on startup"
+        default y
+        help
+            The Task Watchdog Timer can be used to make sure individual tasks are still
+            running. Enabling this option will cause the Task Watchdog Timer to be
+            initialized automatically at startup. The Task Watchdog timer can be
+            initialized after startup as well (see Task Watchdog Timer API Reference)
+
+    config ESP_TASK_WDT_PANIC
+        bool "Invoke panic handler on Task Watchdog timeout"
+        depends on ESP_TASK_WDT
+        default n
+        help
+            If this option is enabled, the Task Watchdog Timer will be configured to
+            trigger the panic handler when it times out. This can also be configured
+            at run time (see Task Watchdog Timer API Reference)
+
+    config ESP_TASK_WDT_TIMEOUT_S
+        int "Task Watchdog timeout period (seconds)"
+        depends on ESP_TASK_WDT
+        range 1 60
+        default 5
+        help
+            Timeout period configuration for the Task Watchdog Timer in seconds.
+            This is also configurable at run time (see Task Watchdog Timer API Reference)
+
+    config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
+        bool "Watch CPU0 Idle Task"
+        depends on ESP_TASK_WDT
+        default y
+        help
+            If this option is enabled, the Task Watchdog Timer will watch the CPU0
+            Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
+            of CPU starvation as the Idle Task not being called is usually a symptom of
+            CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
+            tasks depend on the Idle Task getting some runtime every now and then.
+
+    config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
+        bool "Watch CPU1 Idle Task"
+        depends on ESP_TASK_WDT && !FREERTOS_UNICORE
+        default y
+        help
+            If this option is enabled, the Task Wtachdog Timer will wach the CPU1
+            Idle Task.
+
+endmenu # Common ESP-related

components/esp_common/include/esp_system.h

@@ -37,7 +37,7 @@ typedef enum {
 /** @cond */
 #define TWO_UNIVERSAL_MAC_ADDR 2
 #define FOUR_UNIVERSAL_MAC_ADDR 4
-#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
 /** @endcond */
 
 /**

components/esp_common/include/esp_task.h

@@ -47,12 +47,12 @@
 
 /* idf task */
 #define ESP_TASK_TIMER_PRIO           (ESP_TASK_PRIO_MAX - 3)
-#define ESP_TASK_TIMER_STACK          (CONFIG_TIMER_TASK_STACK_SIZE +  TASK_EXTRA_STACK_SIZE)
+#define ESP_TASK_TIMER_STACK          (CONFIG_ESP_TIMER_TASK_STACK_SIZE +  TASK_EXTRA_STACK_SIZE)
 #define ESP_TASKD_EVENT_PRIO          (ESP_TASK_PRIO_MAX - 5)
-#define ESP_TASKD_EVENT_STACK         (CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
+#define ESP_TASKD_EVENT_STACK         (CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
 #define ESP_TASK_TCPIP_PRIO           (ESP_TASK_PRIO_MAX - 7)
 #define ESP_TASK_TCPIP_STACK          (CONFIG_LWIP_TCPIP_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
 #define ESP_TASK_MAIN_PRIO            (ESP_TASK_PRIO_MIN + 1)
-#define ESP_TASK_MAIN_STACK           (CONFIG_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
+#define ESP_TASK_MAIN_STACK           (CONFIG_ESP_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
 
 #endif

components/esp_common/sdkconfig.rename

@@ -0,0 +1,28 @@
+# sdkconfig replacement configurations for deprecated options formatted as
+# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
+
+CONFIG_SYSTEM_EVENT_QUEUE_SIZE                          CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
+CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE                     CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
+CONFIG_MAIN_TASK_STACK_SIZE                             CONFIG_ESP_MAIN_TASK_STACK_SIZE
+CONFIG_IPC_TASK_STACK_SIZE                              CONFIG_ESP_IPC_TASK_STACK_SIZE
+CONFIG_TIMER_TASK_STACK_SIZE                            CONFIG_ESP_TIMER_TASK_STACK_SIZE
+CONFIG_CONSOLE_UART                                     CONFIG_ESP_CONSOLE_UART
+CONFIG_CONSOLE_UART_DEFAULT                             CONFIG_ESP_CONSOLE_UART_DEFAULT
+CONFIG_CONSOLE_UART_CUSTOM                              CONFIG_ESP_CONSOLE_UART_CUSTOM
+CONFIG_CONSOLE_UART_NONE                                CONFIG_ESP_CONSOLE_UART_NONE
+CONFIG_CONSOLE_UART_NUM                                 CONFIG_ESP_CONSOLE_UART_NUM
+CONFIG_CONSOLE_UART_CUSTOM_NUM_0                        CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0
+CONFIG_CONSOLE_UART_CUSTOM_NUM_1                        CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1
+CONFIG_CONSOLE_UART_TX_GPIO                             CONFIG_ESP_CONSOLE_UART_TX_GPIO
+CONFIG_CONSOLE_UART_RX_GPIO                             CONFIG_ESP_CONSOLE_UART_RX_GPIO
+CONFIG_CONSOLE_UART_BAUDRATE                            CONFIG_ESP_CONSOLE_UART_BAUDRATE
+CONFIG_GDBSTUB_SUPPORT_TASKS                            CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
+CONFIG_GDBSTUB_MAX_TASKS                                CONFIG_ESP_GDBSTUB_MAX_TASKS
+CONFIG_INT_WDT                                          CONFIG_ESP_INT_WDT
+CONFIG_INT_WDT_TIMEOUT_MS                               CONFIG_ESP_INT_WDT_TIMEOUT_MS
+CONFIG_INT_WDT_CHECK_CPU1                               CONFIG_ESP_INT_WDT_CHECK_CPU1
+CONFIG_TASK_WDT                                         CONFIG_ESP_TASK_WDT
+CONFIG_TASK_WDT_PANIC                                   CONFIG_ESP_TASK_WDT_PANIC
+CONFIG_TASK_WDT_TIMEOUT_S                               CONFIG_ESP_TASK_WDT_TIMEOUT_S
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0                    CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1                    CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1

components/esp_common/src/ipc.c

@@ -92,7 +92,7 @@ static void esp_ipc_init()
     for (int i = 0; i < portNUM_PROCESSORS; ++i) {
         snprintf(task_name, sizeof(task_name), "ipc%d", i);
         s_ipc_sem[i] = xSemaphoreCreateBinary();
-        portBASE_TYPE res = xTaskCreatePinnedToCore(ipc_task, task_name, CONFIG_IPC_TASK_STACK_SIZE, (void*) i,
+        portBASE_TYPE res = xTaskCreatePinnedToCore(ipc_task, task_name, CONFIG_ESP_IPC_TASK_STACK_SIZE, (void*) i,
                                                     configMAX_PRIORITIES - 1, NULL, i);
         assert(res == pdTRUE);
     }

components/esp_event/default_event_loop.c

@@ -76,7 +76,7 @@ esp_err_t esp_event_loop_create_default()
     }
 
     esp_event_loop_args_t loop_args = {
-        .queue_size = CONFIG_SYSTEM_EVENT_QUEUE_SIZE,
+        .queue_size = CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE,
         .task_name = "sys_evt",
         .task_stack_size = ESP_TASKD_EVENT_STACK,
         .task_priority = ESP_TASKD_EVENT_PRIO,

components/esp_event/test/test_event.c

@@ -42,7 +42,7 @@ static const char* TAG = "test_event";
 
 #define TEST_TEARDOWN() \
         test_teardown(); \
-        vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); \
+        vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)); \
         TEST_ASSERT_EQUAL(free_mem_before, heap_caps_get_free_size(MALLOC_CAP_DEFAULT));
 
 typedef struct {
@@ -118,7 +118,7 @@ static BaseType_t test_event_get_core()
 static esp_event_loop_args_t test_event_get_default_loop_args()
 {
     esp_event_loop_args_t loop_config = {
-        .queue_size = CONFIG_SYSTEM_EVENT_QUEUE_SIZE,
+        .queue_size = CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE,
         .task_name = "loop",
         .task_priority = s_test_priority,
         .task_stack_size = 2048,
@@ -855,11 +855,11 @@ static void performance_test(bool dedicated_task)
     // Enabling profiling will slow down event dispatch, so the set threshold
     // is not valid when it is enabled.
 #else
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
     TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH, "%d", average);
 #else
     TEST_PERFORMANCE_GREATER_THAN(EVENT_DISPATCH_PSRAM, "%d", average);
-#endif // CONFIG_SPIRAM_SUPPORT
+#endif // CONFIG_ESP32_SPIRAM_SUPPORT
 #endif // CONFIG_ESP_EVENT_LOOP_PROFILING
 }
 
@@ -912,11 +912,11 @@ TEST_CASE("can post to loop from handler - dedicated task", "[event]")
     }
 
     TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_w_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0,
-                         pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
+                         pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
 
     xSemaphoreGive(arg.mutex);
 
-    vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
+    vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_event_loop_delete(loop_w_task));
 
@@ -964,15 +964,15 @@ TEST_CASE("can post to loop from handler - no dedicated task", "[event]")
 
     TEST_ASSERT_EQUAL(ESP_OK, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV1, &loop_wo_task, sizeof(&loop_wo_task), portMAX_DELAY));
 
-    vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
+    vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
 
     // For loop without tasks, posting is more restrictive. Posting should wait until execution of handler finishes
     TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, esp_event_post_to(loop_wo_task, s_test_base1, TEST_EVENT_BASE1_EV2, NULL, 0,
-                         pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
+                         pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER)));
 
     xSemaphoreGive(arg.mutex);
 
-    vTaskDelay(pdMS_TO_TICKS(CONFIG_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
+    vTaskDelay(pdMS_TO_TICKS(CONFIG_ESP_INT_WDT_TIMEOUT_MS * TEST_CONFIG_WAIT_MULTIPLIER));
 
     vTaskDelete(mtask);
 

components/esp_wifi/CMakeLists.txt

@@ -11,14 +11,14 @@ set(COMPONENT_PRIV_INCLUDEDIRS)
 set(COMPONENT_REQUIRES)
 set(COMPONENT_PRIV_REQUIRES "wpa_supplicant" "nvs_flash")
 
-if(NOT CONFIG_NO_BLOBS)
+if(NOT CONFIG_ESP32_NO_BLOBS)
     set(COMPONENT_ADD_LDFRAGMENTS "linker.lf")
 endif()
 
 register_component()
 target_link_libraries(${COMPONENT_LIB} "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib_${IDF_TARGET}")
 
-if(NOT CONFIG_NO_BLOBS)
+if(NOT CONFIG_ESP32_NO_BLOBS)
     target_link_libraries(${COMPONENT_LIB} "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib_${IDF_TARGET}")
     target_link_libraries(${COMPONENT_LIB} coexist core espnow mesh net80211 phy pp rtc smartconfig wpa2 wpa wps)
 endif()
@@ -43,4 +43,4 @@ if(CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION)
     add_dependencies(app phy_init_data)
 
     esptool_py_flash_project_args(phy ${phy_partition_offset} ${phy_init_data_bin} FLASH_IN_PROJECT)
-endif()
+endif()

components/esp_wifi/Kconfig

@@ -45,10 +45,10 @@ menu Wi-Fi
 
     config ESP32_WIFI_STATIC_RX_BUFFER_NUM
         int "Max number of WiFi static RX buffers"
-        range 2 25 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        range 8 25 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        default 10 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        default 16 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+        range 2 25 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        range 8 25 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        default 10 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
         help
             Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM.
             The static rx buffers are allocated when esp_wifi_init is called, they are not freed
@@ -170,10 +170,10 @@ menu Wi-Fi
     config ESP32_WIFI_RX_BA_WIN
         int "WiFi AMPDU RX BA window size"
         depends on ESP32_WIFI_AMPDU_RX_ENABLED
-        range 2 32 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        range 16 32 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        default 6 if !WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
-        default 16 if WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST
+        range 2 32 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        range 16 32 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        default 6 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+        default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
         help
             Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better
             compatibility but more memory. Most of time we should NOT change the default value unless special

components/esp_wifi/component.mk

@@ -5,7 +5,7 @@
 COMPONENT_ADD_INCLUDEDIRS := include
 COMPONENT_SRCDIRS := src
 
-ifndef CONFIG_NO_BLOBS
+ifndef CONFIG_ESP32_NO_BLOBS
     LIBS := core rtc net80211 pp wpa smartconfig coexist wps wpa2 espnow phy mesh
     COMPONENT_ADD_LDFLAGS += -L$(COMPONENT_PATH)/lib_$(IDF_TARGET) \
                           $(addprefix -l,$(LIBS))

components/esp_wifi/src/phy_init.c

@@ -582,7 +582,7 @@ static esp_err_t store_cal_data_to_nvs_handle(nvs_handle handle,
     return err;
 }
 
-#if CONFIG_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
 static void esp_phy_reduce_tx_power(esp_phy_init_data_t* init_data)
 {
     uint8_t i;
@@ -603,7 +603,7 @@ void esp_phy_load_cal_and_init(phy_rf_module_t module)
         abort();
     }
 
-#if CONFIG_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
     const esp_phy_init_data_t* phy_init_data = esp_phy_get_init_data();
     if (phy_init_data == NULL) {
         ESP_LOGE(TAG, "failed to obtain PHY init data");
@@ -653,7 +653,7 @@ void esp_phy_load_cal_and_init(phy_rf_module_t module)
     esp_phy_rf_init(init_data, PHY_RF_CAL_FULL, cal_data, module);
 #endif
 
-#if CONFIG_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
     esp_phy_release_init_data(phy_init_data);
     free(init_data);
 #else

components/ethernet/emac_main.c

@@ -1116,7 +1116,7 @@ esp_err_t esp_eth_init_internal(eth_config_t *config)
     periph_module_enable(PERIPH_EMAC_MODULE);
 
     if (emac_config.clock_mode != ETH_CLOCK_GPIO0_IN) {
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
         if (esp_spiram_is_initialized()) {
             ESP_LOGE(TAG, "GPIO16 and GPIO17 has been occupied by PSRAM, Only ETH_CLOCK_GPIO_IN is supported!");
             ret = ESP_FAIL;

components/freertos/port.c

@@ -435,7 +435,7 @@ void vPortSetStackWatchpoint( void* pxStackStart ) {
 	esp_set_watchpoint(1, (char*)addr, 32, ESP_WATCHPOINT_STORE);
 }
 
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
 /*
  * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
  */
@@ -459,7 +459,7 @@ void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t
 	vPortCPUReleaseMutexIntsDisabled(&extram_mux);
 #endif
 }
-#endif //defined(CONFIG_SPIRAM_SUPPORT)
+#endif //defined(CONFIG_ESP32_SPIRAM_SUPPORT)
 
 
 

components/freertos/portmux_impl.h

@@ -64,7 +64,7 @@
 #undef PORTMUX_COMPARE_SET_FN_NAME
 
 
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
 
 #define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledExtram
 #define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledExtram
@@ -91,7 +91,7 @@
 
 
 static inline bool __attribute__((always_inline)) vPortCPUAcquireMutexIntsDisabled(PORTMUX_AQUIRE_MUX_FN_ARGS) {
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
 	if (esp_ptr_external_ram(mux)) {
 		return vPortCPUAcquireMutexIntsDisabledExtram(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux));
 	}
@@ -101,7 +101,7 @@ static inline bool __attribute__((always_inline)) vPortCPUAcquireMutexIntsDisabl
 
 
 static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS) {
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
 	if (esp_ptr_external_ram(mux)) {
 		vPortCPUReleaseMutexIntsDisabledExtram(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux));
 		return;

components/freertos/test/test_spinlocks.c

@@ -48,7 +48,7 @@ TEST_CASE("portMUX spinlocks (no contention)", "[freertos]")
 #ifdef CONFIG_FREERTOS_UNICORE
     TEST_PERFORMANCE_LESS_THAN(FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE, "%d cycles/op", ((end - start)/REPEAT_OPS));
 #else
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
     TEST_PERFORMANCE_LESS_THAN(FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM, "%d cycles/op", ((end - start)/REPEAT_OPS));
 #else
     TEST_PERFORMANCE_LESS_THAN(FREERTOS_SPINLOCK_CYCLES_PER_OP, "%d cycles/op", ((end - start)/REPEAT_OPS));

components/mbedtls/Kconfig

@@ -24,7 +24,7 @@ menu "mbedTLS"
 
         config MBEDTLS_EXTERNAL_MEM_ALLOC
             bool "External SPIRAM"
-            depends on SPIRAM_SUPPORT
+            depends on ESP32_SPIRAM_SUPPORT
 
         config MBEDTLS_DEFAULT_MEM_ALLOC
             bool "Default alloc mode"

components/newlib/Kconfig

@@ -0,0 +1,72 @@
+menu "Newlib"
+
+    choice NEWLIB_STDOUT_LINE_ENDING
+        prompt "Line ending for UART output"
+        default NEWLIB_STDOUT_LINE_ENDING_CRLF
+        help
+            This option allows configuring the desired line endings sent to UART
+            when a newline ('\n', LF) appears on stdout.
+            Three options are possible:
+
+            CRLF: whenever LF is encountered, prepend it with CR
+
+            LF: no modification is applied, stdout is sent as is
+
+            CR: each occurence of LF is replaced with CR
+
+            This option doesn't affect behavior of the UART driver (drivers/uart.h).
+
+        config NEWLIB_STDOUT_LINE_ENDING_CRLF
+            bool "CRLF"
+        config NEWLIB_STDOUT_LINE_ENDING_LF
+            bool "LF"
+        config NEWLIB_STDOUT_LINE_ENDING_CR
+            bool "CR"
+    endchoice
+
+    choice NEWLIB_STDIN_LINE_ENDING
+        prompt "Line ending for UART input"
+        default NEWLIB_STDIN_LINE_ENDING_CR
+        help
+            This option allows configuring which input sequence on UART produces
+            a newline ('\n', LF) on stdin.
+            Three options are possible:
+
+            CRLF: CRLF is converted to LF
+
+            LF: no modification is applied, input is sent to stdin as is
+
+            CR: each occurence of CR is replaced with LF
+
+            This option doesn't affect behavior of the UART driver (drivers/uart.h).
+
+        config NEWLIB_STDIN_LINE_ENDING_CRLF
+            bool "CRLF"
+        config NEWLIB_STDIN_LINE_ENDING_LF
+            bool "LF"
+        config NEWLIB_STDIN_LINE_ENDING_CR
+            bool "CR"
+    endchoice
+
+    config NEWLIB_NANO_FORMAT
+        bool "Enable 'nano' formatting options for printf/scanf family"
+        default n
+        help
+            ESP32 ROM contains parts of newlib C library, including printf/scanf family
+            of functions. These functions have been compiled with so-called "nano"
+            formatting option. This option doesn't support 64-bit integer formats and C99
+            features, such as positional arguments.
+
+            For more details about "nano" formatting option, please see newlib readme file,
+            search for '--enable-newlib-nano-formatted-io':
+            https://sourceware.org/newlib/README
+
+            If this option is enabled, build system will use functions available in
+            ROM, reducing the application binary size. Functions available in ROM run
+            faster than functions which run from flash. Functions available in ROM can
+            also run when flash instruction cache is disabled.
+
+            If you need 64-bit integer formatting support or C99 features, keep this
+            option disabled.
+
+endmenu # Newlib

components/newlib/test/test_newlib.c

@@ -125,14 +125,14 @@ static bool fn_in_rom(void *fn, const char *name)
 
 TEST_CASE("check if ROM or Flash is used for functions", "[newlib]")
 {
-#if defined(CONFIG_NEWLIB_NANO_FORMAT) && !defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_NEWLIB_NANO_FORMAT) && !defined(CONFIG_ESP32_SPIRAM_SUPPORT)
     TEST_ASSERT(fn_in_rom(printf, "printf"));
     TEST_ASSERT(fn_in_rom(sscanf, "sscanf"));
 #else
     TEST_ASSERT_FALSE(fn_in_rom(printf, "printf"));
     TEST_ASSERT_FALSE(fn_in_rom(sscanf, "sscanf"));
 #endif
-#if !defined(CONFIG_SPIRAM_SUPPORT)
+#if !defined(CONFIG_ESP32_SPIRAM_SUPPORT)
     TEST_ASSERT(fn_in_rom(atoi,   "atoi"));
     TEST_ASSERT(fn_in_rom(strtol, "strtol"));
 #else

components/newlib/test/test_time.c

@@ -346,7 +346,7 @@ void test_posix_timers_clock (void)
     printf("WITH_RTC    ");
 #endif
 
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
     printf("External (crystal) Frequency = %d Hz\n", rtc_clk_slow_freq_get_hz());
 #else
     printf("Internal Frequency = %d Hz\n", rtc_clk_slow_freq_get_hz());

components/pthread/pthread.c

@@ -504,13 +504,13 @@ int pthread_once(pthread_once_t *once_control, void (*init_routine)(void))
     }
 
     uint32_t res = 1;
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
     if (esp_ptr_external_ram(once_control)) {
         uxPortCompareSetExtram((uint32_t *) &once_control->init_executed, 0, &res);
     } else {
 #endif
         uxPortCompareSet((uint32_t *) &once_control->init_executed, 0, &res);
-#if defined(CONFIG_SPIRAM_SUPPORT)
+#if defined(CONFIG_ESP32_SPIRAM_SUPPORT)
     }
 #endif
     // Check if compare and set was successful

components/sdmmc/test/test_sd.c

@@ -29,7 +29,7 @@
 #include <unistd.h>
 
 // Can't test eMMC (slot 0) and PSRAM together
-#ifndef CONFIG_SPIRAM_SUPPORT
+#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
 #define WITH_EMMC_TEST
 #endif
 

components/soc/esp32/rtc_clk.c

@@ -127,7 +127,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
     REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
     REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
 
-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
     /* TOUCH sensor can provide additional current to external XTAL.
        In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
     SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
@@ -141,7 +141,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
        So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
      */
     SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
-#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#endif // CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
     /* Power up external xtal */
     SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
 }
@@ -155,10 +155,10 @@ void rtc_clk_32k_enable(bool enable)
         CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
         CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
 
-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
         /* Power down TOUCH */
         CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
-#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
+#endif // CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
     }
 }
 

components/soc/esp32/soc_memory_layout.c

@@ -60,7 +60,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
     { "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
     { "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
     { "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
     //Type 15: SPI SRAM data
     { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
 #endif
@@ -75,7 +75,7 @@ Because of requirements in the coalescing code which merges adjacent regions, th
 from low to high start address.
 */
 const soc_memory_region_t soc_memory_regions[] = {
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
     { 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
 #endif
     { 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
@@ -158,15 +158,15 @@ SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM A
 
 SOC_RESERVE_MEMORY_REGION(0x3ffae000, 0x3ffae6e0, rom_data);
 
-#if CONFIG_MEMMAP_TRACEMEM
-#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
+#if CONFIG_ESP32_MEMMAP_TRACEMEM
+#if CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
 SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region, 32K for both cpu
 #else
 SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace mem region, 16K (upper-half) for pro cpu
 #endif
 #endif
 
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
 SOC_RESERVE_MEMORY_REGION(0x3f800000, 0x3fC00000, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
 #endif
 

components/soc/esp32/test/test_rtc_clk.c

@@ -97,7 +97,7 @@ TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
 
 static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
 {
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 
     const int test_duration_sec = 10;
     ref_clock_init();
@@ -164,7 +164,7 @@ static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_m
     uint32_t end_time;
     rtc_slow_freq_t selected_src_freq;
     stop_rtc_external_quartz();
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
     uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
     printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
             bootstrap_cycles,
@@ -219,7 +219,7 @@ static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_m
     printf("Test passed successfully\n");
 }
 
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
 // PSRAM tests run on ESP-WROVER-KIT boards, which have the 32k XTAL installed.
 // Other tests may run on DevKitC boards, which don't have a 32k XTAL.
 TEST_CASE("Test starting external RTC quartz", "[rtc_clk]")
@@ -228,7 +228,7 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk]")
     uint32_t start_time;
     uint32_t end_time;
     stop_rtc_external_quartz();
-#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
     uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
     printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
             bootstrap_cycles,
@@ -285,4 +285,4 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
     start_freq(RTC_SLOW_FREQ_RTC, 0);
 }
 
-#endif // CONFIG_SPIRAM_SUPPORT
+#endif // CONFIG_ESP32_SPIRAM_SUPPORT

components/soc/include/soc/soc_memory_layout.h

@@ -161,7 +161,7 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
 {
     bool r;
     r = ((intptr_t)p >= SOC_BYTE_ACCESSIBLE_LOW && (intptr_t)p < SOC_BYTE_ACCESSIBLE_HIGH);
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
     r |= ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
 #endif
     return r;

components/spi_flash/flash_mmap.c

@@ -226,7 +226,7 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
        entire cache.
     */
     if (need_flush) {
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
         esp_spiram_writeback_cache();
 #endif
         Cache_Flush(0);
@@ -421,7 +421,7 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
         }
 
         if (is_page_mapped_in_cache(page)) {
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_ESP32_SPIRAM_SUPPORT
             esp_spiram_writeback_cache();
 #endif
             Cache_Flush(0);

components/spi_flash/test/test_read_write.c

@@ -219,7 +219,7 @@ TEST_CASE("Test spi_flash_write", "[spi_flash]")
     ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40080000, 16));
 }
 
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
 
 TEST_CASE("spi_flash_read can read into buffer in external RAM", "[spi_flash]")
 {
@@ -265,4 +265,4 @@ TEST_CASE("spi_flash_write can write from external RAM buffer", "[spi_flash]")
     free(buf_int);
 }
 
-#endif // CONFIG_SPIRAM_SUPPORT
+#endif // CONFIG_ESP32_SPIRAM_SUPPORT

components/ulp/ld/esp32.ulp.ld

@@ -4,7 +4,7 @@
 #define HEADER_SIZE			12
 MEMORY
 {
-    ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM
+    ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 }
 
 SECTIONS

components/ulp/test/test_ulp.c

@@ -46,7 +46,7 @@ static void hexdump(const uint32_t* src, size_t count) {
 
 TEST_CASE("ulp add test", "[ulp]")
 {
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     const ulp_insn_t program[] = {
         I_MOVI(R3, 16),
         I_LD(R0, R3, 0),
@@ -61,14 +61,14 @@ TEST_CASE("ulp add test", "[ulp]")
     TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
     TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
     ets_delay_us(1000);
-    hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
+    hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
     TEST_ASSERT_EQUAL(10 + 11, RTC_SLOW_MEM[18] & 0xffff);
 }
 
 TEST_CASE("ulp branch test", "[ulp]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     const ulp_insn_t program[] = {
         I_MOVI(R0, 34),     // r0 = dst
         M_LABEL(1),
@@ -84,12 +84,12 @@ TEST_CASE("ulp branch test", "[ulp]")
     };
     RTC_SLOW_MEM[32] = 42;
     RTC_SLOW_MEM[33] = 18;
-    hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
+    hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
     size_t size = sizeof(program)/sizeof(ulp_insn_t);
     ulp_process_macros_and_load(0, program, &size);
     ulp_run(0);
     printf("\n\n");
-    hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
+    hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
     for (int i = 34; i < 64; ++i) {
         TEST_ASSERT_EQUAL(42 - 18, RTC_SLOW_MEM[i] & 0xffff);
     }
@@ -98,8 +98,8 @@ TEST_CASE("ulp branch test", "[ulp]")
 
 TEST_CASE("ulp wakeup test", "[ulp][ignore]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     const ulp_insn_t program[] = {
         I_MOVI(R1, 1024),
         M_LABEL(1),
@@ -126,9 +126,9 @@ TEST_CASE("ulp wakeup test", "[ulp][ignore]")
 
 TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
     CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
 
     const ulp_insn_t program[] = {
@@ -166,8 +166,8 @@ TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
 
 TEST_CASE("ULP I_WR_REG instruction test", "[ulp]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     typedef struct {
         int low;
         int width;
@@ -220,8 +220,8 @@ TEST_CASE("ULP I_WR_REG instruction test", "[ulp]")
 
 TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
     const ulp_insn_t program[] = {
         I_MOVI(R0, 0),                  // R0 is LED state
         I_MOVI(R2, 16),                 // loop R2 from 16 down to 0
@@ -269,7 +269,7 @@ TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
 
 TEST_CASE("ulp power consumption in deep sleep", "[ulp][ignore]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
     ulp_insn_t insn = I_HALT();
     memcpy(&RTC_SLOW_MEM[0], &insn, sizeof(insn));
 
@@ -289,8 +289,8 @@ TEST_CASE("ulp timer setting", "[ulp]")
      * Program calls I_HALT each time and gets restarted by the timer.
      * Compare the expected number of times the program runs with the actual.
      */
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
 
     const int offset = 6;
     const ulp_insn_t program[] = {
@@ -332,11 +332,11 @@ TEST_CASE("ulp timer setting", "[ulp]")
 
 TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
 
-    hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
+    hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
     printf("\n\n");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
 
     // Allow TSENS to be controlled by the ULP
     SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
@@ -348,7 +348,7 @@ TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
     // data start offset
     size_t offset = 20;
     // number of samples to collect
-    RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
+    RTC_SLOW_MEM[offset] = (CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
     // sample counter
     RTC_SLOW_MEM[offset + 1] = 0;
 
@@ -384,11 +384,11 @@ TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
 
 TEST_CASE("can use ADC in deep sleep", "[ulp][ignore]")
 {
-    assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
+    assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
 
-    hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
+    hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
     printf("\n\n");
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
 
     SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
     SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
@@ -428,7 +428,7 @@ TEST_CASE("can use ADC in deep sleep", "[ulp][ignore]")
     // data start offset
     size_t offset = 20;
     // number of samples to collect
-    RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
+    RTC_SLOW_MEM[offset] = (CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
     // sample counter
     RTC_SLOW_MEM[offset + 1] = 0;
 

components/ulp/ulp.c

@@ -70,10 +70,10 @@ esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, siz
     if (program_size_bytes < sizeof(ulp_binary_header_t)) {
         return ESP_ERR_INVALID_SIZE;
     }
-    if (load_addr_bytes > CONFIG_ULP_COPROC_RESERVE_MEM) {
+    if (load_addr_bytes > CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) {
         return ESP_ERR_INVALID_ARG;
     }
-    if (load_addr_bytes + program_size_bytes > CONFIG_ULP_COPROC_RESERVE_MEM) {
+    if (load_addr_bytes + program_size_bytes > CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) {
         return ESP_ERR_INVALID_SIZE;
     }
 

components/ulp/ulp_macro.c

@@ -167,7 +167,7 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog
         ++read_ptr;
     }
     size_t real_program_size = *psize - macro_count;
-    const size_t ulp_mem_end = CONFIG_ULP_COPROC_RESERVE_MEM / sizeof(ulp_insn_t);
+    const size_t ulp_mem_end = CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / sizeof(ulp_insn_t);
     if (load_addr > ulp_mem_end) {
         ESP_LOGW(TAG, "invalid load address %x, max is %x",
                 load_addr, ulp_mem_end);

components/unity/unity_port_esp32.c

@@ -33,7 +33,7 @@ void unity_putc(int c)
 
 void unity_flush()
 {
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 }
 
 /* To start a unit test from a GDB session without console input,

components/vfs/test/test_vfs_fd.c

@@ -260,7 +260,7 @@ TEST_CASE("Open & write & close through VFS passes performance test", "[vfs]")
     const int64_t time_diff_us = esp_timer_get_time() - begin;
     const int ns_per_iter = (int) (time_diff_us * 1000 / iter_count);
     TEST_ESP_OK( esp_vfs_unregister(VFS_PREF1) );
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
     TEST_PERFORMANCE_LESS_THAN(VFS_OPEN_WRITE_CLOSE_TIME_PSRAM, "%dns", ns_per_iter);
 #else
     TEST_PERFORMANCE_LESS_THAN(VFS_OPEN_WRITE_CLOSE_TIME, "%dns", ns_per_iter);

components/vfs/test/test_vfs_uart.c

@@ -31,11 +31,11 @@
 
 static void fwrite_str_loopback(const char* str, size_t size)
 {
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     UART0.conf0.loopback = 1;
     fwrite(str, 1, size, stdout);
     fflush(stdout);
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     vTaskDelay(2 / portTICK_PERIOD_MS);
     UART0.conf0.loopback = 0;
 }
@@ -48,7 +48,7 @@ static void flush_stdin_stdout()
         ;
     }
     fflush(stdout);
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 }
 
 TEST_CASE("can read from stdin", "[vfs]")
@@ -179,9 +179,9 @@ TEST_CASE("can write to UART while another task is reading", "[vfs]")
 
     flush_stdin_stdout();
 
-    ESP_ERROR_CHECK( uart_driver_install(CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK( uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
             256, 0, 0, NULL, 0) );
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
 
     xTaskCreate(&read_task_fn, "vfs_read", 4096, &read_arg, 5, NULL);
@@ -197,8 +197,8 @@ TEST_CASE("can write to UART while another task is reading", "[vfs]")
 
     TEST_ASSERT_EQUAL(0, strcmp(write_arg.str, read_arg.out_buffer));
 
-    esp_vfs_dev_uart_use_nonblocking(CONFIG_CONSOLE_UART_NUM);
-    uart_driver_delete(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM);
+    uart_driver_delete(CONFIG_ESP_CONSOLE_UART_NUM);
     vSemaphoreDelete(read_arg.done);
     vSemaphoreDelete(write_arg.done);
 }

docs/en/api-guides/event-handling.rst

@@ -28,7 +28,7 @@ This event loop implementation is started using :cpp:func:`esp_event_loop_init`
 
 Both the pointer to event handler function, and an arbitrary context pointer are passed to :cpp:func:`esp_event_loop_init`. 
 
-When Wi-Fi, Ethernet, or IP stack generate an event, this event is sent to a high-priority ``event`` task via a queue. Application-provided event handler function is called in the context of this task. Event task stack size and event queue size can be adjusted using :ref:`CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE` and :ref:`CONFIG_SYSTEM_EVENT_QUEUE_SIZE` options, respectively.
+When Wi-Fi, Ethernet, or IP stack generate an event, this event is sent to a high-priority ``event`` task via a queue. Application-provided event handler function is called in the context of this task. Event task stack size and event queue size can be adjusted using :ref:`CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE` and :ref:`CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE` options, respectively.
 
 Event handler receives a pointer to the event structure (:cpp:type:`system_event_t`) which describes current event. This structure follows a *tagged union* pattern: ``event_id`` member indicates the type of event, and ``event_info`` member is a union of description structures. Application event handler will typically use ``switch(event->event_id)`` to handle different kinds of events.
 

docs/en/api-guides/fatal-errors.rst

@@ -11,7 +11,7 @@ In certain situations, execution of the program can not be continued in a well d
 - System level checks and safeguards:
 
   - :doc:`Interrupt watchdog <../api-reference/system/wdts>` timeout
-  - :doc:`Task watchdog <../api-reference/system/wdts>` timeout (only fatal if :ref:`CONFIG_TASK_WDT_PANIC` is set)
+  - :doc:`Task watchdog <../api-reference/system/wdts>` timeout (only fatal if :ref:`CONFIG_ESP_TASK_WDT_PANIC` is set)
   - Cache access error
   - Brownout detection event
   - Stack overflow
@@ -260,7 +260,7 @@ Other Fatal Errors
 Brownout
 ^^^^^^^^
 
-ESP32 has a built-in brownout detector, which is enabled by default. Brownout detector can trigger system reset if supply voltage goes below safe level. Brownout detector can be configured using :ref:`CONFIG_BROWNOUT_DET` and :ref:`CONFIG_BROWNOUT_DET_LVL_SEL` options.
+ESP32 has a built-in brownout detector, which is enabled by default. Brownout detector can trigger system reset if supply voltage goes below safe level. Brownout detector can be configured using :ref:`CONFIG_ESP32_BROWNOUT_DET` and :ref:`CONFIG_ESP32_BROWNOUT_DET_LVL_SEL` options.
 When brownout detector triggers, the following message is printed::
 
     Brownout detector was triggered

docs/en/api-reference/system/ipc.rst

@@ -29,7 +29,7 @@ until the IPC Task has completed execution of the given function.
 Functions executed by IPCs must be functions of type 
 `void func(void *arg)`. To run more complex functions which require a larger 
 stack, the IPC tasks' stack size can be configured by modifying 
-:ref:`CONFIG_IPC_TASK_STACK_SIZE` in `menuconfig`. The IPC API is protected by a
+:ref:`CONFIG_ESP_IPC_TASK_STACK_SIZE` in `menuconfig`. The IPC API is protected by a
 mutex hence simultaneous IPC calls are not possible.
 
 Care should taken to avoid deadlock when writing functions to be executed by

docs/en/api-reference/system/system.rst

@@ -91,7 +91,7 @@ If the universally administered MAC addresses are not enough for all of the netw
 
 See `this article <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`_ for the definition of local and universally administered MAC addresses.
 
-The number of universally administered MAC address can be configured using :ref:`CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS`.
+The number of universally administered MAC address can be configured using :ref:`CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES`.
 
 If the number of universal MAC addresses is two, only two interfaces (Wi-Fi Station and Bluetooth) receive a universally administered MAC address. These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. The remaining two interfaces (Wi-Fi SoftAP and Ethernet) receive local MAC addresses. These are derived from the universal Wi-Fi station and Bluetooth MAC addresses, respectively.
 

docs/en/api-reference/system/wdts.rst

@@ -63,10 +63,10 @@ longer call :cpp:func:`esp_task_wdt_reset`. Once all tasks have unsubscribed
 form the TWDT, the TWDT can be deinitialized by calling 
 :cpp:func:`esp_task_wdt_deinit()`.
 
-By default :ref:`CONFIG_TASK_WDT` in ``make menuconfig`` will be enabled causing
+By default :ref:`CONFIG_ESP_TASK_WDT` in ``make menuconfig`` will be enabled causing
 the TWDT to be initialized automatically during startup. Likewise
-:ref:`CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0` and 
-:ref:`CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1` are also enabled by default causing
+:ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0` and 
+:ref:`CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1` are also enabled by default causing
 the two Idle Tasks to be subscribed to the TWDT during startup.
 
 JTAG and watchdogs

examples/bluetooth/ble_throughput/throughput_client/sdkconfig.defaults

@@ -17,6 +17,6 @@ CONFIG_MONITOR_BAUD=921600
 #
 # ESP32-specific
 #
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
 CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
-CONFIG_CONSOLE_UART_BAUDRATE=921600
+CONFIG_ESP_CONSOLE_UART_BAUDRATE=921600

examples/bluetooth/ble_throughput/throughput_server/sdkconfig.defaults

@@ -17,6 +17,6 @@ CONFIG_MONITOR_BAUD=921600
 #
 # ESP32-specific
 #
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
 CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
-CONFIG_CONSOLE_UART_BAUDRATE=921600
+CONFIG_ESP_CONSOLE_UART_BAUDRATE=921600

examples/common_components/protocol_examples_common/stdin_out.c

@@ -19,10 +19,10 @@ esp_err_t example_configure_stdin_stdout()
     setvbuf(stdin, NULL, _IONBF, 0);
     setvbuf(stdout, NULL, _IONBF, 0);
     /* Install UART driver for interrupt-driven reads and writes */
-    ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK( uart_driver_install( (uart_port_t)CONFIG_ESP_CONSOLE_UART_NUM,
             256, 0, 0, NULL, 0) );
     /* Tell VFS to use UART driver */
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_vfs_dev_uart_set_rx_line_endings(ESP_LINE_ENDINGS_CR);
     /* Move the caret to the beginning of the next line on '\n' */
     esp_vfs_dev_uart_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);

examples/ethernet/iperf/main/iperf_example_main.c

@@ -68,20 +68,20 @@ static void initialize_console()
      * correct while APB frequency is changing in light sleep mode.
      */
     const uart_config_t uart_config = {
-        .baud_rate = CONFIG_CONSOLE_UART_BAUDRATE,
+        .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE,
         .data_bits = UART_DATA_8_BITS,
         .parity = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .use_ref_tick = true
     };
-    ESP_ERROR_CHECK(uart_param_config(CONFIG_CONSOLE_UART_NUM, &uart_config));
+    ESP_ERROR_CHECK(uart_param_config(CONFIG_ESP_CONSOLE_UART_NUM, &uart_config));
 
     /* Install UART driver for interrupt-driven reads and writes */
-    ESP_ERROR_CHECK(uart_driver_install(CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK(uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
                                         256, 0, 0, NULL, 0));
 
     /* Tell VFS to use UART driver */
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
     /* Initialize the console */
     esp_console_config_t console_config = {

examples/ethernet/iperf/sdkconfig.defaults

@@ -3,7 +3,7 @@ CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
 CONFIG_LOG_BOOTLOADER_LEVEL=2
 
 # Increase main task stack size
-CONFIG_MAIN_TASK_STACK_SIZE=7168
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=7168
 
 # Enable filesystem
 CONFIG_PARTITION_TABLE_CUSTOM=y

examples/peripherals/i2c/i2c_tools/main/i2ctools_example_main.c

@@ -68,20 +68,20 @@ static void initialize_console()
      * correct while APB frequency is changing in light sleep mode.
      */
     const uart_config_t uart_config = {
-        .baud_rate = CONFIG_CONSOLE_UART_BAUDRATE,
+        .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE,
         .data_bits = UART_DATA_8_BITS,
         .parity = UART_PARITY_DISABLE,
         .stop_bits = UART_STOP_BITS_1,
         .use_ref_tick = true
     };
-    ESP_ERROR_CHECK(uart_param_config(CONFIG_CONSOLE_UART_NUM, &uart_config));
+    ESP_ERROR_CHECK(uart_param_config(CONFIG_ESP_CONSOLE_UART_NUM, &uart_config));
 
     /* Install UART driver for interrupt-driven reads and writes */
-    ESP_ERROR_CHECK(uart_driver_install(CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK(uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
                                         256, 0, 0, NULL, 0));
 
     /* Tell VFS to use UART driver */
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
     /* Initialize the console */
     esp_console_config_t console_config = {

examples/peripherals/i2c/i2c_tools/sdkconfig.defaults

@@ -3,7 +3,7 @@ CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
 CONFIG_LOG_BOOTLOADER_LEVEL=2
 
 # Increase main task stack size
-CONFIG_MAIN_TASK_STACK_SIZE=7168
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=7168
 
 # Enable filesystem
 CONFIG_PARTITION_TABLE_CUSTOM=y

examples/protocols/asio/chat_client/sdkconfig.defaults

@@ -1 +1 @@
-CONFIG_MAIN_TASK_STACK_SIZE=8192
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

examples/protocols/asio/chat_server/sdkconfig.defaults

@@ -1 +1 @@
-CONFIG_MAIN_TASK_STACK_SIZE=8192
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

examples/protocols/asio/tcp_echo_server/sdkconfig.defaults

@@ -1 +1 @@
-CONFIG_MAIN_TASK_STACK_SIZE=8192
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

examples/protocols/asio/udp_echo_server/sdkconfig.defaults

@@ -1 +1 @@
-CONFIG_MAIN_TASK_STACK_SIZE=8192
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

examples/storage/semihost_vfs/main/semihost_vfs_example_main.c

@@ -52,7 +52,7 @@ void app_main(void)
     fflush(fout); // ensure that all data are sent to the host file
     // ftell can also be used, get file size before closing it in `freopen`
     int count = ftell(fout);
-    stdout = freopen("/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM), "w", fout);
+    stdout = freopen("/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM), "w", fout);
     if (stdout == NULL) {
         ESP_LOGE(TAG, "Failed to reopen semihosted stdout (%d)!", errno);
         return;

examples/system/console/components/cmd_system/cmd_system.c

@@ -287,13 +287,13 @@ static int light_sleep(int argc, char **argv)
     if (io_count > 0) {
         ESP_ERROR_CHECK( esp_sleep_enable_gpio_wakeup() );
     }
-    if (CONFIG_CONSOLE_UART_NUM <= UART_NUM_1) {
+    if (CONFIG_ESP_CONSOLE_UART_NUM <= UART_NUM_1) {
         ESP_LOGI(TAG, "Enabling UART wakeup (press ENTER to exit light sleep)");
-        ESP_ERROR_CHECK( uart_set_wakeup_threshold(CONFIG_CONSOLE_UART_NUM, 3) );
-        ESP_ERROR_CHECK( esp_sleep_enable_uart_wakeup(CONFIG_CONSOLE_UART_NUM) );
+        ESP_ERROR_CHECK( uart_set_wakeup_threshold(CONFIG_ESP_CONSOLE_UART_NUM, 3) );
+        ESP_ERROR_CHECK( esp_sleep_enable_uart_wakeup(CONFIG_ESP_CONSOLE_UART_NUM) );
     }
     fflush(stdout);
-    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+    uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_light_sleep_start();
     esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
     const char *cause_str;

examples/system/console/main/console_example_main.c

@@ -71,20 +71,20 @@ static void initialize_console()
      * correct while APB frequency is changing in light sleep mode.
      */
     const uart_config_t uart_config = {
-            .baud_rate = CONFIG_CONSOLE_UART_BAUDRATE,
+            .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE,
             .data_bits = UART_DATA_8_BITS,
             .parity = UART_PARITY_DISABLE,
             .stop_bits = UART_STOP_BITS_1,
             .use_ref_tick = true
     };
-    ESP_ERROR_CHECK( uart_param_config(CONFIG_CONSOLE_UART_NUM, &uart_config) );
+    ESP_ERROR_CHECK( uart_param_config(CONFIG_ESP_CONSOLE_UART_NUM, &uart_config) );
 
     /* Install UART driver for interrupt-driven reads and writes */
-    ESP_ERROR_CHECK( uart_driver_install(CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK( uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
             256, 0, 0, NULL, 0) );
 
     /* Tell VFS to use UART driver */
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
     /* Initialize the console */
     esp_console_config_t console_config = {

examples/system/console/sdkconfig.defaults

@@ -3,7 +3,7 @@ CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
 CONFIG_LOG_BOOTLOADER_LEVEL=2
 
 # Increase main task stack size
-CONFIG_MAIN_TASK_STACK_SIZE=7168
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=7168
 
 # Enable filesystem
 CONFIG_PARTITION_TABLE_CUSTOM=y

examples/system/deep_sleep/main/deep_sleep_example_main.c

@@ -31,13 +31,13 @@ static RTC_DATA_ATTR struct timeval sleep_enter_time;
 /*
  * Offset (in 32-bit words) in RTC Slow memory where the data is placed
  * by the ULP coprocessor. It can be chosen to be any value greater or equal
- * to ULP program size, and less than the CONFIG_ULP_COPROC_RESERVE_MEM/4 - 6,
+ * to ULP program size, and less than the CONFIG_ESP32_ULP_COPROC_RESERVE_MEM/4 - 6,
  * where 6 is the number of words used by the ULP coprocessor.
  */
 #define ULP_DATA_OFFSET     36
 
-_Static_assert(ULP_DATA_OFFSET < CONFIG_ULP_COPROC_RESERVE_MEM/4 - 6,
-        "ULP_DATA_OFFSET is set too high, or CONFIG_ULP_COPROC_RESERVE_MEM is not sufficient");
+_Static_assert(ULP_DATA_OFFSET < CONFIG_ESP32_ULP_COPROC_RESERVE_MEM/4 - 6,
+        "ULP_DATA_OFFSET is set too high, or CONFIG_ESP32_ULP_COPROC_RESERVE_MEM is not sufficient");
 
 /**
  * @brief Start ULP temperature monitoring program
@@ -242,7 +242,7 @@ static void start_ulp_temperature_monitoring()
     CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
 
     // Clear the part of RTC_SLOW_MEM reserved for the ULP. Makes debugging easier.
-    memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
+    memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
 
     // The first word of memory (at data offset) is used to store the initial temperature (T0)
     // Zero it out here, then ULP will update it on the first run.

examples/system/deep_sleep/sdkconfig.defaults

@@ -1,6 +1,6 @@
 CONFIG_ESP32_DEFAULT_CPU_FREQ_80=y
 CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=80
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=512
+CONFIG_ESP32_ULP_COPROC_ENABLED=y
+CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=512
 CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
+CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y

examples/system/himem/sdkconfig.defaults

@@ -1,4 +1,4 @@
-CONFIG_SPIRAM_SUPPORT=y
+CONFIG_ESP32_SPIRAM_SUPPORT=y
 CONFIG_SPIRAM_BOOT_INIT=y
 CONFIG_SPIRAM_IGNORE_NOTFOUND=
 CONFIG_SPIRAM_USE_MALLOC=y

examples/system/light_sleep/main/light_sleep_example_main.c

@@ -57,7 +57,7 @@ void app_main()
         /* To make sure the complete line is printed before entering sleep mode,
          * need to wait until UART TX FIFO is empty:
          */
-        uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+        uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 
         /* Get timestamp before entering sleep */
         int64_t t_before_us = esp_timer_get_time();

examples/system/task_watchdog/main/task_watchdog_example_main.c

@@ -49,10 +49,10 @@ void app_main()
     CHECK_ERROR_CODE(esp_task_wdt_init(TWDT_TIMEOUT_S, false), ESP_OK);
 
     //Subscribe Idle Tasks to TWDT if they were not subscribed at startup
-#ifndef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0
+#ifndef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
     esp_task_wdt_add(xTaskGetIdleTaskHandleForCPU(0));
 #endif
-#ifndef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1
+#ifndef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
     esp_task_wdt_add(xTaskGetIdleTaskHandleForCPU(1));
 #endif
 

examples/system/ulp/sdkconfig.defaults

@@ -1,6 +1,6 @@
 # Enable ULP
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=1024
+CONFIG_ESP32_ULP_COPROC_ENABLED=y
+CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=1024
 # Set log level to Warning to produce clean output
 CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
 CONFIG_LOG_BOOTLOADER_LEVEL=2

examples/system/ulp_adc/sdkconfig.defaults

@@ -1,6 +1,6 @@
 # Enable ULP
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=1024
+CONFIG_ESP32_ULP_COPROC_ENABLED=y
+CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=1024
 # Set log level to Warning to produce clean output
 CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
 CONFIG_LOG_BOOTLOADER_LEVEL=2

examples/system/unit_test/test/sdkconfig.defaults

@@ -1 +1 @@
-CONFIG_TASK_WDT=
+CONFIG_ESP_TASK_WDT=

examples/wifi/iperf/main/iperf_example_main.c

@@ -37,11 +37,11 @@ static void initialize_console()
     esp_vfs_dev_uart_set_tx_line_endings(ESP_LINE_ENDINGS_CRLF);
 
     /* Install UART driver for interrupt-driven reads and writes */
-    ESP_ERROR_CHECK( uart_driver_install(CONFIG_CONSOLE_UART_NUM,
+    ESP_ERROR_CHECK( uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
                                          256, 0, 0, NULL, 0) );
 
     /* Tell VFS to use UART driver */
-    esp_vfs_dev_uart_use_driver(CONFIG_CONSOLE_UART_NUM);
+    esp_vfs_dev_uart_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
     /* Initialize the console */
     esp_console_config_t console_config = {

examples/wifi/iperf/sdkconfig.defaults

@@ -2,7 +2,7 @@ CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
 CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=16
 CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=64
@@ -15,8 +15,8 @@ CONFIG_ESP32_WIFI_RX_BA_WIN=32
 CONFIG_FREERTOS_UNICORE=n
 CONFIG_FREERTOS_HZ=1000
 
-CONFIG_INT_WDT=n
-CONFIG_TASK_WDT=n
+CONFIG_ESP_INT_WDT=n
+CONFIG_ESP_TASK_WDT=n
 
 CONFIG_LWIP_TCP_SND_BUF_DEFAULT=65534
 CONFIG_LWIP_TCP_WND_DEFAULT=65534

examples/wifi/iperf/sdkconfig.defaults.00

@@ -1,6 +1,6 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=

examples/wifi/iperf/sdkconfig.defaults.01

@@ -1,9 +1,9 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_FREERTOS_UNICORE=
 CONFIG_FREERTOS_HZ=1000

examples/wifi/iperf/sdkconfig.defaults.02

@@ -1,9 +1,9 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_FREERTOS_UNICORE=
 CONFIG_FREERTOS_HZ=1000

examples/wifi/iperf/sdkconfig.defaults.03

@@ -1,9 +1,9 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_FREERTOS_UNICORE=
 CONFIG_FREERTOS_HZ=1000

examples/wifi/iperf/sdkconfig.defaults.04

@@ -1,9 +1,9 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_FREERTOS_UNICORE=
 CONFIG_FREERTOS_HZ=1000

examples/wifi/iperf/sdkconfig.defaults.05

@@ -1,9 +1,9 @@
 CONFIG_MEMMAP_SMP=y
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_FREERTOS_UNICORE=
 CONFIG_FREERTOS_HZ=1000

examples/wifi/iperf/sdkconfig.defaults.06

@@ -1,4 +1,4 @@
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=4096
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=4096
 
 CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=16
 CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=64
@@ -11,8 +11,8 @@ CONFIG_ESP32_WIFI_RX_BA_WIN=32
 CONFIG_FREERTOS_UNICORE=y
 CONFIG_FREERTOS_HZ=1000
 
-CONFIG_INT_WDT=
-CONFIG_TASK_WDT=
+CONFIG_ESP_INT_WDT=
+CONFIG_ESP_TASK_WDT=
 
 CONFIG_LWIP_TCP_SND_BUF_DEFAULT=65534
 CONFIG_LWIP_TCP_WND_DEFAULT=65534