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@@ -34,6 +34,25 @@
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return ret; \
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}
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+#define FETCH_ADD(n, type) type __atomic_fetch_add_ ## n (type* ptr, type value, int memorder) \
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+{ \
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+ unsigned state = portENTER_CRITICAL_NESTED(); \
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+ type ret = *ptr; \
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+ *ptr = *ptr + value; \
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+ portEXIT_CRITICAL_NESTED(state); \
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+ return ret; \
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+}
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+
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+#define FETCH_SUB(n, type) type __atomic_fetch_sub_ ## n (type* ptr, type value, int memorder) \
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+{ \
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+ unsigned state = portENTER_CRITICAL_NESTED(); \
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+ type ret = *ptr; \
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+ *ptr = *ptr - value; \
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+ portEXIT_CRITICAL_NESTED(state); \
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+ return ret; \
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+}
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+
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+
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//this piece of code should only be compiled if the cpu doesn't support atomic compare and swap (s32c1i)
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#if XCHAL_HAVE_S32C1I == 0
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@@ -44,4 +63,14 @@ CMP_EXCHANGE(2, uint16_t)
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CMP_EXCHANGE(4, uint32_t)
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CMP_EXCHANGE(8, uint64_t)
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+FETCH_ADD(1, uint8_t)
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+FETCH_ADD(2, uint16_t)
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+FETCH_ADD(4, uint32_t)
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+FETCH_ADD(8, uint64_t)
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+
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+FETCH_SUB(1, uint8_t)
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+FETCH_SUB(2, uint16_t)
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+FETCH_SUB(4, uint32_t)
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+FETCH_SUB(8, uint64_t)
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+
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#endif
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