soc: update the csv headers for esp32s3

components/hal/esp32s3/include/hal/touch_sensor_ll.h

@@ -170,7 +170,7 @@ static inline void touch_ll_get_voltage_attenuation(touch_volt_atten_t *atten)
  */
 static inline void touch_ll_set_slope(touch_pad_t touch_num, touch_cnt_slope_t slope)
 {
-    RTCIO.touch_pad[touch_num].dac = slope;
+    abort();//IDF-3417
 }
 
 /**
@@ -185,7 +185,7 @@ static inline void touch_ll_set_slope(touch_pad_t touch_num, touch_cnt_slope_t s
  */
 static inline void touch_ll_get_slope(touch_pad_t touch_num, touch_cnt_slope_t *slope)
 {
-    *slope = (touch_cnt_slope_t)RTCIO.touch_pad[touch_num].dac;
+    abort();//IDF-3417
 }
 
 /**

components/soc/esp32s3/include/soc/apb_ctrl_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_APB_CTRL_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
 /* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
@@ -637,6 +637,14 @@ tes. 3: 2048 bytes..*/
 #define APB_CTRL_RETENTION_INV_CFG_V  0xFFFFFFFF
 #define APB_CTRL_RETENTION_INV_CFG_S  0
 
+#define APB_CTRL_RETENTION_CTRL5_REG          (DR_REG_APB_CTRL_BASE + 0xC8)
+/* APB_CTRL_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_RETENTION_DISABLE    (BIT(0))
+#define APB_CTRL_RETENTION_DISABLE_M  (BIT(0))
+#define APB_CTRL_RETENTION_DISABLE_V  0x1
+#define APB_CTRL_RETENTION_DISABLE_S  0
+
 #define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
 /* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
 /*description: Version control.*/

components/soc/esp32s3/include/soc/apb_ctrl_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,9 @@
 // limitations under the License.
 #ifndef _SOC_APB_CTRL_STRUCT_H_
 #define _SOC_APB_CTRL_STRUCT_H_
+
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -20,304 +23,310 @@ extern "C" {
 typedef volatile struct {
     union {
         struct {
-            uint32_t pre_div:     10;
-            uint32_t clk_320m_en:  1;
-            uint32_t clk_en:       1;
-            uint32_t rst_tick:     1;
-            uint32_t reserved13:  19;
+            uint32_t pre_div                       :    10;
+            uint32_t clk_320m_en                   :    1;
+            uint32_t clk_en                        :    1;
+            uint32_t rst_tick                      :    1;
+            uint32_t reserved13                    :    19;
         };
         uint32_t val;
     } clk_conf;
     union {
         struct {
-            uint32_t xtal_tick:     8;
-            uint32_t ck8m_tick:     8;
-            uint32_t tick_enable:   1;
-            uint32_t reserved17:   15;
+            uint32_t xtal_tick                     :    8;
+            uint32_t ck8m_tick                     :    8;
+            uint32_t tick_enable                   :    1;
+            uint32_t reserved17                    :    15;
         };
         uint32_t val;
     } tick_conf;
     union {
         struct {
-            uint32_t clk20_oen:       1;
-            uint32_t clk22_oen:       1;
-            uint32_t clk44_oen:       1;
-            uint32_t clk_bb_oen:      1;
-            uint32_t clk80_oen:       1;
-            uint32_t clk160_oen:      1;
-            uint32_t clk_320m_oen:    1;
-            uint32_t clk_adc_inf_oen: 1;
-            uint32_t clk_dac_cpu_oen: 1;
-            uint32_t clk40x_bb_oen:   1;
-            uint32_t clk_xtal_oen:    1;
-            uint32_t reserved11:     21;
+            uint32_t clk20_oen                     :    1;
+            uint32_t clk22_oen                     :    1;
+            uint32_t clk44_oen                     :    1;
+            uint32_t clk_bb_oen                    :    1;
+            uint32_t clk80_oen                     :    1;
+            uint32_t clk160_oen                    :    1;
+            uint32_t clk_320m_oen                  :    1;
+            uint32_t clk_adc_inf_oen               :    1;
+            uint32_t clk_dac_cpu_oen               :    1;
+            uint32_t clk40x_bb_oen                 :    1;
+            uint32_t clk_xtal_oen                  :    1;
+            uint32_t reserved11                    :    21;
         };
         uint32_t val;
     } clk_out_en;
-    uint32_t wifi_bb_cfg;                              /**/
-    uint32_t wifi_bb_cfg_2;                            /**/
-    uint32_t wifi_clk_en;                              /**/
-    uint32_t wifi_rst_en;                              /**/
+    uint32_t wifi_bb_cfg;
+    uint32_t wifi_bb_cfg_2;
+    uint32_t wifi_clk_en;
+    uint32_t wifi_rst_en;
     union {
         struct {
-            uint32_t peri_io_swap: 8;
-            uint32_t reserved8:   24;
+            uint32_t peri_io_swap                  :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } host_inf_sel;
     union {
         struct {
-            uint32_t ext_mem_pms_lock: 1;
-            uint32_t reserved1:       31;
+            uint32_t ext_mem_pms_lock              :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } ext_mem_pms_lock;
     union {
         struct {
-            uint32_t writeback_bypass: 1;              /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
-            uint32_t reserved1:       31;
+            uint32_t writeback_bypass              :    1;  /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } ext_mem_writeback_bypass;
     union {
         struct {
-            uint32_t flash_ace0_attr: 9;
-            uint32_t reserved9:      23;
+            uint32_t flash_ace0_attr               :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } flash_ace0_attr;
     union {
         struct {
-            uint32_t flash_ace1_attr: 9;
-            uint32_t reserved9:      23;
+            uint32_t flash_ace1_attr               :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } flash_ace1_attr;
     union {
         struct {
-            uint32_t flash_ace2_attr: 9;
-            uint32_t reserved9:      23;
+            uint32_t flash_ace2_attr               :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } flash_ace2_attr;
     union {
         struct {
-            uint32_t flash_ace3_attr: 9;
-            uint32_t reserved9:      23;
+            uint32_t flash_ace3_attr               :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } flash_ace3_attr;
-    uint32_t flash_ace0_addr;                          /**/
-    uint32_t flash_ace1_addr;                          /**/
-    uint32_t flash_ace2_addr;                          /**/
-    uint32_t flash_ace3_addr;                          /**/
+    uint32_t flash_ace0_addr;
+    uint32_t flash_ace1_addr;
+    uint32_t flash_ace2_addr;
+    uint32_t flash_ace3_addr;
     union {
         struct {
-            uint32_t flash_ace0_size:16;
-            uint32_t reserved16:     16;
+            uint32_t flash_ace0_size               :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } flash_ace0_size;
     union {
         struct {
-            uint32_t flash_ace1_size:16;
-            uint32_t reserved16:     16;
+            uint32_t flash_ace1_size               :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } flash_ace1_size;
     union {
         struct {
-            uint32_t flash_ace2_size:16;
-            uint32_t reserved16:     16;
+            uint32_t flash_ace2_size               :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } flash_ace2_size;
     union {
         struct {
-            uint32_t flash_ace3_size:16;
-            uint32_t reserved16:     16;
+            uint32_t flash_ace3_size               :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } flash_ace3_size;
     union {
         struct {
-            uint32_t sram_ace0_attr: 9;
-            uint32_t reserved9:     23;
+            uint32_t sram_ace0_attr                :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } sram_ace0_attr;
     union {
         struct {
-            uint32_t sram_ace1_attr: 9;
-            uint32_t reserved9:     23;
+            uint32_t sram_ace1_attr                :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } sram_ace1_attr;
     union {
         struct {
-            uint32_t sram_ace2_attr: 9;
-            uint32_t reserved9:     23;
+            uint32_t sram_ace2_attr                :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } sram_ace2_attr;
     union {
         struct {
-            uint32_t sram_ace3_attr: 9;
-            uint32_t reserved9:     23;
+            uint32_t sram_ace3_attr                :    9;
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } sram_ace3_attr;
-    uint32_t sram_ace0_addr;                           /**/
-    uint32_t sram_ace1_addr;                           /**/
-    uint32_t sram_ace2_addr;                           /**/
-    uint32_t sram_ace3_addr;                           /**/
+    uint32_t sram_ace0_addr;
+    uint32_t sram_ace1_addr;
+    uint32_t sram_ace2_addr;
+    uint32_t sram_ace3_addr;
     union {
         struct {
-            uint32_t sram_ace0_size:16;
-            uint32_t reserved16:    16;
+            uint32_t sram_ace0_size                :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } sram_ace0_size;
     union {
         struct {
-            uint32_t sram_ace1_size:16;
-            uint32_t reserved16:    16;
+            uint32_t sram_ace1_size                :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } sram_ace1_size;
     union {
         struct {
-            uint32_t sram_ace2_size:16;
-            uint32_t reserved16:    16;
+            uint32_t sram_ace2_size                :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } sram_ace2_size;
     union {
         struct {
-            uint32_t sram_ace3_size:16;
-            uint32_t reserved16:    16;
+            uint32_t sram_ace3_size                :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } sram_ace3_size;
     union {
         struct {
-            uint32_t spi_mem_reject_int: 1;
-            uint32_t spi_mem_reject_clr: 1;
-            uint32_t spi_mem_reject_cde: 5;
-            uint32_t reserved7:         25;
+            uint32_t spi_mem_reject_int            :    1;
+            uint32_t spi_mem_reject_clr            :    1;
+            uint32_t spi_mem_reject_cde            :    5;
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } spi_mem_pms_ctrl;
-    uint32_t spi_mem_reject_addr;                      /**/
+    uint32_t spi_mem_reject_addr;
     union {
         struct {
-            uint32_t sdio_win_access_en: 1;
-            uint32_t reserved1:         31;
+            uint32_t sdio_win_access_en            :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } sdio_ctrl;
     union {
         struct {
-            uint32_t redcy_sig0: 31;
-            uint32_t redcy_andor: 1;
+            uint32_t redcy_sig0                    :    31;
+            uint32_t redcy_andor                   :    1;
         };
         uint32_t val;
     } redcy_sig0;
     union {
         struct {
-            uint32_t redcy_sig1:  31;
-            uint32_t redcy_nandor: 1;
+            uint32_t redcy_sig1                    :    31;
+            uint32_t redcy_nandor                  :    1;
         };
         uint32_t val;
     } redcy_sig1;
     union {
         struct {
-            uint32_t agc_mem_force_pu:  1;
-            uint32_t agc_mem_force_pd:  1;
-            uint32_t pbus_mem_force_pu: 1;
-            uint32_t pbus_mem_force_pd: 1;
-            uint32_t dc_mem_force_pu:   1;
-            uint32_t dc_mem_force_pd:   1;
-            uint32_t freq_mem_force_pu: 1;
-            uint32_t freq_mem_force_pd: 1;
-            uint32_t reserved8:        24;
+            uint32_t agc_mem_force_pu              :    1;
+            uint32_t agc_mem_force_pd              :    1;
+            uint32_t pbus_mem_force_pu             :    1;
+            uint32_t pbus_mem_force_pd             :    1;
+            uint32_t dc_mem_force_pu               :    1;
+            uint32_t dc_mem_force_pd               :    1;
+            uint32_t freq_mem_force_pu             :    1;
+            uint32_t freq_mem_force_pd             :    1;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } front_end_mem_pd;
     union {
         struct {
-            uint32_t reserved0:      18;               /*reserved*/
-            uint32_t flash_page_size: 2;               /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t sram_page_size:  2;               /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reserved22:     10;               /*reserved*/
+            uint32_t reserved0                     :    18;  /*reserved*/
+            uint32_t flash_page_size               :    2;  /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t sram_page_size                :    2;  /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t reserved22                    :    10;  /*reserved*/
         };
         uint32_t val;
     } spi_mem_ecc_ctrl;
     uint32_t reserved_a4;
     union {
         struct {
-            uint32_t rom_clkgate_force_on:  3;
-            uint32_t sram_clkgate_force_on:11;
-            uint32_t reserved14:           18;
+            uint32_t rom_clkgate_force_on          :    3;
+            uint32_t sram_clkgate_force_on         :    11;
+            uint32_t reserved14                    :    18;
         };
         uint32_t val;
     } clkgate_force_on;
     union {
         struct {
-            uint32_t rom_power_down:  3;
-            uint32_t sram_power_down:11;
-            uint32_t reserved14:     18;
+            uint32_t rom_power_down                :    3;
+            uint32_t sram_power_down               :    11;
+            uint32_t reserved14                    :    18;
         };
         uint32_t val;
     } mem_power_down;
     union {
         struct {
-            uint32_t rom_power_up:  3;
-            uint32_t sram_power_up:11;
-            uint32_t reserved14:   18;
+            uint32_t rom_power_up                  :    3;
+            uint32_t sram_power_up                 :    11;
+            uint32_t reserved14                    :    18;
         };
         uint32_t val;
     } mem_power_up;
     union {
         struct {
-            uint32_t retention_cpu_link_addr:27;
-            uint32_t nobypass_cpu_iso_rst:    1;
-            uint32_t reserved28:              4;
+            uint32_t retention_cpu_link_addr       :    27;
+            uint32_t nobypass_cpu_iso_rst          :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } retention_ctrl;
     union {
         struct {
-            uint32_t retention_tag_link_addr:27;
-            uint32_t reserved27:              5;
+            uint32_t retention_tag_link_addr       :    27;
+            uint32_t reserved27                    :    5;
         };
         uint32_t val;
     } retention_ctrl1;
     union {
         struct {
-            uint32_t reserved0:              4;
-            uint32_t ret_icache_size:        8;
-            uint32_t reserved12:             1;
-            uint32_t ret_icache_vld_size:    8;
-            uint32_t reserved21:             1;
-            uint32_t ret_icache_start_point: 8;
-            uint32_t reserved30:             1;
-            uint32_t ret_icache_enable:      1;
+            uint32_t reserved0                     :    4;
+            uint32_t ret_icache_size               :    8;
+            uint32_t reserved12                    :    1;
+            uint32_t ret_icache_vld_size           :    8;
+            uint32_t reserved21                    :    1;
+            uint32_t ret_icache_start_point        :    8;
+            uint32_t reserved30                    :    1;
+            uint32_t ret_icache_enable             :    1;
         };
         uint32_t val;
     } retention_ctrl2;
     union {
         struct {
-            uint32_t reserved0:              4;
-            uint32_t ret_dcache_size:        9;
-            uint32_t ret_dcache_vld_size:    9;
-            uint32_t ret_dcache_start_point: 9;
-            uint32_t ret_dcache_enable:      1;
+            uint32_t reserved0                     :    4;
+            uint32_t ret_dcache_size               :    9;
+            uint32_t ret_dcache_vld_size           :    9;
+            uint32_t ret_dcache_start_point        :    9;
+            uint32_t ret_dcache_enable             :    1;
         };
         uint32_t val;
     } retention_ctrl3;
     uint32_t retention_ctrl4;
-    uint32_t reserved_c8;
+    union {
+        struct {
+            uint32_t retention_disable             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } retention_ctrl5;
     uint32_t reserved_cc;
     uint32_t reserved_d0;
     uint32_t reserved_d4;
@@ -522,11 +531,13 @@ typedef volatile struct {
     uint32_t reserved_3f0;
     uint32_t reserved_3f4;
     uint32_t reserved_3f8;
-    uint32_t date;                                     /*Version control*/
+    uint32_t date;
 } apb_ctrl_dev_t;
 extern apb_ctrl_dev_t APB_CTRL;
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* _SOC_APB_CTRL_STRUCT_H_ */
+
+
+#endif /*_SOC_APB_CTRL_STRUCT_H_ */

components/soc/esp32s3/include/soc/apb_saradc_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_APB_SARADC_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x0)
 /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */

components/soc/esp32s3/include/soc/apb_saradc_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_APB_SARADC_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {

components/soc/esp32s3/include/soc/assist_debug_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,1322 +11,1328 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_ASSIST_DEBUG_REG_H_
+#define _SOC_ASSIST_DEBUG_REG_H_
 
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "soc.h"
-
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x0)
 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
 
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004)
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4)
 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
 
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008)
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8)
 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
 
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC)
 /* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
 /* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
 /* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10)
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14)
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x18)
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
 /* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x20)
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x24)
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x28)
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x2C)
 /* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x30)
 /* ASSIST_DEBUG_CORE_0_AREA_SP : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V) << (ASSIST_DEBUG_CORE_0_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x34)
 /* ASSIST_DEBUG_CORE_0_AREA_PC : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V) << (ASSIST_DEBUG_CORE_0_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038)
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x38)
 /* ASSIST_DEBUG_CORE_0_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE 0x000000FF
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_M ((ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V) << (ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S))
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V 0xFF
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE    0x000000FF
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S))
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V  0xFF
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x3C)
 /* ASSIST_DEBUG_CORE_0_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V) << (ASSIST_DEBUG_CORE_0_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x40)
 /* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V) << (ASSIST_DEBUG_CORE_0_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044)
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x44)
 /* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V) << (ASSIST_DEBUG_CORE_0_SP_PC_S))
-#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x48)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V 0x1
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4C)
 /* ASSIST_DEBUG_CORE_0_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V 0x1
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x50)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x54)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS 0x000000FF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V 0xFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS    0x000000FF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V  0xFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x58)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x5C)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x60)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x64)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x68)
 /* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C)
+#define ASSIST_DEBUG_CORE_0_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x6C)
 /* ASSIST_DEBUG_CORE_0_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_SP 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_SP_M ((ASSIST_DEBUG_CORE_0_RCD_SP_V) << (ASSIST_DEBUG_CORE_0_RCD_SP_S))
-#define ASSIST_DEBUG_CORE_0_RCD_SP_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_SP_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_SP_M  ((ASSIST_DEBUG_CORE_0_RCD_SP_V)<<(ASSIST_DEBUG_CORE_0_RCD_SP_S))
+#define ASSIST_DEBUG_CORE_0_RCD_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_SP_S  0
 
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x70)
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
 
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x74)
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
 /* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x78)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 22
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  22
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x003FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x003FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x7C)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000FFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x80)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x84)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 22
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  22
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x003FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x003FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x88)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8C)
 /* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
 
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090)
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x90)
 /* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S  11
 /* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
 
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094)
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x94)
 /* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S  11
 /* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S  10
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
 
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098)
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x98)
 /* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S  11
 /* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S  10
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
 
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x09C)
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x9C)
 /* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S 11
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S  11
 /* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S 10
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S  10
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S 9
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
 /* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S 8
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S 7
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S 6
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S 5
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S 4
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S 3
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S 2
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S 1
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V 0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A0)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA0)
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A4)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA4)
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A8)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA8)
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0AC)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xAC)
 /* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B0)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB0)
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B4)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB4)
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B8)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB8)
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0BC)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xBC)
 /* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C0)
+#define ASSIST_DEBUG_CORE_1_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC0)
 /* ASSIST_DEBUG_CORE_1_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_PC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PC_M ((ASSIST_DEBUG_CORE_1_AREA_PC_V) << (ASSIST_DEBUG_CORE_1_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PC_M  ((ASSIST_DEBUG_CORE_1_AREA_PC_V)<<(ASSIST_DEBUG_CORE_1_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
 
-#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C4)
+#define ASSIST_DEBUG_CORE_1_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC4)
 /* ASSIST_DEBUG_CORE_1_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_AREA_SP 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_SP_M ((ASSIST_DEBUG_CORE_1_AREA_SP_V) << (ASSIST_DEBUG_CORE_1_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_1_AREA_SP_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_SP_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_SP_M  ((ASSIST_DEBUG_CORE_1_AREA_SP_V)<<(ASSIST_DEBUG_CORE_1_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
 
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C8)
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC8)
 /* ASSIST_DEBUG_CORE_1_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE 0x000000FF
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_M ((ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V) << (ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S))
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V 0xFF
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE    0x000000FF
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S))
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V  0xFF
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S  0
 
-#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0CC)
+#define ASSIST_DEBUG_CORE_1_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xCC)
 /* ASSIST_DEBUG_CORE_1_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MIN_M ((ASSIST_DEBUG_CORE_1_SP_MIN_V) << (ASSIST_DEBUG_CORE_1_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_1_SP_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MIN_M  ((ASSIST_DEBUG_CORE_1_SP_MIN_V)<<(ASSIST_DEBUG_CORE_1_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D0)
+#define ASSIST_DEBUG_CORE_1_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD0)
 /* ASSIST_DEBUG_CORE_1_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MAX_M ((ASSIST_DEBUG_CORE_1_SP_MAX_V) << (ASSIST_DEBUG_CORE_1_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_1_SP_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MAX_M  ((ASSIST_DEBUG_CORE_1_SP_MAX_V)<<(ASSIST_DEBUG_CORE_1_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D4)
+#define ASSIST_DEBUG_CORE_1_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD4)
 /* ASSIST_DEBUG_CORE_1_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_SP_PC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_PC_M ((ASSIST_DEBUG_CORE_1_SP_PC_V) << (ASSIST_DEBUG_CORE_1_SP_PC_S))
-#define ASSIST_DEBUG_CORE_1_SP_PC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_PC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_PC_M  ((ASSIST_DEBUG_CORE_1_SP_PC_V)<<(ASSIST_DEBUG_CORE_1_SP_PC_S))
+#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D8)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD8)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V 0x1
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V  0x1
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0DC)
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xDC)
 /* ASSIST_DEBUG_CORE_1_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_M (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_V 0x1
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_V  0x1
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E0)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE0)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E4)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE4)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS 0x000000FF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V 0xFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS    0x000000FF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V  0xFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E8)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE8)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0EC)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xEC)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F0)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF0)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F4)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF4)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F8)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF8)
 /* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S  0
 
-#define ASSIST_DEBUG_CORE_1_RCD_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0FC)
+#define ASSIST_DEBUG_CORE_1_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xFC)
 /* ASSIST_DEBUG_CORE_1_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_RCD_SP 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_SP_M ((ASSIST_DEBUG_CORE_1_RCD_SP_V) << (ASSIST_DEBUG_CORE_1_RCD_SP_S))
-#define ASSIST_DEBUG_CORE_1_RCD_SP_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_SP_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_SP_M  ((ASSIST_DEBUG_CORE_1_RCD_SP_V)<<(ASSIST_DEBUG_CORE_1_RCD_SP_S))
+#define ASSIST_DEBUG_CORE_1_RCD_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_SP_S  0
 
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x100)
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S 25
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S 24
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 0x00FFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
 
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x104)
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S 25
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V 0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S 24
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
 /* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 0x00FFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x108)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S 22
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  22
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 0x003FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V 0x3FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x003FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10C)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10C)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 0x0000FFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V 0xFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x110)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x110)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x114)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x114)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V 0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S 22
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  22
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 0x003FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V 0x3FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x003FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x118)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x118)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  0
 
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x11C)
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x11C)
 /* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
 
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x120)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x120)
 /* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V) << (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
 
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x124)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x124)
 /* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V) << (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
 
-#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x128)
+#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x128)
 /* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(6))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(6))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 6
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE    (BIT(6))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(6))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  6
 /* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MODE 0x00000007
-#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V) << (ASSIST_DEBUG_LOG_MODE_S))
-#define ASSIST_DEBUG_LOG_MODE_V 0x7
-#define ASSIST_DEBUG_LOG_MODE_S 3
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MODE    0x00000007
+#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
+#define ASSIST_DEBUG_LOG_MODE_V  0x7
+#define ASSIST_DEBUG_LOG_MODE_S  3
 /* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_ENA 0x00000007
-#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V) << (ASSIST_DEBUG_LOG_ENA_S))
-#define ASSIST_DEBUG_LOG_ENA_V 0x7
-#define ASSIST_DEBUG_LOG_ENA_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_ENA    0x00000007
+#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
+#define ASSIST_DEBUG_LOG_ENA_V  0x7
+#define ASSIST_DEBUG_LOG_ENA_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x12C)
+#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x12C)
 /* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V) << (ASSIST_DEBUG_LOG_DATA_0_S))
-#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_0    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
+#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x130)
+#define ASSIST_DEBUG_LOG_DATA_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x130)
 /* ASSIST_DEBUG_LOG_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_1 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_1_M ((ASSIST_DEBUG_LOG_DATA_1_V) << (ASSIST_DEBUG_LOG_DATA_1_S))
-#define ASSIST_DEBUG_LOG_DATA_1_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_1_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_1    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_1_M  ((ASSIST_DEBUG_LOG_DATA_1_V)<<(ASSIST_DEBUG_LOG_DATA_1_S))
+#define ASSIST_DEBUG_LOG_DATA_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_1_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x134)
+#define ASSIST_DEBUG_LOG_DATA_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x134)
 /* ASSIST_DEBUG_LOG_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_2 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_2_M ((ASSIST_DEBUG_LOG_DATA_2_V) << (ASSIST_DEBUG_LOG_DATA_2_S))
-#define ASSIST_DEBUG_LOG_DATA_2_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_2_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_2    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_2_M  ((ASSIST_DEBUG_LOG_DATA_2_V)<<(ASSIST_DEBUG_LOG_DATA_2_S))
+#define ASSIST_DEBUG_LOG_DATA_2_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_2_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x138)
+#define ASSIST_DEBUG_LOG_DATA_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x138)
 /* ASSIST_DEBUG_LOG_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_3 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_3_M ((ASSIST_DEBUG_LOG_DATA_3_V) << (ASSIST_DEBUG_LOG_DATA_3_S))
-#define ASSIST_DEBUG_LOG_DATA_3_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_3_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_3    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_3_M  ((ASSIST_DEBUG_LOG_DATA_3_V)<<(ASSIST_DEBUG_LOG_DATA_3_S))
+#define ASSIST_DEBUG_LOG_DATA_3_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_3_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x13C)
+#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x13C)
 /* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V) << (ASSIST_DEBUG_LOG_DATA_SIZE_S))
-#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_SIZE    0x0000FFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
+#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
 
-#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x140)
+#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x140)
 /* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V) << (ASSIST_DEBUG_LOG_MIN_S))
-#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
+#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_S  0
 
-#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x144)
+#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x144)
 /* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V) << (ASSIST_DEBUG_LOG_MAX_S))
-#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
+#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x148)
+#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x148)
 /* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V) << (ASSIST_DEBUG_LOG_MEM_START_S))
-#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_START    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
+#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14C)
+#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14C)
 /* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V) << (ASSIST_DEBUG_LOG_MEM_END_S))
-#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_END    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
+#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x150)
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x150)
 /* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V) << (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x154)
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x154)
 /* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
-
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
-/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003040 ; */
-/*description: */
-#define ASSIST_DEBUG_DATE 0x0FFFFFFF
-#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V) << (ASSIST_DEBUG_DATE_S))
-#define ASSIST_DEBUG_DATE_V 0xFFFFFFF
-#define ASSIST_DEBUG_DATE_S 0
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG    (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
+
+#define ASSIST_DEBUG_REG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
+/* ASSIST_DEBUG_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003040 ; */
+/*description: .*/
+#define ASSIST_DEBUG_REG_DATE    0x0FFFFFFF
+#define ASSIST_DEBUG_REG_DATE_M  ((ASSIST_DEBUG_REG_DATE_V)<<(ASSIST_DEBUG_REG_DATE_S))
+#define ASSIST_DEBUG_REG_DATE_V  0xFFFFFFF
+#define ASSIST_DEBUG_REG_DATE_S  0
+
 
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_REG_H_ */

components/soc/esp32s3/include/soc/assist_debug_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,398 +11,399 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
+#define _SOC_ASSIST_DEBUG_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
-            uint32_t core_0_area_dram0_0_rd_ena:         1;
-            uint32_t core_0_area_dram0_0_wr_ena:         1;
-            uint32_t core_0_area_dram0_1_rd_ena:         1;
-            uint32_t core_0_area_dram0_1_wr_ena:         1;
-            uint32_t core_0_area_pif_0_rd_ena:           1;
-            uint32_t core_0_area_pif_0_wr_ena:           1;
-            uint32_t core_0_area_pif_1_rd_ena:           1;
-            uint32_t core_0_area_pif_1_wr_ena:           1;
-            uint32_t core_0_sp_spill_min_ena:            1;
-            uint32_t core_0_sp_spill_max_ena:            1;
-            uint32_t core_0_iram0_exception_monitor_ena: 1;
-            uint32_t core_0_dram0_exception_monitor_ena: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_0_interrupt_ena;
     union {
         struct {
-            uint32_t core_0_area_dram0_0_rd_raw:         1;
-            uint32_t core_0_area_dram0_0_wr_raw:         1;
-            uint32_t core_0_area_dram0_1_rd_raw:         1;
-            uint32_t core_0_area_dram0_1_wr_raw:         1;
-            uint32_t core_0_area_pif_0_rd_raw:           1;
-            uint32_t core_0_area_pif_0_wr_raw:           1;
-            uint32_t core_0_area_pif_1_rd_raw:           1;
-            uint32_t core_0_area_pif_1_wr_raw:           1;
-            uint32_t core_0_sp_spill_min_raw:            1;
-            uint32_t core_0_sp_spill_max_raw:            1;
-            uint32_t core_0_iram0_exception_monitor_raw: 1;
-            uint32_t core_0_dram0_exception_monitor_raw: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_0_interrupt_raw;
     union {
         struct {
-            uint32_t core_0_area_dram0_0_rd_rls:         1;
-            uint32_t core_0_area_dram0_0_wr_rls:         1;
-            uint32_t core_0_area_dram0_1_rd_rls:         1;
-            uint32_t core_0_area_dram0_1_wr_rls:         1;
-            uint32_t core_0_area_pif_0_rd_rls:           1;
-            uint32_t core_0_area_pif_0_wr_rls:           1;
-            uint32_t core_0_area_pif_1_rd_rls:           1;
-            uint32_t core_0_area_pif_1_wr_rls:           1;
-            uint32_t core_0_sp_spill_min_rls:            1;
-            uint32_t core_0_sp_spill_max_rls:            1;
-            uint32_t core_0_iram0_exception_monitor_rls: 1;
-            uint32_t core_0_dram0_exception_monitor_rls: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_0_interrupt_rls;
     union {
         struct {
-            uint32_t core_0_area_dram0_0_rd_clr:         1;
-            uint32_t core_0_area_dram0_0_wr_clr:         1;
-            uint32_t core_0_area_dram0_1_rd_clr:         1;
-            uint32_t core_0_area_dram0_1_wr_clr:         1;
-            uint32_t core_0_area_pif_0_rd_clr:           1;
-            uint32_t core_0_area_pif_0_wr_clr:           1;
-            uint32_t core_0_area_pif_1_rd_clr:           1;
-            uint32_t core_0_area_pif_1_wr_clr:           1;
-            uint32_t core_0_sp_spill_min_clr:            1;
-            uint32_t core_0_sp_spill_max_clr:            1;
-            uint32_t core_0_iram0_exception_monitor_clr: 1;
-            uint32_t core_0_dram0_exception_monitor_clr: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_0_interrupt_clr;
-    uint32_t core_0_area_dram0_0_min;                         /**/
-    uint32_t core_0_area_dram0_0_max;                         /**/
-    uint32_t core_0_area_dram0_1_min;                         /**/
-    uint32_t core_0_area_dram0_1_max;                         /**/
-    uint32_t core_0_area_pif_0_min;                           /**/
-    uint32_t core_0_area_pif_0_max;                           /**/
-    uint32_t core_0_area_pif_1_min;                           /**/
-    uint32_t core_0_area_pif_1_max;                           /**/
-    uint32_t core_0_area_sp;                                  /**/
-    uint32_t core_0_area_pc;                                  /**/
+    uint32_t core_0_area_dram0_0_min;
+    uint32_t core_0_area_dram0_0_max;
+    uint32_t core_0_area_dram0_1_min;
+    uint32_t core_0_area_dram0_1_max;
+    uint32_t core_0_area_pif_0_min;
+    uint32_t core_0_area_pif_0_max;
+    uint32_t core_0_area_pif_1_min;
+    uint32_t core_0_area_pif_1_max;
+    uint32_t core_0_area_sp;
+    uint32_t core_0_area_pc;
     union {
         struct {
-            uint32_t core_0_sp_unstable: 8;
-            uint32_t reserved8:         24;
+            uint32_t core_0_sp_unstable            :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } core_0_sp_unstable;
-    uint32_t core_0_sp_min;                                   /**/
-    uint32_t core_0_sp_max;                                   /**/
-    uint32_t core_0_sp_pc;                                    /**/
+    uint32_t core_0_sp_min;
+    uint32_t core_0_sp_max;
+    uint32_t core_0_sp_pc;
     union {
         struct {
-            uint32_t core_0_rcd_pdebugenable: 1;
-            uint32_t reserved1:              31;
+            uint32_t core_0_rcd_pdebugenable       :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } core_0_rcd_pdebugenable;
     union {
         struct {
-            uint32_t core_0_rcd_recording: 1;
-            uint32_t reserved1:           31;
+            uint32_t core_0_rcd_recording          :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } core_0_rcd_recording;
-    uint32_t core_0_rcd_pdebuginst;                           /**/
+    uint32_t core_0_rcd_pdebuginst;
     union {
         struct {
-            uint32_t core_0_rcd_pdebugstatus: 8;
-            uint32_t reserved8:              24;
+            uint32_t core_0_rcd_pdebugstatus       :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } core_0_rcd_pdebugstatus;
-    uint32_t core_0_rcd_pdebugdata;                           /**/
-    uint32_t core_0_rcd_pdebugpc;                             /**/
-    uint32_t core_0_rcd_pdebugls0stat;                        /**/
-    uint32_t core_0_rcd_pdebugls0addr;                        /**/
-    uint32_t core_0_rcd_pdebugls0data;                        /**/
-    uint32_t core_0_rcd_sp;                                   /**/
+    uint32_t core_0_rcd_pdebugdata;
+    uint32_t core_0_rcd_pdebugpc;
+    uint32_t core_0_rcd_pdebugls0stat;
+    uint32_t core_0_rcd_pdebugls0addr;
+    uint32_t core_0_rcd_pdebugls0data;
+    uint32_t core_0_rcd_sp;
     union {
         struct {
-            uint32_t core_0_iram0_recording_addr_0:     24;
-            uint32_t core_0_iram0_recording_wr_0:        1;
-            uint32_t core_0_iram0_recording_loadstore_0: 1;
-            uint32_t reserved26:                         6;
+            uint32_t core_0_iram0_recording_addr_0 :    24;
+            uint32_t core_0_iram0_recording_wr_0   :    1;
+            uint32_t core_0_iram0_recording_loadstore_0:    1;
+            uint32_t reserved26                    :    6;
         };
         uint32_t val;
     } core_0_iram0_exception_monitor_0;
     union {
         struct {
-            uint32_t core_0_iram0_recording_addr_1:     24;
-            uint32_t core_0_iram0_recording_wr_1:        1;
-            uint32_t core_0_iram0_recording_loadstore_1: 1;
-            uint32_t reserved26:                         6;
+            uint32_t core_0_iram0_recording_addr_1 :    24;
+            uint32_t core_0_iram0_recording_wr_1   :    1;
+            uint32_t core_0_iram0_recording_loadstore_1:    1;
+            uint32_t reserved26                    :    6;
         };
         uint32_t val;
     } core_0_iram0_exception_monitor_1;
     union {
         struct {
-            uint32_t core_0_dram0_recording_addr_0: 22;
-            uint32_t core_0_dram0_recording_wr_0:   1;
-            uint32_t reserved23:                    9;
+            uint32_t core_0_dram0_recording_addr_0 :    22;
+            uint32_t core_0_dram0_recording_wr_0   :    1;
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } core_0_dram0_exception_monitor_0;
     union {
         struct {
-            uint32_t core_0_dram0_recording_byteen_0: 16;
-            uint32_t reserved16:                     16;
+            uint32_t core_0_dram0_recording_byteen_0:    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } core_0_dram0_exception_monitor_1;
-    uint32_t core_0_dram0_exception_monitor_2;                /**/
+    uint32_t core_0_dram0_exception_monitor_2;
     union {
         struct {
-            uint32_t core_0_dram0_recording_addr_1: 22;
-            uint32_t core_0_dram0_recording_wr_1:   1;
-            uint32_t reserved23:                    9;
+            uint32_t core_0_dram0_recording_addr_1 :    22;
+            uint32_t core_0_dram0_recording_wr_1   :    1;
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } core_0_dram0_exception_monitor_3;
     union {
         struct {
-            uint32_t core_0_dram0_recording_byteen_1: 16;
-            uint32_t reserved16:                     16;
+            uint32_t core_0_dram0_recording_byteen_1:    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } core_0_dram0_exception_monitor_4;
-    uint32_t core_0_dram0_exception_monitor_5;                /**/
+    uint32_t core_0_dram0_exception_monitor_5;
     union {
         struct {
-            uint32_t core_1_area_dram0_0_rd_ena:         1;
-            uint32_t core_1_area_dram0_0_wr_ena:         1;
-            uint32_t core_1_area_dram0_1_rd_ena:         1;
-            uint32_t core_1_area_dram0_1_wr_ena:         1;
-            uint32_t core_1_area_pif_0_rd_ena:           1;
-            uint32_t core_1_area_pif_0_wr_ena:           1;
-            uint32_t core_1_area_pif_1_rd_ena:           1;
-            uint32_t core_1_area_pif_1_wr_ena:           1;
-            uint32_t core_1_sp_spill_min_ena:            1;
-            uint32_t core_1_sp_spill_max_ena:            1;
-            uint32_t core_1_iram0_exception_monitor_ena: 1;
-            uint32_t core_1_dram0_exception_monitor_ena: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_1_interrupt_ena;
     union {
         struct {
-            uint32_t core_1_area_dram0_0_rd_raw:         1;
-            uint32_t core_1_area_dram0_0_wr_raw:         1;
-            uint32_t core_1_area_dram0_1_rd_raw:         1;
-            uint32_t core_1_area_dram0_1_wr_raw:         1;
-            uint32_t core_1_area_pif_0_rd_raw:           1;
-            uint32_t core_1_area_pif_0_wr_raw:           1;
-            uint32_t core_1_area_pif_1_rd_raw:           1;
-            uint32_t core_1_area_pif_1_wr_raw:           1;
-            uint32_t core_1_sp_spill_min_raw:            1;
-            uint32_t core_1_sp_spill_max_raw:            1;
-            uint32_t core_1_iram0_exception_monitor_raw: 1;
-            uint32_t core_1_dram0_exception_monitor_raw: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_1_interrupt_raw;
     union {
         struct {
-            uint32_t core_1_area_dram0_0_rd_rls:         1;
-            uint32_t core_1_area_dram0_0_wr_rls:         1;
-            uint32_t core_1_area_dram0_1_rd_rls:         1;
-            uint32_t core_1_area_dram0_1_wr_rls:         1;
-            uint32_t core_1_area_pif_0_rd_rls:           1;
-            uint32_t core_1_area_pif_0_wr_rls:           1;
-            uint32_t core_1_area_pif_1_rd_rls:           1;
-            uint32_t core_1_area_pif_1_wr_rls:           1;
-            uint32_t core_1_sp_spill_min_rls:            1;
-            uint32_t core_1_sp_spill_max_rls:            1;
-            uint32_t core_1_iram0_exception_monitor_rls: 1;
-            uint32_t core_1_dram0_exception_monitor_rls: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_1_interrupt_rls;
     union {
         struct {
-            uint32_t core_1_area_dram0_0_rd_clr:         1;
-            uint32_t core_1_area_dram0_0_wr_clr:         1;
-            uint32_t core_1_area_dram0_1_rd_clr:         1;
-            uint32_t core_1_area_dram0_1_wr_clr:         1;
-            uint32_t core_1_area_pif_0_rd_clr:           1;
-            uint32_t core_1_area_pif_0_wr_clr:           1;
-            uint32_t core_1_area_pif_1_rd_clr:           1;
-            uint32_t core_1_area_pif_1_wr_clr:           1;
-            uint32_t core_1_sp_spill_min_clr:            1;
-            uint32_t core_1_sp_spill_max_clr:            1;
-            uint32_t core_1_iram0_exception_monitor_clr: 1;
-            uint32_t core_1_dram0_exception_monitor_clr: 1;
-            uint32_t reserved12:                        20;
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } core_1_interrupt_clr;
-    uint32_t core_1_area_dram0_0_min;                         /**/
-    uint32_t core_1_area_dram0_0_max;                         /**/
-    uint32_t core_1_area_dram0_1_min;                         /**/
-    uint32_t core_1_area_dram0_1_max;                         /**/
-    uint32_t core_1_area_pif_0_min;                           /**/
-    uint32_t core_1_area_pif_0_max;                           /**/
-    uint32_t core_1_area_pif_1_min;                           /**/
-    uint32_t core_1_area_pif_1_max;                           /**/
-    uint32_t core_1_area_pc;                                  /**/
-    uint32_t core_1_area_sp;                                  /**/
+    uint32_t core_1_area_dram0_0_min;
+    uint32_t core_1_area_dram0_0_max;
+    uint32_t core_1_area_dram0_1_min;
+    uint32_t core_1_area_dram0_1_max;
+    uint32_t core_1_area_pif_0_min;
+    uint32_t core_1_area_pif_0_max;
+    uint32_t core_1_area_pif_1_min;
+    uint32_t core_1_area_pif_1_max;
+    uint32_t core_1_area_pc;
+    uint32_t core_1_area_sp;
     union {
         struct {
-            uint32_t core_1_sp_unstable: 8;
-            uint32_t reserved8:         24;
+            uint32_t core_1_sp_unstable            :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } core_1_sp_unstable;
-    uint32_t core_1_sp_min;                                   /**/
-    uint32_t core_1_sp_max;                                   /**/
-    uint32_t core_1_sp_pc;                                    /**/
+    uint32_t core_1_sp_min;
+    uint32_t core_1_sp_max;
+    uint32_t core_1_sp_pc;
     union {
         struct {
-            uint32_t core_1_rcd_pdebugenable: 1;
-            uint32_t reserved1:              31;
+            uint32_t core_1_rcd_pdebugenable       :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } core_1_rcd_pdebugenable;
     union {
         struct {
-            uint32_t core_1_rcd_recording: 1;
-            uint32_t reserved1:           31;
+            uint32_t core_1_rcd_recording          :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } core_1_rcd_recording;
-    uint32_t core_1_rcd_pdebuginst;                           /**/
+    uint32_t core_1_rcd_pdebuginst;
     union {
         struct {
-            uint32_t core_1_rcd_pdebugstatus: 8;
-            uint32_t reserved8:              24;
+            uint32_t core_1_rcd_pdebugstatus       :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } core_1_rcd_pdebugstatus;
-    uint32_t core_1_rcd_pdebugdata;                           /**/
-    uint32_t core_1_rcd_pdebugpc;                             /**/
-    uint32_t core_1_rcd_pdebugls0stat;                        /**/
-    uint32_t core_1_rcd_pdebugls0addr;                        /**/
-    uint32_t core_1_rcd_pdebugls0data;                        /**/
-    uint32_t core_1_rcd_sp;                                   /**/
+    uint32_t core_1_rcd_pdebugdata;
+    uint32_t core_1_rcd_pdebugpc;
+    uint32_t core_1_rcd_pdebugls0stat;
+    uint32_t core_1_rcd_pdebugls0addr;
+    uint32_t core_1_rcd_pdebugls0data;
+    uint32_t core_1_rcd_sp;
     union {
         struct {
-            uint32_t core_1_iram0_recording_addr_0:     24;
-            uint32_t core_1_iram0_recording_wr_0:        1;
-            uint32_t core_1_iram0_recording_loadstore_0: 1;
-            uint32_t reserved26:                         6;
+            uint32_t core_1_iram0_recording_addr_0 :    24;
+            uint32_t core_1_iram0_recording_wr_0   :    1;
+            uint32_t core_1_iram0_recording_loadstore_0:    1;
+            uint32_t reserved26                    :    6;
         };
         uint32_t val;
     } core_1_iram0_exception_monitor_0;
     union {
         struct {
-            uint32_t core_1_iram0_recording_addr_1:     24;
-            uint32_t core_1_iram0_recording_wr_1:        1;
-            uint32_t core_1_iram0_recording_loadstore_1: 1;
-            uint32_t reserved26:                         6;
+            uint32_t core_1_iram0_recording_addr_1 :    24;
+            uint32_t core_1_iram0_recording_wr_1   :    1;
+            uint32_t core_1_iram0_recording_loadstore_1:    1;
+            uint32_t reserved26                    :    6;
         };
         uint32_t val;
     } core_1_iram0_exception_monitor_1;
     union {
         struct {
-            uint32_t core_1_dram0_recording_addr_0: 22;
-            uint32_t core_1_dram0_recording_wr_0:   1;
-            uint32_t reserved23:                    9;
+            uint32_t core_1_dram0_recording_addr_0 :    22;
+            uint32_t core_1_dram0_recording_wr_0   :    1;
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } core_1_dram0_exception_monitor_0;
     union {
         struct {
-            uint32_t core_1_dram0_recording_byteen_0: 16;
-            uint32_t reserved16:                     16;
+            uint32_t core_1_dram0_recording_byteen_0:    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } core_1_dram0_exception_monitor_1;
-    uint32_t core_1_dram0_exception_monitor_2;                /**/
+    uint32_t core_1_dram0_exception_monitor_2;
     union {
         struct {
-            uint32_t core_1_dram0_recording_addr_1: 22;
-            uint32_t core_1_dram0_recording_wr_1:   1;
-            uint32_t reserved23:                    9;
+            uint32_t core_1_dram0_recording_addr_1 :    22;
+            uint32_t core_1_dram0_recording_wr_1   :    1;
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } core_1_dram0_exception_monitor_3;
     union {
         struct {
-            uint32_t core_1_dram0_recording_byteen_1: 16;
-            uint32_t reserved16:                     16;
+            uint32_t core_1_dram0_recording_byteen_1:    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } core_1_dram0_exception_monitor_4;
-    uint32_t core_1_dram0_exception_monitor_5;                /**/
+    uint32_t core_1_dram0_exception_monitor_5;
     union {
         struct {
-            uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
-            uint32_t reserved20:                      12;
+            uint32_t core_x_iram0_dram0_limit_cycle_0:    20;
+            uint32_t reserved20                    :    12;
         };
         uint32_t val;
     } core_x_iram0_dram0_exception_monitor_0;
     union {
         struct {
-            uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
-            uint32_t reserved20:                      12;
+            uint32_t core_x_iram0_dram0_limit_cycle_1:    20;
+            uint32_t reserved20                    :    12;
         };
         uint32_t val;
     } core_x_iram0_dram0_exception_monitor_1;
     union {
         struct {
-            uint32_t log_ena:             3;
-            uint32_t log_mode:            3;
-            uint32_t log_mem_loop_enable: 1;
-            uint32_t reserved7:          25;
+            uint32_t log                           :    3;
+            uint32_t log_mode                      :    3;
+            uint32_t log_mem_loopble               :    1;
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } log_setting;
-    uint32_t log_data_0;                                      /**/
-    uint32_t log_data_1;                                      /**/
-    uint32_t log_data_2;                                      /**/
-    uint32_t log_data_3;                                      /**/
+    uint32_t log_data_0;
+    uint32_t log_data_1;
+    uint32_t log_data_2;
+    uint32_t log_data_3;
     union {
         struct {
-            uint32_t log_data_size: 16;
-            uint32_t reserved16:   16;
+            uint32_t log_data_size                 :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } log_data_mask;
-    uint32_t log_min;                                         /**/
-    uint32_t log_max;                                         /**/
-    uint32_t log_mem_start;                                   /**/
-    uint32_t log_mem_end;                                     /**/
-    uint32_t log_mem_writing_addr;                            /**/
+    uint32_t log_min;
+    uint32_t log_max;
+    uint32_t log_mem_start;
+    uint32_t log_mem_end;
+    uint32_t log_mem_writing_addr;
     union {
         struct {
-            uint32_t log_mem_full_flag: 1;
-            uint32_t reserved1:        31;
+            uint32_t log_mem_full_flag             :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } log_mem_full_flag;
@@ -449,15 +450,17 @@ typedef volatile struct {
     uint32_t reserved_1f8;
     union {
         struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
+            uint32_t assist_debug_reg_date         :    28;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
-    } date;
+    } reg_date;
 } assist_debug_dev_t;
-
 extern assist_debug_dev_t ASSIST_DEBUG;
-
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */

components/soc/esp32s3/include/soc/dport_reg.h

@@ -13,6 +13,7 @@
 // limitations under the License.
 #pragma once
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/efuse_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_EFUSE_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0)
 /* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */

components/soc/esp32s3/include/soc/efuse_struct.h

@@ -15,10 +15,10 @@
 #define _SOC_EFUSE_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     uint32_t pgm_data0;

components/soc/esp32s3/include/soc/extmem_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,12 +11,14 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
 
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define EXTMEM_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0)
 /* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
@@ -1204,7 +1206,7 @@ thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..
 #define EXTMEM_CORE0_DBUS_TAG_ATTR_S  0
 
 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x104)
-/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
 /*description: The bits are used to indicate the virtual address of CPU access dbus when authen
 tication fail..*/
 #define EXTMEM_CORE0_DBUS_VADDR    0xFFFFFFFF
@@ -1236,7 +1238,7 @@ thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..
 #define EXTMEM_CORE0_IBUS_TAG_ATTR_S  0
 
 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x10C)
-/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
 /*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
 ntication fail..*/
 #define EXTMEM_CORE0_IBUS_VADDR    0xFFFFFFFF
@@ -1268,7 +1270,7 @@ thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..
 #define EXTMEM_CORE1_DBUS_TAG_ATTR_S  0
 
 #define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x114)
-/* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
 /*description: The bits are used to indicate the virtual address of CPU access dbus when authen
 tication fail..*/
 #define EXTMEM_CORE1_DBUS_VADDR    0xFFFFFFFF
@@ -1300,7 +1302,7 @@ thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..
 #define EXTMEM_CORE1_IBUS_TAG_ATTR_S  0
 
 #define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x11C)
-/* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
 /*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
 ntication fail..*/
 #define EXTMEM_CORE1_IBUS_VADDR    0xFFFFFFFF
@@ -1370,14 +1372,14 @@ enable, 1: disable.*/
 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
 
 #define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x130)
-/* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */
+/* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h001 ; */
 /*description: The bit is used to indicate whether dcache main fsm is in idle state or not. 1:
 in idle state,  0: not in idle state.*/
 #define EXTMEM_DCACHE_STATE    0x00000FFF
 #define EXTMEM_DCACHE_STATE_M  ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S))
 #define EXTMEM_DCACHE_STATE_V  0xFFF
 #define EXTMEM_DCACHE_STATE_S  12
-/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h001 ; */
 /*description: The bit is used to indicate whether  icache main fsm is in idle state or not. 1:
  in idle state,  0: not in idle state.*/
 #define EXTMEM_ICACHE_STATE    0x00000FFF
@@ -1658,7 +1660,7 @@ mory on the specified cache..*/
 
 #define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */
-/*description: Reserved..*/
+/*description: version information..*/
 #define EXTMEM_DATE    0x0FFFFFFF
 #define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
 #define EXTMEM_DATE_V  0xFFFFFFF
@@ -1668,3 +1670,7 @@ mory on the specified cache..*/
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */

components/soc/esp32s3/include/soc/extmem_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,14 +11,15 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_EXTMEM_STRUCT_H_
+#define _SOC_EXTMEM_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
@@ -49,469 +50,469 @@ typedef volatile struct {
     } dcache_tag_power_ctrl;
     union {
         struct {
-            uint32_t dcache_prelock_sct0_en: 1;                 /*The bit is used to enable the first section of prelock function.*/
-            uint32_t dcache_prelock_sct1_en: 1;                 /*The bit is used to enable the second section of prelock function.*/
-            uint32_t reserved2:             30;
+            uint32_t dcache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
+            uint32_t dcache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } dcache_prelock_ctrl;
-    uint32_t dcache_prelock_sct0_addr;                          /*The bits are used to configure the first start virtual address of data prelock  which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/
-    uint32_t dcache_prelock_sct1_addr;                          /*The bits are used to configure the second start virtual address of data prelock  which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/
+    uint32_t dcache_prelock_sct0_addr;
+    uint32_t dcache_prelock_sct1_addr;
     union {
         struct {
-            uint32_t dcache_prelock_sct1_size:16;               /*The bits are used to configure the second length of data locking  which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
-            uint32_t dcache_prelock_sct0_size:16;               /*The bits are used to configure the first length of data locking  which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
+            uint32_t dcache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
+            uint32_t dcache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
         };
         uint32_t val;
     } dcache_prelock_sct_size;
     union {
         struct {
-            uint32_t dcache_lock_ena:   1;                      /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
-            uint32_t dcache_unlock_ena: 1;                      /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
-            uint32_t dcache_lock_done:  1;                      /*The bit is used to indicate unlock/lock operation is finished.*/
-            uint32_t reserved3:        29;
+            uint32_t dcache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
+            uint32_t dcache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
+            uint32_t dcache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } dcache_lock_ctrl;
-    uint32_t dcache_lock_addr;                                  /*The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/
+    uint32_t dcache_lock_addr;
     union {
         struct {
-            uint32_t dcache_lock_size:16;                       /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
-            uint32_t reserved16:      16;
+            uint32_t dcache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } dcache_lock_size;
     union {
         struct {
-            uint32_t dcache_invalidate_ena: 1;                  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
-            uint32_t dcache_writeback_ena:  1;                  /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
-            uint32_t dcache_clean_ena:      1;                  /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
-            uint32_t dcache_sync_done:      1;                  /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
-            uint32_t reserved4:            28;
+            uint32_t dcache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
+            uint32_t dcache_writeback_ena          :    1;  /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
+            uint32_t dcache_clean_ena              :    1;  /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
+            uint32_t dcache_sync_done              :    1;  /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
+            uint32_t reserved4                     :    28;
         };
         uint32_t val;
     } dcache_sync_ctrl;
-    uint32_t dcache_sync_addr;                                  /*The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/
+    uint32_t dcache_sync_addr;
     union {
         struct {
-            uint32_t dcache_sync_size:23;                       /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
-            uint32_t reserved23:       9;
+            uint32_t dcache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } dcache_sync_size;
     union {
         struct {
-            uint32_t dcache_occupy_ena:  1;                     /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
-            uint32_t dcache_occupy_done: 1;                     /*The bit is used to indicate occupy operation is finished.*/
-            uint32_t reserved2:         30;
+            uint32_t dcache_occupy_ena             :    1;  /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
+            uint32_t dcache_occupy_done            :    1;  /*The bit is used to indicate occupy operation is finished.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } dcache_occupy_ctrl;
-    uint32_t dcache_occupy_addr;                                /*The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/
+    uint32_t dcache_occupy_addr;
     union {
         struct {
-            uint32_t dcache_occupy_size:16;                     /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
-            uint32_t reserved16:        16;
+            uint32_t dcache_occupy_size            :    16;  /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } dcache_occupy_size;
     union {
         struct {
-            uint32_t dcache_preload_ena:   1;                   /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
-            uint32_t dcache_preload_done:  1;                   /*The bit is used to indicate preload operation is finished.*/
-            uint32_t dcache_preload_order: 1;                   /*The bit is used to configure the direction of preload operation. 1: descending  0: ascending.*/
-            uint32_t reserved3:           29;
+            uint32_t dcache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
+            uint32_t dcache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
+            uint32_t dcache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } dcache_preload_ctrl;
-    uint32_t dcache_preload_addr;                               /*The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/
+    uint32_t dcache_preload_addr;
     union {
         struct {
-            uint32_t dcache_preload_size:16;                    /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
-            uint32_t reserved16:         16;
+            uint32_t dcache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } dcache_preload_size;
     union {
         struct {
-            uint32_t dcache_autoload_sct0_ena:     1;           /*The bits are used to enable the first section for autoload operation.*/
-            uint32_t dcache_autoload_sct1_ena:     1;           /*The bits are used to enable the second section for autoload operation.*/
-            uint32_t dcache_autoload_ena:          1;           /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable  0: disable.*/
-            uint32_t dcache_autoload_done:         1;           /*The bit is used to indicate autoload operation is finished.*/
-            uint32_t dcache_autoload_order:        1;           /*The bits are used to configure the direction of autoload. 1: descending  0: ascending.*/
-            uint32_t dcache_autoload_rqst:         2;           /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
-            uint32_t dcache_autoload_size:         2;           /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
-            uint32_t dcache_autoload_buffer_clear: 1;           /*The bit is used to clear autoload buffer in dcache.*/
-            uint32_t reserved10:                  22;
+            uint32_t dcache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
+            uint32_t dcache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
+            uint32_t dcache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. */
+            uint32_t dcache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
+            uint32_t dcache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
+            uint32_t dcache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
+            uint32_t dcache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
+            uint32_t dcache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in dcache.*/
+            uint32_t reserved10                    :    22;
         };
         uint32_t val;
     } dcache_autoload_ctrl;
-    uint32_t dcache_autoload_sct0_addr;                         /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
+    uint32_t dcache_autoload_sct0_addr;
     union {
         struct {
-            uint32_t dcache_autoload_sct0_size:27;              /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
-            uint32_t reserved27:                5;
+            uint32_t dcache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
+            uint32_t reserved27                    :    5;
         };
         uint32_t val;
     } dcache_autoload_sct0_size;
-    uint32_t dcache_autoload_sct1_addr;                         /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
+    uint32_t dcache_autoload_sct1_addr;
     union {
         struct {
-            uint32_t dcache_autoload_sct1_size:27;              /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
-            uint32_t reserved27:                5;
+            uint32_t dcache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
+            uint32_t reserved27                    :    5;
         };
         uint32_t val;
     } dcache_autoload_sct1_size;
     union {
         struct {
-            uint32_t icache_enable:         1;                  /*The bit is used to activate the data cache. 0: disable  1: enable*/
-            uint32_t icache_way_mode:       1;                  /*The bit is used to configure cache way mode.0: 4-way  1: 8-way*/
-            uint32_t icache_size_mode:      1;                  /*The bit is used to configure cache memory size.0: 16KB  1: 32KB*/
-            uint32_t icache_blocksize_mode: 1;                  /*The bit is used to configure cache block size.0: 16 bytes  1: 32 bytes*/
-            uint32_t reserved4:            28;
+            uint32_t icache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
+            uint32_t icache_way_mode               :    1;  /*The bit is used to configure cache way mode.0: 4-way, 1: 8-way*/
+            uint32_t icache_size_mode              :    1;  /*The bit is used to configure cache memory size.0: 16KB, 1: 32KB*/
+            uint32_t icache_blocksize_mode         :    1;  /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes*/
+            uint32_t reserved4                     :    28;
         };
         uint32_t val;
     } icache_ctrl;
     union {
         struct {
-            uint32_t icache_shut_core0_bus: 1;                  /*The bit is used to disable core0 ibus  0: enable  1: disable*/
-            uint32_t icache_shut_core1_bus: 1;                  /*The bit is used to disable core1 ibus  0: enable  1: disable*/
-            uint32_t reserved2:            30;
+            uint32_t icache_shut_core0_bus         :    1;  /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/
+            uint32_t icache_shut_core1_bus         :    1;  /*The bit is used to disable core1 ibus, 0: enable, 1: disable*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } icache_ctrl1;
     union {
         struct {
-            uint32_t icache_tag_mem_force_on: 1;                /*The bit is used to close clock gating of  icache tag memory. 1: close gating  0: open clock gating.*/
-            uint32_t icache_tag_mem_force_pd: 1;                /*The bit is used to power  icache tag memory down  0: follow rtc_lslp  1: power down*/
-            uint32_t icache_tag_mem_force_pu: 1;                /*The bit is used to power  icache tag memory up  0: follow rtc_lslp  1: power up*/
-            uint32_t reserved3:              29;
+            uint32_t icache_tag_mem_force_on       :    1;  /*The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.*/
+            uint32_t icache_tag_mem_force_pd       :    1;  /*The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down*/
+            uint32_t icache_tag_mem_force_pu       :    1;  /*The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } icache_tag_power_ctrl;
     union {
         struct {
-            uint32_t icache_prelock_sct0_en: 1;                 /*The bit is used to enable the first section of prelock function.*/
-            uint32_t icache_prelock_sct1_en: 1;                 /*The bit is used to enable the second section of prelock function.*/
-            uint32_t reserved2:             30;
+            uint32_t icache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
+            uint32_t icache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } icache_prelock_ctrl;
-    uint32_t icache_prelock_sct0_addr;                          /*The bits are used to configure the first start virtual address of data prelock  which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
-    uint32_t icache_prelock_sct1_addr;                          /*The bits are used to configure the second start virtual address of data prelock  which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
+    uint32_t icache_prelock_sct0_addr;
+    uint32_t icache_prelock_sct1_addr;
     union {
         struct {
-            uint32_t icache_prelock_sct1_size:16;               /*The bits are used to configure the second length of data locking  which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
-            uint32_t icache_prelock_sct0_size:16;               /*The bits are used to configure the first length of data locking  which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
+            uint32_t icache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
+            uint32_t icache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
         };
         uint32_t val;
     } icache_prelock_sct_size;
     union {
         struct {
-            uint32_t icache_lock_ena:   1;                      /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
-            uint32_t icache_unlock_ena: 1;                      /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
-            uint32_t icache_lock_done:  1;                      /*The bit is used to indicate unlock/lock operation is finished.*/
-            uint32_t reserved3:        29;
+            uint32_t icache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
+            uint32_t icache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
+            uint32_t icache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } icache_lock_ctrl;
-    uint32_t icache_lock_addr;                                  /*The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
+    uint32_t icache_lock_addr;
     union {
         struct {
-            uint32_t icache_lock_size:16;                       /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
-            uint32_t reserved16:      16;
+            uint32_t icache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } icache_lock_size;
     union {
         struct {
-            uint32_t icache_invalidate_ena: 1;                  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
-            uint32_t icache_sync_done:      1;                  /*The bit is used to indicate invalidate operation is finished.*/
-            uint32_t reserved2:            30;
+            uint32_t icache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
+            uint32_t icache_sync_done              :    1;  /*The bit is used to indicate invalidate operation is finished.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } icache_sync_ctrl;
-    uint32_t icache_sync_addr;                                  /*The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
+    uint32_t icache_sync_addr;
     union {
         struct {
-            uint32_t icache_sync_size:23;                       /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
-            uint32_t reserved23:       9;
+            uint32_t icache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
     } icache_sync_size;
     union {
         struct {
-            uint32_t icache_preload_ena:   1;                   /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
-            uint32_t icache_preload_done:  1;                   /*The bit is used to indicate preload operation is finished.*/
-            uint32_t icache_preload_order: 1;                   /*The bit is used to configure the direction of preload operation. 1: descending  0: ascending.*/
-            uint32_t reserved3:           29;
+            uint32_t icache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
+            uint32_t icache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
+            uint32_t icache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } icache_preload_ctrl;
-    uint32_t icache_preload_addr;                               /*The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
+    uint32_t icache_preload_addr;
     union {
         struct {
-            uint32_t icache_preload_size:16;                    /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
-            uint32_t reserved16:         16;
+            uint32_t icache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } icache_preload_size;
     union {
         struct {
-            uint32_t icache_autoload_sct0_ena:     1;           /*The bits are used to enable the first section for autoload operation.*/
-            uint32_t icache_autoload_sct1_ena:     1;           /*The bits are used to enable the second section for autoload operation.*/
-            uint32_t icache_autoload_ena:          1;           /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable  0: disable.*/
-            uint32_t icache_autoload_done:         1;           /*The bit is used to indicate autoload operation is finished.*/
-            uint32_t icache_autoload_order:        1;           /*The bits are used to configure the direction of autoload. 1: descending  0: ascending.*/
-            uint32_t icache_autoload_rqst:         2;           /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
-            uint32_t icache_autoload_size:         2;           /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
-            uint32_t icache_autoload_buffer_clear: 1;           /*The bit is used to clear autoload buffer in icache.*/
-            uint32_t reserved10:                  22;
+            uint32_t icache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
+            uint32_t icache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
+            uint32_t icache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. */
+            uint32_t icache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
+            uint32_t icache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
+            uint32_t icache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
+            uint32_t icache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
+            uint32_t icache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in icache.*/
+            uint32_t reserved10                    :    22;
         };
         uint32_t val;
     } icache_autoload_ctrl;
-    uint32_t icache_autoload_sct0_addr;                         /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+    uint32_t icache_autoload_sct0_addr;
     union {
         struct {
-            uint32_t icache_autoload_sct0_size:27;              /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
-            uint32_t reserved27:                5;
+            uint32_t icache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+            uint32_t reserved27                    :    5;
         };
         uint32_t val;
     } icache_autoload_sct0_size;
-    uint32_t icache_autoload_sct1_addr;                         /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+    uint32_t icache_autoload_sct1_addr;
     union {
         struct {
-            uint32_t icache_autoload_sct1_size:27;              /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
-            uint32_t reserved27:                5;
+            uint32_t icache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+            uint32_t reserved27                    :    5;
         };
         uint32_t val;
     } icache_autoload_sct1_size;
-    uint32_t ibus_to_flash_start_vaddr;                         /*The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/
-    uint32_t ibus_to_flash_end_vaddr;                           /*The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/
-    uint32_t dbus_to_flash_start_vaddr;                         /*The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/
-    uint32_t dbus_to_flash_end_vaddr;                           /*The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/
+    uint32_t ibus_to_flash_start_vaddr;
+    uint32_t ibus_to_flash_end_vaddr;
+    uint32_t dbus_to_flash_start_vaddr;
+    uint32_t dbus_to_flash_end_vaddr;
     union {
         struct {
-            uint32_t dcache_acs_cnt_clr: 1;                     /*The bit is used to clear dcache counter.*/
-            uint32_t icache_acs_cnt_clr: 1;                     /*The bit is used to clear icache counter.*/
-            uint32_t reserved2:         30;
+            uint32_t dcache_acs_cnt_clr            :    1;  /*The bit is used to clear dcache counter.*/
+            uint32_t icache_acs_cnt_clr            :    1;  /*The bit is used to clear icache counter.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } cache_acs_cnt_clr;
-    uint32_t ibus_acs_miss_cnt;                                 /*The bits are used to count the number of the cache miss caused by ibus access flash/spiram.*/
-    uint32_t ibus_acs_cnt;                                      /*The bits are used to count the number of ibus access flash/spiram through icache.*/
-    uint32_t dbus_acs_flash_miss_cnt;                           /*The bits are used to count the number of the cache miss caused by dbus access flash.*/
-    uint32_t dbus_acs_spiram_miss_cnt;                          /*The bits are used to count the number of the cache miss caused by dbus access spiram.*/
-    uint32_t dbus_acs_cnt;                                      /*The bits are used to count the number of dbus access flash/spiram through dcache.*/
+    uint32_t ibus_acs_miss_cnt;
+    uint32_t ibus_acs_cnt;
+    uint32_t dbus_acs_flash_miss_cnt;
+    uint32_t dbus_acs_spiram_miss_cnt;
+    uint32_t dbus_acs_cnt;
     union {
         struct {
-            uint32_t icache_sync_op_fault:            1;        /*The bit is used to enable interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault:         1;        /*The bit is used to enable interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault:            1;        /*The bit is used to enable interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault:         1;        /*The bit is used to enable interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash:              1;        /*The bit is used to enable interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault:                 1;        /*The bit is used to enable interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc:               1;        /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_cnt_ovf:                    1;        /*The bit is used to enable interrupt by ibus counter overflow.*/
-            uint32_t dbus_cnt_ovf:                    1;        /*The bit is used to enable interrupt by dbus counter overflow.*/
-            uint32_t reserved9:                      23;
+            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash            :    1;  /*The bit is used to enable interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault               :    1;  /*The bit is used to enable interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by ibus counter overflow.*/
+            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by dbus counter overflow.*/
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } cache_ilg_int_ena;
     union {
         struct {
-            uint32_t icache_sync_op_fault:            1;        /*The bit is used to clear interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault:         1;        /*The bit is used to clear interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault:            1;        /*The bit is used to clear interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault:         1;        /*The bit is used to clear interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash:              1;        /*The bit is used to clear interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault:                 1;        /*The bit is used to clear interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc:               1;        /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_cnt_ovf:                    1;        /*The bit is used to clear interrupt by ibus counter overflow.*/
-            uint32_t dbus_cnt_ovf:                    1;        /*The bit is used to clear interrupt by dbus counter overflow.*/
-            uint32_t reserved9:                      23;
+            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash            :    1;  /*The bit is used to clear interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault               :    1;  /*The bit is used to clear interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by ibus counter overflow.*/
+            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by dbus counter overflow.*/
+            uint32_t reserved9                     :    23;
         };
         uint32_t val;
     } cache_ilg_int_clr;
     union {
         struct {
-            uint32_t icache_sync_op_fault_st:         1;        /*The bit is used to indicate interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault_st:      1;        /*The bit is used to indicate interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault_st:         1;        /*The bit is used to indicate interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault_st:      1;        /*The bit is used to indicate interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash_st:           1;        /*The bit is used to indicate interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault_st:              1;        /*The bit is used to indicate interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc_st:            1;        /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_acs_cnt_ovf_st:             1;        /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
-            uint32_t ibus_acs_miss_cnt_ovf_st:        1;        /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
-            uint32_t dbus_acs_cnt_ovf_st:             1;        /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
-            uint32_t dbus_acs_flash_miss_cnt_ovf_st:  1;        /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
-            uint32_t dbus_acs_spiram_miss_cnt_ovf_st: 1;        /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
-            uint32_t reserved12:                     20;
+            uint32_t icache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash_st         :    1;  /*The bit is used to indicate interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault_st            :    1;  /*The bit is used to indicate interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc_st          :    1;  /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
+            uint32_t ibus_acs_miss_cnt_ovf_st      :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
+            uint32_t dbus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
+            uint32_t dbus_acs_flash_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
+            uint32_t dbus_acs_spiram_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } cache_ilg_int_st;
     union {
         struct {
-            uint32_t core0_ibus_acs_msk_ic:         1;          /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_ic:              1;          /*The bit is used to enable interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject:             1;          /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dc:         1;          /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject:             1;          /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t reserved5:                    27;
+            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core0_acs_cache_int_ena;
     union {
         struct {
-            uint32_t core0_ibus_acs_msk_ic:         1;          /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_ic:              1;          /*The bit is used to clear interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject:             1;          /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dc:         1;          /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject:             1;          /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t reserved5:                    27;
+            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core0_acs_cache_int_clr;
     union {
         struct {
-            uint32_t core0_ibus_acs_msk_icache_st: 1;           /*The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_icache_st:      1;           /*The bit is used to indicate interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject_st:         1;           /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dcache_st: 1;           /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject_st:         1;           /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t reserved5:                   27;
+            uint32_t core0_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core0_acs_cache_int_st;
     union {
         struct {
-            uint32_t core1_ibus_acs_msk_ic:         1;          /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_ic:              1;          /*The bit is used to enable interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject:             1;          /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dc:         1;          /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject:             1;          /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t reserved5:                    27;
+            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core1_acs_cache_int_ena;
     union {
         struct {
-            uint32_t core1_ibus_acs_msk_ic:         1;          /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_ic:              1;          /*The bit is used to clear interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject:             1;          /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dc:         1;          /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject:             1;          /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t reserved5:                    27;
+            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core1_acs_cache_int_clr;
     union {
         struct {
-            uint32_t core1_ibus_acs_msk_icache_st: 1;           /*The bit is used to indicate interrupt by cpu access  icache while the core1_ibus is disabled or  icache is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_icache_st:      1;           /*The bit is used to indicate interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject_st:         1;           /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dcache_st: 1;           /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject_st:         1;           /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t reserved5:                   27;
+            uint32_t core1_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core1_ibus is disabled or  icache is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
         };
         uint32_t val;
     } core1_acs_cache_int_st;
     union {
         struct {
-            uint32_t core0_dbus_tag_attr: 3;                    /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core0_dbus_attr:     3;                    /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core0_dbus_world:    1;                    /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0  1: WORLD1*/
-            uint32_t reserved7:          25;
+            uint32_t core0_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } core0_dbus_reject_st;
-    uint32_t core0_dbus_reject_vaddr;                           /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/
+    uint32_t core0_dbus_reject_vaddr;
     union {
         struct {
-            uint32_t core0_ibus_tag_attr: 3;                    /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core0_ibus_attr:     3;                    /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
-            uint32_t core0_ibus_world:    1;                    /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0  1: WORLD1*/
-            uint32_t reserved7:          25;
+            uint32_t core0_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
+            uint32_t core0_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } core0_ibus_reject_st;
-    uint32_t core0_ibus_reject_vaddr;                           /*The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.*/
+    uint32_t core0_ibus_reject_vaddr;
     union {
         struct {
-            uint32_t core1_dbus_tag_attr: 3;                    /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core1_dbus_attr:     3;                    /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core1_dbus_world:    1;                    /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0  1: WORLD1*/
-            uint32_t reserved7:          25;
+            uint32_t core1_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } core1_dbus_reject_st;
-    uint32_t core1_dbus_reject_vaddr;                           /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/
+    uint32_t core1_dbus_reject_vaddr;
     union {
         struct {
-            uint32_t core1_ibus_tag_attr: 3;                    /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-            uint32_t core1_ibus_attr:     3;                    /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
-            uint32_t core1_ibus_world:    1;                    /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0  1: WORLD1*/
-            uint32_t reserved7:          25;
+            uint32_t core1_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
+            uint32_t core1_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
         };
         uint32_t val;
     } core1_ibus_reject_st;
-    uint32_t core1_ibus_reject_vaddr;                           /*The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.*/
+    uint32_t core1_ibus_reject_vaddr;
     union {
         struct {
-            uint32_t cache_mmu_fault_content:16;                /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
-            uint32_t cache_mmu_fault_code:    4;                /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default  1: cpu miss  2: preload miss  3: writeback  4: cpu miss evict recovery address  5: load miss evict recovery address  6: external dma tx  7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
-            uint32_t reserved20:             12;
+            uint32_t cache_mmu_fault_content       :    16;  /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
+            uint32_t cache_mmu_fault_code          :    4;  /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. */
+            uint32_t reserved20                    :    12;
         };
         uint32_t val;
     } cache_mmu_fault_content;
-    uint32_t cache_mmu_fault_vaddr;                             /*The bits are used to indicate the virtual address which cause mmu fault..*/
+    uint32_t cache_mmu_fault_vaddr;
     union {
         struct {
-            uint32_t cache_flash_wrap_around:   1;              /*The bit is used to enable wrap around mode when read data from flash.*/
-            uint32_t cache_sram_rd_wrap_around: 1;              /*The bit is used to enable wrap around mode when read data from spiram.*/
-            uint32_t reserved2:                30;
+            uint32_t cache_flash_wrap_around       :    1;  /*The bit is used to enable wrap around mode when read data from flash.*/
+            uint32_t cache_sram_rd_wrap_around     :    1;  /*The bit is used to enable wrap around mode when read data from spiram.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } cache_wrap_around_ctrl;
     union {
         struct {
-            uint32_t cache_mmu_mem_force_on: 1;                 /*The bit is used to enable clock gating to save power when access mmu memory  0: enable  1: disable*/
-            uint32_t cache_mmu_mem_force_pd: 1;                 /*The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power down*/
-            uint32_t cache_mmu_mem_force_pu: 1;                 /*The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power up*/
-            uint32_t reserved3:             29;
+            uint32_t cache_mmu_mem_force_on        :    1;  /*The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable*/
+            uint32_t cache_mmu_mem_force_pd        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down*/
+            uint32_t cache_mmu_mem_force_pu        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } cache_mmu_power_ctrl;
     union {
         struct {
-            uint32_t icache_state:12;                           /*The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state   0: not in idle state*/
-            uint32_t dcache_state:12;                           /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state   0: not in idle state*/
-            uint32_t reserved24:   8;
+            uint32_t icache_state                  :    12;  /*The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
+            uint32_t dcache_state                  :    12;  /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
+            uint32_t reserved24                    :    8;
         };
         uint32_t val;
     } cache_state;
     union {
         struct {
-            uint32_t record_disable_db_encrypt:   1;            /*Reserved.*/
-            uint32_t record_disable_g0cb_decrypt: 1;            /*Reserved.*/
-            uint32_t reserved2:                  30;
+            uint32_t record_disable_db_encrypt     :    1;  /*Reserved.*/
+            uint32_t record_disable_g0cb_decrypt   :    1;  /*Reserved.*/
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } cache_encrypt_decrypt_record_disable;
     union {
         struct {
-            uint32_t clk_force_on_manual_crypt: 1;              /*The bit is used to close clock gating of manual crypt clock. 1: close gating  0: open clock gating.*/
-            uint32_t clk_force_on_auto_crypt:   1;              /*The bit is used to close clock gating of automatic crypt clock. 1: close gating  0: open clock gating.*/
-            uint32_t clk_force_on_crypt:        1;              /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating  0: open clock gating.*/
-            uint32_t reserved3:                29;
+            uint32_t clk_force_on_manual_crypt     :    1;  /*The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t clk_force_on_auto_crypt       :    1;  /*The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t clk_force_on_crypt            :    1;  /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } cache_encrypt_decrypt_clk_force_on;
     union {
         struct {
-            uint32_t alloc_wb_hold_arbiter: 1;                  /*Reserved.*/
-            uint32_t reserved1:            31;
+            uint32_t alloc_wb_hold_arbiter         :    1;  /*Reserved.*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } cache_bridge_arbiter_ctrl;
@@ -548,56 +549,56 @@ typedef volatile struct {
     } cache_mmu_owner;
     union {
         struct {
-            uint32_t cache_ignore_preload_mmu_entry_fault: 1;   /*The bit is used to disable checking mmu entry fault by preload operation.*/
-            uint32_t cache_ignore_sync_mmu_entry_fault:    1;   /*The bit is used to disable checking mmu entry fault by sync operation.*/
-            uint32_t cache_trace_ena:                      1;   /*The bit is used to enable cache trace function.*/
-            uint32_t reserved3:                           29;
+            uint32_t cache_ignore_preload_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by preload operation.*/
+            uint32_t cache_ignore_sync_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by sync operation.*/
+            uint32_t cache_trace_ena               :    1;  /*The bit is used to enable cache trace function.*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } cache_conf_misc;
     union {
         struct {
-            uint32_t dcache_freeze_ena:  1;                     /*The bit is used to enable dcache freeze mode*/
-            uint32_t dcache_freeze_mode: 1;                     /*The bit is used to configure freeze mode  0:  assert busy if CPU miss 1: assert hit if CPU miss*/
-            uint32_t dcache_freeze_done: 1;                     /*The bit is used to indicate dcache freeze success*/
-            uint32_t reserved3:         29;
+            uint32_t dcache_freeze_ena             :    1;  /*The bit is used to enable dcache freeze mode*/
+            uint32_t dcache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
+            uint32_t dcache_freeze_done            :    1;  /*The bit is used to indicate dcache freeze success*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } dcache_freeze;
     union {
         struct {
-            uint32_t icache_freeze_ena:  1;                     /*The bit is used to enable icache freeze mode*/
-            uint32_t icache_freeze_mode: 1;                     /*The bit is used to configure freeze mode  0:  assert busy if CPU miss 1: assert hit if CPU miss*/
-            uint32_t icache_freeze_done: 1;                     /*The bit is used to indicate icache freeze success*/
-            uint32_t reserved3:         29;
+            uint32_t icache_freeze_ena             :    1;  /*The bit is used to enable icache freeze mode*/
+            uint32_t icache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
+            uint32_t icache_freeze_done            :    1;  /*The bit is used to indicate icache freeze success*/
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
     } icache_freeze;
     union {
         struct {
-            uint32_t icache_atomic_operate_ena: 1;              /*The bit is used to activate icache atomic operation protection. In this case  sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
-            uint32_t reserved1:                31;
+            uint32_t icache_atomic_operate_ena     :    1;  /*The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } icache_atomic_operate_ena;
     union {
         struct {
-            uint32_t dcache_atomic_operate_ena: 1;              /*The bit is used to activate dcache atomic operation protection. In this case  sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
-            uint32_t reserved1:                31;
+            uint32_t dcache_atomic_operate_ena     :    1;  /*The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } dcache_atomic_operate_ena;
     union {
         struct {
-            uint32_t cache_request_bypass: 1;                   /*The bit is used to disable request recording which could cause performance issue*/
-            uint32_t reserved1:           31;
+            uint32_t cache_request_bypass          :    1;  /*The bit is used to disable request recording which could cause performance issue*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } cache_request;
     union {
         struct {
-            uint32_t clk_en:     1;                             /*Reserved.*/
-            uint32_t reserved1: 31;
+            uint32_t clk_en                        :    1;  /*Reserved.*/
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } clock_gate;
@@ -609,21 +610,21 @@ typedef volatile struct {
     uint32_t reserved_17c;
     union {
         struct {
-            uint32_t icache_tag_object: 1;                      /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
-            uint32_t dcache_tag_object: 1;                      /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
-            uint32_t reserved2:        30;                      /*Reserved*/
+            uint32_t icache_tag_object             :    1;  /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
+            uint32_t dcache_tag_object             :    1;  /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
+            uint32_t reserved2                     :    30;  /*Reserved*/
         };
         uint32_t val;
     } cache_tag_object_ctrl;
     union {
         struct {
-            uint32_t cache_tag_way_object: 3;                   /*Set this bits to select which way of the tag-object will be accessed. 0: way0  1: way1  2: way2  3: way3  ..  7: way7.*/
-            uint32_t reserved3:           29;                   /*Reserved*/
+            uint32_t cache_tag_way_object          :    3;  /*Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.*/
+            uint32_t reserved3                     :    29;  /*Reserved*/
         };
         uint32_t val;
     } cache_tag_way_object;
-    uint32_t cache_vaddr;                                       /*Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.*/
-    uint32_t cache_tag_content;                                 /*This is a constant place where we can write data to or read data from the tag memory on the specified cache.*/
+    uint32_t cache_vaddr;
+    uint32_t cache_tag_content;
     uint32_t reserved_190;
     uint32_t reserved_194;
     uint32_t reserved_198;
@@ -781,15 +782,17 @@ typedef volatile struct {
     uint32_t reserved_3f8;
     union {
         struct {
-            uint32_t date:      28;                             /*Reserved.*/
-            uint32_t reserved28: 4;
+            uint32_t extmem_reg_date               :    28;  /*version information.*/
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } date;
 } extmem_dev_t;
-
 extern extmem_dev_t EXTMEM;
-
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_EXTMEM_STRUCT_H_ */

components/soc/esp32s3/include/soc/gdma_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_GDMA_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define GDMA_IN_CONF0_CH0_REG          (DR_REG_GDMA_BASE + 0x0)
 /* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */

components/soc/esp32s3/include/soc/gdma_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_GDMA_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     struct {

components/soc/esp32s3/include/soc/gpio_sd_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_GPIO_SD_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0)
 /* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */

components/soc/esp32s3/include/soc/gpio_sd_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_GPIO_SD_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {

components/soc/esp32s3/include/soc/gpio_sig_map.h

@@ -1,9 +1,9 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-//
+
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -11,7 +11,8 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_GPIO_SIG_MAP_H_
+#define _SOC_GPIO_SIG_MAP_H_
 
 #define SPIQ_IN_IDX                   0
 #define SPIQ_OUT_IDX                  0
@@ -443,6 +444,7 @@
 #define RX_STATUS_IDX                 248
 #define CLK_GPIO_IDX                  249
 #define NBT_BLE_IDX                   250
+#define USB_JTAG_TDO_BRIDGE_IDX       251
 #define USB_JTAG_TRST_IDX             251
 #define CORE1_GPIO_IN3_IDX            252
 #define CORE1_GPIO_OUT3_IDX           252
@@ -453,3 +455,5 @@
 #define CORE1_GPIO_IN6_IDX            255
 #define CORE1_GPIO_OUT6_IDX           255
 #define SIG_GPIO_OUT_IDX              256
+#define GPIO_MAP_DATE_IDX             0x1907040
+#endif  /* _SOC_GPIO_SIG_MAP_H_ */

components/soc/esp32s3/include/soc/gpio_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,179 +11,180 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_GPIO_STRUCT_H_
+#define _SOC_GPIO_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
-    uint32_t bt_select;                               /**/
-    uint32_t out;                                     /**/
-    uint32_t out_w1ts;                                /**/
-    uint32_t out_w1tc;                                /**/
+    uint32_t bt_select;
+    uint32_t out;
+    uint32_t out_w1ts;
+    uint32_t out_w1tc;
     union {
         struct {
-            uint32_t data:      22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } out1;
     union {
         struct {
-            uint32_t data:      22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } out1_w1ts;
     union {
         struct {
-            uint32_t data:      22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } out1_w1tc;
     union {
         struct {
-            uint32_t sel:        8;
-            uint32_t reserved8: 24;
+            uint32_t sel                           :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } sdio_select;
-    uint32_t enable;                                  /**/
-    uint32_t enable_w1ts;                             /**/
-    uint32_t enable_w1tc;                             /**/
+    uint32_t enable;
+    uint32_t enable_w1ts;
+    uint32_t enable_w1tc;
     union {
         struct {
-            uint32_t data:       22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } enable1;
     union {
         struct {
-            uint32_t data:       22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } enable1_w1ts;
     union {
         struct {
-            uint32_t data:       22;
-            uint32_t reserved22: 10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } enable1_w1tc;
     union {
         struct {
-            uint32_t strapping: 16;
-            uint32_t reserved16: 16;
+            uint32_t strapping                     :    16;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } strap;
-    uint32_t in;                                      /**/
+    uint32_t in;
     union {
         struct {
-            uint32_t data:        22;
-            uint32_t reserved22:  10;
+            uint32_t data                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } in1;
-    uint32_t status;                                  /**/
-    uint32_t status_w1ts;                             /**/
-    uint32_t status_w1tc;                             /**/
+    uint32_t status;
+    uint32_t status_w1ts;
+    uint32_t status_w1tc;
     union {
         struct {
-            uint32_t intr_st:         22;
-            uint32_t reserved22:      10;
+            uint32_t intr_st                       :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } status1;
     union {
         struct {
-            uint32_t intr_st:         22;
-            uint32_t reserved22:      10;
+            uint32_t intr_st                       :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } status1_w1ts;
     union {
         struct {
-            uint32_t intr_st:         22;
-            uint32_t reserved22:      10;
+            uint32_t intr_st                       :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } status1_w1tc;
-    uint32_t pcpu_int;                                /**/
-    uint32_t pcpu_nmi_int;                            /**/
-    uint32_t cpusdio_int;                             /**/
+    uint32_t pcpu_int;
+    uint32_t pcpu_nmi_int;
+    uint32_t cpusdio_int;
     union {
         struct {
-            uint32_t intr:      22;
-            uint32_t reserved22: 10;
+            uint32_t intr                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } pcpu_int1;
     union {
         struct {
-            uint32_t intr:          22;
-            uint32_t reserved22:    10;
+            uint32_t intr                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } pcpu_nmi_int1;
     union {
         struct {
-            uint32_t intr:      22;
-            uint32_t reserved22: 10;
+            uint32_t intr                          :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } cpusdio_int1;
     union {
         struct {
-            uint32_t sync2_bypass:       2;
-            uint32_t pad_driver:         1;
-            uint32_t sync1_bypass:       2;
-            uint32_t reserved5:          2;
-            uint32_t int_type:           3;
-            uint32_t wakeup_enable:      1;
-            uint32_t config:             2;
-            uint32_t int_ena:            5;
-            uint32_t reserved18:        14;
+            uint32_t sync2_bypass                  :    2;
+            uint32_t pad_driver                    :    1;
+            uint32_t sync1_bypass                  :    2;
+            uint32_t reserved5                     :    2;
+            uint32_t int_type                      :    3;
+            uint32_t wakeup_enable                 :    1;
+            uint32_t config                        :    2;
+            uint32_t int_ena                       :    5;
+            uint32_t reserved18                    :    14;
         };
         uint32_t val;
     } pin[54];
-    uint32_t status_next;                             /**/
+    uint32_t status_next;
     union {
         struct {
-            uint32_t intr_st_next:         22;
-            uint32_t reserved22:           10;
+            uint32_t intr_st_next                  :    22;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } status_next1;
     union {
         struct {
-            uint32_t func_sel:         6;
-            uint32_t sig_in_inv:       1;
-            uint32_t sig_in_sel:       1;
-            uint32_t reserved8:       24;
+            uint32_t func_sel                      :    6;
+            uint32_t sig_in_inv                    :    1;
+            uint32_t sig_in_sel                    :    1;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } func_in_sel_cfg[256];
     union {
         struct {
-            uint32_t func_sel:          9;
-            uint32_t inv_sel:           1;
-            uint32_t oen_sel:           1;
-            uint32_t oen_inv_sel:       1;
-            uint32_t reserved12:       20;
+            uint32_t func_sel                      :    9;
+            uint32_t inv_sel                       :    1;
+            uint32_t oen_sel                       :    1;
+            uint32_t oen_inv_sel                   :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } func_out_sel_cfg[54];
     union {
         struct {
-            uint32_t clk_en:     1;
-            uint32_t reserved1: 31;
+            uint32_t clk_en                        :    1;
+            uint32_t reserved1                     :    31;
         };
         uint32_t val;
     } clock_gate;
@@ -240,15 +241,17 @@ typedef volatile struct {
     uint32_t reserved_6f8;
     union {
         struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
+            uint32_t date                          :    28;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } date;
 } gpio_dev_t;
-
 extern gpio_dev_t GPIO;
-
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_GPIO_STRUCT_H_ */

components/soc/esp32s3/include/soc/hinf_struct.h

@@ -13,6 +13,7 @@
 // limitations under the License.
 #pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/host_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,1788 +11,1794 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_HOST_REG_H_
+#define _SOC_HOST_REG_H_
 
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "soc.h"
-
-#define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
+#define HOST_SLCHOST_FUNC2_2_REG          (DR_REG_SLCHOST_BASE + 0x20)
 /* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define HOST_SLC_FUNC1_MDSTAT (BIT(0))
-#define HOST_SLC_FUNC1_MDSTAT_M (BIT(0))
-#define HOST_SLC_FUNC1_MDSTAT_V 0x1
-#define HOST_SLC_FUNC1_MDSTAT_S 0
+/*description: .*/
+#define HOST_SLC_FUNC1_MDSTAT    (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_M  (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_V  0x1
+#define HOST_SLC_FUNC1_MDSTAT_S  0
 
-#define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
+#define HOST_SLCHOST_GPIO_STATUS0_REG          (DR_REG_SLCHOST_BASE + 0x34)
 /* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF
-#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V) << (HOST_GPIO_SDIO_INT0_S))
-#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF
-#define HOST_GPIO_SDIO_INT0_S 0
+/*description: .*/
+#define HOST_GPIO_SDIO_INT0    0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_M  ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S))
+#define HOST_GPIO_SDIO_INT0_V  0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_S  0
 
-#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
+#define HOST_SLCHOST_GPIO_STATUS1_REG          (DR_REG_SLCHOST_BASE + 0x38)
 /* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT1 0x003FFFFF
-#define HOST_GPIO_SDIO_INT1_M ((HOST_GPIO_SDIO_INT1_V) << (HOST_GPIO_SDIO_INT1_S))
-#define HOST_GPIO_SDIO_INT1_V 0x3FFFFF
-#define HOST_GPIO_SDIO_INT1_S 0
+/*description: .*/
+#define HOST_GPIO_SDIO_INT1    0x003FFFFF
+#define HOST_GPIO_SDIO_INT1_M  ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S))
+#define HOST_GPIO_SDIO_INT1_V  0x3FFFFF
+#define HOST_GPIO_SDIO_INT1_S  0
 
-#define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C)
+#define HOST_SLCHOST_GPIO_IN0_REG          (DR_REG_SLCHOST_BASE + 0x3C)
 /* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_IN0 0xFFFFFFFF
-#define HOST_GPIO_SDIO_IN0_M ((HOST_GPIO_SDIO_IN0_V) << (HOST_GPIO_SDIO_IN0_S))
-#define HOST_GPIO_SDIO_IN0_V 0xFFFFFFFF
-#define HOST_GPIO_SDIO_IN0_S 0
+/*description: .*/
+#define HOST_GPIO_SDIO_IN0    0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_M  ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S))
+#define HOST_GPIO_SDIO_IN0_V  0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_S  0
 
-#define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
+#define HOST_SLCHOST_GPIO_IN1_REG          (DR_REG_SLCHOST_BASE + 0x40)
 /* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_IN1 0x003FFFFF
-#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V) << (HOST_GPIO_SDIO_IN1_S))
-#define HOST_GPIO_SDIO_IN1_V 0x3FFFFF
-#define HOST_GPIO_SDIO_IN1_S 0
+/*description: .*/
+#define HOST_GPIO_SDIO_IN1    0x003FFFFF
+#define HOST_GPIO_SDIO_IN1_M  ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S))
+#define HOST_GPIO_SDIO_IN1_V  0x3FFFFF
+#define HOST_GPIO_SDIO_IN1_S  0
 
-#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
+#define HOST_SLC0HOST_TOKEN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x44)
 /* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_EOF 0x0000000F
-#define HOST_SLC0_RX_PF_EOF_M ((HOST_SLC0_RX_PF_EOF_V) << (HOST_SLC0_RX_PF_EOF_S))
-#define HOST_SLC0_RX_PF_EOF_V 0xF
-#define HOST_SLC0_RX_PF_EOF_S 28
+/*description: .*/
+#define HOST_SLC0_RX_PF_EOF    0x0000000F
+#define HOST_SLC0_RX_PF_EOF_M  ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S))
+#define HOST_SLC0_RX_PF_EOF_V  0xF
+#define HOST_SLC0_RX_PF_EOF_S  28
 /* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_TOKEN1 0x00000FFF
-#define HOST_HOSTSLC0_TOKEN1_M ((HOST_HOSTSLC0_TOKEN1_V) << (HOST_HOSTSLC0_TOKEN1_S))
-#define HOST_HOSTSLC0_TOKEN1_V 0xFFF
-#define HOST_HOSTSLC0_TOKEN1_S 16
+/*description: .*/
+#define HOST_HOSTSLC0_TOKEN1    0x00000FFF
+#define HOST_HOSTSLC0_TOKEN1_M  ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S))
+#define HOST_HOSTSLC0_TOKEN1_V  0xFFF
+#define HOST_HOSTSLC0_TOKEN1_S  16
 /* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID (BIT(12))
-#define HOST_SLC0_RX_PF_VALID_M (BIT(12))
-#define HOST_SLC0_RX_PF_VALID_V 0x1
-#define HOST_SLC0_RX_PF_VALID_S 12
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID    (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_M  (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_V  0x1
+#define HOST_SLC0_RX_PF_VALID_S  12
 /* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0 0x00000FFF
-#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V) << (HOST_SLC0_TOKEN0_S))
-#define HOST_SLC0_TOKEN0_V 0xFFF
-#define HOST_SLC0_TOKEN0_S 0
+/*description: .*/
+#define HOST_SLC0_TOKEN0    0x00000FFF
+#define HOST_SLC0_TOKEN0_M  ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S))
+#define HOST_SLC0_TOKEN0_V  0xFFF
+#define HOST_SLC0_TOKEN0_S  0
 
-#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
+#define HOST_SLC0_HOST_PF_REG          (DR_REG_SLCHOST_BASE + 0x48)
 /* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define HOST_SLC0_PF_DATA 0xFFFFFFFF
-#define HOST_SLC0_PF_DATA_M ((HOST_SLC0_PF_DATA_V) << (HOST_SLC0_PF_DATA_S))
-#define HOST_SLC0_PF_DATA_V 0xFFFFFFFF
-#define HOST_SLC0_PF_DATA_S 0
+/*description: .*/
+#define HOST_SLC0_PF_DATA    0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_M  ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S))
+#define HOST_SLC0_PF_DATA_V  0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_S  0
 
-#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
+#define HOST_SLC0HOST_INT_RAW_REG          (DR_REG_SLCHOST_BASE + 0x50)
 /* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_RAW (BIT(25))
-#define HOST_GPIO_SDIO_INT_RAW_M (BIT(25))
-#define HOST_GPIO_SDIO_INT_RAW_V 0x1
-#define HOST_GPIO_SDIO_INT_RAW_S 25
+/*description: .*/
+#define HOST_GPIO_SDIO_INT_RAW    (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_V  0x1
+#define HOST_GPIO_SDIO_INT_RAW_S  25
 /* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24
+/*description: .*/
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW    (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
 /* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23
+/*description: .*/
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW    (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
 /* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_RAW_M (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_RAW_V 0x1
-#define HOST_SLC0_EXT_BIT3_INT_RAW_S 22
+/*description: .*/
+#define HOST_SLC0_EXT_BIT3_INT_RAW    (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_RAW_S  22
 /* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_RAW_M (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_RAW_V 0x1
-#define HOST_SLC0_EXT_BIT2_INT_RAW_S 21
+/*description: .*/
+#define HOST_SLC0_EXT_BIT2_INT_RAW    (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_RAW_S  21
 /* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_RAW_M (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_RAW_V 0x1
-#define HOST_SLC0_EXT_BIT1_INT_RAW_S 20
+/*description: .*/
+#define HOST_SLC0_EXT_BIT1_INT_RAW    (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_RAW_S  20
 /* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1
-#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19
+/*description: .*/
+#define HOST_SLC0_EXT_BIT0_INT_RAW    (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_RAW_S  19
 /* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_M (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x1
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_S 18
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID_INT_RAW    (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_S  18
 /* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_RAW (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_RAW_M (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_RAW_V 0x1
-#define HOST_SLC0_TX_OVF_INT_RAW_S 17
+/*description: .*/
+#define HOST_SLC0_TX_OVF_INT_RAW    (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_V  0x1
+#define HOST_SLC0_TX_OVF_INT_RAW_S  17
 /* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_RAW (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_RAW_M (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_RAW_V 0x1
-#define HOST_SLC0_RX_UDF_INT_RAW_S 16
+/*description: .*/
+#define HOST_SLC0_RX_UDF_INT_RAW    (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_V  0x1
+#define HOST_SLC0_RX_UDF_INT_RAW_S  16
 /* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1
-#define HOST_SLC0HOST_TX_START_INT_RAW_S 15
+/*description: .*/
+#define HOST_SLC0HOST_TX_START_INT_RAW    (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_RAW_S  15
 /* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_RAW (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_RAW_M (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_RAW_V 0x1
-#define HOST_SLC0HOST_RX_START_INT_RAW_S 14
+/*description: .*/
+#define HOST_SLC0HOST_RX_START_INT_RAW    (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_RAW_S  14
 /* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_M (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x1
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_S 13
+/*description: .*/
+#define HOST_SLC0HOST_RX_EOF_INT_RAW    (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_S  13
 /* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_M (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x1
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_S 12
+/*description: .*/
+#define HOST_SLC0HOST_RX_SOF_INT_RAW    (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_S  12
 /* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11
+/*description: .*/
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW    (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
 /* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10
+/*description: .*/
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW    (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
 /* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9
+/*description: .*/
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
 /* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8
+/*description: .*/
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
 /* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW    (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
 /* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW    (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
 /* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW    (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
 /* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW    (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
 /* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW    (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
 /* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW    (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
 /* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW    (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
 /* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW    (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
 
-#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
+#define HOST_SLC0HOST_INT_ST_REG          (DR_REG_SLCHOST_BASE + 0x58)
 /* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ST (BIT(25))
-#define HOST_GPIO_SDIO_INT_ST_M (BIT(25))
-#define HOST_GPIO_SDIO_INT_ST_V 0x1
-#define HOST_GPIO_SDIO_INT_ST_S 25
+/*description: .*/
+#define HOST_GPIO_SDIO_INT_ST    (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_V  0x1
+#define HOST_GPIO_SDIO_INT_ST_S  25
 /* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24
+/*description: .*/
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST    (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
 /* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23
+/*description: .*/
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST    (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
 /* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ST (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ST_M (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ST_V 0x1
-#define HOST_SLC0_EXT_BIT3_INT_ST_S 22
+/*description: .*/
+#define HOST_SLC0_EXT_BIT3_INT_ST    (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ST_S  22
 /* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1
-#define HOST_SLC0_EXT_BIT2_INT_ST_S 21
+/*description: .*/
+#define HOST_SLC0_EXT_BIT2_INT_ST    (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ST_S  21
 /* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ST_M (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ST_V 0x1
-#define HOST_SLC0_EXT_BIT1_INT_ST_S 20
+/*description: .*/
+#define HOST_SLC0_EXT_BIT1_INT_ST    (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ST_S  20
 /* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ST (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ST_M (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ST_V 0x1
-#define HOST_SLC0_EXT_BIT0_INT_ST_S 19
+/*description: .*/
+#define HOST_SLC0_EXT_BIT0_INT_ST    (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ST_S  19
 /* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ST_M (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ST_V 0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ST_S 18
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID_INT_ST    (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ST_S  18
 /* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ST (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ST_V 0x1
-#define HOST_SLC0_TX_OVF_INT_ST_S 17
+/*description: .*/
+#define HOST_SLC0_TX_OVF_INT_ST    (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ST_S  17
 /* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ST (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ST_M (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ST_V 0x1
-#define HOST_SLC0_RX_UDF_INT_ST_S 16
+/*description: .*/
+#define HOST_SLC0_RX_UDF_INT_ST    (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ST_S  16
 /* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ST (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ST_M (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ST_V 0x1
-#define HOST_SLC0HOST_TX_START_INT_ST_S 15
+/*description: .*/
+#define HOST_SLC0HOST_TX_START_INT_ST    (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ST_S  15
 /* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ST (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ST_M (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ST_V 0x1
-#define HOST_SLC0HOST_RX_START_INT_ST_S 14
+/*description: .*/
+#define HOST_SLC0HOST_RX_START_INT_ST    (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ST_S  14
 /* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13
+/*description: .*/
+#define HOST_SLC0HOST_RX_EOF_INT_ST    (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ST_S  13
 /* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ST_M (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ST_V 0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ST_S 12
+/*description: .*/
+#define HOST_SLC0HOST_RX_SOF_INT_ST    (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ST_S  12
 /* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11
+/*description: .*/
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST    (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
 /* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10
+/*description: .*/
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST    (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
 /* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9
+/*description: .*/
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST    (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
 /* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8
+/*description: .*/
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST    (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
 /* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_M (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_S 7
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT7_INT_ST    (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_S  7
 /* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_M (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_S 6
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT6_INT_ST    (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_S  6
 /* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT5_INT_ST    (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_S  5
 /* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_M (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_S 4
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT4_INT_ST    (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_S  4
 /* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_M (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_S 3
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT3_INT_ST    (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_S  3
 /* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_M (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_S 2
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT2_INT_ST    (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_S  2
 /* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT1_INT_ST    (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_S  1
 /* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_M (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_S 0
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT0_INT_ST    (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_S  0
 
-#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
+#define HOST_SLCHOST_PKT_LEN_REG          (DR_REG_SLCHOST_BASE + 0x60)
 /* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN_CHECK 0x00000FFF
-#define HOST_HOSTSLC0_LEN_CHECK_M ((HOST_HOSTSLC0_LEN_CHECK_V) << (HOST_HOSTSLC0_LEN_CHECK_S))
-#define HOST_HOSTSLC0_LEN_CHECK_V 0xFFF
-#define HOST_HOSTSLC0_LEN_CHECK_S 20
+/*description: .*/
+#define HOST_HOSTSLC0_LEN_CHECK    0x00000FFF
+#define HOST_HOSTSLC0_LEN_CHECK_M  ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S))
+#define HOST_HOSTSLC0_LEN_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN_CHECK_S  20
 /* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN 0x000FFFFF
-#define HOST_HOSTSLC0_LEN_M ((HOST_HOSTSLC0_LEN_V) << (HOST_HOSTSLC0_LEN_S))
-#define HOST_HOSTSLC0_LEN_V 0xFFFFF
-#define HOST_HOSTSLC0_LEN_S 0
+/*description: .*/
+#define HOST_HOSTSLC0_LEN    0x000FFFFF
+#define HOST_HOSTSLC0_LEN_M  ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S))
+#define HOST_HOSTSLC0_LEN_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN_S  0
 
-#define HOST_SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
+#define HOST_SLCHOST_STATE_W0_REG          (DR_REG_SLCHOST_BASE + 0x64)
 /* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE3 0x000000FF
-#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V) << (HOST_SLCHOST_STATE3_S))
-#define HOST_SLCHOST_STATE3_V 0xFF
-#define HOST_SLCHOST_STATE3_S 24
+/*description: .*/
+#define HOST_SLCHOST_STATE3    0x000000FF
+#define HOST_SLCHOST_STATE3_M  ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S))
+#define HOST_SLCHOST_STATE3_V  0xFF
+#define HOST_SLCHOST_STATE3_S  24
 /* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE2 0x000000FF
-#define HOST_SLCHOST_STATE2_M ((HOST_SLCHOST_STATE2_V) << (HOST_SLCHOST_STATE2_S))
-#define HOST_SLCHOST_STATE2_V 0xFF
-#define HOST_SLCHOST_STATE2_S 16
+/*description: .*/
+#define HOST_SLCHOST_STATE2    0x000000FF
+#define HOST_SLCHOST_STATE2_M  ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S))
+#define HOST_SLCHOST_STATE2_V  0xFF
+#define HOST_SLCHOST_STATE2_S  16
 /* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE1 0x000000FF
-#define HOST_SLCHOST_STATE1_M ((HOST_SLCHOST_STATE1_V) << (HOST_SLCHOST_STATE1_S))
-#define HOST_SLCHOST_STATE1_V 0xFF
-#define HOST_SLCHOST_STATE1_S 8
+/*description: .*/
+#define HOST_SLCHOST_STATE1    0x000000FF
+#define HOST_SLCHOST_STATE1_M  ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S))
+#define HOST_SLCHOST_STATE1_V  0xFF
+#define HOST_SLCHOST_STATE1_S  8
 /* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE0 0x000000FF
-#define HOST_SLCHOST_STATE0_M ((HOST_SLCHOST_STATE0_V) << (HOST_SLCHOST_STATE0_S))
-#define HOST_SLCHOST_STATE0_V 0xFF
-#define HOST_SLCHOST_STATE0_S 0
+/*description: .*/
+#define HOST_SLCHOST_STATE0    0x000000FF
+#define HOST_SLCHOST_STATE0_M  ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S))
+#define HOST_SLCHOST_STATE0_V  0xFF
+#define HOST_SLCHOST_STATE0_S  0
 
-#define HOST_SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
+#define HOST_SLCHOST_STATE_W1_REG          (DR_REG_SLCHOST_BASE + 0x68)
 /* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE7 0x000000FF
-#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V) << (HOST_SLCHOST_STATE7_S))
-#define HOST_SLCHOST_STATE7_V 0xFF
-#define HOST_SLCHOST_STATE7_S 24
+/*description: .*/
+#define HOST_SLCHOST_STATE7    0x000000FF
+#define HOST_SLCHOST_STATE7_M  ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S))
+#define HOST_SLCHOST_STATE7_V  0xFF
+#define HOST_SLCHOST_STATE7_S  24
 /* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE6 0x000000FF
-#define HOST_SLCHOST_STATE6_M ((HOST_SLCHOST_STATE6_V) << (HOST_SLCHOST_STATE6_S))
-#define HOST_SLCHOST_STATE6_V 0xFF
-#define HOST_SLCHOST_STATE6_S 16
+/*description: .*/
+#define HOST_SLCHOST_STATE6    0x000000FF
+#define HOST_SLCHOST_STATE6_M  ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S))
+#define HOST_SLCHOST_STATE6_V  0xFF
+#define HOST_SLCHOST_STATE6_S  16
 /* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE5 0x000000FF
-#define HOST_SLCHOST_STATE5_M ((HOST_SLCHOST_STATE5_V) << (HOST_SLCHOST_STATE5_S))
-#define HOST_SLCHOST_STATE5_V 0xFF
-#define HOST_SLCHOST_STATE5_S 8
+/*description: .*/
+#define HOST_SLCHOST_STATE5    0x000000FF
+#define HOST_SLCHOST_STATE5_M  ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S))
+#define HOST_SLCHOST_STATE5_V  0xFF
+#define HOST_SLCHOST_STATE5_S  8
 /* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE4 0x000000FF
-#define HOST_SLCHOST_STATE4_M ((HOST_SLCHOST_STATE4_V) << (HOST_SLCHOST_STATE4_S))
-#define HOST_SLCHOST_STATE4_V 0xFF
-#define HOST_SLCHOST_STATE4_S 0
+/*description: .*/
+#define HOST_SLCHOST_STATE4    0x000000FF
+#define HOST_SLCHOST_STATE4_M  ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S))
+#define HOST_SLCHOST_STATE4_V  0xFF
+#define HOST_SLCHOST_STATE4_S  0
 
-#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C)
+#define HOST_SLCHOST_CONF_W0_REG          (DR_REG_SLCHOST_BASE + 0x6C)
 /* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF3 0x000000FF
-#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V) << (HOST_SLCHOST_CONF3_S))
-#define HOST_SLCHOST_CONF3_V 0xFF
-#define HOST_SLCHOST_CONF3_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF3    0x000000FF
+#define HOST_SLCHOST_CONF3_M  ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S))
+#define HOST_SLCHOST_CONF3_V  0xFF
+#define HOST_SLCHOST_CONF3_S  24
 /* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF2 0x000000FF
-#define HOST_SLCHOST_CONF2_M ((HOST_SLCHOST_CONF2_V) << (HOST_SLCHOST_CONF2_S))
-#define HOST_SLCHOST_CONF2_V 0xFF
-#define HOST_SLCHOST_CONF2_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF2    0x000000FF
+#define HOST_SLCHOST_CONF2_M  ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S))
+#define HOST_SLCHOST_CONF2_V  0xFF
+#define HOST_SLCHOST_CONF2_S  16
 /* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF1 0x000000FF
-#define HOST_SLCHOST_CONF1_M ((HOST_SLCHOST_CONF1_V) << (HOST_SLCHOST_CONF1_S))
-#define HOST_SLCHOST_CONF1_V 0xFF
-#define HOST_SLCHOST_CONF1_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF1    0x000000FF
+#define HOST_SLCHOST_CONF1_M  ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S))
+#define HOST_SLCHOST_CONF1_V  0xFF
+#define HOST_SLCHOST_CONF1_S  8
 /* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF0 0x000000FF
-#define HOST_SLCHOST_CONF0_M ((HOST_SLCHOST_CONF0_V) << (HOST_SLCHOST_CONF0_S))
-#define HOST_SLCHOST_CONF0_V 0xFF
-#define HOST_SLCHOST_CONF0_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF0    0x000000FF
+#define HOST_SLCHOST_CONF0_M  ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S))
+#define HOST_SLCHOST_CONF0_V  0xFF
+#define HOST_SLCHOST_CONF0_S  0
 
-#define HOST_SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
+#define HOST_SLCHOST_CONF_W1_REG          (DR_REG_SLCHOST_BASE + 0x70)
 /* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF7 0x000000FF
-#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V) << (HOST_SLCHOST_CONF7_S))
-#define HOST_SLCHOST_CONF7_V 0xFF
-#define HOST_SLCHOST_CONF7_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF7    0x000000FF
+#define HOST_SLCHOST_CONF7_M  ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S))
+#define HOST_SLCHOST_CONF7_V  0xFF
+#define HOST_SLCHOST_CONF7_S  24
 /* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF6 0x000000FF
-#define HOST_SLCHOST_CONF6_M ((HOST_SLCHOST_CONF6_V) << (HOST_SLCHOST_CONF6_S))
-#define HOST_SLCHOST_CONF6_V 0xFF
-#define HOST_SLCHOST_CONF6_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF6    0x000000FF
+#define HOST_SLCHOST_CONF6_M  ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S))
+#define HOST_SLCHOST_CONF6_V  0xFF
+#define HOST_SLCHOST_CONF6_S  16
 /* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF5 0x000000FF
-#define HOST_SLCHOST_CONF5_M ((HOST_SLCHOST_CONF5_V) << (HOST_SLCHOST_CONF5_S))
-#define HOST_SLCHOST_CONF5_V 0xFF
-#define HOST_SLCHOST_CONF5_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF5    0x000000FF
+#define HOST_SLCHOST_CONF5_M  ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S))
+#define HOST_SLCHOST_CONF5_V  0xFF
+#define HOST_SLCHOST_CONF5_S  8
 /* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF4 0x000000FF
-#define HOST_SLCHOST_CONF4_M ((HOST_SLCHOST_CONF4_V) << (HOST_SLCHOST_CONF4_S))
-#define HOST_SLCHOST_CONF4_V 0xFF
-#define HOST_SLCHOST_CONF4_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF4    0x000000FF
+#define HOST_SLCHOST_CONF4_M  ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S))
+#define HOST_SLCHOST_CONF4_V  0xFF
+#define HOST_SLCHOST_CONF4_S  0
 
-#define HOST_SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
+#define HOST_SLCHOST_CONF_W2_REG          (DR_REG_SLCHOST_BASE + 0x74)
 /* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF11 0x000000FF
-#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V) << (HOST_SLCHOST_CONF11_S))
-#define HOST_SLCHOST_CONF11_V 0xFF
-#define HOST_SLCHOST_CONF11_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF11    0x000000FF
+#define HOST_SLCHOST_CONF11_M  ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S))
+#define HOST_SLCHOST_CONF11_V  0xFF
+#define HOST_SLCHOST_CONF11_S  24
 /* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF10 0x000000FF
-#define HOST_SLCHOST_CONF10_M ((HOST_SLCHOST_CONF10_V) << (HOST_SLCHOST_CONF10_S))
-#define HOST_SLCHOST_CONF10_V 0xFF
-#define HOST_SLCHOST_CONF10_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF10    0x000000FF
+#define HOST_SLCHOST_CONF10_M  ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S))
+#define HOST_SLCHOST_CONF10_V  0xFF
+#define HOST_SLCHOST_CONF10_S  16
 /* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF9 0x000000FF
-#define HOST_SLCHOST_CONF9_M ((HOST_SLCHOST_CONF9_V) << (HOST_SLCHOST_CONF9_S))
-#define HOST_SLCHOST_CONF9_V 0xFF
-#define HOST_SLCHOST_CONF9_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF9    0x000000FF
+#define HOST_SLCHOST_CONF9_M  ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S))
+#define HOST_SLCHOST_CONF9_V  0xFF
+#define HOST_SLCHOST_CONF9_S  8
 /* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF8 0x000000FF
-#define HOST_SLCHOST_CONF8_M ((HOST_SLCHOST_CONF8_V) << (HOST_SLCHOST_CONF8_S))
-#define HOST_SLCHOST_CONF8_V 0xFF
-#define HOST_SLCHOST_CONF8_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF8    0x000000FF
+#define HOST_SLCHOST_CONF8_M  ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S))
+#define HOST_SLCHOST_CONF8_V  0xFF
+#define HOST_SLCHOST_CONF8_S  0
 
-#define HOST_SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
+#define HOST_SLCHOST_CONF_W3_REG          (DR_REG_SLCHOST_BASE + 0x78)
 /* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF15 0x000000FF
-#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V) << (HOST_SLCHOST_CONF15_S))
-#define HOST_SLCHOST_CONF15_V 0xFF
-#define HOST_SLCHOST_CONF15_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF15    0x000000FF
+#define HOST_SLCHOST_CONF15_M  ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S))
+#define HOST_SLCHOST_CONF15_V  0xFF
+#define HOST_SLCHOST_CONF15_S  24
 /* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF14 0x000000FF
-#define HOST_SLCHOST_CONF14_M ((HOST_SLCHOST_CONF14_V) << (HOST_SLCHOST_CONF14_S))
-#define HOST_SLCHOST_CONF14_V 0xFF
-#define HOST_SLCHOST_CONF14_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF14    0x000000FF
+#define HOST_SLCHOST_CONF14_M  ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S))
+#define HOST_SLCHOST_CONF14_V  0xFF
+#define HOST_SLCHOST_CONF14_S  16
 /* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF13 0x000000FF
-#define HOST_SLCHOST_CONF13_M ((HOST_SLCHOST_CONF13_V) << (HOST_SLCHOST_CONF13_S))
-#define HOST_SLCHOST_CONF13_V 0xFF
-#define HOST_SLCHOST_CONF13_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF13    0x000000FF
+#define HOST_SLCHOST_CONF13_M  ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S))
+#define HOST_SLCHOST_CONF13_V  0xFF
+#define HOST_SLCHOST_CONF13_S  8
 /* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF12 0x000000FF
-#define HOST_SLCHOST_CONF12_M ((HOST_SLCHOST_CONF12_V) << (HOST_SLCHOST_CONF12_S))
-#define HOST_SLCHOST_CONF12_V 0xFF
-#define HOST_SLCHOST_CONF12_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF12    0x000000FF
+#define HOST_SLCHOST_CONF12_M  ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S))
+#define HOST_SLCHOST_CONF12_V  0xFF
+#define HOST_SLCHOST_CONF12_S  0
 
-#define HOST_SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7C)
+#define HOST_SLCHOST_CONF_W4_REG          (DR_REG_SLCHOST_BASE + 0x7C)
 /* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: Interrupt to target CPU*/
-#define HOST_SLCHOST_CONF19 0x000000FF
-#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V) << (HOST_SLCHOST_CONF19_S))
-#define HOST_SLCHOST_CONF19_V 0xFF
-#define HOST_SLCHOST_CONF19_S 24
+/*description: Interrupt to target CPU.*/
+#define HOST_SLCHOST_CONF19    0x000000FF
+#define HOST_SLCHOST_CONF19_M  ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S))
+#define HOST_SLCHOST_CONF19_V  0xFF
+#define HOST_SLCHOST_CONF19_S  24
 /* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF18 0x000000FF
-#define HOST_SLCHOST_CONF18_M ((HOST_SLCHOST_CONF18_V) << (HOST_SLCHOST_CONF18_S))
-#define HOST_SLCHOST_CONF18_V 0xFF
-#define HOST_SLCHOST_CONF18_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF18    0x000000FF
+#define HOST_SLCHOST_CONF18_M  ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S))
+#define HOST_SLCHOST_CONF18_V  0xFF
+#define HOST_SLCHOST_CONF18_S  16
 /* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: SLC timeout enable*/
-#define HOST_SLCHOST_CONF17 0x000000FF
-#define HOST_SLCHOST_CONF17_M ((HOST_SLCHOST_CONF17_V) << (HOST_SLCHOST_CONF17_S))
-#define HOST_SLCHOST_CONF17_V 0xFF
-#define HOST_SLCHOST_CONF17_S 8
-/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */
-/*description: SLC timeout value*/
-#define HOST_SLCHOST_CONF16 0x000000FF
-#define HOST_SLCHOST_CONF16_M ((HOST_SLCHOST_CONF16_V) << (HOST_SLCHOST_CONF16_S))
-#define HOST_SLCHOST_CONF16_V 0xFF
-#define HOST_SLCHOST_CONF16_S 0
+/*description: SLC timeout enable.*/
+#define HOST_SLCHOST_CONF17    0x000000FF
+#define HOST_SLCHOST_CONF17_M  ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S))
+#define HOST_SLCHOST_CONF17_V  0xFF
+#define HOST_SLCHOST_CONF17_S  8
+/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hff ; */
+/*description: SLC timeout value.*/
+#define HOST_SLCHOST_CONF16    0x000000FF
+#define HOST_SLCHOST_CONF16_M  ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S))
+#define HOST_SLCHOST_CONF16_V  0xFF
+#define HOST_SLCHOST_CONF16_S  0
 
-#define HOST_SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
+#define HOST_SLCHOST_CONF_W5_REG          (DR_REG_SLCHOST_BASE + 0x80)
 /* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF23 0x000000FF
-#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V) << (HOST_SLCHOST_CONF23_S))
-#define HOST_SLCHOST_CONF23_V 0xFF
-#define HOST_SLCHOST_CONF23_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF23    0x000000FF
+#define HOST_SLCHOST_CONF23_M  ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S))
+#define HOST_SLCHOST_CONF23_V  0xFF
+#define HOST_SLCHOST_CONF23_S  24
 /* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF22 0x000000FF
-#define HOST_SLCHOST_CONF22_M ((HOST_SLCHOST_CONF22_V) << (HOST_SLCHOST_CONF22_S))
-#define HOST_SLCHOST_CONF22_V 0xFF
-#define HOST_SLCHOST_CONF22_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF22    0x000000FF
+#define HOST_SLCHOST_CONF22_M  ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S))
+#define HOST_SLCHOST_CONF22_V  0xFF
+#define HOST_SLCHOST_CONF22_S  16
 /* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF21 0x000000FF
-#define HOST_SLCHOST_CONF21_M ((HOST_SLCHOST_CONF21_V) << (HOST_SLCHOST_CONF21_S))
-#define HOST_SLCHOST_CONF21_V 0xFF
-#define HOST_SLCHOST_CONF21_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF21    0x000000FF
+#define HOST_SLCHOST_CONF21_M  ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S))
+#define HOST_SLCHOST_CONF21_V  0xFF
+#define HOST_SLCHOST_CONF21_S  8
 /* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF20 0x000000FF
-#define HOST_SLCHOST_CONF20_M ((HOST_SLCHOST_CONF20_V) << (HOST_SLCHOST_CONF20_S))
-#define HOST_SLCHOST_CONF20_V 0xFF
-#define HOST_SLCHOST_CONF20_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF20    0x000000FF
+#define HOST_SLCHOST_CONF20_M  ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S))
+#define HOST_SLCHOST_CONF20_V  0xFF
+#define HOST_SLCHOST_CONF20_S  0
 
-#define HOST_SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
+#define HOST_SLCHOST_WIN_CMD_REG          (DR_REG_SLCHOST_BASE + 0x84)
 /* HOST_SLCHOST_WIN_CMD : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: */
-#define HOST_SLCHOST_WIN_CMD 0x0000FFFF
-#define HOST_SLCHOST_WIN_CMD_M ((HOST_SLCHOST_WIN_CMD_V) << (HOST_SLCHOST_WIN_CMD_S))
-#define HOST_SLCHOST_WIN_CMD_V 0xFFFF
-#define HOST_SLCHOST_WIN_CMD_S 0
+/*description: .*/
+#define HOST_SLCHOST_WIN_CMD    0x0000FFFF
+#define HOST_SLCHOST_WIN_CMD_M  ((HOST_SLCHOST_WIN_CMD_V)<<(HOST_SLCHOST_WIN_CMD_S))
+#define HOST_SLCHOST_WIN_CMD_V  0xFFFF
+#define HOST_SLCHOST_WIN_CMD_S  0
 
-#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
+#define HOST_SLCHOST_CONF_W6_REG          (DR_REG_SLCHOST_BASE + 0x88)
 /* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF27 0x000000FF
-#define HOST_SLCHOST_CONF27_M ((HOST_SLCHOST_CONF27_V) << (HOST_SLCHOST_CONF27_S))
-#define HOST_SLCHOST_CONF27_V 0xFF
-#define HOST_SLCHOST_CONF27_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF27    0x000000FF
+#define HOST_SLCHOST_CONF27_M  ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S))
+#define HOST_SLCHOST_CONF27_V  0xFF
+#define HOST_SLCHOST_CONF27_S  24
 /* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF26 0x000000FF
-#define HOST_SLCHOST_CONF26_M ((HOST_SLCHOST_CONF26_V) << (HOST_SLCHOST_CONF26_S))
-#define HOST_SLCHOST_CONF26_V 0xFF
-#define HOST_SLCHOST_CONF26_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF26    0x000000FF
+#define HOST_SLCHOST_CONF26_M  ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S))
+#define HOST_SLCHOST_CONF26_V  0xFF
+#define HOST_SLCHOST_CONF26_S  16
 /* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF25 0x000000FF
-#define HOST_SLCHOST_CONF25_M ((HOST_SLCHOST_CONF25_V) << (HOST_SLCHOST_CONF25_S))
-#define HOST_SLCHOST_CONF25_V 0xFF
-#define HOST_SLCHOST_CONF25_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF25    0x000000FF
+#define HOST_SLCHOST_CONF25_M  ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S))
+#define HOST_SLCHOST_CONF25_V  0xFF
+#define HOST_SLCHOST_CONF25_S  8
 /* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF24 0x000000FF
-#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V) << (HOST_SLCHOST_CONF24_S))
-#define HOST_SLCHOST_CONF24_V 0xFF
-#define HOST_SLCHOST_CONF24_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF24    0x000000FF
+#define HOST_SLCHOST_CONF24_M  ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S))
+#define HOST_SLCHOST_CONF24_V  0xFF
+#define HOST_SLCHOST_CONF24_S  0
 
-#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C)
+#define HOST_SLCHOST_CONF_W7_REG          (DR_REG_SLCHOST_BASE + 0x8C)
 /* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF31 0x000000FF
-#define HOST_SLCHOST_CONF31_M ((HOST_SLCHOST_CONF31_V) << (HOST_SLCHOST_CONF31_S))
-#define HOST_SLCHOST_CONF31_V 0xFF
-#define HOST_SLCHOST_CONF31_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF31    0x000000FF
+#define HOST_SLCHOST_CONF31_M  ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S))
+#define HOST_SLCHOST_CONF31_V  0xFF
+#define HOST_SLCHOST_CONF31_S  24
 /* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF30 0x000000FF
-#define HOST_SLCHOST_CONF30_M ((HOST_SLCHOST_CONF30_V) << (HOST_SLCHOST_CONF30_S))
-#define HOST_SLCHOST_CONF30_V 0xFF
-#define HOST_SLCHOST_CONF30_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF30    0x000000FF
+#define HOST_SLCHOST_CONF30_M  ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S))
+#define HOST_SLCHOST_CONF30_V  0xFF
+#define HOST_SLCHOST_CONF30_S  16
 /* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF29 0x000000FF
-#define HOST_SLCHOST_CONF29_M ((HOST_SLCHOST_CONF29_V) << (HOST_SLCHOST_CONF29_S))
-#define HOST_SLCHOST_CONF29_V 0xFF
-#define HOST_SLCHOST_CONF29_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF29    0x000000FF
+#define HOST_SLCHOST_CONF29_M  ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S))
+#define HOST_SLCHOST_CONF29_V  0xFF
+#define HOST_SLCHOST_CONF29_S  8
 /* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF28 0x000000FF
-#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V) << (HOST_SLCHOST_CONF28_S))
-#define HOST_SLCHOST_CONF28_V 0xFF
-#define HOST_SLCHOST_CONF28_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF28    0x000000FF
+#define HOST_SLCHOST_CONF28_M  ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S))
+#define HOST_SLCHOST_CONF28_V  0xFF
+#define HOST_SLCHOST_CONF28_S  0
 
-#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
+#define HOST_SLCHOST_PKT_LEN0_REG          (DR_REG_SLCHOST_BASE + 0x90)
 /* HOST_HOSTSLC0_LEN0_CHECK : RO ;bitpos:[31:20] ;default: 12'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN0_CHECK 0x00000FFF
-#define HOST_HOSTSLC0_LEN0_CHECK_M ((HOST_HOSTSLC0_LEN0_CHECK_V) << (HOST_HOSTSLC0_LEN0_CHECK_S))
-#define HOST_HOSTSLC0_LEN0_CHECK_V 0xFFF
-#define HOST_HOSTSLC0_LEN0_CHECK_S 20
+/*description: .*/
+#define HOST_HOSTSLC0_LEN0_CHECK    0x00000FFF
+#define HOST_HOSTSLC0_LEN0_CHECK_M  ((HOST_HOSTSLC0_LEN0_CHECK_V)<<(HOST_HOSTSLC0_LEN0_CHECK_S))
+#define HOST_HOSTSLC0_LEN0_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN0_CHECK_S  20
 /* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN0 0x000FFFFF
-#define HOST_HOSTSLC0_LEN0_M ((HOST_HOSTSLC0_LEN0_V) << (HOST_HOSTSLC0_LEN0_S))
-#define HOST_HOSTSLC0_LEN0_V 0xFFFFF
-#define HOST_HOSTSLC0_LEN0_S 0
+/*description: .*/
+#define HOST_HOSTSLC0_LEN0    0x000FFFFF
+#define HOST_HOSTSLC0_LEN0_M  ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S))
+#define HOST_HOSTSLC0_LEN0_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN0_S  0
 
-#define HOST_SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
+#define HOST_SLCHOST_PKT_LEN1_REG          (DR_REG_SLCHOST_BASE + 0x94)
 /* HOST_HOSTSLC0_LEN1_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN1_CHECK 0x00000FFF
-#define HOST_HOSTSLC0_LEN1_CHECK_M ((HOST_HOSTSLC0_LEN1_CHECK_V) << (HOST_HOSTSLC0_LEN1_CHECK_S))
-#define HOST_HOSTSLC0_LEN1_CHECK_V 0xFFF
-#define HOST_HOSTSLC0_LEN1_CHECK_S 20
+/*description: .*/
+#define HOST_HOSTSLC0_LEN1_CHECK    0x00000FFF
+#define HOST_HOSTSLC0_LEN1_CHECK_M  ((HOST_HOSTSLC0_LEN1_CHECK_V)<<(HOST_HOSTSLC0_LEN1_CHECK_S))
+#define HOST_HOSTSLC0_LEN1_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN1_CHECK_S  20
 /* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN1 0x000FFFFF
-#define HOST_HOSTSLC0_LEN1_M ((HOST_HOSTSLC0_LEN1_V) << (HOST_HOSTSLC0_LEN1_S))
-#define HOST_HOSTSLC0_LEN1_V 0xFFFFF
-#define HOST_HOSTSLC0_LEN1_S 0
+/*description: .*/
+#define HOST_HOSTSLC0_LEN1    0x000FFFFF
+#define HOST_HOSTSLC0_LEN1_M  ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S))
+#define HOST_HOSTSLC0_LEN1_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN1_S  0
 
-#define HOST_SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
+#define HOST_SLCHOST_PKT_LEN2_REG          (DR_REG_SLCHOST_BASE + 0x98)
 /* HOST_HOSTSLC0_LEN2_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN2_CHECK 0x00000FFF
-#define HOST_HOSTSLC0_LEN2_CHECK_M ((HOST_HOSTSLC0_LEN2_CHECK_V) << (HOST_HOSTSLC0_LEN2_CHECK_S))
-#define HOST_HOSTSLC0_LEN2_CHECK_V 0xFFF
-#define HOST_HOSTSLC0_LEN2_CHECK_S 20
+/*description: .*/
+#define HOST_HOSTSLC0_LEN2_CHECK    0x00000FFF
+#define HOST_HOSTSLC0_LEN2_CHECK_M  ((HOST_HOSTSLC0_LEN2_CHECK_V)<<(HOST_HOSTSLC0_LEN2_CHECK_S))
+#define HOST_HOSTSLC0_LEN2_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN2_CHECK_S  20
 /* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN2 0x000FFFFF
-#define HOST_HOSTSLC0_LEN2_M ((HOST_HOSTSLC0_LEN2_V) << (HOST_HOSTSLC0_LEN2_S))
-#define HOST_HOSTSLC0_LEN2_V 0xFFFFF
-#define HOST_HOSTSLC0_LEN2_S 0
+/*description: .*/
+#define HOST_HOSTSLC0_LEN2    0x000FFFFF
+#define HOST_HOSTSLC0_LEN2_M  ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S))
+#define HOST_HOSTSLC0_LEN2_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN2_S  0
 
-#define HOST_SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9C)
+#define HOST_SLCHOST_CONF_W8_REG          (DR_REG_SLCHOST_BASE + 0x9C)
 /* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF35 0x000000FF
-#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V) << (HOST_SLCHOST_CONF35_S))
-#define HOST_SLCHOST_CONF35_V 0xFF
-#define HOST_SLCHOST_CONF35_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF35    0x000000FF
+#define HOST_SLCHOST_CONF35_M  ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S))
+#define HOST_SLCHOST_CONF35_V  0xFF
+#define HOST_SLCHOST_CONF35_S  24
 /* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF34 0x000000FF
-#define HOST_SLCHOST_CONF34_M ((HOST_SLCHOST_CONF34_V) << (HOST_SLCHOST_CONF34_S))
-#define HOST_SLCHOST_CONF34_V 0xFF
-#define HOST_SLCHOST_CONF34_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF34    0x000000FF
+#define HOST_SLCHOST_CONF34_M  ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S))
+#define HOST_SLCHOST_CONF34_V  0xFF
+#define HOST_SLCHOST_CONF34_S  16
 /* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF33 0x000000FF
-#define HOST_SLCHOST_CONF33_M ((HOST_SLCHOST_CONF33_V) << (HOST_SLCHOST_CONF33_S))
-#define HOST_SLCHOST_CONF33_V 0xFF
-#define HOST_SLCHOST_CONF33_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF33    0x000000FF
+#define HOST_SLCHOST_CONF33_M  ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S))
+#define HOST_SLCHOST_CONF33_V  0xFF
+#define HOST_SLCHOST_CONF33_S  8
 /* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF32 0x000000FF
-#define HOST_SLCHOST_CONF32_M ((HOST_SLCHOST_CONF32_V) << (HOST_SLCHOST_CONF32_S))
-#define HOST_SLCHOST_CONF32_V 0xFF
-#define HOST_SLCHOST_CONF32_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF32    0x000000FF
+#define HOST_SLCHOST_CONF32_M  ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S))
+#define HOST_SLCHOST_CONF32_V  0xFF
+#define HOST_SLCHOST_CONF32_S  0
 
-#define HOST_SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xA0)
+#define HOST_SLCHOST_CONF_W9_REG          (DR_REG_SLCHOST_BASE + 0xA0)
 /* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF39 0x000000FF
-#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V) << (HOST_SLCHOST_CONF39_S))
-#define HOST_SLCHOST_CONF39_V 0xFF
-#define HOST_SLCHOST_CONF39_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF39    0x000000FF
+#define HOST_SLCHOST_CONF39_M  ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S))
+#define HOST_SLCHOST_CONF39_V  0xFF
+#define HOST_SLCHOST_CONF39_S  24
 /* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF38 0x000000FF
-#define HOST_SLCHOST_CONF38_M ((HOST_SLCHOST_CONF38_V) << (HOST_SLCHOST_CONF38_S))
-#define HOST_SLCHOST_CONF38_V 0xFF
-#define HOST_SLCHOST_CONF38_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF38    0x000000FF
+#define HOST_SLCHOST_CONF38_M  ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S))
+#define HOST_SLCHOST_CONF38_V  0xFF
+#define HOST_SLCHOST_CONF38_S  16
 /* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF37 0x000000FF
-#define HOST_SLCHOST_CONF37_M ((HOST_SLCHOST_CONF37_V) << (HOST_SLCHOST_CONF37_S))
-#define HOST_SLCHOST_CONF37_V 0xFF
-#define HOST_SLCHOST_CONF37_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF37    0x000000FF
+#define HOST_SLCHOST_CONF37_M  ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S))
+#define HOST_SLCHOST_CONF37_V  0xFF
+#define HOST_SLCHOST_CONF37_S  8
 /* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF36 0x000000FF
-#define HOST_SLCHOST_CONF36_M ((HOST_SLCHOST_CONF36_V) << (HOST_SLCHOST_CONF36_S))
-#define HOST_SLCHOST_CONF36_V 0xFF
-#define HOST_SLCHOST_CONF36_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF36    0x000000FF
+#define HOST_SLCHOST_CONF36_M  ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S))
+#define HOST_SLCHOST_CONF36_V  0xFF
+#define HOST_SLCHOST_CONF36_S  0
 
-#define HOST_SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xA4)
+#define HOST_SLCHOST_CONF_W10_REG          (DR_REG_SLCHOST_BASE + 0xA4)
 /* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF43 0x000000FF
-#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V) << (HOST_SLCHOST_CONF43_S))
-#define HOST_SLCHOST_CONF43_V 0xFF
-#define HOST_SLCHOST_CONF43_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF43    0x000000FF
+#define HOST_SLCHOST_CONF43_M  ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S))
+#define HOST_SLCHOST_CONF43_V  0xFF
+#define HOST_SLCHOST_CONF43_S  24
 /* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF42 0x000000FF
-#define HOST_SLCHOST_CONF42_M ((HOST_SLCHOST_CONF42_V) << (HOST_SLCHOST_CONF42_S))
-#define HOST_SLCHOST_CONF42_V 0xFF
-#define HOST_SLCHOST_CONF42_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF42    0x000000FF
+#define HOST_SLCHOST_CONF42_M  ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S))
+#define HOST_SLCHOST_CONF42_V  0xFF
+#define HOST_SLCHOST_CONF42_S  16
 /* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF41 0x000000FF
-#define HOST_SLCHOST_CONF41_M ((HOST_SLCHOST_CONF41_V) << (HOST_SLCHOST_CONF41_S))
-#define HOST_SLCHOST_CONF41_V 0xFF
-#define HOST_SLCHOST_CONF41_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF41    0x000000FF
+#define HOST_SLCHOST_CONF41_M  ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S))
+#define HOST_SLCHOST_CONF41_V  0xFF
+#define HOST_SLCHOST_CONF41_S  8
 /* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF40 0x000000FF
-#define HOST_SLCHOST_CONF40_M ((HOST_SLCHOST_CONF40_V) << (HOST_SLCHOST_CONF40_S))
-#define HOST_SLCHOST_CONF40_V 0xFF
-#define HOST_SLCHOST_CONF40_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF40    0x000000FF
+#define HOST_SLCHOST_CONF40_M  ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S))
+#define HOST_SLCHOST_CONF40_V  0xFF
+#define HOST_SLCHOST_CONF40_S  0
 
-#define HOST_SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xA8)
+#define HOST_SLCHOST_CONF_W11_REG          (DR_REG_SLCHOST_BASE + 0xA8)
 /* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF47 0x000000FF
-#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V) << (HOST_SLCHOST_CONF47_S))
-#define HOST_SLCHOST_CONF47_V 0xFF
-#define HOST_SLCHOST_CONF47_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF47    0x000000FF
+#define HOST_SLCHOST_CONF47_M  ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S))
+#define HOST_SLCHOST_CONF47_V  0xFF
+#define HOST_SLCHOST_CONF47_S  24
 /* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF46 0x000000FF
-#define HOST_SLCHOST_CONF46_M ((HOST_SLCHOST_CONF46_V) << (HOST_SLCHOST_CONF46_S))
-#define HOST_SLCHOST_CONF46_V 0xFF
-#define HOST_SLCHOST_CONF46_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF46    0x000000FF
+#define HOST_SLCHOST_CONF46_M  ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S))
+#define HOST_SLCHOST_CONF46_V  0xFF
+#define HOST_SLCHOST_CONF46_S  16
 /* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF45 0x000000FF
-#define HOST_SLCHOST_CONF45_M ((HOST_SLCHOST_CONF45_V) << (HOST_SLCHOST_CONF45_S))
-#define HOST_SLCHOST_CONF45_V 0xFF
-#define HOST_SLCHOST_CONF45_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF45    0x000000FF
+#define HOST_SLCHOST_CONF45_M  ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S))
+#define HOST_SLCHOST_CONF45_V  0xFF
+#define HOST_SLCHOST_CONF45_S  8
 /* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF44 0x000000FF
-#define HOST_SLCHOST_CONF44_M ((HOST_SLCHOST_CONF44_V) << (HOST_SLCHOST_CONF44_S))
-#define HOST_SLCHOST_CONF44_V 0xFF
-#define HOST_SLCHOST_CONF44_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF44    0x000000FF
+#define HOST_SLCHOST_CONF44_M  ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S))
+#define HOST_SLCHOST_CONF44_V  0xFF
+#define HOST_SLCHOST_CONF44_S  0
 
-#define HOST_SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xAC)
+#define HOST_SLCHOST_CONF_W12_REG          (DR_REG_SLCHOST_BASE + 0xAC)
 /* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF51 0x000000FF
-#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V) << (HOST_SLCHOST_CONF51_S))
-#define HOST_SLCHOST_CONF51_V 0xFF
-#define HOST_SLCHOST_CONF51_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF51    0x000000FF
+#define HOST_SLCHOST_CONF51_M  ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S))
+#define HOST_SLCHOST_CONF51_V  0xFF
+#define HOST_SLCHOST_CONF51_S  24
 /* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF50 0x000000FF
-#define HOST_SLCHOST_CONF50_M ((HOST_SLCHOST_CONF50_V) << (HOST_SLCHOST_CONF50_S))
-#define HOST_SLCHOST_CONF50_V 0xFF
-#define HOST_SLCHOST_CONF50_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF50    0x000000FF
+#define HOST_SLCHOST_CONF50_M  ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S))
+#define HOST_SLCHOST_CONF50_V  0xFF
+#define HOST_SLCHOST_CONF50_S  16
 /* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF49 0x000000FF
-#define HOST_SLCHOST_CONF49_M ((HOST_SLCHOST_CONF49_V) << (HOST_SLCHOST_CONF49_S))
-#define HOST_SLCHOST_CONF49_V 0xFF
-#define HOST_SLCHOST_CONF49_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF49    0x000000FF
+#define HOST_SLCHOST_CONF49_M  ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S))
+#define HOST_SLCHOST_CONF49_V  0xFF
+#define HOST_SLCHOST_CONF49_S  8
 /* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF48 0x000000FF
-#define HOST_SLCHOST_CONF48_M ((HOST_SLCHOST_CONF48_V) << (HOST_SLCHOST_CONF48_S))
-#define HOST_SLCHOST_CONF48_V 0xFF
-#define HOST_SLCHOST_CONF48_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF48    0x000000FF
+#define HOST_SLCHOST_CONF48_M  ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S))
+#define HOST_SLCHOST_CONF48_V  0xFF
+#define HOST_SLCHOST_CONF48_S  0
 
-#define HOST_SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xB0)
+#define HOST_SLCHOST_CONF_W13_REG          (DR_REG_SLCHOST_BASE + 0xB0)
 /* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF55 0x000000FF
-#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V) << (HOST_SLCHOST_CONF55_S))
-#define HOST_SLCHOST_CONF55_V 0xFF
-#define HOST_SLCHOST_CONF55_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF55    0x000000FF
+#define HOST_SLCHOST_CONF55_M  ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S))
+#define HOST_SLCHOST_CONF55_V  0xFF
+#define HOST_SLCHOST_CONF55_S  24
 /* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF54 0x000000FF
-#define HOST_SLCHOST_CONF54_M ((HOST_SLCHOST_CONF54_V) << (HOST_SLCHOST_CONF54_S))
-#define HOST_SLCHOST_CONF54_V 0xFF
-#define HOST_SLCHOST_CONF54_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF54    0x000000FF
+#define HOST_SLCHOST_CONF54_M  ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S))
+#define HOST_SLCHOST_CONF54_V  0xFF
+#define HOST_SLCHOST_CONF54_S  16
 /* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF53 0x000000FF
-#define HOST_SLCHOST_CONF53_M ((HOST_SLCHOST_CONF53_V) << (HOST_SLCHOST_CONF53_S))
-#define HOST_SLCHOST_CONF53_V 0xFF
-#define HOST_SLCHOST_CONF53_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF53    0x000000FF
+#define HOST_SLCHOST_CONF53_M  ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S))
+#define HOST_SLCHOST_CONF53_V  0xFF
+#define HOST_SLCHOST_CONF53_S  8
 /* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF52 0x000000FF
-#define HOST_SLCHOST_CONF52_M ((HOST_SLCHOST_CONF52_V) << (HOST_SLCHOST_CONF52_S))
-#define HOST_SLCHOST_CONF52_V 0xFF
-#define HOST_SLCHOST_CONF52_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF52    0x000000FF
+#define HOST_SLCHOST_CONF52_M  ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S))
+#define HOST_SLCHOST_CONF52_V  0xFF
+#define HOST_SLCHOST_CONF52_S  0
 
-#define HOST_SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xB4)
+#define HOST_SLCHOST_CONF_W14_REG          (DR_REG_SLCHOST_BASE + 0xB4)
 /* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF59 0x000000FF
-#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V) << (HOST_SLCHOST_CONF59_S))
-#define HOST_SLCHOST_CONF59_V 0xFF
-#define HOST_SLCHOST_CONF59_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF59    0x000000FF
+#define HOST_SLCHOST_CONF59_M  ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S))
+#define HOST_SLCHOST_CONF59_V  0xFF
+#define HOST_SLCHOST_CONF59_S  24
 /* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF58 0x000000FF
-#define HOST_SLCHOST_CONF58_M ((HOST_SLCHOST_CONF58_V) << (HOST_SLCHOST_CONF58_S))
-#define HOST_SLCHOST_CONF58_V 0xFF
-#define HOST_SLCHOST_CONF58_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF58    0x000000FF
+#define HOST_SLCHOST_CONF58_M  ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S))
+#define HOST_SLCHOST_CONF58_V  0xFF
+#define HOST_SLCHOST_CONF58_S  16
 /* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF57 0x000000FF
-#define HOST_SLCHOST_CONF57_M ((HOST_SLCHOST_CONF57_V) << (HOST_SLCHOST_CONF57_S))
-#define HOST_SLCHOST_CONF57_V 0xFF
-#define HOST_SLCHOST_CONF57_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF57    0x000000FF
+#define HOST_SLCHOST_CONF57_M  ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S))
+#define HOST_SLCHOST_CONF57_V  0xFF
+#define HOST_SLCHOST_CONF57_S  8
 /* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF56 0x000000FF
-#define HOST_SLCHOST_CONF56_M ((HOST_SLCHOST_CONF56_V) << (HOST_SLCHOST_CONF56_S))
-#define HOST_SLCHOST_CONF56_V 0xFF
-#define HOST_SLCHOST_CONF56_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF56    0x000000FF
+#define HOST_SLCHOST_CONF56_M  ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S))
+#define HOST_SLCHOST_CONF56_V  0xFF
+#define HOST_SLCHOST_CONF56_S  0
 
-#define HOST_SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xB8)
+#define HOST_SLCHOST_CONF_W15_REG          (DR_REG_SLCHOST_BASE + 0xB8)
 /* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF63 0x000000FF
-#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V) << (HOST_SLCHOST_CONF63_S))
-#define HOST_SLCHOST_CONF63_V 0xFF
-#define HOST_SLCHOST_CONF63_S 24
+/*description: .*/
+#define HOST_SLCHOST_CONF63    0x000000FF
+#define HOST_SLCHOST_CONF63_M  ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S))
+#define HOST_SLCHOST_CONF63_V  0xFF
+#define HOST_SLCHOST_CONF63_S  24
 /* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF62 0x000000FF
-#define HOST_SLCHOST_CONF62_M ((HOST_SLCHOST_CONF62_V) << (HOST_SLCHOST_CONF62_S))
-#define HOST_SLCHOST_CONF62_V 0xFF
-#define HOST_SLCHOST_CONF62_S 16
+/*description: .*/
+#define HOST_SLCHOST_CONF62    0x000000FF
+#define HOST_SLCHOST_CONF62_M  ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S))
+#define HOST_SLCHOST_CONF62_V  0xFF
+#define HOST_SLCHOST_CONF62_S  16
 /* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF61 0x000000FF
-#define HOST_SLCHOST_CONF61_M ((HOST_SLCHOST_CONF61_V) << (HOST_SLCHOST_CONF61_S))
-#define HOST_SLCHOST_CONF61_V 0xFF
-#define HOST_SLCHOST_CONF61_S 8
+/*description: .*/
+#define HOST_SLCHOST_CONF61    0x000000FF
+#define HOST_SLCHOST_CONF61_M  ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S))
+#define HOST_SLCHOST_CONF61_V  0xFF
+#define HOST_SLCHOST_CONF61_S  8
 /* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF60 0x000000FF
-#define HOST_SLCHOST_CONF60_M ((HOST_SLCHOST_CONF60_V) << (HOST_SLCHOST_CONF60_S))
-#define HOST_SLCHOST_CONF60_V 0xFF
-#define HOST_SLCHOST_CONF60_S 0
+/*description: .*/
+#define HOST_SLCHOST_CONF60    0x000000FF
+#define HOST_SLCHOST_CONF60_M  ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S))
+#define HOST_SLCHOST_CONF60_V  0xFF
+#define HOST_SLCHOST_CONF60_S  0
 
-#define HOST_SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xBC)
+#define HOST_SLCHOST_CHECK_SUM0_REG          (DR_REG_SLCHOST_BASE + 0xBC)
 /* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V) << (HOST_SLCHOST_CHECK_SUM0_S))
-#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM0_S 0
+/*description: .*/
+#define HOST_SLCHOST_CHECK_SUM0    0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_M  ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S))
+#define HOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_S  0
 
-#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0)
+#define HOST_SLCHOST_CHECK_SUM1_REG          (DR_REG_SLCHOST_BASE + 0xC0)
 /* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM1_M ((HOST_SLCHOST_CHECK_SUM1_V) << (HOST_SLCHOST_CHECK_SUM1_S))
-#define HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM1_S 0
+/*description: .*/
+#define HOST_SLCHOST_CHECK_SUM1    0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_M  ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S))
+#define HOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_S  0
 
-#define HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xC8)
+#define HOST_SLC0HOST_TOKEN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0xC8)
 /* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_WD 0x00000FFF
-#define HOST_SLC0HOST_TOKEN1_WD_M ((HOST_SLC0HOST_TOKEN1_WD_V) << (HOST_SLC0HOST_TOKEN1_WD_S))
-#define HOST_SLC0HOST_TOKEN1_WD_V 0xFFF
-#define HOST_SLC0HOST_TOKEN1_WD_S 16
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN1_WD    0x00000FFF
+#define HOST_SLC0HOST_TOKEN1_WD_M  ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S))
+#define HOST_SLC0HOST_TOKEN1_WD_V  0xFFF
+#define HOST_SLC0HOST_TOKEN1_WD_S  16
 /* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF
-#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V) << (HOST_SLC0HOST_TOKEN0_WD_S))
-#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF
-#define HOST_SLC0HOST_TOKEN0_WD_S 0
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN0_WD    0x00000FFF
+#define HOST_SLC0HOST_TOKEN0_WD_M  ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S))
+#define HOST_SLC0HOST_TOKEN0_WD_V  0xFFF
+#define HOST_SLC0HOST_TOKEN0_WD_S  0
 
-#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0)
+#define HOST_SLCHOST_TOKEN_CON_REG          (DR_REG_SLCHOST_BASE + 0xD0)
 /* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_LEN_WR (BIT(8))
-#define HOST_SLC0HOST_LEN_WR_M (BIT(8))
-#define HOST_SLC0HOST_LEN_WR_V 0x1
-#define HOST_SLC0HOST_LEN_WR_S 8
+/*description: .*/
+#define HOST_SLC0HOST_LEN_WR    (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_M  (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_V  0x1
+#define HOST_SLC0HOST_LEN_WR_S  8
 /* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_WR (BIT(3))
-#define HOST_SLC0HOST_TOKEN1_WR_M (BIT(3))
-#define HOST_SLC0HOST_TOKEN1_WR_V 0x1
-#define HOST_SLC0HOST_TOKEN1_WR_S 3
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN1_WR    (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_M  (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_V  0x1
+#define HOST_SLC0HOST_TOKEN1_WR_S  3
 /* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_WR (BIT(2))
-#define HOST_SLC0HOST_TOKEN0_WR_M (BIT(2))
-#define HOST_SLC0HOST_TOKEN0_WR_V 0x1
-#define HOST_SLC0HOST_TOKEN0_WR_S 2
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN0_WR    (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_M  (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_V  0x1
+#define HOST_SLC0HOST_TOKEN0_WR_S  2
 /* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1))
-#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1))
-#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1
-#define HOST_SLC0HOST_TOKEN1_DEC_S 1
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN1_DEC    (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_M  (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_V  0x1
+#define HOST_SLC0HOST_TOKEN1_DEC_S  1
 /* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0))
-#define HOST_SLC0HOST_TOKEN0_DEC_M (BIT(0))
-#define HOST_SLC0HOST_TOKEN0_DEC_V 0x1
-#define HOST_SLC0HOST_TOKEN0_DEC_S 0
+/*description: .*/
+#define HOST_SLC0HOST_TOKEN0_DEC    (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_M  (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_V  0x1
+#define HOST_SLC0HOST_TOKEN0_DEC_S  0
 
-#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4)
+#define HOST_SLC0HOST_INT_CLR_REG          (DR_REG_SLCHOST_BASE + 0xD4)
 /* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_CLR (BIT(25))
-#define HOST_GPIO_SDIO_INT_CLR_M (BIT(25))
-#define HOST_GPIO_SDIO_INT_CLR_V 0x1
-#define HOST_GPIO_SDIO_INT_CLR_S 25
+/*description: .*/
+#define HOST_GPIO_SDIO_INT_CLR    (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_V  0x1
+#define HOST_GPIO_SDIO_INT_CLR_S  25
 /* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24
+/*description: .*/
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR    (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
 /* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23
+/*description: .*/
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR    (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
 /* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_CLR_M (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_CLR_V 0x1
-#define HOST_SLC0_EXT_BIT3_INT_CLR_S 22
+/*description: .*/
+#define HOST_SLC0_EXT_BIT3_INT_CLR    (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_CLR_S  22
 /* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_CLR_M (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_CLR_V 0x1
-#define HOST_SLC0_EXT_BIT2_INT_CLR_S 21
+/*description: .*/
+#define HOST_SLC0_EXT_BIT2_INT_CLR    (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_CLR_S  21
 /* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_CLR_M (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_CLR_V 0x1
-#define HOST_SLC0_EXT_BIT1_INT_CLR_S 20
+/*description: .*/
+#define HOST_SLC0_EXT_BIT1_INT_CLR    (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_CLR_S  20
 /* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1
-#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19
+/*description: .*/
+#define HOST_SLC0_EXT_BIT0_INT_CLR    (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_CLR_S  19
 /* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_M (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x1
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_S 18
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID_INT_CLR    (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_S  18
 /* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_CLR (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_CLR_M (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_CLR_V 0x1
-#define HOST_SLC0_TX_OVF_INT_CLR_S 17
+/*description: .*/
+#define HOST_SLC0_TX_OVF_INT_CLR    (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_V  0x1
+#define HOST_SLC0_TX_OVF_INT_CLR_S  17
 /* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_CLR (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_CLR_M (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_CLR_V 0x1
-#define HOST_SLC0_RX_UDF_INT_CLR_S 16
+/*description: .*/
+#define HOST_SLC0_RX_UDF_INT_CLR    (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_V  0x1
+#define HOST_SLC0_RX_UDF_INT_CLR_S  16
 /* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1
-#define HOST_SLC0HOST_TX_START_INT_CLR_S 15
+/*description: .*/
+#define HOST_SLC0HOST_TX_START_INT_CLR    (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_CLR_S  15
 /* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_CLR (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_CLR_M (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_CLR_V 0x1
-#define HOST_SLC0HOST_RX_START_INT_CLR_S 14
+/*description: .*/
+#define HOST_SLC0HOST_RX_START_INT_CLR    (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_CLR_S  14
 /* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_M (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x1
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_S 13
+/*description: .*/
+#define HOST_SLC0HOST_RX_EOF_INT_CLR    (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_S  13
 /* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_M (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x1
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_S 12
+/*description: .*/
+#define HOST_SLC0HOST_RX_SOF_INT_CLR    (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_S  12
 /* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11
+/*description: .*/
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR    (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
 /* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10
+/*description: .*/
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR    (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
 /* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9
+/*description: .*/
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
 /* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8
+/*description: .*/
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
 /* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR    (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
 /* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR    (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
 /* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR    (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
 /* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR    (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
 /* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR    (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
 /* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR    (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
 /* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR    (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
 /* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR    (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
 
-#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC)
+#define HOST_SLC0HOST_FUNC1_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xDC)
 /* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25))
-#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25))
-#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1
-#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25
+/*description: .*/
+#define HOST_FN1_GPIO_SDIO_INT_ENA    (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_M  (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_V  0x1
+#define HOST_FN1_GPIO_SDIO_INT_ENA_S  25
 /* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24))
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24))
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24
+/*description: .*/
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
 /* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23
+/*description: .*/
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
 /* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22))
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (BIT(22))
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22
+/*description: .*/
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
 /* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21))
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21
+/*description: .*/
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
 /* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20))
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (BIT(20))
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20
+/*description: .*/
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
 /* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19))
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19
+/*description: .*/
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
 /* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18))
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18))
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18
+/*description: .*/
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
 /* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17))
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17))
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17
+/*description: .*/
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA    (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
 /* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16))
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M (BIT(16))
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16
+/*description: .*/
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA    (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
 /* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15))
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x1
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15
+/*description: .*/
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA    (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
 /* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14))
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (BIT(14))
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x1
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14
+/*description: .*/
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA    (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
 /* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13
+/*description: .*/
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
 /* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12))
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12))
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x1
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12
+/*description: .*/
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
 /* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11
+/*description: .*/
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
 /* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10))
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10))
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10
+/*description: .*/
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
 /* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9
+/*description: .*/
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
 /* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8))
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8))
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8
+/*description: .*/
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
 /* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
 /* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6))
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6))
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
 /* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
 /* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4))
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4))
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
 /* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
 /* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2))
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2))
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
 /* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
 /* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0))
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0))
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x1
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0
+/*description: .*/
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
 
-#define HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xEC)
+#define HOST_SLC0HOST_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xEC)
 /* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ENA (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA_M (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA_V 0x1
-#define HOST_GPIO_SDIO_INT_ENA_S 25
+/*description: .*/
+#define HOST_GPIO_SDIO_INT_ENA    (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_V  0x1
+#define HOST_GPIO_SDIO_INT_ENA_S  25
 /* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24
+/*description: .*/
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
 /* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23
+/*description: .*/
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
 /* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA_M (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA_V 0x1
-#define HOST_SLC0_EXT_BIT3_INT_ENA_S 22
+/*description: .*/
+#define HOST_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA_S  22
 /* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA_V 0x1
-#define HOST_SLC0_EXT_BIT2_INT_ENA_S 21
+/*description: .*/
+#define HOST_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA_S  21
 /* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA_M (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA_V 0x1
-#define HOST_SLC0_EXT_BIT1_INT_ENA_S 20
+/*description: .*/
+#define HOST_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA_S  20
 /* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1
-#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19
+/*description: .*/
+#define HOST_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA_S  19
 /* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_S 18
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_S  18
 /* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ENA (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA_M (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA_V 0x1
-#define HOST_SLC0_TX_OVF_INT_ENA_S 17
+/*description: .*/
+#define HOST_SLC0_TX_OVF_INT_ENA    (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ENA_S  17
 /* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ENA (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA_M (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA_V 0x1
-#define HOST_SLC0_RX_UDF_INT_ENA_S 16
+/*description: .*/
+#define HOST_SLC0_RX_UDF_INT_ENA    (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ENA_S  16
 /* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1
-#define HOST_SLC0HOST_TX_START_INT_ENA_S 15
+/*description: .*/
+#define HOST_SLC0HOST_TX_START_INT_ENA    (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA_S  15
 /* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ENA (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA_M (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA_V 0x1
-#define HOST_SLC0HOST_RX_START_INT_ENA_S 14
+/*description: .*/
+#define HOST_SLC0HOST_RX_START_INT_ENA    (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA_S  14
 /* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_S 13
+/*description: .*/
+#define HOST_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_S  13
 /* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_S 12
+/*description: .*/
+#define HOST_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_S  12
 /* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11
+/*description: .*/
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
 /* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10
+/*description: .*/
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
 /* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9
+/*description: .*/
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
 /* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8
+/*description: .*/
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
 /* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
 /* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
 /* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
 /* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
 /* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
 /* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
 /* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
 /* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
 
-#define HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF4)
+#define HOST_SLC0HOST_RX_INFOR_REG          (DR_REG_SLCHOST_BASE + 0xF4)
 /* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF
-#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V) << (HOST_SLC0HOST_RX_INFOR_S))
-#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF
-#define HOST_SLC0HOST_RX_INFOR_S 0
+/*description: .*/
+#define HOST_SLC0HOST_RX_INFOR    0x000FFFFF
+#define HOST_SLC0HOST_RX_INFOR_M  ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S))
+#define HOST_SLC0HOST_RX_INFOR_V  0xFFFFF
+#define HOST_SLC0HOST_RX_INFOR_S  0
 
-#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC)
+#define HOST_SLC0HOST_LEN_WD_REG          (DR_REG_SLCHOST_BASE + 0xFC)
 /* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_LEN_WD 0xFFFFFFFF
-#define HOST_SLC0HOST_LEN_WD_M ((HOST_SLC0HOST_LEN_WD_V) << (HOST_SLC0HOST_LEN_WD_S))
-#define HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFF
-#define HOST_SLC0HOST_LEN_WD_S 0
+/*description: .*/
+#define HOST_SLC0HOST_LEN_WD    0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_M  ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S))
+#define HOST_SLC0HOST_LEN_WD_V  0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_S  0
 
-#define HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
+#define HOST_SLC_APBWIN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0x100)
 /* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_WDATA 0xFFFFFFFF
-#define HOST_SLC_APBWIN_WDATA_M ((HOST_SLC_APBWIN_WDATA_V) << (HOST_SLC_APBWIN_WDATA_S))
-#define HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFF
-#define HOST_SLC_APBWIN_WDATA_S 0
+/*description: .*/
+#define HOST_SLC_APBWIN_WDATA    0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_M  ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S))
+#define HOST_SLC_APBWIN_WDATA_V  0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_S  0
 
-#define HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
+#define HOST_SLC_APBWIN_CONF_REG          (DR_REG_SLCHOST_BASE + 0x104)
 /* HOST_SLC_APBWIN_BUS : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_BUS (BIT(30))
-#define HOST_SLC_APBWIN_BUS_M (BIT(30))
-#define HOST_SLC_APBWIN_BUS_V 0x1
-#define HOST_SLC_APBWIN_BUS_S 30
+/*description: .*/
+#define HOST_SLC_APBWIN_BUS    (BIT(30))
+#define HOST_SLC_APBWIN_BUS_M  (BIT(30))
+#define HOST_SLC_APBWIN_BUS_V  0x1
+#define HOST_SLC_APBWIN_BUS_S  30
 /* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_START (BIT(29))
-#define HOST_SLC_APBWIN_START_M (BIT(29))
-#define HOST_SLC_APBWIN_START_V 0x1
-#define HOST_SLC_APBWIN_START_S 29
+/*description: .*/
+#define HOST_SLC_APBWIN_START    (BIT(29))
+#define HOST_SLC_APBWIN_START_M  (BIT(29))
+#define HOST_SLC_APBWIN_START_V  0x1
+#define HOST_SLC_APBWIN_START_S  29
 /* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_WR (BIT(28))
-#define HOST_SLC_APBWIN_WR_M (BIT(28))
-#define HOST_SLC_APBWIN_WR_V 0x1
-#define HOST_SLC_APBWIN_WR_S 28
+/*description: .*/
+#define HOST_SLC_APBWIN_WR    (BIT(28))
+#define HOST_SLC_APBWIN_WR_M  (BIT(28))
+#define HOST_SLC_APBWIN_WR_V  0x1
+#define HOST_SLC_APBWIN_WR_S  28
 /* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_ADDR 0x0FFFFFFF
-#define HOST_SLC_APBWIN_ADDR_M ((HOST_SLC_APBWIN_ADDR_V) << (HOST_SLC_APBWIN_ADDR_S))
-#define HOST_SLC_APBWIN_ADDR_V 0xFFFFFFF
-#define HOST_SLC_APBWIN_ADDR_S 0
+/*description: .*/
+#define HOST_SLC_APBWIN_ADDR    0x0FFFFFFF
+#define HOST_SLC_APBWIN_ADDR_M  ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S))
+#define HOST_SLC_APBWIN_ADDR_V  0xFFFFFFF
+#define HOST_SLC_APBWIN_ADDR_S  0
 
-#define HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
+#define HOST_SLC_APBWIN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x108)
 /* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF
-#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V) << (HOST_SLC_APBWIN_RDATA_S))
-#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF
-#define HOST_SLC_APBWIN_RDATA_S 0
+/*description: .*/
+#define HOST_SLC_APBWIN_RDATA    0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_M  ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S))
+#define HOST_SLC_APBWIN_RDATA_V  0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_S  0
 
-#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C)
+#define HOST_SLCHOST_RDCLR0_REG          (DR_REG_SLCHOST_BASE + 0x10C)
 /* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
-/*description: */
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FF
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V) << (HOST_SLCHOST_SLC0_BIT6_CLRADDR_S))
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x1FF
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9
+/*description: .*/
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR    0x000001FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x1FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
 /* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */
-/*description: */
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FF
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V) << (HOST_SLCHOST_SLC0_BIT7_CLRADDR_S))
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x1FF
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0
+/*description: .*/
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR    0x000001FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x1FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
 
-#define HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
+#define HOST_SLC0HOST_INT_ENA1_REG          (DR_REG_SLCHOST_BASE + 0x114)
 /* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA1_V 0x1
-#define HOST_GPIO_SDIO_INT_ENA1_S 25
+/*description: .*/
+#define HOST_GPIO_SDIO_INT_ENA1    (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_V  0x1
+#define HOST_GPIO_SDIO_INT_ENA1_S  25
 /* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24
+/*description: .*/
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1    (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
 /* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23
+/*description: .*/
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1    (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
 /* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_M (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x1
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_S 22
+/*description: .*/
+#define HOST_SLC0_EXT_BIT3_INT_ENA1    (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_S  22
 /* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21
+/*description: .*/
+#define HOST_SLC0_EXT_BIT2_INT_ENA1    (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_S  21
 /* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_M (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x1
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_S 20
+/*description: .*/
+#define HOST_SLC0_EXT_BIT1_INT_ENA1    (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_S  20
 /* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_M (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x1
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_S 19
+/*description: .*/
+#define HOST_SLC0_EXT_BIT0_INT_ENA1    (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_S  19
 /* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18
+/*description: .*/
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1    (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
 /* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1
-#define HOST_SLC0_TX_OVF_INT_ENA1_S 17
+/*description: .*/
+#define HOST_SLC0_TX_OVF_INT_ENA1    (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ENA1_S  17
 /* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA1_M (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA1_V 0x1
-#define HOST_SLC0_RX_UDF_INT_ENA1_S 16
+/*description: .*/
+#define HOST_SLC0_RX_UDF_INT_ENA1    (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ENA1_S  16
 /* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA1_M (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA1_V 0x1
-#define HOST_SLC0HOST_TX_START_INT_ENA1_S 15
+/*description: .*/
+#define HOST_SLC0HOST_TX_START_INT_ENA1    (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA1_S  15
 /* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA1_M (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA1_V 0x1
-#define HOST_SLC0HOST_RX_START_INT_ENA1_S 14
+/*description: .*/
+#define HOST_SLC0HOST_RX_START_INT_ENA1    (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA1_S  14
 /* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13
+/*description: .*/
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1    (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
 /* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12
+/*description: .*/
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1    (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
 /* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11
+/*description: .*/
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1    (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
 /* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10
+/*description: .*/
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1    (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
 /* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9
+/*description: .*/
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
 /* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8
+/*description: .*/
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
 /* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1    (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
 /* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1    (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
 /* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1    (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
 /* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1    (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
 /* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1    (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
 /* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1    (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
 /* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1    (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
 /* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0
+/*description: .*/
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1    (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
 
-#define HOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178)
+#define HOST_SLCHOSTDATE_REG          (DR_REG_SLCHOST_BASE + 0x178)
 /* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */
-/*description: */
-#define HOST_SLCHOST_DATE 0xFFFFFFFF
-#define HOST_SLCHOST_DATE_M ((HOST_SLCHOST_DATE_V) << (HOST_SLCHOST_DATE_S))
-#define HOST_SLCHOST_DATE_V 0xFFFFFFFF
-#define HOST_SLCHOST_DATE_S 0
+/*description: .*/
+#define HOST_SLCHOST_DATE    0xFFFFFFFF
+#define HOST_SLCHOST_DATE_M  ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S))
+#define HOST_SLCHOST_DATE_V  0xFFFFFFFF
+#define HOST_SLCHOST_DATE_S  0
 
-#define HOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17C)
+#define HOST_SLCHOSTID_REG          (DR_REG_SLCHOST_BASE + 0x17C)
 /* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */
-/*description: */
-#define HOST_SLCHOST_ID 0xFFFFFFFF
-#define HOST_SLCHOST_ID_M ((HOST_SLCHOST_ID_V) << (HOST_SLCHOST_ID_S))
-#define HOST_SLCHOST_ID_V 0xFFFFFFFF
-#define HOST_SLCHOST_ID_S 0
+/*description: .*/
+#define HOST_SLCHOST_ID    0xFFFFFFFF
+#define HOST_SLCHOST_ID_M  ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S))
+#define HOST_SLCHOST_ID_V  0xFFFFFFFF
+#define HOST_SLCHOST_ID_S  0
 
-#define HOST_SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1F0)
+#define HOST_SLCHOST_CONF_REG          (DR_REG_SLCHOST_BASE + 0x1F0)
 /* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define HOST_HSPEED_CON_EN (BIT(27))
-#define HOST_HSPEED_CON_EN_M (BIT(27))
-#define HOST_HSPEED_CON_EN_V 0x1
-#define HOST_HSPEED_CON_EN_S 27
+/*description: .*/
+#define HOST_HSPEED_CON_EN    (BIT(27))
+#define HOST_HSPEED_CON_EN_M  (BIT(27))
+#define HOST_HSPEED_CON_EN_V  0x1
+#define HOST_HSPEED_CON_EN_S  27
 /* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SDIO_PAD_PULLUP (BIT(26))
-#define HOST_SDIO_PAD_PULLUP_M (BIT(26))
-#define HOST_SDIO_PAD_PULLUP_V 0x1
-#define HOST_SDIO_PAD_PULLUP_S 26
+/*description: .*/
+#define HOST_SDIO_PAD_PULLUP    (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_M  (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_V  0x1
+#define HOST_SDIO_PAD_PULLUP_S  26
 /* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SDIO20_INT_DELAY (BIT(25))
-#define HOST_SDIO20_INT_DELAY_M (BIT(25))
-#define HOST_SDIO20_INT_DELAY_V 0x1
-#define HOST_SDIO20_INT_DELAY_S 25
+/*description: .*/
+#define HOST_SDIO20_INT_DELAY    (BIT(25))
+#define HOST_SDIO20_INT_DELAY_M  (BIT(25))
+#define HOST_SDIO20_INT_DELAY_V  0x1
+#define HOST_SDIO20_INT_DELAY_S  25
 /* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_QUICK_IN 0x0000001F
-#define HOST_FRC_QUICK_IN_M ((HOST_FRC_QUICK_IN_V) << (HOST_FRC_QUICK_IN_S))
-#define HOST_FRC_QUICK_IN_V 0x1F
-#define HOST_FRC_QUICK_IN_S 20
+/*description: .*/
+#define HOST_FRC_QUICK_IN    0x0000001F
+#define HOST_FRC_QUICK_IN_M  ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S))
+#define HOST_FRC_QUICK_IN_V  0x1F
+#define HOST_FRC_QUICK_IN_S  20
 /* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_POS_SAMP 0x0000001F
-#define HOST_FRC_POS_SAMP_M ((HOST_FRC_POS_SAMP_V) << (HOST_FRC_POS_SAMP_S))
-#define HOST_FRC_POS_SAMP_V 0x1F
-#define HOST_FRC_POS_SAMP_S 15
+/*description: .*/
+#define HOST_FRC_POS_SAMP    0x0000001F
+#define HOST_FRC_POS_SAMP_M  ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S))
+#define HOST_FRC_POS_SAMP_V  0x1F
+#define HOST_FRC_POS_SAMP_S  15
 /* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_NEG_SAMP 0x0000001F
-#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V) << (HOST_FRC_NEG_SAMP_S))
-#define HOST_FRC_NEG_SAMP_V 0x1F
-#define HOST_FRC_NEG_SAMP_S 10
+/*description: .*/
+#define HOST_FRC_NEG_SAMP    0x0000001F
+#define HOST_FRC_NEG_SAMP_M  ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S))
+#define HOST_FRC_NEG_SAMP_V  0x1F
+#define HOST_FRC_NEG_SAMP_S  10
 /* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_SDIO20 0x0000001F
-#define HOST_FRC_SDIO20_M ((HOST_FRC_SDIO20_V) << (HOST_FRC_SDIO20_S))
-#define HOST_FRC_SDIO20_V 0x1F
-#define HOST_FRC_SDIO20_S 5
+/*description: .*/
+#define HOST_FRC_SDIO20    0x0000001F
+#define HOST_FRC_SDIO20_M  ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S))
+#define HOST_FRC_SDIO20_V  0x1F
+#define HOST_FRC_SDIO20_S  5
 /* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_SDIO11 0x0000001F
-#define HOST_FRC_SDIO11_M ((HOST_FRC_SDIO11_V) << (HOST_FRC_SDIO11_S))
-#define HOST_FRC_SDIO11_V 0x1F
-#define HOST_FRC_SDIO11_S 0
+/*description: .*/
+#define HOST_FRC_SDIO11    0x0000001F
+#define HOST_FRC_SDIO11_M  ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S))
+#define HOST_FRC_SDIO11_V  0x1F
+#define HOST_FRC_SDIO11_S  0
 
-#define HOST_SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1F4)
+#define HOST_SLCHOST_INF_ST_REG          (DR_REG_SLCHOST_BASE + 0x1F4)
 /* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO_QUICK_IN 0x0000001F
-#define HOST_SDIO_QUICK_IN_M ((HOST_SDIO_QUICK_IN_V) << (HOST_SDIO_QUICK_IN_S))
-#define HOST_SDIO_QUICK_IN_V 0x1F
-#define HOST_SDIO_QUICK_IN_S 10
+/*description: .*/
+#define HOST_SDIO_QUICK_IN    0x0000001F
+#define HOST_SDIO_QUICK_IN_M  ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S))
+#define HOST_SDIO_QUICK_IN_V  0x1F
+#define HOST_SDIO_QUICK_IN_S  10
 /* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO_NEG_SAMP 0x0000001F
-#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V) << (HOST_SDIO_NEG_SAMP_S))
-#define HOST_SDIO_NEG_SAMP_V 0x1F
-#define HOST_SDIO_NEG_SAMP_S 5
+/*description: .*/
+#define HOST_SDIO_NEG_SAMP    0x0000001F
+#define HOST_SDIO_NEG_SAMP_M  ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S))
+#define HOST_SDIO_NEG_SAMP_V  0x1F
+#define HOST_SDIO_NEG_SAMP_S  5
 /* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO20_MODE 0x0000001F
-#define HOST_SDIO20_MODE_M ((HOST_SDIO20_MODE_V) << (HOST_SDIO20_MODE_S))
-#define HOST_SDIO20_MODE_V 0x1F
-#define HOST_SDIO20_MODE_S 0
+/*description: .*/
+#define HOST_SDIO20_MODE    0x0000001F
+#define HOST_SDIO20_MODE_M  ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S))
+#define HOST_SDIO20_MODE_V  0x1F
+#define HOST_SDIO20_MODE_S  0
+
 
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_HOST_REG_H_ */

components/soc/esp32s3/include/soc/host_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_HOST_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     uint32_t reserved_0;

components/soc/esp32s3/include/soc/i2c_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,281 +11,282 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_I2C_STRUCT_H_
+#define _SOC_I2C_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
-            uint32_t period                        :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t period                        :    9;  /*This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } scl_low_period;
     union {
         struct {
-            uint32_t sda_force_out                 :    1;
-            uint32_t scl_force_out                 :    1;
-            uint32_t sample_scl_level              :    1;
-            uint32_t rx_full_ack_level             :    1;
-            uint32_t ms_mode                       :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t tx_lsb_first                  :    1;
-            uint32_t rx_lsb_first                  :    1;
-            uint32_t clk_en                        :    1;
-            uint32_t arbitration_en                :    1;
-            uint32_t fsm_rst                       :    1;
-            uint32_t conf_upgate                   :    1;
-            uint32_t slv_tx_auto_start_en          :    1;
-            uint32_t addr_10bit_rw_check_en        :    1;
-            uint32_t addr_broadcasting_en          :    1;
-            uint32_t reserved15                    :    17;
+            uint32_t sda_force_out                 :    1;  /*0: direct output; 1: open drain output.*/
+            uint32_t scl_force_out                 :    1;  /*0: direct output; 1: open drain output.*/
+            uint32_t sample_scl_level              :    1;  /*This register is used to select the sample mode.; 1: sample SDA data on the SCL low level.; 0: sample SDA data on the SCL high level.*/
+            uint32_t rx_full_ack_level             :    1;  /*This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.*/
+            uint32_t ms_mode                       :    1;  /*Set this bit to configure the module as an I2C Master. Clear this bit to configure the; module as an I2C Slave. */
+            uint32_t trans_start                   :    1;  /*Set this bit to start sending the data in txfifo. */
+            uint32_t tx_lsb_first                  :    1;  /*This bit is used to control the sending mode for data needing to be sent. ; 1: send data from the least significant bit;; 0: send data from the most significant bit.*/
+            uint32_t rx_lsb_first                  :    1;  /*This bit is used to control the storage mode for received data.; 1: receive data from the least significant bit;; 0: receive data from the most significant bit.*/
+            uint32_t clk_en                        :    1;  /*Reserved*/
+            uint32_t arbitration_en                :    1;  /*This is the enable bit for arbitration_lost.*/
+            uint32_t fsm_rst                       :    1;  /*This register is used to reset the scl FMS.*/
+            uint32_t conf_upgate                   :    1;  /*synchronization bit*/
+            uint32_t slv_tx_auto_start_en          :    1;  /*This is the enable bit for slave to send data automatically*/
+            uint32_t addr_10bit_rw_check_en        :    1;  /*This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol*/
+            uint32_t addr_broadcasting_en          :    1;  /*This is the enable bit to support the 7bit general call function. */
+            uint32_t reserved15                    :    17;  /*Reserved*/
         };
         uint32_t val;
     } ctr;
     union {
         struct {
-            uint32_t resp_rec                      :    1;
-            uint32_t slave_rw                      :    1;
-            uint32_t reserved2                     :    1;
-            uint32_t arb_lost                      :    1;
-            uint32_t bus_busy                      :    1;
-            uint32_t slave_addressed               :    1;
-            uint32_t reserved6                     :    1;
-            uint32_t reserved7                     :    1;
-            uint32_t rx_fifo_cnt                   :    6;
-            uint32_t stretch_cause                 :    2;
-            uint32_t reserved16                    :    2;
-            uint32_t tx_fifo_cnt                   :    6;
-            uint32_t scl_main_state_last           :    3;
-            uint32_t reserved27                    :    1;
-            uint32_t scl_state_last                :    3;
-            uint32_t reserved31                    :    1;
+            uint32_t resp_rec                      :    1;  /*The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.*/
+            uint32_t slave_rw                      :    1;  /*When in slave mode, 1: master reads from slave; 0: master writes to slave.*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t arb_lost                      :    1;  /*When the I2C controller loses control of SCL line, this register changes to 1.*/
+            uint32_t bus_busy                      :    1;  /*1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. */
+            uint32_t slave_addressed               :    1;  /*When configured as an I2C Slave, and the address sent by the master is; equal to the address of the slave, then this bit will be of high level.*/
+            uint32_t reserved6                     :    1;  /*Reserved*/
+            uint32_t reserved7                     :    1;  /*Reserved*/
+            uint32_t rx_fifo_cnt                   :    6;  /*This field represents the amount of data needed to be sent. */
+            uint32_t stretch_cause                 :    2;  /*The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.*/
+            uint32_t reserved16                    :    2;  /*Reserved*/
+            uint32_t tx_fifo_cnt                   :    6;  /*This field stores the amount of received data in RAM. */
+            uint32_t scl_main_state_last           :    3;  /*This field indicates the states of the I2C module state machine. ; 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK*/
+            uint32_t reserved27                    :    1;  /*Reserved*/
+            uint32_t scl_state_last                :    3;  /*This field indicates the states of the state machine used to produce SCL.; 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop*/
+            uint32_t reserved31                    :    1;  /*Reserved*/
         };
         uint32_t val;
     } sr;
     union {
         struct {
-            uint32_t tout                          :    5;
-            uint32_t time_out_en                   :    1;
-            uint32_t reserved6                     :    26;
+            uint32_t tout                          :    5;  /*This register is used to configure the timeout for receiving a data bit in APB; clock cycles. */
+            uint32_t time_out_en                   :    1;  /*This is the enable bit for time out control.*/
+            uint32_t reserved6                     :    26;  /*Reserved*/
         };
         uint32_t val;
     } timeout;
     union {
         struct {
-            uint32_t addr:         15;
-            uint32_t reserved15:   16;
-            uint32_t en_10bit:      1;
+            uint32_t addr                          :    15;  /*When configured as an I2C Slave, this field is used to configure the slave address.*/
+            uint32_t reserved15                    :    16;  /*Reserved*/
+            uint32_t en_10bit                      :    1;  /*This field is used to enable the slave 10-bit addressing mode in master mode. */
         };
         uint32_t val;
     } slave_addr;
     union {
         struct {
-            uint32_t rx_fifo_raddr                 :    5;
-            uint32_t rx_fifo_waddr                 :    5;
-            uint32_t tx_fifo_raddr                 :    5;
-            uint32_t tx_fifo_waddr                 :    5;
-            uint32_t reserved20                    :    1;
-            uint32_t reserved21                    :    1;
-            uint32_t slave_rw_point                :    8;
-            uint32_t reserved30                    :    2;
+            uint32_t rx_fifo_raddr                 :    5;  /*This is the offset address of the APB reading from rxfifo*/
+            uint32_t rx_fifo_waddr                 :    5;  /*This is the offset address of i2c module receiving data and writing to rxfifo.*/
+            uint32_t tx_fifo_raddr                 :    5;  /*This is the offset address of i2c module reading from txfifo.*/
+            uint32_t tx_fifo_waddr                 :    5;  /*This is the offset address of APB bus writing to txfifo.*/
+            uint32_t reserved20                    :    1;  /*Reserved*/
+            uint32_t reserved21                    :    1;  /*Reserved*/
+            uint32_t slave_rw_point                :    8;  /*The received data in I2C slave mode.*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
         };
         uint32_t val;
     } fifo_st;
     union {
         struct {
-            uint32_t rx_fifo_wm_thrhd              :    5;
-            uint32_t tx_fifo_wm_thrhd              :    5;
-            uint32_t nonfifo_en                    :    1;
-            uint32_t fifo_addr_cfg_en              :    1;
-            uint32_t rx_fifo_rst                   :    1;
-            uint32_t tx_fifo_rst                   :    1;
-            uint32_t fifo_prt_en                   :    1;
-            uint32_t reserved15                    :    5;
-            uint32_t reserved20                    :    6;
-            uint32_t reserved26                    :    1;
-            uint32_t reserved27                    :    5;
+            uint32_t rx_fifo_wm_thrhd              :    5;  /*The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. */
+            uint32_t tx_fifo_wm_thrhd              :    5;  /*The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. */
+            uint32_t nonfifo_en                    :    1;  /*Set this bit to enable APB nonfifo access. */
+            uint32_t fifo_addr_cfg_en              :    1;  /*When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. */
+            uint32_t rx_fifo_rst                   :    1;  /*Set this bit to reset rx-fifo.*/
+            uint32_t tx_fifo_rst                   :    1;  /*Set this bit to reset tx-fifo.*/
+            uint32_t fifo_prt_en                   :    1;  /*The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.*/
+            uint32_t reserved15                    :    5;  /*Reserved*/
+            uint32_t reserved20                    :    6;  /*Reserved*/
+            uint32_t reserved26                    :    1;  /*Reserved*/
+            uint32_t reserved27                    :    5;  /*Reserved*/
         };
         uint32_t val;
     } fifo_conf;
     union {
         struct {
-            uint32_t data                           :   8;
-            uint32_t reserved8                      :   24;
+            uint32_t data                          :    8;  /*The value of rx FIFO read data.*/
+            uint32_t reserved8                     :    24;  /*Reserved*/
         };
         uint32_t val;
     } fifo_data;
     union {
         struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
+            uint32_t rx_fifo_wm                    :    1;  /*The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.*/
+            uint32_t tx_fifo_wm                    :    1;  /*The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.*/
+            uint32_t rx_fifo_ovf                   :    1;  /*The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.*/
+            uint32_t end_detect                    :    1;  /*The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t byte_trans_done               :    1;  /*The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t arbitration_lost              :    1;  /*The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. */
+            uint32_t mst_tx_fifo_udf               :    1;  /*The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t trans_complete                :    1;  /*The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t time_out                      :    1;  /*The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. */
+            uint32_t trans_start                   :    1;  /*The raw interrupt bit for the I2C_TRANS_START_INT interrupt.*/
+            uint32_t nack                          :    1;  /*The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t tx_fifo_ovf                   :    1;  /*The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.*/
+            uint32_t rx_fifo_udf                   :    1;  /*The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.*/
+            uint32_t scl_st_to                     :    1;  /*The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.*/
+            uint32_t scl_main_st_to                :    1;  /*The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/
+            uint32_t det_start                     :    1;  /*The raw interrupt bit for I2C_DET_START_INT interrupt.*/
+            uint32_t slave_stretch                 :    1;  /*The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t general_call                  :    1;  /*The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
         };
         uint32_t val;
     } int_raw;
     union {
         struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
+            uint32_t rx_fifo_wm                    :    1;  /*Set this bit to clear I2C_RXFIFO_WM_INT interrupt.*/
+            uint32_t tx_fifo_wm                    :    1;  /*Set this bit to clear I2C_TXFIFO_WM_INT interrupt.*/
+            uint32_t rx_fifo_ovf                   :    1;  /*Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.*/
+            uint32_t end_detect                    :    1;  /*Set this bit to clear the I2C_END_DETECT_INT interrupt. */
+            uint32_t byte_trans_done               :    1;  /*Set this bit to clear the I2C_END_DETECT_INT interrupt. */
+            uint32_t arbitration_lost              :    1;  /*Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. */
+            uint32_t mst_tx_fifo_udf               :    1;  /*Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t trans_complete                :    1;  /*Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t time_out                      :    1;  /*Set this bit to clear the I2C_TIME_OUT_INT interrupt. */
+            uint32_t trans_start                   :    1;  /*Set this bit to clear the I2C_TRANS_START_INT interrupt.*/
+            uint32_t nack                          :    1;  /*Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t tx_fifo_ovf                   :    1;  /*Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.*/
+            uint32_t rx_fifo_udf                   :    1;  /*Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.*/
+            uint32_t scl_st_to                     :    1;  /*Set this bit to clear I2C_SCL_ST_TO_INT interrupt.*/
+            uint32_t scl_main_st_to                :    1;  /*Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.*/
+            uint32_t det_start                     :    1;  /*Set this bit to clear I2C_DET_START_INT interrupt.*/
+            uint32_t slave_stretch                 :    1;  /*Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t general_call                  :    1;  /*Set this bit for I2C_GENARAL_CALL_INT interrupt.*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
         };
         uint32_t val;
     } int_clr;
     union {
         struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
+            uint32_t rx_fifo_wm                    :    1;  /*The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.*/
+            uint32_t tx_fifo_wm                    :    1;  /*The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.*/
+            uint32_t rx_fifo_ovf                   :    1;  /*The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.*/
+            uint32_t end_detect                    :    1;  /*The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t byte_trans_done               :    1;  /*The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t arbitration_lost              :    1;  /*The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. */
+            uint32_t mst_tx_fifo_udf               :    1;  /*The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t trans_complete                :    1;  /*The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t time_out                      :    1;  /*The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. */
+            uint32_t trans_start                   :    1;  /*The interrupt enable bit for the I2C_TRANS_START_INT interrupt.*/
+            uint32_t nack                          :    1;  /*The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t tx_fifo_ovf                   :    1;  /*The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.*/
+            uint32_t rx_fifo_udf                   :    1;  /*The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.*/
+            uint32_t scl_st_to                     :    1;  /*The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.*/
+            uint32_t scl_main_st_to                :    1;  /*The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/
+            uint32_t det_start                     :    1;  /*The interrupt enable bit for I2C_DET_START_INT interrupt.*/
+            uint32_t slave_stretch                 :    1;  /*The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t general_call                  :    1;  /*The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
         };
         uint32_t val;
     } int_ena;
     union {
         struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
+            uint32_t rx_fifo_wm                    :    1;  /*The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.*/
+            uint32_t tx_fifo_wm                    :    1;  /*The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.*/
+            uint32_t rx_fifo_ovf                   :    1;  /*The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.*/
+            uint32_t end_detect                    :    1;  /*The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t byte_trans_done               :    1;  /*The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */
+            uint32_t arbitration_lost              :    1;  /*The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. */
+            uint32_t mst_tx_fifo_udf               :    1;  /*The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t trans_complete                :    1;  /*The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.*/
+            uint32_t time_out                      :    1;  /*The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. */
+            uint32_t trans_start                   :    1;  /*The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.*/
+            uint32_t nack                          :    1;  /*The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t tx_fifo_ovf                   :    1;  /*The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.*/
+            uint32_t rx_fifo_udf                   :    1;  /*The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.*/
+            uint32_t scl_st_to                     :    1;  /*The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.*/
+            uint32_t scl_main_st_to                :    1;  /*The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/
+            uint32_t det_start                     :    1;  /*The masked interrupt status bit for I2C_DET_START_INT interrupt.*/
+            uint32_t slave_stretch                 :    1;  /*The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.*/
+            uint32_t general_call                  :    1;  /*The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
         };
         uint32_t val;
     } int_status;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure the time to hold the data after the negative; edge of SCL, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } sda_hold;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure for how long SDA is sampled, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } sda_sample;
     union {
         struct {
-            uint32_t period                        :    9;
-            uint32_t scl_wait_high_period          :    7;
-            uint32_t reserved16                    :    16;
+            uint32_t period                        :    9;  /*This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. */
+            uint32_t scl_wait_high_period          :    7;  /*This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. */
+            uint32_t reserved16                    :    16;  /*Reserved*/
         };
         uint32_t val;
     } scl_high_period;
     uint32_t reserved_3c;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure the time between the negative edge; of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } scl_start_hold;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure the time between the positive; edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } scl_rstart_setup;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure the delay after the STOP condition,; in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } scl_stop_hold;
     union {
         struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t time                          :    9;  /*This register is used to configure the time between the positive edge; of SCL and the positive edge of SDA, in I2C module clock cycles. */
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } scl_stop_setup;
     union {
         struct {
-            uint32_t scl_thres                     :    4;
-            uint32_t sda_thres                     :    4;
-            uint32_t scl_en                        :    1;
-            uint32_t sda_en                        :    1;
-            uint32_t reserved10                    :    22;
+            uint32_t scl_thres                     :    4;  /*When a pulse on the SCL input has smaller width than this register value; in I2C module clock cycles, the I2C controller will ignore that pulse. */
+            uint32_t sda_thres                     :    4;  /*When a pulse on the SDA input has smaller width than this register value; in I2C module clock cycles, the I2C controller will ignore that pulse. */
+            uint32_t scl_en                        :    1;  /*This is the filter enable bit for SCL. */
+            uint32_t sda_en                        :    1;  /*This is the filter enable bit for SDA. */
+            uint32_t reserved10                    :    22;  /*Reserved*/
         };
         uint32_t val;
     } filter_cfg;
     union {
         struct {
-            uint32_t sclk_div_num                  :    8;
-            uint32_t sclk_div_a                    :    6;
-            uint32_t sclk_div_b                    :    6;
-            uint32_t sclk_sel                      :    1;
-            uint32_t sclk_active                   :    1;
-            uint32_t reserved22                    :    10;
+            uint32_t sclk_div_num                  :    8;  /*the integral part of the fractional divisor for i2c module*/
+            uint32_t sclk_div_a                    :    6;  /*the numerator of the fractional part of the fractional divisor for i2c module*/
+            uint32_t sclk_div_b                    :    6;  /*the denominator of the fractional part of the fractional divisor for i2c module*/
+            uint32_t sclk_sel                      :    1;  /*The clock selection for i2c module:0-XTAL;1-CLK_8MHz.*/
+            uint32_t sclk_active                   :    1;  /*The clock switch for i2c module*/
+            uint32_t reserved22                    :    10;  /*Reserved*/
         };
         uint32_t val;
     } clk_conf;
@@ -303,36 +304,36 @@ typedef volatile struct {
     } command[8];
     union {
         struct {
-            uint32_t scl_st_to                     :    5;  /*no more than 23*/
-            uint32_t reserved5                     :    27;
+            uint32_t scl_st_to                     :    5;  /*The threshold value of SCL_FSM state unchanged period. It should be o more than 23*/
+            uint32_t reserved5                     :    27;  /*Reserved*/
         };
         uint32_t val;
     } scl_st_time_out;
     union {
         struct {
-            uint32_t scl_main_st_to                :    5;  /*no more than 23*/
-            uint32_t reserved5                     :    27;
+            uint32_t scl_main_st_to                :    5;  /*The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23*/
+            uint32_t reserved5                     :    27;  /*Reserved*/
         };
         uint32_t val;
     } scl_main_st_time_out;
     union {
         struct {
-            uint32_t scl_rst_slv_en                :    1;
-            uint32_t scl_rst_slv_num               :    5;
-            uint32_t scl_pd_en                     :    1;
-            uint32_t sda_pd_en                     :    1;
-            uint32_t reserved8                     :    24;
+            uint32_t scl_rst_slv_en                :    1;  /*When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].*/
+            uint32_t scl_rst_slv_num               :    5;  /*Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.*/
+            uint32_t scl_pd_en                     :    1;  /*The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.*/
+            uint32_t sda_pd_en                     :    1;  /*The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.*/
+            uint32_t reserved8                     :    24;  /*Reserved*/
         };
         uint32_t val;
     } scl_sp_conf;
     union {
         struct {
-            uint32_t stretch_protect_num           :    10;
-            uint32_t slave_scl_stretch_en          :    1;
-            uint32_t slave_scl_stretch_clr         :    1;
-            uint32_t slave_byte_ack_ctl_en         :    1;
-            uint32_t slave_byte_ack_level          :    1;
-            uint32_t reserved14                    :    18;
+            uint32_t stretch_protect_num           :    10;  /*Configure the period of I2C slave stretching SCL line.*/
+            uint32_t slave_scl_stretch_en          :    1;  /*The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause.*/
+            uint32_t slave_scl_stretch_clr         :    1;  /*Set this bit to clear the I2C slave SCL stretch function.*/
+            uint32_t slave_byte_ack_ctl_en         :    1;  /*The enable bit for slave to control ACK level function.*/
+            uint32_t slave_byte_ack_level          :    1;  /*Set the ACK level when slave controlling ACK level function enables.*/
+            uint32_t reserved14                    :    18;  /*Reserved*/
         };
         uint32_t val;
     } scl_stretch_conf;
@@ -405,3 +406,7 @@ extern i2c_dev_t I2C1;
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_I2C_STRUCT_H_ */

components/soc/esp32s3/include/soc/i2s_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_I2S_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0xC)
 /* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
@@ -1096,6 +1096,7 @@ n counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
 #define I2S_DATE_V  0xFFFFFFF
 #define I2S_DATE_S  0
 
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/include/soc/i2s_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,9 @@
 // limitations under the License.
 #ifndef _SOC_I2S_STRUCT_H_
 #define _SOC_I2S_STRUCT_H_
+
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -156,60 +159,60 @@ typedef volatile struct {
     } rx_clkm_conf;
     union {
         struct {
-            uint32_t tx_clkm_div_num: 8;                  /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
-            uint32_t reserved8:      18;                  /*Reserved*/
-            uint32_t tx_clk_active:   1;                  /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel:      2;                  /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
-            uint32_t clk_en:          1;                  /*Set this bit to enable clk gate*/
-            uint32_t reserved30:      2;                  /*Reserved*/
+            uint32_t tx_clkm_div_num               :    8;  /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
+            uint32_t reserved8                     :    18;  /* Reserved*/
+            uint32_t tx_clk_active                 :    1;  /*I2S Tx module clock enable signal.*/
+            uint32_t tx_clk_sel                    :    2;  /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
         };
         uint32_t val;
     } tx_clkm_conf;
     union {
         struct {
-            uint32_t rx_clkm_div_z:   9;                  /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
-            uint32_t rx_clkm_div_y:   9;                  /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
-            uint32_t rx_clkm_div_x:   9;                  /*For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-            uint32_t rx_clkm_div_yn1: 1;                  /*For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
-            uint32_t reserved28:      4;                  /*Reserved*/
+            uint32_t rx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). */
+            uint32_t rx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). */
+            uint32_t rx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. */
+            uint32_t rx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. */
+            uint32_t reserved28                    :    4;  /* Reserved*/
         };
         uint32_t val;
     } rx_clkm_div_conf;
     union {
         struct {
-            uint32_t tx_clkm_div_z:   9;                  /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
-            uint32_t tx_clkm_div_y:   9;                  /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
-            uint32_t tx_clkm_div_x:   9;                  /*For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-            uint32_t tx_clkm_div_yn1: 1;                  /*For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
-            uint32_t reserved28:      4;                  /*Reserved*/
+            uint32_t tx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). */
+            uint32_t tx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). */
+            uint32_t tx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. */
+            uint32_t tx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. */
+            uint32_t reserved28                    :    4;  /* Reserved*/
         };
         uint32_t val;
     } tx_clkm_div_conf;
     union {
         struct {
-            uint32_t txhp_bypass:                1;       /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
-            uint32_t tx_sinc_osr2:               4;       /*I2S TX PDM OSR2 value*/
-            uint32_t tx_prescale:                8;       /*I2S TX PDM prescale for sigmadelta*/
-            uint32_t tx_hp_in_shift:             2;       /*I2S TX PDM sigmadelta scale shift number: 0:/2   1:x1   2:x2   3: x4*/
-            uint32_t tx_lp_in_shift:             2;       /*I2S TX PDM sigmadelta scale shift number: 0:/2   1:x1   2:x2   3: x4*/
-            uint32_t tx_sinc_in_shift:           2;       /*I2S TX PDM sigmadelta scale shift number: 0:/2   1:x1   2:x2   3: x4*/
-            uint32_t tx_sigmadelta_in_shift:     2;       /*I2S TX PDM sigmadelta scale shift number: 0:/2   1:x1   2:x2   3: x4*/
-            uint32_t tx_sigmadelta_dither2:      1;       /*I2S TX PDM sigmadelta dither2 value*/
-            uint32_t tx_sigmadelta_dither:       1;       /*I2S TX PDM sigmadelta dither value*/
-            uint32_t tx_dac_2out_en:             1;       /*I2S TX PDM dac mode enable*/
-            uint32_t tx_dac_mode_en:             1;       /*I2S TX PDM dac 2channel enable*/
-            uint32_t pcm2pdm_conv_en:            1;       /*I2S TX PDM Converter enable*/
-            uint32_t reserved26:                 6;       /*Reserved*/
+            uint32_t tx_hp_bypass                  :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
+            uint32_t tx_sinc_osr2                  :    4;  /*I2S TX PDM OSR2 value*/
+            uint32_t tx_prescale                   :    8;  /*I2S TX PDM prescale for sigmadelta*/
+            uint32_t tx_hp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_lp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sinc_in_shift              :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sigmadelta_in_shift        :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sigmadelta_dither2         :    1;  /*I2S TX PDM sigmadelta dither2 value*/
+            uint32_t tx_sigmadelta_dither          :    1;  /*I2S TX PDM sigmadelta dither value*/
+            uint32_t tx_dac_2out_en                :    1;  /*I2S TX PDM dac mode enable*/
+            uint32_t tx_dac_mode_en                :    1;  /*I2S TX PDM dac 2channel enable*/
+            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
         };
         uint32_t val;
     } tx_pcm2pdm_conf;
     union {
         struct {
-            uint32_t tx_pdm_fp:         10;               /*I2S TX PDM Fp*/
-            uint32_t tx_pdm_fs:         10;               /*I2S TX PDM Fs*/
-            uint32_t tx_iir_hp_mult12_5: 3;               /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
-            uint32_t tx_iir_hp_mult12_0: 3;               /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
-            uint32_t reserved26:         6;               /*Reserved*/
+            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
+            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
+            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
+            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
         };
         uint32_t val;
     } tx_pcm2pdm_conf1;
@@ -217,110 +220,110 @@ typedef volatile struct {
     uint32_t reserved_4c;
     union {
         struct {
-            uint32_t rx_tdm_chan0_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan1_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan2_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan3_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan4_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan5_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan6_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan7_en:     1;              /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan8_en:     1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan9_en:     1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan10_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan11_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan12_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan13_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan14_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_chan15_en:    1;              /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable  just input 0 in this channel.*/
-            uint32_t rx_tdm_tot_chan_num: 4;              /*The total channel number of I2S TX TDM mode.*/
-            uint32_t reserved20:         12;              /*Reserved*/
+            uint32_t rx_tdm_chan0_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan1_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan2_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan3_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan4_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan5_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan6_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan7_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
+            uint32_t reserved20                    :    12;  /* Reserved*/
         };
         uint32_t val;
     } rx_tdm_ctrl;
     union {
         struct {
-            uint32_t tx_tdm_chan0_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan1_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan2_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan3_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan4_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan5_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan6_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan7_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan8_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan9_en:     1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan10_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan11_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan12_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan13_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan14_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan15_en:    1;              /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_tot_chan_num: 4;              /*The total channel number of I2S TX TDM mode.*/
-            uint32_t tx_tdm_skip_msk_en:  1;              /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
-            uint32_t reserved21:         11;              /*Reserved*/
+            uint32_t tx_tdm_chan0_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan1_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan2_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan3_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan4_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan5_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan6_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan7_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan8_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan9_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan10_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan11_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan12_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan13_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan14_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan15_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
+            uint32_t tx_tdm_skip_msk_en            :    1;  /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+            uint32_t reserved21                    :    11;  /* Reserved*/
         };
         uint32_t val;
     } tx_tdm_ctrl;
     union {
         struct {
-            uint32_t rx_sd_in_dm:   2;                    /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2:     2;
-            uint32_t rx_sd1_in_dm:  2;                    /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved6:     2;
-            uint32_t rx_sd2_in_dm:  2;                    /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved10:    2;
-            uint32_t rx_sd3_in_dm:  2;                    /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved14:    2;
-            uint32_t rx_ws_out_dm:  2;                    /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18:    2;                    /*Reserved*/
-            uint32_t rx_bck_out_dm: 2;                    /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22:    2;                    /*Reserved*/
-            uint32_t rx_ws_in_dm:   2;                    /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26:    2;                    /*Reserved*/
-            uint32_t rx_bck_in_dm:  2;                    /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30:    2;                    /*Reserved*/
+            uint32_t rx_sd_in_dm                   :    2;  /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;
+            uint32_t rx_sd1_in_dm                  :    2;  /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    2;
+            uint32_t rx_sd2_in_dm                  :    2;  /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved10                    :    2;
+            uint32_t rx_sd3_in_dm                  :    2;  /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved14                    :    2;
+            uint32_t rx_ws_out_dm                  :    2;  /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t rx_bck_out_dm                 :    2;  /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t rx_ws_in_dm                   :    2;  /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t rx_bck_in_dm                  :    2;  /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
         };
         uint32_t val;
     } rx_timing;
     union {
         struct {
-            uint32_t tx_sd_out_dm:  2;                    /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2:     2;                    /*Reserved*/
-            uint32_t tx_sd1_out_dm: 2;                    /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved6:    10;                    /*Reserved*/
-            uint32_t tx_ws_out_dm:  2;                    /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18:    2;                    /*Reserved*/
-            uint32_t tx_bck_out_dm: 2;                    /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22:    2;                    /*Reserved*/
-            uint32_t tx_ws_in_dm:   2;                    /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26:    2;                    /*Reserved*/
-            uint32_t tx_bck_in_dm:  2;                    /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30:    2;                    /*Reserved*/
+            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;  /* Reserved*/
+            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    10;  /* Reserved*/
+            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
         };
         uint32_t val;
     } tx_timing;
     union {
         struct {
-            uint32_t fifo_timeout:          8;            /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
-            uint32_t fifo_timeout_shift:    3;            /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
-            uint32_t fifo_timeout_ena:      1;            /*The enable bit for FIFO timeout*/
-            uint32_t reserved12:           20;            /*Reserved*/
+            uint32_t fifo_timeout                  :    8;  /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value  */
+            uint32_t fifo_timeout_shift            :    3;  /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+            uint32_t fifo_timeout_ena              :    1;  /*The enable bit for FIFO timeout*/
+            uint32_t reserved12                    :    20;  /* Reserved*/
         };
         uint32_t val;
     } lc_hung_conf;
     union {
         struct {
-            uint32_t rx_eof_num:12;                       /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
-            uint32_t reserved12:20;                       /*Reserved*/
+            uint32_t rx_eof_num                    :    12;  /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
+            uint32_t reserved12                    :    20;  /* Reserved*/
         };
         uint32_t val;
     } rxeof_num;
-    uint32_t conf_sigle_data;                             /*I2S signal data register*/
+    uint32_t conf_sigle_data;
     union {
         struct {
-            uint32_t tx_idle:    1;                       /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
-            uint32_t reserved1: 31;                       /*Reserved*/
+            uint32_t tx_idle                       :    1;  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
+            uint32_t reserved1                     :    31;  /* Reserved*/
         };
         uint32_t val;
     } state;
@@ -330,8 +333,8 @@ typedef volatile struct {
     uint32_t reserved_7c;
     union {
         struct {
-            uint32_t date:      28;                       /*I2S version control register*/
-            uint32_t reserved28: 4;                       /*Reserved*/
+            uint32_t date                          :    28;  /*I2S version control register*/
+            uint32_t reserved28                    :    4;  /* Reserved*/
         };
         uint32_t val;
     } date;
@@ -342,4 +345,6 @@ extern i2s_dev_t I2S1;
 }
 #endif
 
-#endif  /* _SOC_I2S_STRUCT_H_ */
+
+
+#endif /*_SOC_I2S_STRUCT_H_ */

components/soc/esp32s3/include/soc/interrupt_core0_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_INTERRUPT_CORE0_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define DR_REG_INTERRUPT_CORE0_BASE                 DR_REG_INTERRUPT_BASE
 

components/soc/esp32s3/include/soc/interrupt_core0_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,7 @@
 // limitations under the License.
 #ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_
 #define _SOC_INTERRUPT_CORE0_STRUCT_H_
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/interrupt_core1_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_INTERRUPT_CORE1_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define DR_REG_INTERRUPT_CORE1_BASE                 DR_REG_INTERRUPT_BASE
 

components/soc/esp32s3/include/soc/interrupt_core1_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,7 @@
 // limitations under the License.
 #ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_
 #define _SOC_INTERRUPT_CORE1_STRUCT_H_
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/interrupt_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,7 +11,21 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_INTERRUPT_REG_H_
+#define _SOC_INTERRUPT_REG_H_
 
 #include "interrupt_core0_reg.h"
 #include "interrupt_core1_reg.h"
+#include "soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_REG_H_ */

components/soc/esp32s3/include/soc/interrupt_struct.h

@@ -0,0 +1,32 @@
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_INTERRUPT_STRUCT_H_
+#define _SOC_INTERRUPT_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+} interrupt_dev_t;
+extern interrupt_dev_t INTERRUPT;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_STRUCT_H_ */

components/soc/esp32s3/include/soc/lcd_cam_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_LCD_CAM_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define LCD_CAM_LCD_CLOCK_REG          (DR_REG_LCD_CAM_BASE + 0x0)
 /* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */

components/soc/esp32s3/include/soc/lcd_cam_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,10 +11,11 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_LCD_CAM_STRUCT_H_
+#define _SOC_LCD_CAM_STRUCT_H_
 
-#include <stdint.h>
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -22,181 +23,180 @@ extern "C" {
 typedef volatile struct {
     union {
         struct {
-            uint32_t lcd_clkcnt_n:       6; /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
-            uint32_t lcd_clk_equ_sysclk: 1; /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
-            uint32_t lcd_ck_idle_edge:   1; /*1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.*/
-            uint32_t lcd_ck_out_edge:    1; /*1: LCD_PCLK is high on the first half clock 0: LCD_PCLK is high on the second half clock*/
-            uint32_t lcd_clkm_div_num:   8; /*Integral LCD clock divider value*/
-            uint32_t lcd_clkm_div_b:     6; /*Fractional clock divider numerator value*/
-            uint32_t lcd_clkm_div_a:     6; /*Fractional clock divider denominator value*/
-            uint32_t lcd_clk_sel:        2; /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t clk_en:             1; /*Set this bit to enable clk gate*/
+            uint32_t lcd_clkcnt_n                  :    6;  /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
+            uint32_t lcd_clk_equ_sysclk            :    1;  /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
+            uint32_t lcd_ck_idle_edge              :    1;  /*1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle. */
+            uint32_t lcd_ck_out_edge               :    1;
+            uint32_t lcd_clkm_div_num              :    8;  /*Integral LCD clock divider value*/
+            uint32_t lcd_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
+            uint32_t lcd_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
+            uint32_t lcd_clk_sel                   :    2;  /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
         };
         uint32_t val;
     } lcd_clock;
     union {
         struct {
-            uint32_t cam_stop_en:            1; /*Camera stop enable signal  1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
-            uint32_t cam_vsync_filter_thres: 3; /*Filter threshold value for CAM_VSYNC signal.*/
-            uint32_t cam_update:             1; /*1: Update Camera registers  will be cleared by hardware. 0 : Not care.*/
-            uint32_t cam_byte_order:         1; /*1: Change data bit order  change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode  and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t cam_bit_order:          1; /*1: invert data byte order  only valid in 2 byte mode. 0: Not change.*/
-            uint32_t cam_line_int_en:        1; /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
-            uint32_t cam_vs_eof_en:          1; /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
-            uint32_t cam_clkm_div_num:       8; /*Integral Camera clock divider value*/
-            uint32_t cam_clkm_div_b:         6; /*Fractional clock divider numerator value*/
-            uint32_t cam_clkm_div_a:         6; /*Fractional clock divider denominator value*/
-            uint32_t cam_clk_sel:            2; /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t reserved31:             1; /*reserved*/
+            uint32_t cam_stop_en                   :    1;  /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
+            uint32_t cam_vsync_filter_thres        :    3;  /*Filter threshold value for CAM_VSYNC signal.*/
+            uint32_t cam_update                    :    1;  /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/
+            uint32_t cam_byte_order                :    1;  /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
+            uint32_t cam_bit_order                 :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
+            uint32_t cam_line_int_en               :    1;  /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
+            uint32_t cam_vs_eof_en                 :    1;  /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
+            uint32_t cam_clkm_div_num              :    8;  /*Integral Camera clock divider value*/
+            uint32_t cam_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
+            uint32_t cam_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
+            uint32_t cam_clk_sel                   :    2;  /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
         };
         uint32_t val;
     } cam_ctrl;
     union {
         struct {
-            uint32_t cam_rec_data_bytelen: 14; /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
-            uint32_t cam_line_int_num:     7;  /*The line number minus 1 to generate cam_hs_int.*/
-            uint32_t cam_clk_inv:          1;  /*1: Invert  the input signal CAM_PCLK. 0: Not invert.*/
-            uint32_t reserved22:           1;  /*Reserved*/
-            uint32_t cam_vsync_filter_en:  1;  /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
-            uint32_t cam_2byte_en:         1;  /*1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.*/
-            uint32_t cam_de_inv:           1;  /*CAM_DE invert enable signal  valid in high level.*/
-            uint32_t cam_hsync_inv:        1;  /*CAM_HSYNC invert enable signal  valid in high level.*/
-            uint32_t cam_vsync_inv:        1;  /*CAM_VSYNC invert enable signal  valid in high level.*/
-            uint32_t cam_vh_de_mode_en:    1;  /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/
-            uint32_t cam_start:            1;  /*Camera module start signal.*/
-            uint32_t cam_reset:            1;  /*Camera module reset signal.*/
-            uint32_t cam_afifo_reset:      1;  /*Camera AFIFO reset signal.*/
+            uint32_t cam_rec_data_bytelen          :    16;  /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
+            uint32_t cam_line_int_num              :    6;  /*The line number minus 1 to generate cam_hs_int.*/
+            uint32_t cam_clk_inv                   :    1;  /*1: Invert  the input signal CAM_PCLK. 0: Not invert.*/
+            uint32_t cam_vsync_filter_en           :    1;  /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
+            uint32_t cam_2byte_en                  :    1;  /*1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8. */
+            uint32_t cam_de_inv                    :    1;  /*CAM_DE invert enable signal, valid in high level.*/
+            uint32_t cam_hsync_inv                 :    1;  /*CAM_HSYNC invert enable signal, valid in high level.*/
+            uint32_t cam_vsync_inv                 :    1;  /*CAM_VSYNC invert enable signal, valid in high level.*/
+            uint32_t cam_vh_de_mode_en             :    1;  /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/
+            uint32_t cam_start                     :    1;  /*Camera module start signal.*/
+            uint32_t cam_reset                     :    1;  /*Camera module reset signal.*/
+            uint32_t cam_afifo_reset               :    1;  /*Camera AFIFO reset signal.*/
         };
         uint32_t val;
     } cam_ctrl1;
     union {
         struct {
-            uint32_t reserved0:              21; /*reserved*/
-            uint32_t cam_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t cam_conv_yuv2yuv_mode:   2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode  trans_mode must be set to 1.*/
-            uint32_t cam_conv_yuv_mode:       2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode  yuv_mode decides the yuv mode of Data_in*/
-            uint32_t cam_conv_protocol_mode:  1; /*0:BT601. 1:BT709.*/
-            uint32_t cam_conv_data_out_mode:  1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t cam_conv_data_in_mode:   1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t cam_conv_mode_8bits_on:  1; /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t cam_conv_trans_mode:     1; /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t cam_conv_bypass:         1; /*0: Bypass converter. 1: Enable converter.*/
+            uint32_t reserved0                     :    21;  /*reserved*/
+            uint32_t cam_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
+            uint32_t cam_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
+            uint32_t cam_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
+            uint32_t cam_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
+            uint32_t cam_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
+            uint32_t cam_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
+            uint32_t cam_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
+            uint32_t cam_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
+            uint32_t cam_conv_bypass               :    1;  /*0: Bypass converter. 1: Enable converter.*/
         };
         uint32_t val;
     } cam_rgb_yuv;
     union {
         struct {
-            uint32_t reserved0:              20; /*reserved*/
-            uint32_t lcd_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t lcd_conv_txtorx:         1; /*0: txtorx mode off. 1: txtorx mode on.*/
-            uint32_t lcd_conv_yuv2yuv_mode:   2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode  trans_mode must be set to 1.*/
-            uint32_t lcd_conv_yuv_mode:       2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode  yuv_mode decides the yuv mode of Data_in*/
-            uint32_t lcd_conv_protocol_mode:  1; /*0:BT601. 1:BT709.*/
-            uint32_t lcd_conv_data_out_mode:  1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t lcd_conv_data_in_mode:   1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t lcd_conv_mode_8bits_on:  1; /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t lcd_conv_trans_mode:     1; /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t lcd_conv_bypass:         1; /*0: Bypass converter. 1: Enable converter.*/
+            uint32_t reserved0                     :    20;  /*reserved*/
+            uint32_t lcd_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
+            uint32_t lcd_conv_txtorx               :    1;  /*0: txtorx mode off. 1: txtorx mode on.*/
+            uint32_t lcd_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
+            uint32_t lcd_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
+            uint32_t lcd_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
+            uint32_t lcd_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
+            uint32_t lcd_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
+            uint32_t lcd_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
+            uint32_t lcd_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
+            uint32_t lcd_conv_bypass               :    1;  /*0: Bypass converter. 1: Enable converter.*/
         };
         uint32_t val;
     } lcd_rgb_yuv;
     union {
         struct {
-            uint32_t lcd_dout_cyclelen: 13; /*The output data cycles minus 1 of LCD module.*/
-            uint32_t lcd_always_out_en:  1; /*LCD always output when LCD is in LCD_DOUT state  unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
-            uint32_t reserved14:         5; /*reserved*/
-            uint32_t lcd_8bits_order:    1; /*1: invert every two data byte  valid in 1 byte mode. 0: Not change.*/
-            uint32_t lcd_update:         1; /*1: Update LCD registers  will be cleared by hardware. 0 : Not care.*/
-            uint32_t lcd_bit_order:      1; /*1: Change data bit order  change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode  and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t lcd_byte_order:     1; /*1: invert data byte order  only valid in 2 byte mode. 0: Not change.*/
-            uint32_t lcd_2byte_en:       1; /*1: The bit number of output LCD data is 0~15.  0: The bit number of output LCD data is 0~7.*/
-            uint32_t lcd_dout:           1; /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_dummy:          1; /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_cmd:            1; /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_start:          1; /*LCD start sending data enable signal  valid in high level.*/
-            uint32_t lcd_reset:          1; /*The value of  command.*/
-            uint32_t lcd_dummy_cyclelen: 2; /*The dummy cycle length minus 1.*/
-            uint32_t lcd_cmd_2_cycle_en: 1; /*The cycle length of command phase*/
+            uint32_t lcd_dout_cyclelen             :    13;  /*The output data cycles minus 1 of LCD module.*/
+            uint32_t lcd_always_out_en             :    1;  /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
+            uint32_t reserved14                    :    5;  /*reserved*/
+            uint32_t lcd_8bits_order               :    1;  /*1: invert every two data byte, valid in 1 byte mode. 0: Not change.*/
+            uint32_t lcd_update                    :    1;  /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/
+            uint32_t lcd_bit_order                 :    1;  /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
+            uint32_t lcd_byte_order                :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
+            uint32_t lcd_2byte_en                  :    1;  /*1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD data is 0~8. */
+            uint32_t lcd_dout                      :    1;  /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_dummy                     :    1;  /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_cmd                       :    1;  /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
+            uint32_t lcd_start                     :    1;  /*LCD start sending data enable signal, valid in high level.*/
+            uint32_t lcd_reset                     :    1;  /*The value of  command. */
+            uint32_t lcd_dummy_cyclelen            :    2;  /*The dummy cycle length minus 1.*/
+            uint32_t lcd_cmd_2_cycle_en            :    1;  /*The cycle length of command phase*/
         };
         uint32_t val;
     } lcd_user;
     union {
         struct {
-            uint32_t reserved0:               1; /*reserved*/
-            uint32_t lcd_afifo_threshold_num: 5; /*The awfull threshold number of lcd_afifo.*/
-            uint32_t lcd_vfk_cyclelen:        6; /*The setup cycle length minus 1 in LCD non-RGB mode.*/
-            uint32_t lcd_vbk_cyclelen:       13; /*The vertical back blank region cycle length minus 1 in LCD RGB mode  or the hold time cycle length in LCD non-RGB mode.*/
-            uint32_t lcd_next_frame_en:       1; /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
-            uint32_t lcd_bk_en:               1; /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
-            uint32_t lcd_afifo_reset:         1; /*LCD AFIFO reset signal.*/
-            uint32_t lcd_cd_data_set:         1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge.*/
-            uint32_t lcd_cd_dummy_set:        1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge.*/
-            uint32_t lcd_cd_cmd_set:          1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge.*/
-            uint32_t lcd_cd_idle_edge:        1; /*The default value of LCD_CD.*/
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t lcd_afifo_threshold_num       :    5;  /*The awfull threshold number of lcd_afifo.*/
+            uint32_t lcd_vfk_cyclelen              :    6;  /*The setup cycle length minus 1 in LCD non-RGB mode.*/
+            uint32_t lcd_vbk_cyclelen              :    13;  /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/
+            uint32_t lcd_next_frame_en             :    1;  /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
+            uint32_t lcd_bk_en                     :    1;  /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
+            uint32_t lcd_afifo_reset               :    1;  /*LCD AFIFO reset signal.*/
+            uint32_t lcd_cd_data_set               :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_dummy_set              :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_cmd_set                :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge. */
+            uint32_t lcd_cd_idle_edge              :    1;  /*The default value of LCD_CD. */
         };
         uint32_t val;
     } lcd_misc;
     union {
         struct {
-            uint32_t lcd_hb_front:   11; /*It is the horizontal blank front porch of a frame.*/
-            uint32_t lcd_va_height:  10; /*It is the vertical active height of a frame.*/
-            uint32_t lcd_vt_height:  10; /*It is the vertical total height of a frame.*/
-            uint32_t lcd_rgb_mode_en: 1; /*1: Enable reg mode input vsync*/
+            uint32_t lcd_hb_front                  :    11;  /*It is the horizontal blank front porch of a frame. */
+            uint32_t lcd_va_height                 :    10;  /*It is the vertical active height of a frame. */
+            uint32_t lcd_vt_height                 :    10;  /*It is the vertical total height of a frame. */
+            uint32_t lcd_rgb_mode_en               :    1;  /*1: Enable reg mode input vsync*/
         };
         uint32_t val;
     } lcd_ctrl;
     union {
         struct {
-            uint32_t lcd_vb_front: 8;  /*It is the vertical blank front porch of a frame.*/
-            uint32_t lcd_ha_width: 12; /*It is the horizontal active width of a frame.*/
-            uint32_t lcd_ht_width: 12; /*It is the horizontal total width of a frame.*/
+            uint32_t lcd_vb_front                  :    8;  /*It is the vertical blank front porch of a frame. */
+            uint32_t lcd_ha_width                  :    12;  /*It is the horizontal active width of a frame. */
+            uint32_t lcd_ht_width                  :    12;  /*It is the horizontal total width of a frame. */
         };
         uint32_t val;
     } lcd_ctrl1;
     union {
         struct {
-            uint32_t lcd_vsync_width:    7; /*It is the position of LCD_VSYNC active pulse in a line.*/
-            uint32_t lcd_vsync_idle_pol: 1; /*It is the idle value of LCD_VSYNC.*/
-            uint32_t lcd_de_idle_pol:    1; /*It is the idle value of LCD_DE.*/
-            uint32_t lcd_hs_blank_en:    1; /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/
-            uint32_t reserved10:         6; /*reserved*/
-            uint32_t lcd_hsync_width:    7; /*It is the position of LCD_HSYNC active pulse in a line.*/
-            uint32_t lcd_hsync_idle_pol: 1; /*It is the idle value of LCD_HSYNC.*/
-            uint32_t lcd_hsync_position: 8; /*It is the position of LCD_HSYNC active pulse in a line.*/
+            uint32_t lcd_vsync_width               :    7;  /*It is the position of LCD_VSYNC active pulse in a line. */
+            uint32_t lcd_vsync_idle_pol            :    1;  /*It is the idle value of LCD_VSYNC. */
+            uint32_t lcd_de_idle_pol               :    1;  /*It is the idle value of LCD_DE. */
+            uint32_t lcd_hs_blank_en               :    1;  /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */
+            uint32_t reserved10                    :    6;  /*reserved*/
+            uint32_t lcd_hsync_width               :    7;  /*It is the position of LCD_HSYNC active pulse in a line. */
+            uint32_t lcd_hsync_idle_pol            :    1;  /*It is the idle value of LCD_HSYNC. */
+            uint32_t lcd_hsync_position            :    8;  /*It is the position of LCD_HSYNC active pulse in a line. */
         };
         uint32_t val;
     } lcd_ctrl2;
-    uint32_t lcd_cmd_val; /*The LCD write command value.*/
+    uint32_t lcd_cmd_val;
     uint32_t reserved_2c;
     union {
         struct {
-            uint32_t lcd_cd_mode:    2; /*The output LCD_CD is delayed by module clock LCD_CLK*/
-            uint32_t lcd_de_mode:    2; /*The output LCD_DE is delayed by module clock LCD_CLK*/
-            uint32_t lcd_hsync_mode: 2; /*The output LCD_HSYNC is delayed by module clock LCD_CLK*/
-            uint32_t lcd_vsync_mode: 2; /*The output LCD_VSYNC is delayed by module clock LCD_CLK*/
-            uint32_t reserved8:     24; /*reserved*/
+            uint32_t lcd_cd_mode                   :    2;  /*The output LCD_CD is delayed by module clock LCD_CLK*/
+            uint32_t lcd_de_mode                   :    2;  /*The output LCD_DE is delayed by module clock LCD_CLK*/
+            uint32_t lcd_hsync_mode                :    2;  /*The output LCD_HSYNC is delayed by module clock LCD_CLK*/
+            uint32_t lcd_vsync_mode                :    2;  /*The output LCD_VSYNC is delayed by module clock LCD_CLK*/
+            uint32_t reserved8                     :    24;  /*reserved*/
         };
         uint32_t val;
     } lcd_dly_mode;
     uint32_t reserved_34;
     union {
         struct {
-            uint32_t dout0_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout1_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout2_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout3_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout4_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout5_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout6_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout7_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout8_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout9_mode:  2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout10_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout11_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout12_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout13_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout14_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout15_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout0_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout1_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout2_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout3_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout4_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout5_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout6_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout7_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout8_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout9_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout10_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout11_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout12_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout13_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout14_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
+            uint32_t dout15_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
         };
         uint32_t val;
     } lcd_data_dout_mode;
@@ -212,41 +212,41 @@ typedef volatile struct {
     uint32_t reserved_60;
     union {
         struct {
-            uint32_t lcd_vsync:      1; /*The enable bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done: 1; /*The enable bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync:      1; /*The enable bit for Camera frame end interrupt.*/
-            uint32_t cam_hs:         1; /*The enable bit for Camera line interrupt.*/
-            uint32_t reserved4:     28; /*reserved*/
+            uint32_t lcd_vsync                     :    1;  /*The enable bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The enable bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The enable bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The enable bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
         };
         uint32_t val;
     } lc_dma_int_ena;
     union {
         struct {
-            uint32_t lcd_vsync:       1; /*The raw bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done:  1; /*The raw bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync:       1; /*The raw bit for Camera frame end interrupt.*/
-            uint32_t cam_hs:          1; /*The raw bit for Camera line interrupt.*/
-            uint32_t reserved4:      28; /*reserved*/
+            uint32_t lcd_vsync                     :    1;  /*The raw bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The raw bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The raw bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The raw bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
         };
         uint32_t val;
     } lc_dma_int_raw;
     union {
         struct {
-            uint32_t lcd_vsync:       1; /*The status bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done:  1; /*The status bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync:       1; /*The status bit for Camera frame end interrupt.*/
-            uint32_t cam_hs:          1; /*The status bit for Camera transfer end interrupt.*/
-            uint32_t reserved4:      28; /*reserved*/
+            uint32_t lcd_vsync                     :    1;  /*The status bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The status bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The status bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The status bit for Camera transfer end interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
         };
         uint32_t val;
     } lc_dma_int_st;
     union {
         struct {
-            uint32_t lcd_vsync:       1; /*The clear bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done:  1; /*The clear bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync:       1; /*The clear bit for Camera frame end interrupt.*/
-            uint32_t cam_hs:          1; /*The clear bit for Camera line interrupt.*/
-            uint32_t reserved4:      28; /*reserved*/
+            uint32_t lcd_vsync                     :    1;  /*The clear bit for LCD frame end interrupt.*/
+            uint32_t lcd_trans_done                :    1;  /*The clear bit for lcd transfer end interrupt.*/
+            uint32_t cam_vsync                     :    1;  /*The clear bit for Camera frame end interrupt.*/
+            uint32_t cam_hs                        :    1;  /*The clear bit for Camera line interrupt.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
         };
         uint32_t val;
     } lc_dma_int_clr;
@@ -286,15 +286,17 @@ typedef volatile struct {
     uint32_t reserved_f8;
     union {
         struct {
-            uint32_t lc_date:   28; /*LCD_CAM version control register*/
-            uint32_t reserved28: 4; /*reserved*/
+            uint32_t lc_date                       :    28;  /*LCD_CAM version control register*/
+            uint32_t reserved28                    :    4;  /*reserved*/
         };
         uint32_t val;
     } lc_date;
 } lcd_cam_dev_t;
-
 extern lcd_cam_dev_t LCD_CAM;
-
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_LCD_CAM_STRUCT_H_ */

components/soc/esp32s3/include/soc/ledc_reg.h

@@ -13,6 +13,7 @@
 // limitations under the License.
 #pragma once
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/ledc_struct.h

@@ -13,6 +13,7 @@
 // limitations under the License.
 #pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/mcpwm_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,12 +11,16 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_MCPWM_REG_H_
+#define _SOC_MCPWM_REG_H_
 
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+
+#define REG_MCPWM_BASE(i)             (DR_REG_PWM0_BASE + i * (0xE000))
 
 #define MCPWM_CLK_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0)
 /* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
@@ -2896,6 +2900,11 @@ ze.*/
 #define MCPWM_DATE_V  0xFFFFFFF
 #define MCPWM_DATE_S  0
 
+
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_MCPWM_REG_H_ */

components/soc/esp32s3/include/soc/mcpwm_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,14 +11,15 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_MCPWM_STRUCT_H_
+#define _SOC_MCPWM_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
@@ -454,3 +455,7 @@ extern mcpwm_dev_t MCPWM1;
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_MCPWM_STRUCT_H_ */

components/soc/esp32s3/include/soc/pcnt_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_PCNT_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define PCNT_U0_CONF0_REG          (DR_REG_PCNT_BASE + 0x0)
 /* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */

components/soc/esp32s3/include/soc/pcnt_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,14 +11,15 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_PCNT_STRUCT_H_
+#define _SOC_PCNT_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     struct {
         union {
@@ -175,3 +176,7 @@ extern pcnt_dev_t PCNT;
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_PCNT_STRUCT_H_ */

components/soc/esp32s3/include/soc/peri_backup_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_PERI_BACKUP_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define PERI_BACKUP_CONFIG_REG          (DR_REG_PERI_BACKUP_BASE + 0x0)
 /* PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */

components/soc/esp32s3/include/soc/peri_backup_struct.h

@@ -0,0 +1,143 @@
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_PERI_BACKUP_STRUCT_H_
+#define _SOC_PERI_BACKUP_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reg_peri_backup_flow_err      :    3;
+            uint32_t reg_peri_backup_addr_map_mode :    1;
+            uint32_t reg_peri_backup_burst_limit   :    5;
+            uint32_t reg_peri_backup_tout_thres    :    10;
+            uint32_t reg_peri_backup_size          :    10;
+            uint32_t reg_peri_backup_start         :    1;
+            uint32_t reg_peri_backup_to_mem        :    1;
+            uint32_t reg_peri_backup_ena           :    1;
+        };
+        uint32_t val;
+    } config;
+    uint32_t apb_addr;
+    uint32_t mem_addr;
+    uint32_t reg_map0;
+    uint32_t reg_map1;
+    uint32_t reg_map2;
+    uint32_t reg_map3;
+    union {
+        struct {
+            uint32_t reg_peri_backup_done_int_raw  :    1;
+            uint32_t reg_peri_backup_err_int_raw   :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t reg_peri_backup_done_int_st   :    1;
+            uint32_t reg_peri_backup_err_int_st    :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t reg_peri_backup_done_int_ena  :    1;
+            uint32_t reg_peri_backup_err_int_ena   :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t reg_peri_backup_done_int_clr  :    1;
+            uint32_t reg_peri_backup_err_int_clr   :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t reg_date                      :    28;
+            uint32_t reserved28                    :    3;
+            uint32_t reg_clk_en                    :    1;  /*register file clk gating*/
+        };
+        uint32_t val;
+    } date;
+} peri_backup_dev_t;
+extern peri_backup_dev_t PERI_BACKUP;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_PERI_BACKUP_STRUCT_H_ */

components/soc/esp32s3/include/soc/rmt_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,311 +15,311 @@
 #define _SOC_RMT_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     uint32_t data_ch[8];
     union {
         struct {
-            uint32_t tx_start                      :    1;
-            uint32_t mem_rd_rst                    :    1;
-            uint32_t mem_rst                       :    1;
-            uint32_t tx_conti_mode                 :    1;
-            uint32_t mem_tx_wrap_en                :    1;
-            uint32_t idle_out_lv                   :    1;
-            uint32_t idle_out_en                   :    1;
-            uint32_t tx_stop                       :    1;
-            uint32_t div_cnt                       :    8;
-            uint32_t mem_size                      :    4;
-            uint32_t carrier_eff_en                :    1;
-            uint32_t carrier_en                    :    1;
-            uint32_t carrier_out_lv                :    1;
-            uint32_t afifo_rst                     :    1;
-            uint32_t conf_update                   :    1;
-            uint32_t reserved25                    :    7;
+            uint32_t tx_start                      :    1;  /*Set this bit to start sending data on CHANNEL$n.*/
+            uint32_t mem_rd_rst                    :    1;  /*Set this bit to reset read ram address for CHANNEL$n by accessing transmitter.*/
+            uint32_t mem_rst                       :    1;  /*Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo.*/
+            uint32_t tx_conti_mode                 :    1;  /*Set this bit to restart transmission  from the first data to the last data in CHANNEL$n.*/
+            uint32_t mem_tx_wrap_en                :    1;  /*This is the channel $n enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.*/
+            uint32_t idle_out_lv                   :    1;  /*This bit configures the level of output signal in CHANNEL$n when the latter is in IDLE state.*/
+            uint32_t idle_out_en                   :    1;  /*This is the output enable-control bit for CHANNEL$n in IDLE state.*/
+            uint32_t tx_stop                       :    1;  /*Set this bit to stop the transmitter of CHANNEL$n sending data out.*/
+            uint32_t div_cnt                       :    8;  /*This register is used to configure the divider for clock of CHANNEL$n.*/
+            uint32_t mem_size                      :    4;  /*This register is used to configure the maximum size of memory allocated to CHANNEL$n.*/
+            uint32_t carrier_eff_en                :    1;  /*1: Add carrier modulation on the output signal only at the send data state for CHANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNEL$n. Only valid when RMT_CARRIER_EN_CH$n is 1.*/
+            uint32_t carrier_en                    :    1;  /*This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.*/
+            uint32_t carrier_out_lv                :    1;  /*This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level.*/
+            uint32_t afifo_rst                     :    1;  /*Reserved*/
+            uint32_t conf_update                   :    1;  /*synchronization bit for CHANNEL$n*/
+            uint32_t reserved25                    :    7;  /*Reserved*/
         };
         uint32_t val;
     } tx_conf[4];
     struct {
         union {
             struct {
-                uint32_t div_cnt                       :    8;
-                uint32_t idle_thres                    :    15;
-                uint32_t reserved23                    :    1;
-                uint32_t mem_size                      :    4;
-                uint32_t carrier_en                    :    1;
-                uint32_t carrier_out_lv                :    1;
-                uint32_t reserved30                    :    2;
+                uint32_t div_cnt                       :    8;  /*This register is used to configure the divider for clock of CHANNEL$m.*/
+                uint32_t idle_thres                    :    15;  /*When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.*/
+                uint32_t reserved23                    :    1;  /*Reserved*/
+                uint32_t mem_size                      :    4;  /*This register is used to configure the maximum size of memory allocated to CHANNEL$m.*/
+                uint32_t carrier_en                    :    1;  /*This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.*/
+                uint32_t carrier_out_lv                :    1;  /*This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level.*/
+                uint32_t reserved30                    :    2;  /*Reserved*/
             };
             uint32_t val;
         } conf0;
         union {
             struct {
-                uint32_t rx_en                         :    1;
-                uint32_t mem_wr_rst                    :    1;
-                uint32_t mem_rst                       :    1;
-                uint32_t mem_owner                     :    1;
-                uint32_t rx_filter_en                  :    1;
-                uint32_t rx_filter_thres               :    8;
-                uint32_t mem_rx_wrap_en                :    1;
-                uint32_t afifo_rst                     :    1;
-                uint32_t conf_update                   :    1;
-                uint32_t reserved16                    :    16;
+                uint32_t rx_en                         :    1;  /*Set this bit to enable receiver to receive data on CHANNEL$m.*/
+                uint32_t mem_wr_rst                    :    1;  /*Set this bit to reset write ram address for CHANNEL$m by accessing receiver.*/
+                uint32_t mem_rst                       :    1;  /*Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo.*/
+                uint32_t mem_owner                     :    1;  /*This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is using the ram. ; ; 1'h0: APB bus is using the ram.*/
+                uint32_t rx_filter_en                  :    1;  /*This is the receive filter's enable bit for CHANNEL$m.*/
+                uint32_t rx_filter_thres               :    8;  /*Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).*/
+                uint32_t mem_rx_wrap_en                :    1;  /*This is the channel $m enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.*/
+                uint32_t afifo_rst                     :    1;  /*Reserved*/
+                uint32_t conf_update                   :    1;  /*synchronization bit for CHANNEL$m*/
+                uint32_t reserved16                    :    16;  /*Reserved*/
             };
             uint32_t val;
         } conf1;
     } rx_conf[4];
     union {
         struct {
-            uint32_t mem_raddr_ex                  :    10;
-            uint32_t reserved10                    :    1;
-            uint32_t mem_waddr                     :    10;
-            uint32_t reserved21                    :    1;
-            uint32_t state                         :    3;
-            uint32_t mem_empty                     :    1;
-            uint32_t mem_wr_err                    :    1;
-            uint32_t reserved27                    :    5;
+            uint32_t mem_raddr_ex                  :    10;  /*This register records the memory address offset when transmitter of CHANNEL$n is using the RAM.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t mem_waddr                     :    10;  /*This register records the memory address offset when writes RAM over APB bus.*/
+            uint32_t reserved21                    :    1;  /*Reserved*/
+            uint32_t state                         :    3;  /*This register records the FSM status of CHANNEL$n.*/
+            uint32_t mem_empty                     :    1;  /*This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.*/
+            uint32_t mem_wr_err                    :    1;  /*This status bit will be set if the offset address out of memory size when writes via APB bus.*/
+            uint32_t reserved27                    :    5;  /*Reserved*/
         };
         uint32_t val;
     } tx_status[4];
     union {
         struct {
-            uint32_t mem_waddr_ex                  :    10;
-            uint32_t reserved10                    :    1;
-            uint32_t mem_raddr                     :    10;
-            uint32_t reserved21                    :    1;
-            uint32_t state                         :    3;
-            uint32_t mem_owner_err                 :    1;
-            uint32_t mem_full                      :    1;
-            uint32_t mem_rd_err                    :    1;
-            uint32_t reserved28                    :    4;
+            uint32_t mem_waddr_ex                  :    10;  /*This register records the memory address offset when receiver of CHANNEL$m is using the RAM.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t mem_raddr                     :    10;  /*This register records the memory address offset when reads RAM over APB bus.*/
+            uint32_t reserved21                    :    1;  /*Reserved*/
+            uint32_t state                         :    3;  /*This register records the FSM status of CHANNEL$m.*/
+            uint32_t mem_owner_err                 :    1;  /*This status bit will be set when the ownership of memory block is wrong.*/
+            uint32_t mem_full                      :    1;  /*This status bit will be set if the receiver receives more data than the memory size.*/
+            uint32_t mem_rd_err                    :    1;  /*This status bit will be set if the offset address out of memory size when reads via APB bus.*/
+            uint32_t reserved28                    :    4;  /*Reserved*/
         };
         uint32_t val;
     } rx_status[4];
     union {
         struct {
-            uint32_t ch0_tx_end                    :    1;
-            uint32_t ch1_tx_end                    :    1;
-            uint32_t ch2_tx_end                    :    1;
-            uint32_t ch3_tx_end                    :    1;
-            uint32_t ch0_err                       :    1;
-            uint32_t ch1_err                       :    1;
-            uint32_t ch2_err                       :    1;
-            uint32_t ch3_err                       :    1;
-            uint32_t ch0_tx_thr_event              :    1;
-            uint32_t ch1_tx_thr_event              :    1;
-            uint32_t ch2_tx_thr_event              :    1;
-            uint32_t ch3_tx_thr_event              :    1;
-            uint32_t ch0_tx_loop                   :    1;
-            uint32_t ch1_tx_loop                   :    1;
-            uint32_t ch2_tx_loop                   :    1;
-            uint32_t ch3_tx_loop                   :    1;
-            uint32_t ch4_rx_end                    :    1;
-            uint32_t ch5_rx_end                    :    1;
-            uint32_t ch6_rx_end                    :    1;
-            uint32_t ch7_rx_end                    :    1;
-            uint32_t ch4_err                       :    1;
-            uint32_t ch5_err                       :    1;
-            uint32_t ch6_err                       :    1;
-            uint32_t ch7_err                       :    1;
-            uint32_t ch4_rx_thr_event              :    1;
-            uint32_t ch5_rx_thr_event              :    1;
-            uint32_t ch6_rx_thr_event              :    1;
-            uint32_t ch7_rx_thr_event              :    1;
-            uint32_t ch3_dma_access_fail           :    1;
-            uint32_t ch7_dma_access_fail           :    1;
-            uint32_t reserved30                    :    2;
+            uint32_t ch0_tx_end                    :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/
+            uint32_t ch1_tx_end                    :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/
+            uint32_t ch2_tx_end                    :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/
+            uint32_t ch3_tx_end                    :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/
+            uint32_t ch0_err                       :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/
+            uint32_t ch1_err                       :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/
+            uint32_t ch2_err                       :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/
+            uint32_t ch3_err                       :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/
+            uint32_t ch0_tx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/
+            uint32_t ch1_tx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/
+            uint32_t ch2_tx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/
+            uint32_t ch3_tx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/
+            uint32_t ch0_tx_loop                   :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/
+            uint32_t ch1_tx_loop                   :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/
+            uint32_t ch2_tx_loop                   :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/
+            uint32_t ch3_tx_loop                   :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/
+            uint32_t ch4_rx_end                    :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/
+            uint32_t ch5_rx_end                    :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/
+            uint32_t ch6_rx_end                    :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/
+            uint32_t ch7_rx_end                    :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/
+            uint32_t ch4_err                       :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/
+            uint32_t ch5_err                       :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/
+            uint32_t ch6_err                       :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/
+            uint32_t ch7_err                       :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/
+            uint32_t ch4_rx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/
+            uint32_t ch5_rx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/
+            uint32_t ch6_rx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/
+            uint32_t ch7_rx_thr_event              :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/
+            uint32_t ch3_dma_access_fail           :    1;  /*The interrupt raw bit for CHANNEL$n. Triggered when dma accessing CHANNEL$n fails.*/
+            uint32_t ch7_dma_access_fail           :    1;  /*The interrupt raw bit for CHANNEL$m. Triggered when dma accessing CHANNEL$m fails.*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
         };
         uint32_t val;
     } int_raw;
     union {
         struct {
-            uint32_t ch0_tx_end                    :    1;
-            uint32_t ch1_tx_end                    :    1;
-            uint32_t ch2_tx_end                    :    1;
-            uint32_t ch3_tx_end                    :    1;
-            uint32_t ch0_err                       :    1;
-            uint32_t ch1_err                       :    1;
-            uint32_t ch2_err                       :    1;
-            uint32_t ch3_err                       :    1;
-            uint32_t ch0_tx_thr_event              :    1;
-            uint32_t ch1_tx_thr_event              :    1;
-            uint32_t ch2_tx_thr_event              :    1;
-            uint32_t ch3_tx_thr_event              :    1;
-            uint32_t ch0_tx_loop                   :    1;
-            uint32_t ch1_tx_loop                   :    1;
-            uint32_t ch2_tx_loop                   :    1;
-            uint32_t ch3_tx_loop                   :    1;
-            uint32_t ch4_rx_end                    :    1;
-            uint32_t ch5_rx_end                    :    1;
-            uint32_t ch6_rx_end                    :    1;
-            uint32_t ch7_rx_end                    :    1;
-            uint32_t ch4_err                       :    1;
-            uint32_t ch5_err                       :    1;
-            uint32_t ch6_err                       :    1;
-            uint32_t ch7_err                       :    1;
-            uint32_t ch4_rx_thr_event              :    1;
-            uint32_t ch5_rx_thr_event              :    1;
-            uint32_t ch6_rx_thr_event              :    1;
-            uint32_t ch7_rx_thr_event              :    1;
-            uint32_t ch3_dma_access_fail           :    1;
-            uint32_t ch7_dma_access_fail           :    1;
-            uint32_t reserved30                    :    2;
+            uint32_t ch0_tx_end                    :    1;  /*The masked interrupt status bit for CH$n_TX_END_INT.*/
+            uint32_t ch1_tx_end                    :    1;  /*The masked interrupt status bit for CH$n_TX_END_INT.*/
+            uint32_t ch2_tx_end                    :    1;  /*The masked interrupt status bit for CH$n_TX_END_INT.*/
+            uint32_t ch3_tx_end                    :    1;  /*The masked interrupt status bit for CH$n_TX_END_INT.*/
+            uint32_t ch0_err                       :    1;  /*The masked interrupt status bit for CH$n_ERR_INT.*/
+            uint32_t ch1_err                       :    1;  /*The masked interrupt status bit for CH$n_ERR_INT.*/
+            uint32_t ch2_err                       :    1;  /*The masked interrupt status bit for CH$n_ERR_INT.*/
+            uint32_t ch3_err                       :    1;  /*The masked interrupt status bit for CH$n_ERR_INT.*/
+            uint32_t ch0_tx_thr_event              :    1;  /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch1_tx_thr_event              :    1;  /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch2_tx_thr_event              :    1;  /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch3_tx_thr_event              :    1;  /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch0_tx_loop                   :    1;  /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch1_tx_loop                   :    1;  /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch2_tx_loop                   :    1;  /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch3_tx_loop                   :    1;  /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch4_rx_end                    :    1;  /*The masked interrupt status bit for CH$m_RX_END_INT.*/
+            uint32_t ch5_rx_end                    :    1;  /*The masked interrupt status bit for CH$m_RX_END_INT.*/
+            uint32_t ch6_rx_end                    :    1;  /*The masked interrupt status bit for CH$m_RX_END_INT.*/
+            uint32_t ch7_rx_end                    :    1;  /*The masked interrupt status bit for CH$m_RX_END_INT.*/
+            uint32_t ch4_err                       :    1;  /*The masked interrupt status bit for CH$m_ERR_INT.*/
+            uint32_t ch5_err                       :    1;  /*The masked interrupt status bit for CH$m_ERR_INT.*/
+            uint32_t ch6_err                       :    1;  /*The masked interrupt status bit for CH$m_ERR_INT.*/
+            uint32_t ch7_err                       :    1;  /*The masked interrupt status bit for CH$m_ERR_INT.*/
+            uint32_t ch4_rx_thr_event              :    1;  /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch5_rx_thr_event              :    1;  /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch6_rx_thr_event              :    1;  /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch7_rx_thr_event              :    1;  /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch3_dma_access_fail           :    1;  /*The masked interrupt status bit for  CH$n_DMA_ACCESS_FAIL_INT.*/
+            uint32_t ch7_dma_access_fail           :    1;  /*The masked interrupt status bit for  CH$m_DMA_ACCESS_FAIL_INT.*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
         };
         uint32_t val;
     } int_st;
     union {
         struct {
-            uint32_t ch0_tx_end                    :    1;
-            uint32_t ch1_tx_end                    :    1;
-            uint32_t ch2_tx_end                    :    1;
-            uint32_t ch3_tx_end                    :    1;
-            uint32_t ch0_err                       :    1;
-            uint32_t ch1_err                       :    1;
-            uint32_t ch2_err                       :    1;
-            uint32_t ch3_err                       :    1;
-            uint32_t ch0_tx_thr_event              :    1;
-            uint32_t ch1_tx_thr_event              :    1;
-            uint32_t ch2_tx_thr_event              :    1;
-            uint32_t ch3_tx_thr_event              :    1;
-            uint32_t ch0_tx_loop                   :    1;
-            uint32_t ch1_tx_loop                   :    1;
-            uint32_t ch2_tx_loop                   :    1;
-            uint32_t ch3_tx_loop                   :    1;
-            uint32_t ch4_rx_end                    :    1;
-            uint32_t ch5_rx_end                    :    1;
-            uint32_t ch6_rx_end                    :    1;
-            uint32_t ch7_rx_end                    :    1;
-            uint32_t ch4_err                       :    1;
-            uint32_t ch5_err                       :    1;
-            uint32_t ch6_err                       :    1;
-            uint32_t ch7_err                       :    1;
-            uint32_t ch4_rx_thr_event              :    1;
-            uint32_t ch5_rx_thr_event              :    1;
-            uint32_t ch6_rx_thr_event              :    1;
-            uint32_t ch7_rx_thr_event              :    1;
-            uint32_t ch3_dma_access_fail           :    1;
-            uint32_t ch7_dma_access_fail           :    1;
-            uint32_t reserved30                    :    2;
+            uint32_t ch0_tx_end                    :    1;  /*The interrupt enable bit for CH$n_TX_END_INT.*/
+            uint32_t ch1_tx_end                    :    1;  /*The interrupt enable bit for CH$n_TX_END_INT.*/
+            uint32_t ch2_tx_end                    :    1;  /*The interrupt enable bit for CH$n_TX_END_INT.*/
+            uint32_t ch3_tx_end                    :    1;  /*The interrupt enable bit for CH$n_TX_END_INT.*/
+            uint32_t ch0_err                       :    1;  /*The interrupt enable bit for CH$n_ERR_INT.*/
+            uint32_t ch1_err                       :    1;  /*The interrupt enable bit for CH$n_ERR_INT.*/
+            uint32_t ch2_err                       :    1;  /*The interrupt enable bit for CH$n_ERR_INT.*/
+            uint32_t ch3_err                       :    1;  /*The interrupt enable bit for CH$n_ERR_INT.*/
+            uint32_t ch0_tx_thr_event              :    1;  /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch1_tx_thr_event              :    1;  /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch2_tx_thr_event              :    1;  /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch3_tx_thr_event              :    1;  /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/
+            uint32_t ch0_tx_loop                   :    1;  /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch1_tx_loop                   :    1;  /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch2_tx_loop                   :    1;  /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch3_tx_loop                   :    1;  /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/
+            uint32_t ch4_rx_end                    :    1;  /*The interrupt enable bit for CH$m_RX_END_INT.*/
+            uint32_t ch5_rx_end                    :    1;  /*The interrupt enable bit for CH$m_RX_END_INT.*/
+            uint32_t ch6_rx_end                    :    1;  /*The interrupt enable bit for CH$m_RX_END_INT.*/
+            uint32_t ch7_rx_end                    :    1;  /*The interrupt enable bit for CH$m_RX_END_INT.*/
+            uint32_t ch4_err                       :    1;  /*The interrupt enable bit for CH$m_ERR_INT.*/
+            uint32_t ch5_err                       :    1;  /*The interrupt enable bit for CH$m_ERR_INT.*/
+            uint32_t ch6_err                       :    1;  /*The interrupt enable bit for CH$m_ERR_INT.*/
+            uint32_t ch7_err                       :    1;  /*The interrupt enable bit for CH$m_ERR_INT.*/
+            uint32_t ch4_rx_thr_event              :    1;  /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch5_rx_thr_event              :    1;  /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch6_rx_thr_event              :    1;  /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch7_rx_thr_event              :    1;  /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/
+            uint32_t ch3_dma_access_fail           :    1;  /*The interrupt enable bit for CH$n_DMA_ACCESS_FAIL_INT.*/
+            uint32_t ch7_dma_access_fail           :    1;  /*The interrupt enable bit for CH$m_DMA_ACCESS_FAIL_INT.*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
         };
         uint32_t val;
     } int_ena;
     union {
         struct {
-            uint32_t ch0_tx_end                    :    1;
-            uint32_t ch1_tx_end                    :    1;
-            uint32_t ch2_tx_end                    :    1;
-            uint32_t ch3_tx_end                    :    1;
-            uint32_t ch0_err                       :    1;
-            uint32_t ch1_err                       :    1;
-            uint32_t ch2_err                       :    1;
-            uint32_t ch3_err                       :    1;
-            uint32_t ch0_tx_thr_event              :    1;
-            uint32_t ch1_tx_thr_event              :    1;
-            uint32_t ch2_tx_thr_event              :    1;
-            uint32_t ch3_tx_thr_event              :    1;
-            uint32_t ch0_tx_loop                   :    1;
-            uint32_t ch1_tx_loop                   :    1;
-            uint32_t ch2_tx_loop                   :    1;
-            uint32_t ch3_tx_loop                   :    1;
-            uint32_t ch4_rx_end                    :    1;
-            uint32_t ch5_rx_end                    :    1;
-            uint32_t ch6_rx_end                    :    1;
-            uint32_t ch7_rx_end                    :    1;
-            uint32_t ch4_err                       :    1;
-            uint32_t ch5_err                       :    1;
-            uint32_t ch6_err                       :    1;
-            uint32_t ch7_err                       :    1;
-            uint32_t ch4_rx_thr_event              :    1;
-            uint32_t ch5_rx_thr_event              :    1;
-            uint32_t ch6_rx_thr_event              :    1;
-            uint32_t ch7_rx_thr_event              :    1;
-            uint32_t ch3_dma_access_fail           :    1;
-            uint32_t ch7_dma_access_fail           :    1;
-            uint32_t reserved30                    :    2;
+            uint32_t ch0_tx_end                    :    1;  /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/
+            uint32_t ch1_tx_end                    :    1;  /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/
+            uint32_t ch2_tx_end                    :    1;  /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/
+            uint32_t ch3_tx_end                    :    1;  /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/
+            uint32_t ch0_err                       :    1;  /*Set this bit to clear theCH$n_ERR_INT interrupt.*/
+            uint32_t ch1_err                       :    1;  /*Set this bit to clear theCH$n_ERR_INT interrupt.*/
+            uint32_t ch2_err                       :    1;  /*Set this bit to clear theCH$n_ERR_INT interrupt.*/
+            uint32_t ch3_err                       :    1;  /*Set this bit to clear theCH$n_ERR_INT interrupt.*/
+            uint32_t ch0_tx_thr_event              :    1;  /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/
+            uint32_t ch1_tx_thr_event              :    1;  /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/
+            uint32_t ch2_tx_thr_event              :    1;  /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/
+            uint32_t ch3_tx_thr_event              :    1;  /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/
+            uint32_t ch0_tx_loop                   :    1;  /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/
+            uint32_t ch1_tx_loop                   :    1;  /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/
+            uint32_t ch2_tx_loop                   :    1;  /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/
+            uint32_t ch3_tx_loop                   :    1;  /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/
+            uint32_t ch4_rx_end                    :    1;  /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/
+            uint32_t ch5_rx_end                    :    1;  /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/
+            uint32_t ch6_rx_end                    :    1;  /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/
+            uint32_t ch7_rx_end                    :    1;  /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/
+            uint32_t ch4_err                       :    1;  /*Set this bit to clear theCH$m_ERR_INT interrupt.*/
+            uint32_t ch5_err                       :    1;  /*Set this bit to clear theCH$m_ERR_INT interrupt.*/
+            uint32_t ch6_err                       :    1;  /*Set this bit to clear theCH$m_ERR_INT interrupt.*/
+            uint32_t ch7_err                       :    1;  /*Set this bit to clear theCH$m_ERR_INT interrupt.*/
+            uint32_t ch4_rx_thr_event              :    1;  /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/
+            uint32_t ch5_rx_thr_event              :    1;  /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/
+            uint32_t ch6_rx_thr_event              :    1;  /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/
+            uint32_t ch7_rx_thr_event              :    1;  /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/
+            uint32_t ch3_dma_access_fail           :    1;  /*Set this bit to clear the CH$n_DMA_ACCESS_FAIL_INT interrupt.*/
+            uint32_t ch7_dma_access_fail           :    1;  /*Set this bit to clear the CH$m_DMA_ACCESS_FAIL_INT interrupt.*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
         };
         uint32_t val;
     } int_clr;
     union {
         struct {
-            uint32_t low                           :    16;
-            uint32_t high                          :    16;
+            uint32_t low                           :    16;  /*This register is used to configure carrier wave 's low level clock period for CHANNEL$n.*/
+            uint32_t high                          :    16;  /*This register is used to configure carrier wave 's high level clock period for CHANNEL$n.*/
         };
         uint32_t val;
     } tx_carrier[4];
     union {
         struct {
-            uint32_t low_thres                     :    16;
-            uint32_t high_thres                    :    16;
+            uint32_t low_thres                     :    16;  /*The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH$m + 1) for channel $m.*/
+            uint32_t high_thres                    :    16;  /*The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH$m + 1) for channel $m.*/
         };
         uint32_t val;
     } rx_carrier[4];
     union {
         struct {
-            uint32_t limit                         :    9;
-            uint32_t tx_loop_num                   :    10;
-            uint32_t tx_loop_cnt_en                :    1;
-            uint32_t loop_count_reset              :    1;
-            uint32_t loop_stop_en                  :    1;
-            uint32_t reserved22                    :    10;
+            uint32_t limit                         :    9;  /*This register is used to configure the maximum entries that CHANNEL$n can send out.*/
+            uint32_t tx_loop_num                   :    10;  /*This register is used to configure the maximum loop count when tx_conti_mode is valid.*/
+            uint32_t tx_loop_cnt_en                :    1;  /*This register is the enabled bit for loop count.*/
+            uint32_t loop_count_reset              :    1;  /*This register is used to reset the loop count when tx_conti_mode is valid.*/
+            uint32_t loop_stop_en                  :    1;  /*This bit is used to enable the loop send stop function after the loop counter counts to  loop number for CHANNEL$n.*/
+            uint32_t reserved22                    :    10;  /*Reserved*/
         };
         uint32_t val;
     } tx_lim[4];
     union {
         struct {
-            uint32_t rx_lim                        :    9;
-            uint32_t reserved9                     :    23;
+            uint32_t rx_lim                        :    9;  /*This register is used to configure the maximum entries that CHANNEL$m can receive.*/
+            uint32_t reserved9                     :    23;  /*Reserved*/
         };
         uint32_t val;
     } rx_lim[4];
     union {
         struct {
-            uint32_t fifo_mask                     :    1;
-            uint32_t mem_clk_force_on              :    1;
-            uint32_t mem_force_pd                  :    1;
-            uint32_t mem_force_pu                  :    1;
-            uint32_t sclk_div_num                  :    8;
-            uint32_t sclk_div_a                    :    6;
-            uint32_t sclk_div_b                    :    6;
-            uint32_t sclk_sel                      :    2;
-            uint32_t sclk_active                   :    1;
-            uint32_t reserved27                    :    4;
-            uint32_t clk_en                        :    1;
+            uint32_t fifo_mask                     :    1;  /*1'h1: access memory directly.   1'h0: access memory by FIFO.*/
+            uint32_t mem_clk_force_on              :    1;  /*Set this bit to enable the clock for RMT memory.*/
+            uint32_t mem_force_pd                  :    1;  /*Set this bit to power down RMT memory.*/
+            uint32_t mem_force_pu                  :    1;  /*1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.*/
+            uint32_t sclk_div_num                  :    8;  /*the integral part of the fractional divisor*/
+            uint32_t sclk_div_a                    :    6;  /*the numerator of the fractional part of the fractional divisor*/
+            uint32_t sclk_div_b                    :    6;  /*the denominator of the fractional part of the fractional divisor*/
+            uint32_t sclk_sel                      :    2;  /*choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL */
+            uint32_t sclk_active                   :    1;  /*rmt_sclk switch*/
+            uint32_t reserved27                    :    4;  /*Reserved*/
+            uint32_t clk_en                        :    1;  /*RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers*/
         };
         uint32_t val;
     } sys_conf;
     union {
         struct {
-            uint32_t ch0                           :    1;
-            uint32_t ch1                           :    1;
-            uint32_t ch2                           :    1;
-            uint32_t ch3                           :    1;
-            uint32_t en                            :    1;
-            uint32_t reserved5                     :    27;
+            uint32_t ch0                           :    1;  /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/
+            uint32_t ch1                           :    1;  /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/
+            uint32_t ch2                           :    1;  /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/
+            uint32_t ch3                           :    1;  /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/
+            uint32_t en                            :    1;  /*This register is used to enable multiple of channels to start sending data synchronously.*/
+            uint32_t reserved5                     :    27;  /*Reserved*/
         };
         uint32_t val;
     } tx_sim;
     union {
         struct {
-            uint32_t ch0                           :    1;
-            uint32_t ch1                           :    1;
-            uint32_t ch2                           :    1;
-            uint32_t ch3                           :    1;
-            uint32_t ch4                           :    1;
-            uint32_t ch5                           :    1;
-            uint32_t ch6                           :    1;
-            uint32_t ch7                           :    1;
-            uint32_t reserved8                     :    24;
+            uint32_t ch0                           :    1;  /*This register is used to reset the clock divider of CHANNEL$n.*/
+            uint32_t ch1                           :    1;  /*This register is used to reset the clock divider of CHANNEL$n.*/
+            uint32_t ch2                           :    1;  /*This register is used to reset the clock divider of CHANNEL$n.*/
+            uint32_t ch3                           :    1;  /*This register is used to reset the clock divider of CHANNEL$n.*/
+            uint32_t ch4                           :    1;  /*This register is used to reset the clock divider of CHANNEL$m.*/
+            uint32_t ch5                           :    1;  /*This register is used to reset the clock divider of CHANNEL$m.*/
+            uint32_t ch6                           :    1;  /*This register is used to reset the clock divider of CHANNEL$m.*/
+            uint32_t ch7                           :    1;  /*This register is used to reset the clock divider of CHANNEL$m.*/
+            uint32_t reserved8                     :    24;  /*Reserved*/
         };
         uint32_t val;
     } ref_cnt_rst;
     union {
         struct {
-            uint32_t date                          :    28;
-            uint32_t reserved28                    :    4;
+            uint32_t date                          :    28;  /*This is the version register.*/
+            uint32_t reserved28                    :    4;  /*Reserved*/
         };
         uint32_t val;
     } date;

components/soc/esp32s3/include/soc/rtc_cntl_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_RTC_CNTL_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
@@ -2050,14 +2050,14 @@ ork.*/
 #define RTC_WDT_STG_SEL_RESET_RTC       4
 
 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
-/*description: CPU reset counter length*/
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
+/*description: CPU reset counter length.*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
-/*description: system reset counter length*/
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
+/*description: system reset counter length.*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
@@ -3262,7 +3262,7 @@ ork.*/
 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
 
-#define RTC_CNTL_INT_ENA_RTC_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x138)
+#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x138)
 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
 /*description: .*/
 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS    (BIT(20))
@@ -3390,7 +3390,7 @@ ork.*/
 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
 
-#define RTC_CNTL_INT_ENA_RTC_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x13C)
+#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x13C)
 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
 /*description: .*/
 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC    (BIT(20))

components/soc/esp32s3/include/soc/rtc_i2c_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_RTC_I2C_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define RTC_I2C_SCL_LOW_REG          (DR_REG_RTC_I2C_BASE + 0x0)
 /* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
@@ -425,7 +425,7 @@ extern "C" {
 #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
 
 #define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x34)
-/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/* RTC_I2C_DONE :  ;bitpos:[31] ;default:  ; */
 /*description: i2c done.*/
 #define RTC_I2C_DONE    (BIT(31))
 #define RTC_I2C_DONE_M  (BIT(31))

components/soc/esp32s3/include/soc/rtc_i2c_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,14 +11,15 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_RTC_I2C_STRUCT_H_
+#define _SOC_RTC_I2C_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
@@ -225,3 +226,7 @@ extern rtc_i2c_dev_t RTC_I2C;
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_RTC_I2C_STRUCT_H_ */

components/soc/esp32s3/include/soc/rtc_io_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_RTC_IO_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
 /* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:10] ;default: 0 ; */

components/soc/esp32s3/include/soc/rtc_io_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_RTC_IO_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {
@@ -126,8 +126,7 @@ typedef volatile struct {
             uint32_t xpd                           :    1;  /*TOUCH_XPD*/
             uint32_t tie_opt                       :    1;  /*TOUCH_TIE_OPT*/
             uint32_t start                         :    1;  /*TOUCH_START*/
-            uint32_t dac:                3;             /*TOUCH_DAC*/
-            uint32_t reserved26:         1;
+            uint32_t reserved23                    :    4;
             uint32_t rue                           :    1;  /*RUE*/
             uint32_t rde                           :    1;  /*RDE*/
             uint32_t drv                           :    2;  /*DRV*/

components/soc/esp32s3/include/soc/sdmmc_struct.h

@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/sens_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SENS_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SENS_SAR_READER1_CTRL_REG          (DR_REG_SENS_BASE + 0x0)
 /* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */

components/soc/esp32s3/include/soc/sens_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,221 +15,221 @@
 #define _SOC_SENS_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {
         struct {
-            uint32_t sar1_clk_div:    8;                                   /*clock divider*/
-            uint32_t reserved8:      10;
-            uint32_t sar1_clk_gated:  1;
-            uint32_t sar1_sample_num: 8;
-            uint32_t reserved27:      1;
-            uint32_t sar1_data_inv:   1;                                   /*Invert SAR ADC1 data*/
-            uint32_t sar1_int_en:     1;                                   /*enable saradc1 to send out interrupt*/
-            uint32_t reserved30:      2;
+            uint32_t sar1_clk_div                  :    8;  /*clock divider*/
+            uint32_t reserved8                     :    10;
+            uint32_t sar1_clk_gated                :    1;
+            uint32_t sar1_sample_num               :    8;
+            uint32_t reserved27                    :    1;
+            uint32_t sar1_data_inv                 :    1;  /*Invert SAR ADC1 data*/
+            uint32_t sar1_int_en                   :    1;  /*enable saradc1 to send out interrupt*/
+            uint32_t reserved30                    :    2;
         };
         uint32_t val;
     } sar_reader1_ctrl;
-    uint32_t sar_reader1_status;                                           /**/
+    uint32_t sar_reader1_status;
     union {
         struct {
-            uint32_t reserved0:              24;
-            uint32_t force_xpd_amp:           2;
-            uint32_t amp_rst_fb_force:        2;
-            uint32_t amp_short_ref_force:     2;
-            uint32_t amp_short_ref_gnd_force: 2;
+            uint32_t reserved0                     :    24;
+            uint32_t force_xpd_amp                 :    2;
+            uint32_t amp_rst_fb_force              :    2;
+            uint32_t amp_short_ref_force           :    2;
+            uint32_t amp_short_ref_gnd_force       :    2;
         };
         uint32_t val;
     } sar_meas1_ctrl1;
     union {
         struct {
-            uint32_t meas1_data_sar:   16;                                 /*SAR ADC1 data*/
-            uint32_t meas1_done_sar:    1;                                 /*SAR ADC1 conversion done indication*/
-            uint32_t meas1_start_sar:   1;                                 /*SAR ADC1 controller (in RTC) starts conversion*/
-            uint32_t meas1_start_force: 1;                                 /*1: SAR ADC1 controller (in RTC) is started by SW*/
-            uint32_t sar1_en_pad:      12;                                 /*SAR ADC1 pad enable bitmap*/
-            uint32_t sar1_en_pad_force: 1;                                 /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
+            uint32_t meas1_data_sar                :    16;  /*SAR ADC1 data*/
+            uint32_t meas1_done_sar                :    1;  /*SAR ADC1 conversion done indication*/
+            uint32_t meas1_start_sar               :    1;  /*SAR ADC1 controller (in RTC) starts conversion*/
+            uint32_t meas1_start_force             :    1;  /*1: SAR ADC1 controller (in RTC) is started by SW*/
+            uint32_t sar1_en_pad                   :    12;  /*SAR ADC1 pad enable bitmap*/
+            uint32_t sar1_en_pad_force             :    1;  /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
         };
         uint32_t val;
     } sar_meas1_ctrl2;
     union {
         struct {
-            uint32_t reserved0:     31;
-            uint32_t sar1_dig_force: 1;                                    /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
+            uint32_t reserved0                     :    31;
+            uint32_t sar1_dig_force                :    1;  /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
         };
         uint32_t val;
     } sar_meas1_mux;
-    uint32_t sar_atten1;                                                   /*2-bit attenuation for each pad*/
+    uint32_t sar_atten1;
     union {
         struct {
-            uint32_t sar_amp_wait1: 16;
-            uint32_t sar_amp_wait2: 16;
+            uint32_t sar_amp_wait1                 :    16;
+            uint32_t sar_amp_wait2                 :    16;
         };
         uint32_t val;
     } sar_amp_ctrl1;
     union {
         struct {
-            uint32_t sar1_dac_xpd_fsm_idle:      1;
-            uint32_t xpd_sar_amp_fsm_idle:       1;
-            uint32_t amp_rst_fb_fsm_idle:        1;
-            uint32_t amp_short_ref_fsm_idle:     1;
-            uint32_t amp_short_ref_gnd_fsm_idle: 1;
-            uint32_t xpd_sar_fsm_idle:           1;
-            uint32_t sar_rstb_fsm_idle:          1;
-            uint32_t reserved7:                  9;
-            uint32_t sar_amp_wait3:             16;
+            uint32_t sar1_dac_xpd_fsm_idle         :    1;
+            uint32_t xpd_sar_amp_fsm_idle          :    1;
+            uint32_t amp_rst_fb_fsm_idle           :    1;
+            uint32_t amp_short_ref_fsm_idle        :    1;
+            uint32_t amp_short_ref_gnd_fsm_idle    :    1;
+            uint32_t xpd_sar_fsm_idle              :    1;
+            uint32_t sar_rstb_fsm_idle             :    1;
+            uint32_t reserved7                     :    9;
+            uint32_t sar_amp_wait3                 :    16;
         };
         uint32_t val;
     } sar_amp_ctrl2;
     union {
         struct {
-            uint32_t sar1_dac_xpd_fsm:      4;
-            uint32_t xpd_sar_amp_fsm:       4;
-            uint32_t amp_rst_fb_fsm:        4;
-            uint32_t amp_short_ref_fsm:     4;
-            uint32_t amp_short_ref_gnd_fsm: 4;
-            uint32_t xpd_sar_fsm:           4;
-            uint32_t sar_rstb_fsm:          4;
-            uint32_t reserved28:            4;
+            uint32_t sar1_dac_xpd_fsm              :    4;
+            uint32_t xpd_sar_amp_fsm               :    4;
+            uint32_t amp_rst_fb_fsm                :    4;
+            uint32_t amp_short_ref_fsm             :    4;
+            uint32_t amp_short_ref_gnd_fsm         :    4;
+            uint32_t xpd_sar_fsm                   :    4;
+            uint32_t sar_rstb_fsm                  :    4;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } sar_amp_ctrl3;
     union {
         struct {
-            uint32_t sar2_clk_div:        8;                               /*clock divider*/
-            uint32_t reserved8:           8;
-            uint32_t sar2_wait_arb_cycle: 2;                               /*wait arbit stable after sar_done*/
-            uint32_t sar2_clk_gated:      1;
-            uint32_t sar2_sample_num:     8;
-            uint32_t reserved27:          2;
-            uint32_t sar2_data_inv:       1;                               /*Invert SAR ADC2 data*/
-            uint32_t sar2_int_en:         1;                               /*enable saradc2 to send out interrupt*/
-            uint32_t reserved31:          1;
+            uint32_t sar2_clk_div                  :    8;  /*clock divider*/
+            uint32_t reserved8                     :    8;
+            uint32_t sar2_wait_arb_cycle           :    2;  /*wait arbit stable after sar_done*/
+            uint32_t sar2_clk_gated                :    1;
+            uint32_t sar2_sample_num               :    8;
+            uint32_t reserved27                    :    2;
+            uint32_t sar2_data_inv                 :    1;  /*Invert SAR ADC2 data*/
+            uint32_t sar2_int_en                   :    1;  /*enable saradc2 to send out interrupt*/
+            uint32_t reserved31                    :    1;
         };
         uint32_t val;
     } sar_reader2_ctrl;
-    uint32_t sar_reader2_status;                                           /**/
+    uint32_t sar_reader2_status;
     union {
         struct {
-            uint32_t sar2_cntl_state:   3;                                 /*saradc2_cntl_fsm*/
-            uint32_t sar2_pwdet_cal_en: 1;                                 /*rtc control pwdet enable*/
-            uint32_t sar2_pkdet_cal_en: 1;                                 /*rtc control pkdet enable*/
-            uint32_t sar2_en_test:      1;                                 /*SAR2_EN_TEST*/
-            uint32_t sar2_rstb_force:   2;
-            uint32_t sar2_standby_wait: 8;
-            uint32_t sar2_rstb_wait:    8;
-            uint32_t sar2_xpd_wait:     8;
+            uint32_t sar2_cntl_state               :    3;  /*saradc2_cntl_fsm*/
+            uint32_t sar2_pwdet_cal_en             :    1;  /*rtc control pwdet enable*/
+            uint32_t sar2_pkdet_cal_en             :    1;  /*rtc control pkdet enable*/
+            uint32_t sar2_en_test                  :    1;  /*SAR2_EN_TEST*/
+            uint32_t sar2_rstb_force               :    2;
+            uint32_t sar2_standby_wait             :    8;
+            uint32_t sar2_rstb_wait                :    8;
+            uint32_t sar2_xpd_wait                 :    8;
         };
         uint32_t val;
     } sar_meas2_ctrl1;
     union {
         struct {
-            uint32_t meas2_data_sar:   16;                                 /*SAR ADC2 data*/
-            uint32_t meas2_done_sar:    1;                                 /*SAR ADC2 conversion done indication*/
-            uint32_t meas2_start_sar:   1;                                 /*SAR ADC2 controller (in RTC) starts conversion*/
-            uint32_t meas2_start_force: 1;                                 /*1: SAR ADC2 controller (in RTC) is started by SW*/
-            uint32_t sar2_en_pad:      12;                                 /*SAR ADC2 pad enable bitmap*/
-            uint32_t sar2_en_pad_force: 1;                                 /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
+            uint32_t meas2_data_sar                :    16;  /*SAR ADC2 data*/
+            uint32_t meas2_done_sar                :    1;  /*SAR ADC2 conversion done indication*/
+            uint32_t meas2_start_sar               :    1;  /*SAR ADC2 controller (in RTC) starts conversion*/
+            uint32_t meas2_start_force             :    1;  /*1: SAR ADC2 controller (in RTC) is started by SW*/
+            uint32_t sar2_en_pad                   :    12;  /*SAR ADC2 pad enable bitmap*/
+            uint32_t sar2_en_pad_force             :    1;  /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
         };
         uint32_t val;
     } sar_meas2_ctrl2;
     union {
         struct {
-            uint32_t reserved0:     28;
-            uint32_t sar2_pwdet_cct: 3;                                    /*SAR2_PWDET_CCT*/
-            uint32_t sar2_rtc_force: 1;                                    /*in sleep  force to use rtc to control ADC*/
+            uint32_t reserved0                     :    28;
+            uint32_t sar2_pwdet_cct                :    3;  /*SAR2_PWDET_CCT*/
+            uint32_t sar2_rtc_force                :    1;  /*in sleep, force to use rtc to control ADC*/
         };
         uint32_t val;
     } sar_meas2_mux;
-    uint32_t sar_atten2;                                                   /*2-bit attenuation for each pad*/
+    uint32_t sar_atten2;
     union {
         struct {
-            uint32_t reserved0:    29;
-            uint32_t force_xpd_sar: 2;
-            uint32_t sarclk_en:     1;
+            uint32_t reserved0                     :    29;
+            uint32_t force_xpd_sar                 :    2;
+            uint32_t sarclk_en                     :    1;
         };
         uint32_t val;
     } sar_power_xpd_sar;
     union {
         struct {
-            uint32_t i2c_slave_addr1:   11;
-            uint32_t i2c_slave_addr0:   11;
-            uint32_t meas_status:        8;
-            uint32_t reserved30:         2;
+            uint32_t i2c_slave_addr1               :    11;
+            uint32_t i2c_slave_addr0               :    11;
+            uint32_t meas_status                   :    8;
+            uint32_t reserved30                    :    2;
         };
         uint32_t val;
     } sar_slave_addr1;
     union {
         struct {
-            uint32_t i2c_slave_addr3: 11;
-            uint32_t i2c_slave_addr2: 11;
-            uint32_t reserved22:     10;
+            uint32_t i2c_slave_addr3               :    11;
+            uint32_t i2c_slave_addr2               :    11;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } sar_slave_addr2;
     union {
         struct {
-            uint32_t i2c_slave_addr5: 11;
-            uint32_t i2c_slave_addr4: 11;
-            uint32_t reserved22:     10;
+            uint32_t i2c_slave_addr5               :    11;
+            uint32_t i2c_slave_addr4               :    11;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } sar_slave_addr3;
     union {
         struct {
-            uint32_t i2c_slave_addr7: 11;
-            uint32_t i2c_slave_addr6: 11;
-            uint32_t reserved22:     10;
+            uint32_t i2c_slave_addr7               :    11;
+            uint32_t i2c_slave_addr6               :    11;
+            uint32_t reserved22                    :    10;
         };
         uint32_t val;
     } sar_slave_addr4;
     union {
         struct {
-            uint32_t tsens_out:            8;                              /*temperature sensor data out*/
-            uint32_t tsens_ready:          1;                              /*indicate temperature sensor out ready*/
-            uint32_t reserved9:            3;
-            uint32_t tsens_int_en:         1;                              /*enable temperature sensor to send out interrupt*/
-            uint32_t tsens_in_inv:         1;                              /*invert temperature sensor data*/
-            uint32_t tsens_clk_div:        8;                              /*temperature sensor clock divider*/
-            uint32_t tsens_power_up:       1;                              /*temperature sensor power up*/
-            uint32_t tsens_power_up_force: 1;                              /*1: dump out & power up controlled by SW*/
-            uint32_t tsens_dump_out:       1;                              /*temperature sensor dump out*/
-            uint32_t reserved25:           7;
+            uint32_t tsens_out                     :    8;  /*temperature sensor data out*/
+            uint32_t tsens_ready                   :    1;  /*indicate temperature sensor out ready*/
+            uint32_t reserved9                     :    3;
+            uint32_t tsens_int_en                  :    1;  /*enable temperature sensor to send out interrupt*/
+            uint32_t tsens_in_inv                  :    1;  /*invert temperature sensor data*/
+            uint32_t tsens_clk_div                 :    8;  /*temperature sensor clock divider*/
+            uint32_t tsens_power_up                :    1;  /*temperature sensor power up*/
+            uint32_t tsens_power_up_force          :    1;  /*1: dump out & power up controlled by SW*/
+            uint32_t tsens_dump_out                :    1;  /*temperature sensor dump out*/
+            uint32_t reserved25                    :    7;
         };
         uint32_t val;
     } sar_tctrl;
     union {
         struct {
-            uint32_t tsens_xpd_wait: 12;
-            uint32_t tsens_xpd_force: 2;
-            uint32_t tsens_clk_inv:   1;
-            uint32_t reserved15:     17;
+            uint32_t tsens_xpd_wait                :    12;
+            uint32_t tsens_xpd_force               :    2;
+            uint32_t tsens_clk_inv                 :    1;
+            uint32_t reserved15                    :    17;
         };
         uint32_t val;
     } sar_tctrl2;
     union {
         struct {
-            uint32_t sar_i2c_ctrl:       28;                               /*I2C control data*/
-            uint32_t sar_i2c_start:       1;                               /*start I2C*/
-            uint32_t sar_i2c_start_force: 1;                               /*1: I2C started by SW*/
-            uint32_t reserved30:          2;
+            uint32_t sar_i2c_ctrl                  :    28;  /*I2C control data*/
+            uint32_t sar_i2c_start                 :    1;  /*start I2C*/
+            uint32_t sar_i2c_start_force           :    1;  /*1: I2C started by SW*/
+            uint32_t reserved30                    :    2;
         };
         uint32_t val;
     } sar_i2c_ctrl;
     union {
         struct {
-            uint32_t touch_outen:        15;                               /*touch controller output enable*/
-            uint32_t touch_status_clr:    1;                               /*clear all touch active status*/
-            uint32_t touch_data_sel:      2;                               /*3: smooth data 2: baseline 1 0: raw_data*/
-            uint32_t touch_denoise_end:   1;                               /*touch_denoise_done*/
-            uint32_t touch_unit_end:      1;                               /*touch_unit_done*/
-            uint32_t touch_approach_pad2: 4;                               /*indicate which pad is approach pad2*/
-            uint32_t touch_approach_pad1: 4;                               /*indicate which pad is approach pad1*/
-            uint32_t touch_approach_pad0: 4;                               /*indicate which pad is approach pad0*/
+            uint32_t touch_outen                   :    15;  /*touch controller output enable*/
+            uint32_t touch_status_clr              :    1;  /*clear all touch active status*/
+            uint32_t touch_data_sel                :    2;  /*3: smooth data 2: baseline 1,0: raw_data*/
+            uint32_t touch_denoise_end             :    1;  /*touch_denoise_done*/
+            uint32_t touch_unit_end                :    1;  /*touch_unit_done*/
+            uint32_t touch_approach_pad2           :    4;  /*indicate which pad is approach pad2*/
+            uint32_t touch_approach_pad1           :    4;  /*indicate which pad is approach pad1*/
+            uint32_t touch_approach_pad0           :    4;  /*indicate which pad is approach pad0*/
         };
         uint32_t val;
     } sar_touch_conf;
@@ -249,179 +249,152 @@ typedef volatile struct {
     } touch_thresh[14];
     union {
         struct {
-            uint32_t touch_pad_active: 15;                                 /*touch active status*/
-            uint32_t touch_channel_clr: 15;                                /*Clear touch channel*/
-            uint32_t reserved30:        1;
-            uint32_t touch_meas_done:   1;
+            uint32_t touch_pad_active              :    15;  /*touch active status*/
+            uint32_t touch_channel_clr             :    15;  /*Clear touch channel*/
+            uint32_t reserved30                    :    1;
+            uint32_t touch_meas_done               :    1;
         };
         uint32_t val;
     } sar_touch_chn_st;
     union {
         struct {
-            uint32_t touch_denoise_data: 22;                               /*the counter for touch pad 0*/
-            uint32_t touch_scan_curr:    4;
-            uint32_t reserved26:         6;
+            uint32_t touch_denoise_data            :    22;  /*the counter for touch pad 0*/
+            uint32_t touch_scan_curr               :    4;
+            uint32_t reserved26                    :    6;
         };
         uint32_t val;
     } sar_touch_status0;
     union {
         struct {
-            uint32_t touch_pad1_data:    22;
-            uint32_t reserved22:          7;
-            uint32_t touch_pad_debounce:  3;
+            uint32_t touch_pad1_data               :    22;
+            uint32_t reserved22                    :    7;
+            uint32_t touch_pad_debounce            :    3;
         };
         uint32_t val;
     } sar_touch_status[14];
     union {
         struct {
-            uint32_t touch_slp_data:    22;
-            uint32_t reserved22:         7;
-            uint32_t touch_slp_debounce: 3;
+            uint32_t touch_slp_data                :    22;
+            uint32_t reserved22                    :    7;
+            uint32_t touch_slp_debounce            :    3;
         };
         uint32_t val;
-    } sar_touch_status15;
+    } sar_touch_slp_status;
     union {
         struct {
-            uint32_t touch_approach_pad2_cnt: 8;
-            uint32_t touch_approach_pad1_cnt: 8;
-            uint32_t touch_approach_pad0_cnt: 8;
-            uint32_t touch_slp_approach_cnt:  8;
+            uint32_t touch_approach_pad2_cnt       :    8;
+            uint32_t touch_approach_pad1_cnt       :    8;
+            uint32_t touch_approach_pad0_cnt       :    8;
+            uint32_t touch_slp_approach_cnt        :    8;
         };
         uint32_t val;
-    } sar_touch_status16;
+    } sar_touch_appr_status;
     union {
         struct {
-            uint32_t sw_fstep:          16;                                /*frequency step for CW generator*/
-            uint32_t sw_tone_en:         1;                                /*1: enable CW generator*/
-            uint32_t debug_bit_sel:      5;
-            uint32_t dac_dig_force:      1;                                /*1: DAC1 & DAC2 use DMA*/
-            uint32_t dac_clk_force_low:  1;                                /*1: force PDAC_CLK to low*/
-            uint32_t dac_clk_force_high: 1;                                /*1: force PDAC_CLK to high*/
-            uint32_t dac_clk_inv:        1;                                /*1: invert PDAC_CLK*/
-            uint32_t reserved26:         6;
-        };
-        uint32_t val;
-    } sar_dac_ctrl1;
-    union {
-        struct {
-            uint32_t dac_dc1:    8;                                        /*DC offset for DAC1 CW generator*/
-            uint32_t dac_dc2:    8;                                        /*DC offset for DAC2 CW generator*/
-            uint32_t dac_scale1: 2;                                        /*00: no scale*/
-            uint32_t dac_scale2: 2;                                        /*00: no scale*/
-            uint32_t dac_inv1:   2;                                        /*00: do not invert any bits*/
-            uint32_t dac_inv2:   2;                                        /*00: do not invert any bits*/
-            uint32_t dac_cw_en1: 1;                                        /*1: to select CW generator as source to PDAC1_DAC[7:0]*/
-            uint32_t dac_cw_en2: 1;                                        /*1: to select CW generator as source to PDAC2_DAC[7:0]*/
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } sar_dac_ctrl2;
-    union {
-        struct {
-            uint32_t reserved0:        25;
-            uint32_t dbg_trigger:       1;                                 /*trigger cocpu debug registers*/
-            uint32_t clk_en_st:         1;                                 /*check cocpu whether clk on*/
-            uint32_t reset_n:           1;                                 /*check cocpu whether in reset state*/
-            uint32_t eoi:               1;                                 /*check cocpu whether in interrupt state*/
-            uint32_t trap:              1;                                 /*check cocpu whether in trap state*/
-            uint32_t ebreak:            1;                                 /*check cocpu whether in ebreak*/
-            uint32_t reserved31:        1;
+            uint32_t reserved0                     :    25;
+            uint32_t dbg_trigger                   :    1;  /*trigger cocpu debug registers*/
+            uint32_t clk_en_st                     :    1;  /*check cocpu whether clk on*/
+            uint32_t reset_n                       :    1;  /*check cocpu whether in reset state*/
+            uint32_t eoi                           :    1;  /*check cocpu whether in interrupt state*/
+            uint32_t trap                          :    1;  /*check cocpu whether in trap state*/
+            uint32_t ebreak                        :    1;  /*check cocpu whether in ebreak*/
+            uint32_t reserved31                    :    1;
         };
         uint32_t val;
     } sar_cocpu_state;
     union {
         struct {
-            uint32_t touch_done:                             1;            /*int from touch done*/
-            uint32_t touch_inactive:                         1;            /*int from touch inactive*/
-            uint32_t touch_active:                           1;            /*int from touch active*/
-            uint32_t saradc1:                                1;            /*int from saradc1*/
-            uint32_t saradc2:                                1;            /*int from saradc2*/
-            uint32_t tsens:                                  1;            /*int from tsens*/
-            uint32_t start:                                  1;            /*int from start*/
-            uint32_t sw:                                     1;            /*int from software*/
-            uint32_t swd:                                    1;            /*int from super watch dog*/
-            uint32_t touch_timeout:                          1;
-            uint32_t touch_approach_loop_done:               1;
-            uint32_t touch_scan_done:                        1;
-            uint32_t reserved12:                            20;
+            uint32_t touch_done                    :    1;  /*int from touch done*/
+            uint32_t touch_inactive                :    1;  /*int from touch inactive*/
+            uint32_t touch_active                  :    1;  /*int from touch active*/
+            uint32_t saradc1                       :    1;  /*int from saradc1*/
+            uint32_t saradc2                       :    1;  /*int from saradc2*/
+            uint32_t tsens                         :    1;  /*int from tsens*/
+            uint32_t start                         :    1;  /*int from start*/
+            uint32_t sw                            :    1;  /*int from software*/
+            uint32_t swd                           :    1;  /*int from super watch dog*/
+            uint32_t touch_timeout                 :    1;
+            uint32_t touch_approach_loop_done      :    1;
+            uint32_t touch_scan_done               :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_raw;
     union {
         struct {
-            uint32_t touch_done:                             1;
-            uint32_t touch_inactive:                         1;
-            uint32_t touch_active:                           1;
-            uint32_t saradc1:                                1;
-            uint32_t saradc2:                                1;
-            uint32_t tsens:                                  1;
-            uint32_t start:                                  1;
-            uint32_t sw:                                     1;            /*cocpu int enable*/
-            uint32_t swd:                                    1;
-            uint32_t touch_timeout:                          1;
-            uint32_t touch_approach_loop_done:               1;
-            uint32_t touch_scan_done:                        1;
-            uint32_t reserved12:                            20;
+            uint32_t touch_done                    :    1;
+            uint32_t touch_inactive                :    1;
+            uint32_t touch_active                  :    1;
+            uint32_t saradc1                       :    1;
+            uint32_t saradc2                       :    1;
+            uint32_t tsens                         :    1;
+            uint32_t start                         :    1;
+            uint32_t sw                            :    1;  /*cocpu int enable*/
+            uint32_t swd                           :    1;
+            uint32_t touch_timeout                 :    1;
+            uint32_t touch_approach_loop_done      :    1;
+            uint32_t touch_scan_done               :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_ena;
     union {
         struct {
-            uint32_t touch_done:                            1;
-            uint32_t touch_inactive:                        1;
-            uint32_t touch_active:                          1;
-            uint32_t saradc1:                               1;
-            uint32_t saradc2:                               1;
-            uint32_t tsens:                                 1;
-            uint32_t start:                                 1;
-            uint32_t sw:                                    1;             /*cocpu int status*/
-            uint32_t swd:                                   1;
-            uint32_t touch_timeout:                         1;
-            uint32_t touch_approach_loop_done:              1;
-            uint32_t touch_scan_done:                       1;
-            uint32_t reserved12:                           20;
+            uint32_t touch_done                    :    1;
+            uint32_t touch_inactive                :    1;
+            uint32_t touch_active                  :    1;
+            uint32_t saradc1                       :    1;
+            uint32_t saradc2                       :    1;
+            uint32_t tsens                         :    1;
+            uint32_t start                         :    1;
+            uint32_t sw                            :    1;  /*cocpu int status*/
+            uint32_t swd                           :    1;
+            uint32_t touch_timeout                 :    1;
+            uint32_t touch_approach_loop_done      :    1;
+            uint32_t touch_scan_done               :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_st;
     union {
         struct {
-            uint32_t touch_done:                             1;
-            uint32_t touch_inactive:                         1;
-            uint32_t touch_active:                           1;
-            uint32_t saradc1:                                1;
-            uint32_t saradc2:                                1;
-            uint32_t tsens:                                  1;
-            uint32_t start:                                  1;
-            uint32_t sw:                                     1;            /*cocpu int clear*/
-            uint32_t swd:                                    1;
-            uint32_t touch_timeout:                          1;
-            uint32_t touch_approach_loop_done:               1;
-            uint32_t touch_scan_done:                        1;
-            uint32_t reserved12:                            20;
+            uint32_t touch_done                    :    1;
+            uint32_t touch_inactive                :    1;
+            uint32_t touch_active                  :    1;
+            uint32_t saradc1                       :    1;
+            uint32_t saradc2                       :    1;
+            uint32_t tsens                         :    1;
+            uint32_t start                         :    1;
+            uint32_t sw                            :    1;  /*cocpu int clear*/
+            uint32_t swd                           :    1;
+            uint32_t touch_timeout                 :    1;
+            uint32_t touch_approach_loop_done      :    1;
+            uint32_t touch_scan_done               :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_clr;
     union {
         struct {
-            uint32_t pc:            13;                                    /*cocpu Program counter*/
-            uint32_t mem_vld:        1;                                    /*cocpu mem valid output*/
-            uint32_t mem_rdy:        1;                                    /*cocpu mem ready input*/
-            uint32_t mem_wen:        4;                                    /*cocpu mem write enable output*/
-            uint32_t mem_addr:      13;                                    /*cocpu mem address output*/
+            uint32_t pc                            :    13;  /*cocpu Program counter*/
+            uint32_t mem_vld                       :    1;  /*cocpu mem valid output*/
+            uint32_t mem_rdy                       :    1;  /*cocpu mem ready input*/
+            uint32_t mem_wen                       :    4;  /*cocpu mem write enable output*/
+            uint32_t mem_addr                      :    13;  /*cocpu mem address output*/
         };
         uint32_t val;
     } sar_cocpu_debug;
     union {
         struct {
-            uint32_t reserved0:       28;
-            uint32_t xpd_hall:         1;                                  /*Power on hall sensor and connect to VP and VN*/
-            uint32_t xpd_hall_force:   1;                                  /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
-            uint32_t hall_phase:       1;                                  /*Reverse phase of hall sensor*/
-            uint32_t hall_phase_force: 1;                                  /*1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
+            uint32_t reserved0                     :    28;
+            uint32_t xpd_hall                      :    1;  /*Power on hall sensor and connect to VP and VN*/
+            uint32_t xpd_hall_force                :    1;  /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
+            uint32_t hall_phase                    :    1;  /*Reverse phase of hall sensor*/
+            uint32_t hall_phase_force              :    1;  /*1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
         };
         uint32_t val;
     } sar_hall_ctrl;
-    uint32_t sar_nouse;                                                    /**/
+    uint32_t sar_nouse;
     union {
         struct {
             uint32_t reserved0                     :    27;
@@ -435,50 +408,50 @@ typedef volatile struct {
     } sar_peri_clk_gate_conf;
     union {
         struct {
-            uint32_t reserved0:    25;
-            uint32_t reset:         1;
+            uint32_t reserved0                     :    25;
+            uint32_t reset                         :    1;
             uint32_t reserved26                    :    1;
-            uint32_t rtc_i2c_reset: 1;
-            uint32_t reserved28:    1;
-            uint32_t tsens_reset:   1;
-            uint32_t saradc_reset:  1;
-            uint32_t reserved31:    1;
+            uint32_t rtc_i2c_reset                 :    1;
+            uint32_t reserved28                    :    1;
+            uint32_t tsens_reset                   :    1;
+            uint32_t saradc_reset                  :    1;
+            uint32_t reserved31                    :    1;
         };
         uint32_t val;
     } sar_peri_reset_conf;
     union {
         struct {
-            uint32_t touch_done_w1ts:                             1;
-            uint32_t touch_inactive_w1ts:                         1;
-            uint32_t touch_active_w1ts:                           1;
-            uint32_t saradc1_w1ts:                                1;
-            uint32_t saradc2_w1ts:                                1;
-            uint32_t tsens_w1ts:                                  1;
-            uint32_t start_w1ts:                                  1;
-            uint32_t sw_w1ts:                                     1;
-            uint32_t swd_w1ts:                                    1;
-            uint32_t touch_timeout_w1ts:                          1;
-            uint32_t touch_approach_loop_done_w1ts:               1;
-            uint32_t touch_scan_done_w1ts:                        1;
-            uint32_t reserved12:                                 20;
+            uint32_t touch_done_w1ts               :    1;
+            uint32_t touch_inactive_w1ts           :    1;
+            uint32_t touch_active_w1ts             :    1;
+            uint32_t saradc1_w1ts                  :    1;
+            uint32_t saradc2_w1ts                  :    1;
+            uint32_t tsens_w1ts                    :    1;
+            uint32_t start_w1ts                    :    1;
+            uint32_t sw_w1ts                       :    1;
+            uint32_t swd_w1ts                      :    1;
+            uint32_t touch_timeout_w1ts            :    1;
+            uint32_t touch_approach_loop_done_w1ts :    1;
+            uint32_t touch_scan_done_w1ts          :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_ena_w1ts;
     union {
         struct {
-            uint32_t touch_done_w1tc:                             1;
-            uint32_t touch_inactive_w1tc:                         1;
-            uint32_t touch_active_w1tc:                           1;
-            uint32_t saradc1_w1tc:                                1;
-            uint32_t saradc2_w1tc:                                1;
-            uint32_t tsens_w1tc:                                  1;
-            uint32_t start_w1tc:                                  1;
-            uint32_t sw_w1tc:                                     1;
-            uint32_t swd_w1tc:                                    1;
-            uint32_t touch_timeout_w1tc:                          1;
-            uint32_t touch_approach_loop_done_w1tc:               1;
-            uint32_t touch_scan_done_w1tc:                        1;
-            uint32_t reserved12:                                 20;
+            uint32_t touch_done_w1tc               :    1;
+            uint32_t touch_inactive_w1tc           :    1;
+            uint32_t touch_active_w1tc             :    1;
+            uint32_t saradc1_w1tc                  :    1;
+            uint32_t saradc2_w1tc                  :    1;
+            uint32_t tsens_w1tc                    :    1;
+            uint32_t start_w1tc                    :    1;
+            uint32_t sw_w1tc                       :    1;
+            uint32_t swd_w1tc                      :    1;
+            uint32_t touch_timeout_w1tc            :    1;
+            uint32_t touch_approach_loop_done_w1tc :    1;
+            uint32_t touch_scan_done_w1tc          :    1;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } sar_cocpu_int_ena_w1tc;

components/soc/esp32s3/include/soc/sensitive_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SENSITIVE_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG          (DR_REG_SENSITIVE_BASE + 0x0)
 /* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
@@ -1663,12 +1663,6 @@ extern "C" {
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S  12
 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: .*/
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
@@ -2007,12 +2001,6 @@ extern "C" {
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S  12
 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: .*/
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
@@ -2877,12 +2865,6 @@ extern "C" {
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S  12
 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: .*/
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
@@ -3221,12 +3203,6 @@ extern "C" {
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S  12
 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: .*/
 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
@@ -4091,12 +4067,6 @@ extern "C" {
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S  12
 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: .*/
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003
@@ -4739,7 +4709,7 @@ extern "C" {
 #define SENSITIVE_DIS_RTC_CPU_S  0
 
 #define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
-/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101280 ; */
 /*description: .*/
 #define SENSITIVE_DATE    0x0FFFFFFF
 #define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))

components/soc/esp32s3/include/soc/slc_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,1896 +11,1902 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_SLC_REG_H_
+#define _SOC_SLC_REG_H_
 
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "soc.h"
-
-#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
+#define SLC_SLCCONF0_REG          (DR_REG_SLC_BASE + 0x0)
 /* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_V 0x1
-#define SLC_SLC0_WR_RETRY_MASK_EN_S 18
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_MASK_EN    (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_M  (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_V  0x1
+#define SLC_SLC0_WR_RETRY_MASK_EN_S  18
 /* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_SEL (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_M (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_V 0x1
-#define SLC_SLC0_TOKEN_SEL_S 15
+/*description: .*/
+#define SLC_SLC0_TOKEN_SEL    (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_M  (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_V  0x1
+#define SLC_SLC0_TOKEN_SEL_S  15
 /* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_V 0x1
-#define SLC_SLC0_TOKEN_AUTO_CLR_S 14
+/*description: .*/
+#define SLC_SLC0_TOKEN_AUTO_CLR    (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_M  (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_V  0x1
+#define SLC_SLC0_TOKEN_AUTO_CLR_S  14
 /* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TXDATA_BURST_EN (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_V 0x1
-#define SLC_SLC0_TXDATA_BURST_EN_S 13
+/*description: .*/
+#define SLC_SLC0_TXDATA_BURST_EN    (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_M  (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_V  0x1
+#define SLC_SLC0_TXDATA_BURST_EN_S  13
 /* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TXDSCR_BURST_EN (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_V 0x1
-#define SLC_SLC0_TXDSCR_BURST_EN_S 12
+/*description: .*/
+#define SLC_SLC0_TXDSCR_BURST_EN    (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_M  (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_V  0x1
+#define SLC_SLC0_TXDSCR_BURST_EN_S  12
 /* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_AUTO_RET (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_M (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_V 0x1
-#define SLC_SLC0_TXLINK_AUTO_RET_S 11
+/*description: .*/
+#define SLC_SLC0_TXLINK_AUTO_RET    (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_M  (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_V  0x1
+#define SLC_SLC0_TXLINK_AUTO_RET_S  11
 /* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_AUTO_RET (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_M (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_V 0x1
-#define SLC_SLC0_RXLINK_AUTO_RET_S 10
+/*description: .*/
+#define SLC_SLC0_RXLINK_AUTO_RET    (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_M  (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_V  0x1
+#define SLC_SLC0_RXLINK_AUTO_RET_S  10
 /* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RXDATA_BURST_EN (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_M (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_V 0x1
-#define SLC_SLC0_RXDATA_BURST_EN_S 9
+/*description: .*/
+#define SLC_SLC0_RXDATA_BURST_EN    (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_M  (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_V  0x1
+#define SLC_SLC0_RXDATA_BURST_EN_S  9
 /* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RXDSCR_BURST_EN (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_M (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_V 0x1
-#define SLC_SLC0_RXDSCR_BURST_EN_S 8
+/*description: .*/
+#define SLC_SLC0_RXDSCR_BURST_EN    (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_M  (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_V  0x1
+#define SLC_SLC0_RXDSCR_BURST_EN_S  8
 /* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_NO_RESTART_CLR (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_M (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_V 0x1
-#define SLC_SLC0_RX_NO_RESTART_CLR_S 7
+/*description: .*/
+#define SLC_SLC0_RX_NO_RESTART_CLR    (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_M  (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_V  0x1
+#define SLC_SLC0_RX_NO_RESTART_CLR_S  7
 /* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_AUTO_WRBACK (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_M (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_V 0x1
-#define SLC_SLC0_RX_AUTO_WRBACK_S 6
+/*description: .*/
+#define SLC_SLC0_RX_AUTO_WRBACK    (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_M  (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_V  0x1
+#define SLC_SLC0_RX_AUTO_WRBACK_S  6
 /* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_LOOP_TEST (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_M (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_V 0x1
-#define SLC_SLC0_RX_LOOP_TEST_S 5
+/*description: .*/
+#define SLC_SLC0_RX_LOOP_TEST    (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_M  (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_V  0x1
+#define SLC_SLC0_RX_LOOP_TEST_S  5
 /* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_LOOP_TEST (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_M (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_V 0x1
-#define SLC_SLC0_TX_LOOP_TEST_S 4
+/*description: .*/
+#define SLC_SLC0_TX_LOOP_TEST    (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_M  (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_V  0x1
+#define SLC_SLC0_TX_LOOP_TEST_S  4
 /* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_AHBM_RST (BIT(3))
-#define SLC_AHBM_RST_M (BIT(3))
-#define SLC_AHBM_RST_V 0x1
-#define SLC_AHBM_RST_S 3
+/*description: .*/
+#define SLC_AHBM_RST    (BIT(3))
+#define SLC_AHBM_RST_M  (BIT(3))
+#define SLC_AHBM_RST_V  0x1
+#define SLC_AHBM_RST_S  3
 /* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_AHBM_FIFO_RST (BIT(2))
-#define SLC_AHBM_FIFO_RST_M (BIT(2))
-#define SLC_AHBM_FIFO_RST_V 0x1
-#define SLC_AHBM_FIFO_RST_S 2
+/*description: .*/
+#define SLC_AHBM_FIFO_RST    (BIT(2))
+#define SLC_AHBM_FIFO_RST_M  (BIT(2))
+#define SLC_AHBM_FIFO_RST_V  0x1
+#define SLC_AHBM_FIFO_RST_S  2
 /* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_RST (BIT(1))
-#define SLC_SLC0_RX_RST_M (BIT(1))
-#define SLC_SLC0_RX_RST_V 0x1
-#define SLC_SLC0_RX_RST_S 1
+/*description: .*/
+#define SLC_SLC0_RX_RST    (BIT(1))
+#define SLC_SLC0_RX_RST_M  (BIT(1))
+#define SLC_SLC0_RX_RST_V  0x1
+#define SLC_SLC0_RX_RST_S  1
 /* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_RST (BIT(0))
-#define SLC_SLC0_TX_RST_M (BIT(0))
-#define SLC_SLC0_TX_RST_V 0x1
-#define SLC_SLC0_TX_RST_S 0
+/*description: .*/
+#define SLC_SLC0_TX_RST    (BIT(0))
+#define SLC_SLC0_TX_RST_M  (BIT(0))
+#define SLC_SLC0_TX_RST_V  0x1
+#define SLC_SLC0_TX_RST_S  0
 
-#define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
+#define SLC_INT_RAW_REG          (DR_REG_SLC_BASE + 0x4)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S  26
 /* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_RAW (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_M (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_V 0x1
-#define SLC_CMD_DTC_INT_RAW_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_RAW    (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_M  (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_V  0x1
+#define SLC_CMD_DTC_INT_RAW_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S  19
 /* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_RAW (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_V 0x1
-#define SLC_SLC0_TOHOST_INT_RAW_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_RAW    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_V  0x1
+#define SLC_SLC0_TOHOST_INT_RAW_S  18
 /* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_RAW (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_V 0x1
-#define SLC_SLC0_RX_EOF_INT_RAW_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_RAW    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_EOF_INT_RAW_S  17
 /* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_RAW (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_V 0x1
-#define SLC_SLC0_RX_DONE_INT_RAW_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_RAW    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_RX_DONE_INT_RAW_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S  15
 /* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_RAW (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_V 0x1
-#define SLC_SLC0_TX_DONE_INT_RAW_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_RAW    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DONE_INT_RAW_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S  12
 /* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_RAW (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_V 0x1
-#define SLC_SLC0_TX_OVF_INT_RAW_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_RAW    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_OVF_INT_RAW_S  11
 /* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_RAW (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_V 0x1
-#define SLC_SLC0_RX_UDF_INT_RAW_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_RAW    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_UDF_INT_RAW_S  10
 /* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_RAW (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_V 0x1
-#define SLC_SLC0_TX_START_INT_RAW_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_RAW    (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_V  0x1
+#define SLC_SLC0_TX_START_INT_RAW_S  9
 /* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_RAW (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_V 0x1
-#define SLC_SLC0_RX_START_INT_RAW_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_RAW    (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_V  0x1
+#define SLC_SLC0_RX_START_INT_RAW_S  8
 /* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_RAW (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT7_INT_RAW_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_RAW    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT7_INT_RAW_S  7
 /* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_RAW (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT6_INT_RAW_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_RAW    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT6_INT_RAW_S  6
 /* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_RAW (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT5_INT_RAW_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_RAW    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT5_INT_RAW_S  5
 /* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_RAW (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT4_INT_RAW_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_RAW    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT4_INT_RAW_S  4
 /* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_RAW (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT3_INT_RAW_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_RAW    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT3_INT_RAW_S  3
 /* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_RAW (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT2_INT_RAW_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_RAW    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT2_INT_RAW_S  2
 /* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_RAW (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT1_INT_RAW_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_RAW    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT1_INT_RAW_S  1
 /* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_RAW (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_V 0x1
-#define SLC_FRHOST_BIT0_INT_RAW_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_RAW    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT0_INT_RAW_S  0
 
-#define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
+#define SLC_INT_ST_REG          (DR_REG_SLC_BASE + 0x8)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S  26
 /* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ST (BIT(25))
-#define SLC_CMD_DTC_INT_ST_M (BIT(25))
-#define SLC_CMD_DTC_INT_ST_V 0x1
-#define SLC_CMD_DTC_INT_ST_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_ST    (BIT(25))
+#define SLC_CMD_DTC_INT_ST_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ST_V  0x1
+#define SLC_CMD_DTC_INT_ST_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ST (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_ST    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ST (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_ST    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S  19
 /* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ST (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_V 0x1
-#define SLC_SLC0_TOHOST_INT_ST_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_ST    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_V  0x1
+#define SLC_SLC0_TOHOST_INT_ST_S  18
 /* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ST (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_V 0x1
-#define SLC_SLC0_RX_EOF_INT_ST_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_ST    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ST_S  17
 /* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ST (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_V 0x1
-#define SLC_SLC0_RX_DONE_INT_ST_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_ST    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ST_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ST (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_ST    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_S  15
 /* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ST (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_V 0x1
-#define SLC_SLC0_TX_DONE_INT_ST_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_ST    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ST_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S  12
 /* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ST (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_V 0x1
-#define SLC_SLC0_TX_OVF_INT_ST_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_ST    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ST_S  11
 /* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ST (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_V 0x1
-#define SLC_SLC0_RX_UDF_INT_ST_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_ST    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ST_S  10
 /* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ST (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_V 0x1
-#define SLC_SLC0_TX_START_INT_ST_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_ST    (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_V  0x1
+#define SLC_SLC0_TX_START_INT_ST_S  9
 /* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ST (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_V 0x1
-#define SLC_SLC0_RX_START_INT_ST_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_ST    (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_V  0x1
+#define SLC_SLC0_RX_START_INT_ST_S  8
 /* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ST (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_V 0x1
-#define SLC_FRHOST_BIT7_INT_ST_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_ST    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_V  0x1
+#define SLC_FRHOST_BIT7_INT_ST_S  7
 /* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ST (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_V 0x1
-#define SLC_FRHOST_BIT6_INT_ST_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_ST    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_V  0x1
+#define SLC_FRHOST_BIT6_INT_ST_S  6
 /* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ST (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_V 0x1
-#define SLC_FRHOST_BIT5_INT_ST_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_ST    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_V  0x1
+#define SLC_FRHOST_BIT5_INT_ST_S  5
 /* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ST (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_V 0x1
-#define SLC_FRHOST_BIT4_INT_ST_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_ST    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_V  0x1
+#define SLC_FRHOST_BIT4_INT_ST_S  4
 /* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ST (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_V 0x1
-#define SLC_FRHOST_BIT3_INT_ST_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_ST    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_V  0x1
+#define SLC_FRHOST_BIT3_INT_ST_S  3
 /* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ST (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_V 0x1
-#define SLC_FRHOST_BIT2_INT_ST_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_ST    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_V  0x1
+#define SLC_FRHOST_BIT2_INT_ST_S  2
 /* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ST (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_V 0x1
-#define SLC_FRHOST_BIT1_INT_ST_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_ST    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_V  0x1
+#define SLC_FRHOST_BIT1_INT_ST_S  1
 /* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ST (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_V 0x1
-#define SLC_FRHOST_BIT0_INT_ST_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_ST    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_V  0x1
+#define SLC_FRHOST_BIT0_INT_ST_S  0
 
-#define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC)
+#define SLC_INT_ENA_REG          (DR_REG_SLC_BASE + 0xC)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S  26
 /* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ENA (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_M (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_V 0x1
-#define SLC_CMD_DTC_INT_ENA_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_ENA    (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_V  0x1
+#define SLC_CMD_DTC_INT_ENA_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S  19
 /* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ENA (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_V 0x1
-#define SLC_SLC0_TOHOST_INT_ENA_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_ENA    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_V  0x1
+#define SLC_SLC0_TOHOST_INT_ENA_S  18
 /* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ENA (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_V 0x1
-#define SLC_SLC0_RX_EOF_INT_ENA_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_ENA    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ENA_S  17
 /* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ENA (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_V 0x1
-#define SLC_SLC0_RX_DONE_INT_ENA_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_ENA    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ENA_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S  15
 /* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ENA (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_V 0x1
-#define SLC_SLC0_TX_DONE_INT_ENA_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_ENA    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ENA_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S  12
 /* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ENA (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_V 0x1
-#define SLC_SLC0_TX_OVF_INT_ENA_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_ENA    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ENA_S  11
 /* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ENA (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_V 0x1
-#define SLC_SLC0_RX_UDF_INT_ENA_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_ENA    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ENA_S  10
 /* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ENA (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_V 0x1
-#define SLC_SLC0_TX_START_INT_ENA_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_ENA    (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_V  0x1
+#define SLC_SLC0_TX_START_INT_ENA_S  9
 /* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ENA (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_V 0x1
-#define SLC_SLC0_RX_START_INT_ENA_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_ENA    (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_V  0x1
+#define SLC_SLC0_RX_START_INT_ENA_S  8
 /* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ENA (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT7_INT_ENA_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_ENA    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT7_INT_ENA_S  7
 /* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ENA (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT6_INT_ENA_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_ENA    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT6_INT_ENA_S  6
 /* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ENA (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT5_INT_ENA_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_ENA    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT5_INT_ENA_S  5
 /* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ENA (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT4_INT_ENA_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_ENA    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT4_INT_ENA_S  4
 /* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ENA (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT3_INT_ENA_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_ENA    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT3_INT_ENA_S  3
 /* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ENA (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT2_INT_ENA_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_ENA    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT2_INT_ENA_S  2
 /* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ENA (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT1_INT_ENA_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_ENA    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT1_INT_ENA_S  1
 /* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ENA (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_V 0x1
-#define SLC_FRHOST_BIT0_INT_ENA_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_ENA    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT0_INT_ENA_S  0
 
-#define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
+#define SLC_INT_CLR_REG          (DR_REG_SLC_BASE + 0x10)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S  26
 /* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_CLR (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_M (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_V 0x1
-#define SLC_CMD_DTC_INT_CLR_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_CLR    (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_M  (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_V  0x1
+#define SLC_CMD_DTC_INT_CLR_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S  19
 /* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_CLR (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_V 0x1
-#define SLC_SLC0_TOHOST_INT_CLR_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_CLR    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_V  0x1
+#define SLC_SLC0_TOHOST_INT_CLR_S  18
 /* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_CLR (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_V 0x1
-#define SLC_SLC0_RX_EOF_INT_CLR_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_CLR    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_EOF_INT_CLR_S  17
 /* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_CLR (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_V 0x1
-#define SLC_SLC0_RX_DONE_INT_CLR_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_CLR    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_RX_DONE_INT_CLR_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S  15
 /* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_CLR (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_V 0x1
-#define SLC_SLC0_TX_DONE_INT_CLR_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_CLR    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DONE_INT_CLR_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S  12
 /* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_CLR (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_V 0x1
-#define SLC_SLC0_TX_OVF_INT_CLR_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_CLR    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_OVF_INT_CLR_S  11
 /* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_CLR (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_V 0x1
-#define SLC_SLC0_RX_UDF_INT_CLR_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_CLR    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_UDF_INT_CLR_S  10
 /* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_CLR (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_V 0x1
-#define SLC_SLC0_TX_START_INT_CLR_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_CLR    (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_V  0x1
+#define SLC_SLC0_TX_START_INT_CLR_S  9
 /* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_CLR (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_V 0x1
-#define SLC_SLC0_RX_START_INT_CLR_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_CLR    (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_V  0x1
+#define SLC_SLC0_RX_START_INT_CLR_S  8
 /* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_CLR (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT7_INT_CLR_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_CLR    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT7_INT_CLR_S  7
 /* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_CLR (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT6_INT_CLR_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_CLR    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT6_INT_CLR_S  6
 /* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_CLR (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT5_INT_CLR_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_CLR    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT5_INT_CLR_S  5
 /* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_CLR (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT4_INT_CLR_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_CLR    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT4_INT_CLR_S  4
 /* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_CLR (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT3_INT_CLR_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_CLR    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT3_INT_CLR_S  3
 /* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_CLR (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT2_INT_CLR_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_CLR    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT2_INT_CLR_S  2
 /* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_CLR (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT1_INT_CLR_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_CLR    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT1_INT_CLR_S  1
 /* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_CLR (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_V 0x1
-#define SLC_FRHOST_BIT0_INT_CLR_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_CLR    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT0_INT_CLR_S  0
 
-#define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
+#define SLC_SLCRX_STATUS_REG          (DR_REG_SLC_BASE + 0x24)
 /* SLC_SLC0_RX_BUF_LEN : RO ;bitpos:[13:2] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_BUF_LEN 0x00000FFF
-#define SLC_SLC0_RX_BUF_LEN_M ((SLC_SLC0_RX_BUF_LEN_V) << (SLC_SLC0_RX_BUF_LEN_S))
-#define SLC_SLC0_RX_BUF_LEN_V 0xFFF
-#define SLC_SLC0_RX_BUF_LEN_S 2
+/*description: .*/
+#define SLC_SLC0_RX_BUF_LEN    0x00000FFF
+#define SLC_SLC0_RX_BUF_LEN_M  ((SLC_SLC0_RX_BUF_LEN_V)<<(SLC_SLC0_RX_BUF_LEN_S))
+#define SLC_SLC0_RX_BUF_LEN_V  0xFFF
+#define SLC_SLC0_RX_BUF_LEN_S  2
 /* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_EMPTY (BIT(1))
-#define SLC_SLC0_RX_EMPTY_M (BIT(1))
-#define SLC_SLC0_RX_EMPTY_V 0x1
-#define SLC_SLC0_RX_EMPTY_S 1
+/*description: .*/
+#define SLC_SLC0_RX_EMPTY    (BIT(1))
+#define SLC_SLC0_RX_EMPTY_M  (BIT(1))
+#define SLC_SLC0_RX_EMPTY_V  0x1
+#define SLC_SLC0_RX_EMPTY_S  1
 /* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_FULL (BIT(0))
-#define SLC_SLC0_RX_FULL_M (BIT(0))
-#define SLC_SLC0_RX_FULL_V 0x1
-#define SLC_SLC0_RX_FULL_S 0
+/*description: .*/
+#define SLC_SLC0_RX_FULL    (BIT(0))
+#define SLC_SLC0_RX_FULL_M  (BIT(0))
+#define SLC_SLC0_RX_FULL_V  0x1
+#define SLC_SLC0_RX_FULL_S  0
 
-#define SLC_0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28)
+#define SLC_RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x28)
 /* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_RXFIFO_PUSH (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_M (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_V 0x1
-#define SLC_SLC0_RXFIFO_PUSH_S 16
+/*description: .*/
+#define SLC_SLC0_RXFIFO_PUSH    (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_M  (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_V  0x1
+#define SLC_SLC0_RXFIFO_PUSH_S  16
 /* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define SLC_SLC0_RXFIFO_WDATA 0x000001FF
-#define SLC_SLC0_RXFIFO_WDATA_M ((SLC_SLC0_RXFIFO_WDATA_V) << (SLC_SLC0_RXFIFO_WDATA_S))
-#define SLC_SLC0_RXFIFO_WDATA_V 0x1FF
-#define SLC_SLC0_RXFIFO_WDATA_S 0
+/*description: .*/
+#define SLC_SLC0_RXFIFO_WDATA    0x000001FF
+#define SLC_SLC0_RXFIFO_WDATA_M  ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
+#define SLC_SLC0_RXFIFO_WDATA_V  0x1FF
+#define SLC_SLC0_RXFIFO_WDATA_S  0
 
-#define SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30)
+#define SLC_SLCTX_STATUS_REG          (DR_REG_SLC_BASE + 0x30)
 /* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_EMPTY (BIT(1))
-#define SLC_SLC0_TX_EMPTY_M (BIT(1))
-#define SLC_SLC0_TX_EMPTY_V 0x1
-#define SLC_SLC0_TX_EMPTY_S 1
+/*description: .*/
+#define SLC_SLC0_TX_EMPTY    (BIT(1))
+#define SLC_SLC0_TX_EMPTY_M  (BIT(1))
+#define SLC_SLC0_TX_EMPTY_V  0x1
+#define SLC_SLC0_TX_EMPTY_S  1
 /* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_FULL (BIT(0))
-#define SLC_SLC0_TX_FULL_M (BIT(0))
-#define SLC_SLC0_TX_FULL_V 0x1
-#define SLC_SLC0_TX_FULL_S 0
+/*description: .*/
+#define SLC_SLC0_TX_FULL    (BIT(0))
+#define SLC_SLC0_TX_FULL_M  (BIT(0))
+#define SLC_SLC0_TX_FULL_V  0x1
+#define SLC_SLC0_TX_FULL_S  0
 
-#define SLC_0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34)
+#define SLC_TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x34)
 /* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TXFIFO_POP (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_M (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_V 0x1
-#define SLC_SLC0_TXFIFO_POP_S 16
+/*description: .*/
+#define SLC_SLC0_TXFIFO_POP    (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_M  (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_V  0x1
+#define SLC_SLC0_TXFIFO_POP_S  16
 /* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SLC_SLC0_TXFIFO_RDATA 0x000007FF
-#define SLC_SLC0_TXFIFO_RDATA_M ((SLC_SLC0_TXFIFO_RDATA_V) << (SLC_SLC0_TXFIFO_RDATA_S))
-#define SLC_SLC0_TXFIFO_RDATA_V 0x7FF
-#define SLC_SLC0_TXFIFO_RDATA_S 0
+/*description: .*/
+#define SLC_SLC0_TXFIFO_RDATA    0x000007FF
+#define SLC_SLC0_TXFIFO_RDATA_M  ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
+#define SLC_SLC0_TXFIFO_RDATA_V  0x7FF
+#define SLC_SLC0_TXFIFO_RDATA_S  0
 
-#define SLC_0RX_LINK_REG (DR_REG_SLC_BASE + 0x3C)
+#define SLC_RX_LINK_REG          (DR_REG_SLC_BASE + 0x3C)
 /* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_PARK (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_M (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_V 0x1
-#define SLC_SLC0_RXLINK_PARK_S 31
+/*description: .*/
+#define SLC_SLC0_RXLINK_PARK    (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_M  (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_V  0x1
+#define SLC_SLC0_RXLINK_PARK_S  31
 /* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_RESTART (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_M (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_V 0x1
-#define SLC_SLC0_RXLINK_RESTART_S 30
+/*description: .*/
+#define SLC_SLC0_RXLINK_RESTART    (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_M  (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_V  0x1
+#define SLC_SLC0_RXLINK_RESTART_S  30
 /* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_START (BIT(29))
-#define SLC_SLC0_RXLINK_START_M (BIT(29))
-#define SLC_SLC0_RXLINK_START_V 0x1
-#define SLC_SLC0_RXLINK_START_S 29
+/*description: .*/
+#define SLC_SLC0_RXLINK_START    (BIT(29))
+#define SLC_SLC0_RXLINK_START_M  (BIT(29))
+#define SLC_SLC0_RXLINK_START_V  0x1
+#define SLC_SLC0_RXLINK_START_S  29
 /* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_STOP (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_M (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_V 0x1
-#define SLC_SLC0_RXLINK_STOP_S 28
+/*description: .*/
+#define SLC_SLC0_RXLINK_STOP    (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_M  (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_V  0x1
+#define SLC_SLC0_RXLINK_STOP_S  28
 /* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_ADDR 0x000FFFFF
-#define SLC_SLC0_RXLINK_ADDR_M ((SLC_SLC0_RXLINK_ADDR_V) << (SLC_SLC0_RXLINK_ADDR_S))
-#define SLC_SLC0_RXLINK_ADDR_V 0xFFFFF
-#define SLC_SLC0_RXLINK_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RXLINK_ADDR    0x000FFFFF
+#define SLC_SLC0_RXLINK_ADDR_M  ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
+#define SLC_SLC0_RXLINK_ADDR_V  0xFFFFF
+#define SLC_SLC0_RXLINK_ADDR_S  0
 
-#define SLC_0TX_LINK_REG (DR_REG_SLC_BASE + 0x40)
+#define SLC_TX_LINK_REG          (DR_REG_SLC_BASE + 0x40)
 /* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_PARK (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_M (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_V 0x1
-#define SLC_SLC0_TXLINK_PARK_S 31
+/*description: .*/
+#define SLC_SLC0_TXLINK_PARK    (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_M  (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_V  0x1
+#define SLC_SLC0_TXLINK_PARK_S  31
 /* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_RESTART (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_M (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_V 0x1
-#define SLC_SLC0_TXLINK_RESTART_S 30
+/*description: .*/
+#define SLC_SLC0_TXLINK_RESTART    (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_M  (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_V  0x1
+#define SLC_SLC0_TXLINK_RESTART_S  30
 /* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_START (BIT(29))
-#define SLC_SLC0_TXLINK_START_M (BIT(29))
-#define SLC_SLC0_TXLINK_START_V 0x1
-#define SLC_SLC0_TXLINK_START_S 29
+/*description: .*/
+#define SLC_SLC0_TXLINK_START    (BIT(29))
+#define SLC_SLC0_TXLINK_START_M  (BIT(29))
+#define SLC_SLC0_TXLINK_START_V  0x1
+#define SLC_SLC0_TXLINK_START_S  29
 /* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_STOP (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_M (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_V 0x1
-#define SLC_SLC0_TXLINK_STOP_S 28
+/*description: .*/
+#define SLC_SLC0_TXLINK_STOP    (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_M  (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_V  0x1
+#define SLC_SLC0_TXLINK_STOP_S  28
 /* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_ADDR 0x000FFFFF
-#define SLC_SLC0_TXLINK_ADDR_M ((SLC_SLC0_TXLINK_ADDR_V) << (SLC_SLC0_TXLINK_ADDR_S))
-#define SLC_SLC0_TXLINK_ADDR_V 0xFFFFF
-#define SLC_SLC0_TXLINK_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TXLINK_ADDR    0x000FFFFF
+#define SLC_SLC0_TXLINK_ADDR_M  ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
+#define SLC_SLC0_TXLINK_ADDR_V  0xFFFFF
+#define SLC_SLC0_TXLINK_ADDR_S  0
 
-#define SLC_INTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x4C)
+#define SLC_SLCINTVEC_TOHOST_REG          (DR_REG_SLC_BASE + 0x4C)
 /* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INTVEC 0x000000FF
-#define SLC_SLC0_TOHOST_INTVEC_M ((SLC_SLC0_TOHOST_INTVEC_V) << (SLC_SLC0_TOHOST_INTVEC_S))
-#define SLC_SLC0_TOHOST_INTVEC_V 0xFF
-#define SLC_SLC0_TOHOST_INTVEC_S 0
+/*description: .*/
+#define SLC_SLC0_TOHOST_INTVEC    0x000000FF
+#define SLC_SLC0_TOHOST_INTVEC_M  ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
+#define SLC_SLC0_TOHOST_INTVEC_V  0xFF
+#define SLC_SLC0_TOHOST_INTVEC_S  0
 
-#define SLC_0TOKEN0_REG (DR_REG_SLC_BASE + 0x50)
+#define SLC_TOKEN0_REG          (DR_REG_SLC_BASE + 0x50)
 /* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0 0x00000FFF
-#define SLC_SLC0_TOKEN0_M ((SLC_SLC0_TOKEN0_V) << (SLC_SLC0_TOKEN0_S))
-#define SLC_SLC0_TOKEN0_V 0xFFF
-#define SLC_SLC0_TOKEN0_S 16
+/*description: .*/
+#define SLC_SLC0_TOKEN0    0x00000FFF
+#define SLC_SLC0_TOKEN0_M  ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
+#define SLC_SLC0_TOKEN0_V  0xFFF
+#define SLC_SLC0_TOKEN0_S  16
 /* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_INC_MORE (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_M (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_V 0x1
-#define SLC_SLC0_TOKEN0_INC_MORE_S 14
+/*description: .*/
+#define SLC_SLC0_TOKEN0_INC_MORE    (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_M  (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_V  0x1
+#define SLC_SLC0_TOKEN0_INC_MORE_S  14
 /* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_INC (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_M (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_V 0x1
-#define SLC_SLC0_TOKEN0_INC_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN0_INC    (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_M  (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_V  0x1
+#define SLC_SLC0_TOKEN0_INC_S  13
 /* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_WR (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_M (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_V 0x1
-#define SLC_SLC0_TOKEN0_WR_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_WR    (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_V  0x1
+#define SLC_SLC0_TOKEN0_WR_S  12
 /* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_WDATA 0x00000FFF
-#define SLC_SLC0_TOKEN0_WDATA_M ((SLC_SLC0_TOKEN0_WDATA_V) << (SLC_SLC0_TOKEN0_WDATA_S))
-#define SLC_SLC0_TOKEN0_WDATA_V 0xFFF
-#define SLC_SLC0_TOKEN0_WDATA_S 0
+/*description: .*/
+#define SLC_SLC0_TOKEN0_WDATA    0x00000FFF
+#define SLC_SLC0_TOKEN0_WDATA_M  ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
+#define SLC_SLC0_TOKEN0_WDATA_V  0xFFF
+#define SLC_SLC0_TOKEN0_WDATA_S  0
 
-#define SLC_0TOKEN1_REG (DR_REG_SLC_BASE + 0x54)
+#define SLC_TOKEN1_REG          (DR_REG_SLC_BASE + 0x54)
 /* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1 0x00000FFF
-#define SLC_SLC0_TOKEN1_M ((SLC_SLC0_TOKEN1_V) << (SLC_SLC0_TOKEN1_S))
-#define SLC_SLC0_TOKEN1_V 0xFFF
-#define SLC_SLC0_TOKEN1_S 16
+/*description: .*/
+#define SLC_SLC0_TOKEN1    0x00000FFF
+#define SLC_SLC0_TOKEN1_M  ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
+#define SLC_SLC0_TOKEN1_V  0xFFF
+#define SLC_SLC0_TOKEN1_S  16
 /* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_M (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_V 0x1
-#define SLC_SLC0_TOKEN1_INC_MORE_S 14
+/*description: .*/
+#define SLC_SLC0_TOKEN1_INC_MORE    (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_M  (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_V  0x1
+#define SLC_SLC0_TOKEN1_INC_MORE_S  14
 /* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_INC (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_M (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_V 0x1
-#define SLC_SLC0_TOKEN1_INC_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_INC    (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_V  0x1
+#define SLC_SLC0_TOKEN1_INC_S  13
 /* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_WR (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_M (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_V 0x1
-#define SLC_SLC0_TOKEN1_WR_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN1_WR    (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_M  (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_V  0x1
+#define SLC_SLC0_TOKEN1_WR_S  12
 /* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_WDATA 0x00000FFF
-#define SLC_SLC0_TOKEN1_WDATA_M ((SLC_SLC0_TOKEN1_WDATA_V) << (SLC_SLC0_TOKEN1_WDATA_S))
-#define SLC_SLC0_TOKEN1_WDATA_V 0xFFF
-#define SLC_SLC0_TOKEN1_WDATA_S 0
+/*description: .*/
+#define SLC_SLC0_TOKEN1_WDATA    0x00000FFF
+#define SLC_SLC0_TOKEN1_WDATA_M  ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
+#define SLC_SLC0_TOKEN1_WDATA_V  0xFFF
+#define SLC_SLC0_TOKEN1_WDATA_S  0
 
-#define SLC_CONF1_REG (DR_REG_SLC_BASE + 0x60)
+#define SLC_SLCCONF1_REG          (DR_REG_SLC_BASE + 0x60)
 /* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CLK_EN (BIT(22))
-#define SLC_CLK_EN_M (BIT(22))
-#define SLC_CLK_EN_V 0x1
-#define SLC_CLK_EN_S 22
+/*description: .*/
+#define SLC_CLK_EN    (BIT(22))
+#define SLC_CLK_EN_M  (BIT(22))
+#define SLC_CLK_EN_V  0x1
+#define SLC_CLK_EN_S  22
 /* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_HOST_INT_LEVEL_SEL (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_M (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_V 0x1
-#define SLC_HOST_INT_LEVEL_SEL_S 19
+/*description: .*/
+#define SLC_HOST_INT_LEVEL_SEL    (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_M  (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_V  0x1
+#define SLC_HOST_INT_LEVEL_SEL_S  19
 /* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_STITCH_EN (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_M (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_V 0x1
-#define SLC_SLC0_RX_STITCH_EN_S 6
+/*description: .*/
+#define SLC_SLC0_RX_STITCH_EN    (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_M  (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_V  0x1
+#define SLC_SLC0_RX_STITCH_EN_S  6
 /* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_STITCH_EN (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_M (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_V 0x1
-#define SLC_SLC0_TX_STITCH_EN_S 5
+/*description: .*/
+#define SLC_SLC0_TX_STITCH_EN    (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_M  (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_V  0x1
+#define SLC_SLC0_TX_STITCH_EN_S  5
 /* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_LEN_AUTO_CLR (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_M (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_V 0x1
-#define SLC_SLC0_LEN_AUTO_CLR_S 4
+/*description: .*/
+#define SLC_SLC0_LEN_AUTO_CLR    (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_M  (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_V  0x1
+#define SLC_SLC0_LEN_AUTO_CLR_S  4
 /* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SLC_CMD_HOLD_EN (BIT(3))
-#define SLC_CMD_HOLD_EN_M (BIT(3))
-#define SLC_CMD_HOLD_EN_V 0x1
-#define SLC_CMD_HOLD_EN_S 3
+/*description: .*/
+#define SLC_CMD_HOLD_EN    (BIT(3))
+#define SLC_CMD_HOLD_EN_M  (BIT(3))
+#define SLC_CMD_HOLD_EN_V  0x1
+#define SLC_CMD_HOLD_EN_S  3
 /* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_CHECK_SUM_EN (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_M (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_V 0x1
-#define SLC_SLC0_RX_CHECK_SUM_EN_S 2
+/*description: .*/
+#define SLC_SLC0_RX_CHECK_SUM_EN    (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_M  (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_V  0x1
+#define SLC_SLC0_RX_CHECK_SUM_EN_S  2
 /* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_CHECK_SUM_EN (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_M (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_V 0x1
-#define SLC_SLC0_TX_CHECK_SUM_EN_S 1
+/*description: .*/
+#define SLC_SLC0_TX_CHECK_SUM_EN    (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_M  (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_V  0x1
+#define SLC_SLC0_TX_CHECK_SUM_EN_S  1
 /* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_CHECK_OWNER (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_M (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_V 0x1
-#define SLC_SLC0_CHECK_OWNER_S 0
+/*description: .*/
+#define SLC_SLC0_CHECK_OWNER    (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_M  (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_V  0x1
+#define SLC_SLC0_CHECK_OWNER_S  0
 
-#define SLC_0_STATE0_REG (DR_REG_SLC_BASE + 0x64)
+#define SLC_STATE0_REG          (DR_REG_SLC_BASE + 0x64)
 /* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_STATE0 0xFFFFFFFF
-#define SLC_SLC0_STATE0_M ((SLC_SLC0_STATE0_V) << (SLC_SLC0_STATE0_S))
-#define SLC_SLC0_STATE0_V 0xFFFFFFFF
-#define SLC_SLC0_STATE0_S 0
+/*description: .*/
+#define SLC_SLC0_STATE0    0xFFFFFFFF
+#define SLC_SLC0_STATE0_M  ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
+#define SLC_SLC0_STATE0_V  0xFFFFFFFF
+#define SLC_SLC0_STATE0_S  0
 
-#define SLC_0_STATE1_REG (DR_REG_SLC_BASE + 0x68)
+#define SLC_STATE1_REG          (DR_REG_SLC_BASE + 0x68)
 /* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_STATE1 0xFFFFFFFF
-#define SLC_SLC0_STATE1_M ((SLC_SLC0_STATE1_V) << (SLC_SLC0_STATE1_S))
-#define SLC_SLC0_STATE1_V 0xFFFFFFFF
-#define SLC_SLC0_STATE1_S 0
+/*description: .*/
+#define SLC_SLC0_STATE1    0xFFFFFFFF
+#define SLC_SLC0_STATE1_M  ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
+#define SLC_SLC0_STATE1_V  0xFFFFFFFF
+#define SLC_SLC0_STATE1_S  0
 
-#define SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x74)
+#define SLC_SLCBRIDGE_CONF_REG          (DR_REG_SLC_BASE + 0x74)
 /* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
-/*description: */
-#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF
-#define SLC_TX_PUSH_IDLE_NUM_M ((SLC_TX_PUSH_IDLE_NUM_V) << (SLC_TX_PUSH_IDLE_NUM_S))
-#define SLC_TX_PUSH_IDLE_NUM_V 0xFFFF
-#define SLC_TX_PUSH_IDLE_NUM_S 16
+/*description: .*/
+#define SLC_TX_PUSH_IDLE_NUM    0x0000FFFF
+#define SLC_TX_PUSH_IDLE_NUM_M  ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
+#define SLC_TX_PUSH_IDLE_NUM_V  0xFFFF
+#define SLC_TX_PUSH_IDLE_NUM_S  16
 /* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: */
-#define SLC_HDA_MAP_128K (BIT(13))
-#define SLC_HDA_MAP_128K_M (BIT(13))
-#define SLC_HDA_MAP_128K_V 0x1
-#define SLC_HDA_MAP_128K_S 13
+/*description: .*/
+#define SLC_HDA_MAP_128K    (BIT(13))
+#define SLC_HDA_MAP_128K_M  (BIT(13))
+#define SLC_HDA_MAP_128K_V  0x1
+#define SLC_HDA_MAP_128K_S  13
 /* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TX_DUMMY_MODE (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_M (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_V 0x1
-#define SLC_SLC0_TX_DUMMY_MODE_S 12
+/*description: .*/
+#define SLC_SLC0_TX_DUMMY_MODE    (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_M  (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_V  0x1
+#define SLC_SLC0_TX_DUMMY_MODE_S  12
 /* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
-/*description: */
-#define SLC_FIFO_MAP_ENA 0x0000000F
-#define SLC_FIFO_MAP_ENA_M ((SLC_FIFO_MAP_ENA_V) << (SLC_FIFO_MAP_ENA_S))
-#define SLC_FIFO_MAP_ENA_V 0xF
-#define SLC_FIFO_MAP_ENA_S 8
+/*description: .*/
+#define SLC_FIFO_MAP_ENA    0x0000000F
+#define SLC_FIFO_MAP_ENA_M  ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
+#define SLC_FIFO_MAP_ENA_V  0xF
+#define SLC_FIFO_MAP_ENA_S  8
 /* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: */
-#define SLC_TXEOF_ENA 0x0000003F
-#define SLC_TXEOF_ENA_M ((SLC_TXEOF_ENA_V) << (SLC_TXEOF_ENA_S))
-#define SLC_TXEOF_ENA_V 0x3F
-#define SLC_TXEOF_ENA_S 0
+/*description: .*/
+#define SLC_TXEOF_ENA    0x0000003F
+#define SLC_TXEOF_ENA_M  ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
+#define SLC_TXEOF_ENA_V  0x3F
+#define SLC_TXEOF_ENA_S  0
 
-#define SLC_0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x78)
+#define SLC_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x78)
 /* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_M ((SLC_SLC0_TO_EOF_DES_ADDR_V) << (SLC_SLC0_TO_EOF_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TO_EOF_DES_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_M  ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_S  0
 
-#define SLC_0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x7C)
+#define SLC_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x7C)
 /* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V) << (SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S  0
 
-#define SLC_0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x80)
+#define SLC_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x80)
 /* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V) << (SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S  0
 
-#define SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0x90)
+#define SLC_AHB_TEST_REG          (DR_REG_SLC_BASE + 0x90)
 /* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SLC_AHB_TESTADDR 0x00000003
-#define SLC_AHB_TESTADDR_M ((SLC_AHB_TESTADDR_V) << (SLC_AHB_TESTADDR_S))
-#define SLC_AHB_TESTADDR_V 0x3
-#define SLC_AHB_TESTADDR_S 4
+/*description: .*/
+#define SLC_AHB_TESTADDR    0x00000003
+#define SLC_AHB_TESTADDR_M  ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
+#define SLC_AHB_TESTADDR_V  0x3
+#define SLC_AHB_TESTADDR_S  4
 /* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define SLC_AHB_TESTMODE 0x00000007
-#define SLC_AHB_TESTMODE_M ((SLC_AHB_TESTMODE_V) << (SLC_AHB_TESTMODE_S))
-#define SLC_AHB_TESTMODE_V 0x7
-#define SLC_AHB_TESTMODE_S 0
+/*description: .*/
+#define SLC_AHB_TESTMODE    0x00000007
+#define SLC_AHB_TESTMODE_M  ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
+#define SLC_AHB_TESTMODE_V  0x7
+#define SLC_AHB_TESTMODE_S  0
 
-#define SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0x94)
+#define SLC_SDIO_ST_REG          (DR_REG_SLC_BASE + 0x94)
 /* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
-/*description: */
-#define SLC_FUNC1_ACC_STATE 0x0000001F
-#define SLC_FUNC1_ACC_STATE_M ((SLC_FUNC1_ACC_STATE_V) << (SLC_FUNC1_ACC_STATE_S))
-#define SLC_FUNC1_ACC_STATE_V 0x1F
-#define SLC_FUNC1_ACC_STATE_S 16
+/*description: .*/
+#define SLC_FUNC1_ACC_STATE    0x0000001F
+#define SLC_FUNC1_ACC_STATE_M  ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
+#define SLC_FUNC1_ACC_STATE_V  0x1F
+#define SLC_FUNC1_ACC_STATE_S  16
 /* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
-/*description: */
-#define SLC_BUS_ST 0x00000007
-#define SLC_BUS_ST_M ((SLC_BUS_ST_V) << (SLC_BUS_ST_S))
-#define SLC_BUS_ST_V 0x7
-#define SLC_BUS_ST_S 12
+/*description: .*/
+#define SLC_BUS_ST    0x00000007
+#define SLC_BUS_ST_M  ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
+#define SLC_BUS_ST_V  0x7
+#define SLC_BUS_ST_S  12
 /* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SDIO_WAKEUP (BIT(8))
-#define SLC_SDIO_WAKEUP_M (BIT(8))
-#define SLC_SDIO_WAKEUP_V 0x1
-#define SLC_SDIO_WAKEUP_S 8
+/*description: .*/
+#define SLC_SDIO_WAKEUP    (BIT(8))
+#define SLC_SDIO_WAKEUP_M  (BIT(8))
+#define SLC_SDIO_WAKEUP_V  0x1
+#define SLC_SDIO_WAKEUP_S  8
 /* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: */
-#define SLC_FUNC_ST 0x0000000F
-#define SLC_FUNC_ST_M ((SLC_FUNC_ST_V) << (SLC_FUNC_ST_S))
-#define SLC_FUNC_ST_V 0xF
-#define SLC_FUNC_ST_S 4
+/*description: .*/
+#define SLC_FUNC_ST    0x0000000F
+#define SLC_FUNC_ST_M  ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
+#define SLC_FUNC_ST_V  0xF
+#define SLC_FUNC_ST_S  4
 /* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define SLC_CMD_ST 0x00000007
-#define SLC_CMD_ST_M ((SLC_CMD_ST_V) << (SLC_CMD_ST_S))
-#define SLC_CMD_ST_V 0x7
-#define SLC_CMD_ST_S 0
+/*description: .*/
+#define SLC_CMD_ST    0x00000007
+#define SLC_CMD_ST_M  ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
+#define SLC_CMD_ST_V  0x7
+#define SLC_CMD_ST_S  0
 
-#define SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0x98)
+#define SLC_RX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0x98)
 /* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
-/*description: */
-#define SLC_SLC0_RD_RETRY_THRESHOLD 0x000007FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_M ((SLC_SLC0_RD_RETRY_THRESHOLD_V) << (SLC_SLC0_RD_RETRY_THRESHOLD_S))
-#define SLC_SLC0_RD_RETRY_THRESHOLD_V 0x7FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_S 5
+/*description: .*/
+#define SLC_SLC0_RD_RETRY_THRESHOLD    0x000007FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_M  ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
+#define SLC_SLC0_RD_RETRY_THRESHOLD_V  0x7FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_S  5
 /* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_FILL_EN (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_M (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_V 0x1
-#define SLC_SLC0_RX_FILL_EN_S 4
+/*description: .*/
+#define SLC_SLC0_RX_FILL_EN    (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_M  (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_V  0x1
+#define SLC_SLC0_RX_FILL_EN_S  4
 /* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_MODE (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_M (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_V 0x1
-#define SLC_SLC0_RX_EOF_MODE_S 3
+/*description: .*/
+#define SLC_SLC0_RX_EOF_MODE    (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_M  (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_V  0x1
+#define SLC_SLC0_RX_EOF_MODE_S  3
 /* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_FILL_MODE (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_M (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_V 0x1
-#define SLC_SLC0_RX_FILL_MODE_S 2
+/*description: .*/
+#define SLC_SLC0_RX_FILL_MODE    (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_M  (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_V  0x1
+#define SLC_SLC0_RX_FILL_MODE_S  2
 /* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_INFOR_NO_REPLACE (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_M (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_V 0x1
-#define SLC_SLC0_INFOR_NO_REPLACE_S 1
+/*description: .*/
+#define SLC_SLC0_INFOR_NO_REPLACE    (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_M  (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_V  0x1
+#define SLC_SLC0_INFOR_NO_REPLACE_S  1
 /* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_NO_REPLACE (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_M (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_V 0x1
-#define SLC_SLC0_TOKEN_NO_REPLACE_S 0
+/*description: .*/
+#define SLC_SLC0_TOKEN_NO_REPLACE    (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_M  (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_V  0x1
+#define SLC_SLC0_TOKEN_NO_REPLACE_S  0
 
-#define SLC_0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0x9C)
+#define SLC_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0x9C)
 /* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_M ((SLC_SLC0_TXLINK_DSCR_V) << (SLC_SLC0_TXLINK_DSCR_S))
-#define SLC_SLC0_TXLINK_DSCR_V 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_S 0
+/*description: .*/
+#define SLC_SLC0_TXLINK_DSCR    0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_M  ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
+#define SLC_SLC0_TXLINK_DSCR_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_S  0
 
-#define SLC_0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xA0)
+#define SLC_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xA0)
 /* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_M ((SLC_SLC0_TXLINK_DSCR_BF0_V) << (SLC_SLC0_TXLINK_DSCR_BF0_S))
-#define SLC_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_S 0
+/*description: .*/
+#define SLC_SLC0_TXLINK_DSCR_BF0    0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_M  ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
+#define SLC_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_S  0
 
-#define SLC_0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xA4)
+#define SLC_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xA4)
 /* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_M ((SLC_SLC0_TXLINK_DSCR_BF1_V) << (SLC_SLC0_TXLINK_DSCR_BF1_S))
-#define SLC_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_S 0
+/*description: .*/
+#define SLC_SLC0_TXLINK_DSCR_BF1    0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_M  ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
+#define SLC_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_S  0
 
-#define SLC_0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xA8)
+#define SLC_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xA8)
 /* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_M ((SLC_SLC0_RXLINK_DSCR_V) << (SLC_SLC0_RXLINK_DSCR_S))
-#define SLC_SLC0_RXLINK_DSCR_V 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_S 0
+/*description: .*/
+#define SLC_SLC0_RXLINK_DSCR    0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_M  ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
+#define SLC_SLC0_RXLINK_DSCR_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_S  0
 
-#define SLC_0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xAC)
+#define SLC_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xAC)
 /* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_M ((SLC_SLC0_RXLINK_DSCR_BF0_V) << (SLC_SLC0_RXLINK_DSCR_BF0_S))
-#define SLC_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_S 0
+/*description: .*/
+#define SLC_SLC0_RXLINK_DSCR_BF0    0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_M  ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
+#define SLC_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_S  0
 
-#define SLC_0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xB0)
+#define SLC_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xB0)
 /* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_M ((SLC_SLC0_RXLINK_DSCR_BF1_V) << (SLC_SLC0_RXLINK_DSCR_BF1_S))
-#define SLC_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_S 0
+/*description: .*/
+#define SLC_SLC0_RXLINK_DSCR_BF1    0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_M  ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
+#define SLC_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_S  0
 
-#define SLC_0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xCC)
+#define SLC_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xCC)
 /* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V) << (SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S  0
 
-#define SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xD4)
+#define SLC_TOKEN_LAT_REG          (DR_REG_SLC_BASE + 0xD4)
 /* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN 0x00000FFF
-#define SLC_SLC0_TOKEN_M ((SLC_SLC0_TOKEN_V) << (SLC_SLC0_TOKEN_S))
-#define SLC_SLC0_TOKEN_V 0xFFF
-#define SLC_SLC0_TOKEN_S 0
+/*description: .*/
+#define SLC_SLC0_TOKEN    0x00000FFF
+#define SLC_SLC0_TOKEN_M  ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
+#define SLC_SLC0_TOKEN_V  0xFFF
+#define SLC_SLC0_TOKEN_S  0
 
-#define SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xD8)
+#define SLC_TX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0xD8)
 /* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
-/*description: */
-#define SLC_WR_RETRY_THRESHOLD 0x000007FF
-#define SLC_WR_RETRY_THRESHOLD_M ((SLC_WR_RETRY_THRESHOLD_V) << (SLC_WR_RETRY_THRESHOLD_S))
-#define SLC_WR_RETRY_THRESHOLD_V 0x7FF
-#define SLC_WR_RETRY_THRESHOLD_S 0
+/*description: .*/
+#define SLC_WR_RETRY_THRESHOLD    0x000007FF
+#define SLC_WR_RETRY_THRESHOLD_M  ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
+#define SLC_WR_RETRY_THRESHOLD_V  0x7FF
+#define SLC_WR_RETRY_THRESHOLD_S  0
 
-#define SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xDC)
+#define SLC_CMD_INFOR0_REG          (DR_REG_SLC_BASE + 0xDC)
 /* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_CMD_CONTENT0 0xFFFFFFFF
-#define SLC_CMD_CONTENT0_M ((SLC_CMD_CONTENT0_V) << (SLC_CMD_CONTENT0_S))
-#define SLC_CMD_CONTENT0_V 0xFFFFFFFF
-#define SLC_CMD_CONTENT0_S 0
+/*description: .*/
+#define SLC_CMD_CONTENT0    0xFFFFFFFF
+#define SLC_CMD_CONTENT0_M  ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
+#define SLC_CMD_CONTENT0_V  0xFFFFFFFF
+#define SLC_CMD_CONTENT0_S  0
 
-#define SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xE0)
+#define SLC_CMD_INFOR1_REG          (DR_REG_SLC_BASE + 0xE0)
 /* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_CMD_CONTENT1 0xFFFFFFFF
-#define SLC_CMD_CONTENT1_M ((SLC_CMD_CONTENT1_V) << (SLC_CMD_CONTENT1_S))
-#define SLC_CMD_CONTENT1_V 0xFFFFFFFF
-#define SLC_CMD_CONTENT1_S 0
+/*description: .*/
+#define SLC_CMD_CONTENT1    0xFFFFFFFF
+#define SLC_CMD_CONTENT1_M  ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
+#define SLC_CMD_CONTENT1_V  0xFFFFFFFF
+#define SLC_CMD_CONTENT1_S  0
 
-#define SLC_0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xE4)
+#define SLC_LEN_CONF_REG          (DR_REG_SLC_BASE + 0xE4)
 /* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_NEW_PKT_IND (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_M (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_V 0x1
-#define SLC_SLC0_TX_NEW_PKT_IND_S 28
+/*description: .*/
+#define SLC_SLC0_TX_NEW_PKT_IND    (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_M  (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_V  0x1
+#define SLC_SLC0_TX_NEW_PKT_IND_S  28
 /* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_NEW_PKT_IND (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_M (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_V 0x1
-#define SLC_SLC0_RX_NEW_PKT_IND_S 27
+/*description: .*/
+#define SLC_SLC0_RX_NEW_PKT_IND    (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_M  (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_V  0x1
+#define SLC_SLC0_RX_NEW_PKT_IND_S  27
 /* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_GET_USED_DSCR (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_M (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_V 0x1
-#define SLC_SLC0_TX_GET_USED_DSCR_S 26
+/*description: .*/
+#define SLC_SLC0_TX_GET_USED_DSCR    (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_M  (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_V  0x1
+#define SLC_SLC0_TX_GET_USED_DSCR_S  26
 /* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_GET_USED_DSCR (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_M (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_V 0x1
-#define SLC_SLC0_RX_GET_USED_DSCR_S 25
+/*description: .*/
+#define SLC_SLC0_RX_GET_USED_DSCR    (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_M  (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_V  0x1
+#define SLC_SLC0_RX_GET_USED_DSCR_S  25
 /* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_PACKET_LOAD_EN (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_M (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_V 0x1
-#define SLC_SLC0_TX_PACKET_LOAD_EN_S 24
+/*description: .*/
+#define SLC_SLC0_TX_PACKET_LOAD_EN    (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_M  (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_V  0x1
+#define SLC_SLC0_TX_PACKET_LOAD_EN_S  24
 /* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_PACKET_LOAD_EN (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_M (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_V 0x1
-#define SLC_SLC0_RX_PACKET_LOAD_EN_S 23
+/*description: .*/
+#define SLC_SLC0_RX_PACKET_LOAD_EN    (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_M  (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_V  0x1
+#define SLC_SLC0_RX_PACKET_LOAD_EN_S  23
 /* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_INC_MORE (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_M (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_V 0x1
-#define SLC_SLC0_LEN_INC_MORE_S 22
+/*description: .*/
+#define SLC_SLC0_LEN_INC_MORE    (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_M  (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_V  0x1
+#define SLC_SLC0_LEN_INC_MORE_S  22
 /* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_INC (BIT(21))
-#define SLC_SLC0_LEN_INC_M (BIT(21))
-#define SLC_SLC0_LEN_INC_V 0x1
-#define SLC_SLC0_LEN_INC_S 21
+/*description: .*/
+#define SLC_SLC0_LEN_INC    (BIT(21))
+#define SLC_SLC0_LEN_INC_M  (BIT(21))
+#define SLC_SLC0_LEN_INC_V  0x1
+#define SLC_SLC0_LEN_INC_S  21
 /* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_WR (BIT(20))
-#define SLC_SLC0_LEN_WR_M (BIT(20))
-#define SLC_SLC0_LEN_WR_V 0x1
-#define SLC_SLC0_LEN_WR_S 20
+/*description: .*/
+#define SLC_SLC0_LEN_WR    (BIT(20))
+#define SLC_SLC0_LEN_WR_M  (BIT(20))
+#define SLC_SLC0_LEN_WR_V  0x1
+#define SLC_SLC0_LEN_WR_S  20
 /* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_LEN_WDATA 0x000FFFFF
-#define SLC_SLC0_LEN_WDATA_M ((SLC_SLC0_LEN_WDATA_V) << (SLC_SLC0_LEN_WDATA_S))
-#define SLC_SLC0_LEN_WDATA_V 0xFFFFF
-#define SLC_SLC0_LEN_WDATA_S 0
+/*description: .*/
+#define SLC_SLC0_LEN_WDATA    0x000FFFFF
+#define SLC_SLC0_LEN_WDATA_M  ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
+#define SLC_SLC0_LEN_WDATA_V  0xFFFFF
+#define SLC_SLC0_LEN_WDATA_S  0
 
-#define SLC_0_LENGTH_REG (DR_REG_SLC_BASE + 0xE8)
+#define SLC_LENGTH_REG          (DR_REG_SLC_BASE + 0xE8)
 /* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_LEN 0x000FFFFF
-#define SLC_SLC0_LEN_M ((SLC_SLC0_LEN_V) << (SLC_SLC0_LEN_S))
-#define SLC_SLC0_LEN_V 0xFFFFF
-#define SLC_SLC0_LEN_S 0
+/*description: .*/
+#define SLC_SLC0_LEN    0x000FFFFF
+#define SLC_SLC0_LEN_M  ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
+#define SLC_SLC0_LEN_V  0xFFFFF
+#define SLC_SLC0_LEN_S  0
 
-#define SLC_0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xEC)
+#define SLC_TXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xEC)
 /* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S  0
 
-#define SLC_0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF0)
+#define SLC_TXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF0)
 /* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S  0
 
-#define SLC_0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xF4)
+#define SLC_RXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xF4)
 /* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S  0
 
-#define SLC_0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF8)
+#define SLC_RXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF8)
 /* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S  0
 
-#define SLC_0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0xFC)
+#define SLC_TXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0xFC)
 /* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S  0
 
-#define SLC_0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x100)
+#define SLC_TXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x100)
 /* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S  0
 
-#define SLC_0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x104)
+#define SLC_RXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0x104)
 /* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S  0
 
-#define SLC_0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x108)
+#define SLC_RXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x108)
 /* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S  0
 
-#define SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x114)
+#define SLC_SEQ_POSITION_REG          (DR_REG_SLC_BASE + 0x114)
 /* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
-/*description: */
-#define SLC_SLC0_SEQ_POSITION 0x000000FF
-#define SLC_SLC0_SEQ_POSITION_M ((SLC_SLC0_SEQ_POSITION_V) << (SLC_SLC0_SEQ_POSITION_S))
-#define SLC_SLC0_SEQ_POSITION_V 0xFF
-#define SLC_SLC0_SEQ_POSITION_S 0
+/*description: .*/
+#define SLC_SLC0_SEQ_POSITION    0x000000FF
+#define SLC_SLC0_SEQ_POSITION_M  ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
+#define SLC_SLC0_SEQ_POSITION_V  0xFF
+#define SLC_SLC0_SEQ_POSITION_S  0
 
-#define SLC_0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x118)
+#define SLC_DSCR_REC_CONF_REG          (DR_REG_SLC_BASE + 0x118)
 /* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_REC_LIM 0x000003FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_M ((SLC_SLC0_RX_DSCR_REC_LIM_V) << (SLC_SLC0_RX_DSCR_REC_LIM_S))
-#define SLC_SLC0_RX_DSCR_REC_LIM_V 0x3FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_S 0
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_REC_LIM    0x000003FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_M  ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
+#define SLC_SLC0_RX_DSCR_REC_LIM_V  0x3FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_S  0
 
-#define SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x11C)
+#define SLC_SDIO_CRC_ST0_REG          (DR_REG_SLC_BASE + 0x11C)
 /* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT3_CRC_ERR_CNT 0x000000FF
-#define SLC_DAT3_CRC_ERR_CNT_M ((SLC_DAT3_CRC_ERR_CNT_V) << (SLC_DAT3_CRC_ERR_CNT_S))
-#define SLC_DAT3_CRC_ERR_CNT_V 0xFF
-#define SLC_DAT3_CRC_ERR_CNT_S 24
+/*description: .*/
+#define SLC_DAT3_CRC_ERR_CNT    0x000000FF
+#define SLC_DAT3_CRC_ERR_CNT_M  ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
+#define SLC_DAT3_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT3_CRC_ERR_CNT_S  24
 /* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT2_CRC_ERR_CNT 0x000000FF
-#define SLC_DAT2_CRC_ERR_CNT_M ((SLC_DAT2_CRC_ERR_CNT_V) << (SLC_DAT2_CRC_ERR_CNT_S))
-#define SLC_DAT2_CRC_ERR_CNT_V 0xFF
-#define SLC_DAT2_CRC_ERR_CNT_S 16
+/*description: .*/
+#define SLC_DAT2_CRC_ERR_CNT    0x000000FF
+#define SLC_DAT2_CRC_ERR_CNT_M  ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
+#define SLC_DAT2_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT2_CRC_ERR_CNT_S  16
 /* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT1_CRC_ERR_CNT 0x000000FF
-#define SLC_DAT1_CRC_ERR_CNT_M ((SLC_DAT1_CRC_ERR_CNT_V) << (SLC_DAT1_CRC_ERR_CNT_S))
-#define SLC_DAT1_CRC_ERR_CNT_V 0xFF
-#define SLC_DAT1_CRC_ERR_CNT_S 8
+/*description: .*/
+#define SLC_DAT1_CRC_ERR_CNT    0x000000FF
+#define SLC_DAT1_CRC_ERR_CNT_M  ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
+#define SLC_DAT1_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT1_CRC_ERR_CNT_S  8
 /* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT0_CRC_ERR_CNT 0x000000FF
-#define SLC_DAT0_CRC_ERR_CNT_M ((SLC_DAT0_CRC_ERR_CNT_V) << (SLC_DAT0_CRC_ERR_CNT_S))
-#define SLC_DAT0_CRC_ERR_CNT_V 0xFF
-#define SLC_DAT0_CRC_ERR_CNT_S 0
+/*description: .*/
+#define SLC_DAT0_CRC_ERR_CNT    0x000000FF
+#define SLC_DAT0_CRC_ERR_CNT_M  ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
+#define SLC_DAT0_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT0_CRC_ERR_CNT_S  0
 
-#define SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x120)
+#define SLC_SDIO_CRC_ST1_REG          (DR_REG_SLC_BASE + 0x120)
 /* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define SLC_ERR_CNT_CLR (BIT(31))
-#define SLC_ERR_CNT_CLR_M (BIT(31))
-#define SLC_ERR_CNT_CLR_V 0x1
-#define SLC_ERR_CNT_CLR_S 31
+/*description: .*/
+#define SLC_ERR_CNT_CLR    (BIT(31))
+#define SLC_ERR_CNT_CLR_M  (BIT(31))
+#define SLC_ERR_CNT_CLR_V  0x1
+#define SLC_ERR_CNT_CLR_S  31
 /* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_CMD_CRC_ERR_CNT 0x000000FF
-#define SLC_CMD_CRC_ERR_CNT_M ((SLC_CMD_CRC_ERR_CNT_V) << (SLC_CMD_CRC_ERR_CNT_S))
-#define SLC_CMD_CRC_ERR_CNT_V 0xFF
-#define SLC_CMD_CRC_ERR_CNT_S 0
+/*description: .*/
+#define SLC_CMD_CRC_ERR_CNT    0x000000FF
+#define SLC_CMD_CRC_ERR_CNT_M  ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
+#define SLC_CMD_CRC_ERR_CNT_V  0xFF
+#define SLC_CMD_CRC_ERR_CNT_S  0
 
-#define SLC_0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x124)
+#define SLC_EOF_START_DES_REG          (DR_REG_SLC_BASE + 0x124)
 /* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_EOF_START_DES_ADDR 0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_M ((SLC_SLC0_EOF_START_DES_ADDR_V) << (SLC_SLC0_EOF_START_DES_ADDR_S))
-#define SLC_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_EOF_START_DES_ADDR    0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_M  ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
+#define SLC_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_S  0
 
-#define SLC_0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x128)
+#define SLC_PUSH_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x128)
 /* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V) << (SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M  ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S  0
 
-#define SLC_0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x12C)
+#define SLC_DONE_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x12C)
 /* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_M ((SLC_SLC0_RX_DONE_DSCR_ADDR_V) << (SLC_SLC0_RX_DONE_DSCR_ADDR_S))
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_RX_DONE_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_M  ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_S  0
 
-#define SLC_0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x130)
+#define SLC_SUB_START_DES_REG          (DR_REG_SLC_BASE + 0x130)
 /* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V) << (SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S 0
+/*description: .*/
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR    0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M  ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
 
-#define SLC_0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x134)
+#define SLC_DSCR_CNT_REG          (DR_REG_SLC_BASE + 0x134)
 /* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_GET_EOF_OCC (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_M (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_V 0x1
-#define SLC_SLC0_RX_GET_EOF_OCC_S 16
+/*description: .*/
+#define SLC_SLC0_RX_GET_EOF_OCC    (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_M  (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_V  0x1
+#define SLC_SLC0_RX_GET_EOF_OCC_S  16
 /* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_CNT_LAT 0x000003FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_M ((SLC_SLC0_RX_DSCR_CNT_LAT_V) << (SLC_SLC0_RX_DSCR_CNT_LAT_S))
-#define SLC_SLC0_RX_DSCR_CNT_LAT_V 0x3FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_S 0
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_CNT_LAT    0x000003FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_M  ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
+#define SLC_SLC0_RX_DSCR_CNT_LAT_V  0x3FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_S  0
 
-#define SLC_0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x138)
+#define SLC_LEN_LIM_CONF_REG          (DR_REG_SLC_BASE + 0x138)
 /* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
-/*description: */
-#define SLC_SLC0_LEN_LIM 0x000FFFFF
-#define SLC_SLC0_LEN_LIM_M ((SLC_SLC0_LEN_LIM_V) << (SLC_SLC0_LEN_LIM_S))
-#define SLC_SLC0_LEN_LIM_V 0xFFFFF
-#define SLC_SLC0_LEN_LIM_S 0
+/*description: .*/
+#define SLC_SLC0_LEN_LIM    0x000FFFFF
+#define SLC_SLC0_LEN_LIM_M  ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
+#define SLC_SLC0_LEN_LIM_V  0xFFFFF
+#define SLC_SLC0_LEN_LIM_S  0
 
-#define SLC_0INT_ST1_REG (DR_REG_SLC_BASE + 0x13C)
+#define SLC_INT_ST1_REG          (DR_REG_SLC_BASE + 0x13C)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S  26
 /* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ST1 (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_M (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_V 0x1
-#define SLC_CMD_DTC_INT_ST1_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_ST1    (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_V  0x1
+#define SLC_CMD_DTC_INT_ST1_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S  19
 /* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ST1 (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_V 0x1
-#define SLC_SLC0_TOHOST_INT_ST1_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_ST1    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_V  0x1
+#define SLC_SLC0_TOHOST_INT_ST1_S  18
 /* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ST1 (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_V 0x1
-#define SLC_SLC0_RX_EOF_INT_ST1_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_ST1    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ST1_S  17
 /* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ST1 (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_V 0x1
-#define SLC_SLC0_RX_DONE_INT_ST1_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_ST1    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ST1_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S  15
 /* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ST1 (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_V 0x1
-#define SLC_SLC0_TX_DONE_INT_ST1_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_ST1    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ST1_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S  12
 /* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ST1 (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_V 0x1
-#define SLC_SLC0_TX_OVF_INT_ST1_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_ST1    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ST1_S  11
 /* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ST1 (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_V 0x1
-#define SLC_SLC0_RX_UDF_INT_ST1_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_ST1    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ST1_S  10
 /* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ST1 (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_V 0x1
-#define SLC_SLC0_TX_START_INT_ST1_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_ST1    (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_V  0x1
+#define SLC_SLC0_TX_START_INT_ST1_S  9
 /* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ST1 (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_V 0x1
-#define SLC_SLC0_RX_START_INT_ST1_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_ST1    (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_V  0x1
+#define SLC_SLC0_RX_START_INT_ST1_S  8
 /* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ST1 (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT7_INT_ST1_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_ST1    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT7_INT_ST1_S  7
 /* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ST1 (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT6_INT_ST1_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_ST1    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT6_INT_ST1_S  6
 /* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ST1 (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT5_INT_ST1_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_ST1    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT5_INT_ST1_S  5
 /* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ST1 (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT4_INT_ST1_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_ST1    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT4_INT_ST1_S  4
 /* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ST1 (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT3_INT_ST1_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_ST1    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT3_INT_ST1_S  3
 /* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ST1 (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT2_INT_ST1_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_ST1    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT2_INT_ST1_S  2
 /* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ST1 (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT1_INT_ST1_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_ST1    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT1_INT_ST1_S  1
 /* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ST1 (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_V 0x1
-#define SLC_FRHOST_BIT0_INT_ST1_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_ST1    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT0_INT_ST1_S  0
 
-#define SLC_0INT_ENA1_REG (DR_REG_SLC_BASE + 0x140)
+#define SLC_INT_ENA1_REG          (DR_REG_SLC_BASE + 0x140)
 /* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (BIT(27))
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x1
-#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27
+/*description: .*/
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1    (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
 /* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S 26
+/*description: .*/
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1    (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
 /* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ENA1 (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_M (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_V 0x1
-#define SLC_CMD_DTC_INT_ENA1_S 25
+/*description: .*/
+#define SLC_CMD_DTC_INT_ENA1    (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_V  0x1
+#define SLC_CMD_DTC_INT_ENA1_S  25
 /* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S 24
+/*description: .*/
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1    (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S  24
 /* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S 23
+/*description: .*/
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1    (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
 /* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V 0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S 22
+/*description: .*/
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1    (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S  22
 /* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
 /* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S 20
+/*description: .*/
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1    (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
 /* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S 19
+/*description: .*/
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1    (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
 /* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ENA1 (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_M (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_V 0x1
-#define SLC_SLC0_TOHOST_INT_ENA1_S 18
+/*description: .*/
+#define SLC_SLC0_TOHOST_INT_ENA1    (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_V  0x1
+#define SLC_SLC0_TOHOST_INT_ENA1_S  18
 /* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ENA1 (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_M (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_EOF_INT_ENA1_S 17
+/*description: .*/
+#define SLC_SLC0_RX_EOF_INT_ENA1    (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ENA1_S  17
 /* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ENA1 (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_M (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_DONE_INT_ENA1_S 16
+/*description: .*/
+#define SLC_SLC0_RX_DONE_INT_ENA1    (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ENA1_S  16
 /* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S 15
+/*description: .*/
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1    (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S  15
 /* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ENA1 (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_M (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_DONE_INT_ENA1_S 14
+/*description: .*/
+#define SLC_SLC0_TX_DONE_INT_ENA1    (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ENA1_S  14
 /* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S 13
+/*description: .*/
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
 /* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S 12
+/*description: .*/
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
 /* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ENA1 (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_M (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_OVF_INT_ENA1_S 11
+/*description: .*/
+#define SLC_SLC0_TX_OVF_INT_ENA1    (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ENA1_S  11
 /* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ENA1 (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_M (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_UDF_INT_ENA1_S 10
+/*description: .*/
+#define SLC_SLC0_RX_UDF_INT_ENA1    (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ENA1_S  10
 /* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ENA1 (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_M (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_V 0x1
-#define SLC_SLC0_TX_START_INT_ENA1_S 9
+/*description: .*/
+#define SLC_SLC0_TX_START_INT_ENA1    (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_START_INT_ENA1_S  9
 /* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ENA1 (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_M (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_V 0x1
-#define SLC_SLC0_RX_START_INT_ENA1_S 8
+/*description: .*/
+#define SLC_SLC0_RX_START_INT_ENA1    (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_START_INT_ENA1_S  8
 /* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ENA1 (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_M (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT7_INT_ENA1_S 7
+/*description: .*/
+#define SLC_FRHOST_BIT7_INT_ENA1    (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT7_INT_ENA1_S  7
 /* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ENA1 (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_M (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT6_INT_ENA1_S 6
+/*description: .*/
+#define SLC_FRHOST_BIT6_INT_ENA1    (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT6_INT_ENA1_S  6
 /* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ENA1 (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_M (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT5_INT_ENA1_S 5
+/*description: .*/
+#define SLC_FRHOST_BIT5_INT_ENA1    (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT5_INT_ENA1_S  5
 /* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ENA1 (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_M (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT4_INT_ENA1_S 4
+/*description: .*/
+#define SLC_FRHOST_BIT4_INT_ENA1    (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT4_INT_ENA1_S  4
 /* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ENA1 (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_M (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT3_INT_ENA1_S 3
+/*description: .*/
+#define SLC_FRHOST_BIT3_INT_ENA1    (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT3_INT_ENA1_S  3
 /* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ENA1 (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_M (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT2_INT_ENA1_S 2
+/*description: .*/
+#define SLC_FRHOST_BIT2_INT_ENA1    (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT2_INT_ENA1_S  2
 /* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ENA1 (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_M (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT1_INT_ENA1_S 1
+/*description: .*/
+#define SLC_FRHOST_BIT1_INT_ENA1    (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT1_INT_ENA1_S  1
 /* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ENA1 (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_M (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_V 0x1
-#define SLC_FRHOST_BIT0_INT_ENA1_S 0
+/*description: .*/
+#define SLC_FRHOST_BIT0_INT_ENA1    (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT0_INT_ENA1_S  0
 
-#define SLC_DATE_REG (DR_REG_SLC_BASE + 0x1F8)
+#define SLC_SLCDATE_REG          (DR_REG_SLC_BASE + 0x1F8)
 /* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */
-/*description: */
-#define SLC_DATE 0xFFFFFFFF
-#define SLC_DATE_M ((SLC_DATE_V) << (SLC_DATE_S))
-#define SLC_DATE_V 0xFFFFFFFF
-#define SLC_DATE_S 0
+/*description: .*/
+#define SLC_DATE    0xFFFFFFFF
+#define SLC_DATE_M  ((SLC_DATE_V)<<(SLC_DATE_S))
+#define SLC_DATE_V  0xFFFFFFFF
+#define SLC_DATE_S  0
 
-#define SLC_ID_REG (DR_REG_SLC_BASE + 0x1FC)
+#define SLC_SLCID_REG          (DR_REG_SLC_BASE + 0x1FC)
 /* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
-/*description: */
-#define SLC_ID 0xFFFFFFFF
-#define SLC_ID_M ((SLC_ID_V) << (SLC_ID_S))
-#define SLC_ID_V 0xFFFFFFFF
-#define SLC_ID_S 0
+/*description: .*/
+#define SLC_ID    0xFFFFFFFF
+#define SLC_ID_M  ((SLC_ID_V)<<(SLC_ID_S))
+#define SLC_ID_V  0xFFFFFFFF
+#define SLC_ID_S  0
+
 
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_SLC_REG_H_ */

components/soc/esp32s3/include/soc/slc_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,172 +11,172 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
+#ifndef _SOC_SLC_STRUCT_H_
+#define _SOC_SLC_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     union {
         struct {
-            uint32_t slc0_tx_rst:            1;
-            uint32_t slc0_rx_rst:            1;
-            uint32_t ahbm_fifo_rst:          1;
-            uint32_t ahbm_rst:               1;
-            uint32_t slc0_tx_loop_test:      1;
-            uint32_t slc0_rx_loop_test:      1;
-            uint32_t slc0_rx_auto_wrback:    1;
-            uint32_t slc0_rx_no_restart_clr: 1;
-            uint32_t slc0_rxdscr_burst_en:   1;
-            uint32_t slc0_rxdata_burst_en:   1;
-            uint32_t slc0_rxlink_auto_ret:   1;
-            uint32_t slc0_txlink_auto_ret:   1;
-            uint32_t slc0_txdscr_burst_en:   1;
-            uint32_t slc0_txdata_burst_en:   1;
-            uint32_t slc0_token_auto_clr:    1;
-            uint32_t slc0_token_sel:         1;
-            uint32_t reserved16:             2;
-            uint32_t slc0_wr_retry_mask_en:  1;
-            uint32_t reserved19:            13;
+            uint32_t tx_rst                        :    1;
+            uint32_t rx_rst                        :    1;
+            uint32_t ahbm_fifo_rst                 :    1;
+            uint32_t ahbm_rst                      :    1;
+            uint32_t tx_loop_test                  :    1;
+            uint32_t rx_loop_test                  :    1;
+            uint32_t rx_auto_wrback                :    1;
+            uint32_t rx_no_restart_clr             :    1;
+            uint32_t rxdscr_burst_en               :    1;
+            uint32_t rxdata_burst_en               :    1;
+            uint32_t auto_ret                      :    1;
+            uint32_t txdscr_burst_en               :    1;
+            uint32_t txdata_burst_en               :    1;
+            uint32_t token_auto_clr                :    1;
+            uint32_t token_sel                     :    1;
+            uint32_t reserved16                    :    2;
+            uint32_t wr_retry_mask_en              :    1;
+            uint32_t reserved19                    :    13;
         };
         uint32_t val;
-    } conf0;
+    } slcconf0;
     union {
         struct {
-            uint32_t frhost_bit0:                   1;
-            uint32_t frhost_bit1:                   1;
-            uint32_t frhost_bit2:                   1;
-            uint32_t frhost_bit3:                   1;
-            uint32_t frhost_bit4:                   1;
-            uint32_t frhost_bit5:                   1;
-            uint32_t frhost_bit6:                   1;
-            uint32_t frhost_bit7:                   1;
-            uint32_t rx_start:                      1;
-            uint32_t tx_start:                      1;
-            uint32_t rx_udf:                        1;
-            uint32_t tx_ovf:                        1;
-            uint32_t token0_1to0:                   1;
-            uint32_t token1_1to0:                   1;
-            uint32_t tx_done:                       1;
-            uint32_t tx_suc_eof:                    1;
-            uint32_t rx_done:                       1;
-            uint32_t rx_eof:                        1;
-            uint32_t tohost:                        1;
-            uint32_t tx_dscr_err:                   1;
-            uint32_t rx_dscr_err:                   1;
-            uint32_t tx_dscr_empty:                 1;
-            uint32_t host_rd_ack:                   1;
-            uint32_t wr_retry_done:                 1;
-            uint32_t tx_err_eof:                    1;
-            uint32_t cmd_dtc:                       1;
-            uint32_t rx_quick_eof:                  1;
-            uint32_t host_pop_eof_err:              1;
-            uint32_t reserved28:                    4;
+            uint32_t frhost_bit0                   :    1;
+            uint32_t frhost_bit1                   :    1;
+            uint32_t frhost_bit2                   :    1;
+            uint32_t frhost_bit3                   :    1;
+            uint32_t frhost_bit4                   :    1;
+            uint32_t frhost_bit5                   :    1;
+            uint32_t frhost_bit6                   :    1;
+            uint32_t frhost_bit7                   :    1;
+            uint32_t rx_start                      :    1;
+            uint32_t tx_start                      :    1;
+            uint32_t rx_udf                        :    1;
+            uint32_t tx_ovf                        :    1;
+            uint32_t token0_1to0                   :    1;
+            uint32_t token1_1to0                   :    1;
+            uint32_t tx_done                       :    1;
+            uint32_t tx_suc_eof                    :    1;
+            uint32_t rx_done                       :    1;
+            uint32_t rx_eof                        :    1;
+            uint32_t tohost                        :    1;
+            uint32_t tx_dscr_err                   :    1;
+            uint32_t rx_dscr_err                   :    1;
+            uint32_t tx_dscr_empty                 :    1;
+            uint32_t host_rd_ack                   :    1;
+            uint32_t wr_retry_done                 :    1;
+            uint32_t tx_err_eof                    :    1;
+            uint32_t cmd_dtc                       :    1;
+            uint32_t rx_quick_eof                  :    1;
+            uint32_t host_pop_eof_err              :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_raw;
     union {
         struct {
-            uint32_t frhost_bit0:                  1;
-            uint32_t frhost_bit1:                  1;
-            uint32_t frhost_bit2:                  1;
-            uint32_t frhost_bit3:                  1;
-            uint32_t frhost_bit4:                  1;
-            uint32_t frhost_bit5:                  1;
-            uint32_t frhost_bit6:                  1;
-            uint32_t frhost_bit7:                  1;
-            uint32_t rx_start:                     1;
-            uint32_t tx_start:                     1;
-            uint32_t rx_udf:                       1;
-            uint32_t tx_ovf:                       1;
-            uint32_t token0_1to0:                  1;
-            uint32_t token1_1to0:                  1;
-            uint32_t tx_done:                      1;
-            uint32_t tx_suc_eof:                   1;
-            uint32_t rx_done:                      1;
-            uint32_t rx_eof:                       1;
-            uint32_t tohost:                       1;
-            uint32_t tx_dscr_err:                  1;
-            uint32_t rx_dscr_err:                  1;
-            uint32_t tx_dscr_empty:                1;
-            uint32_t host_rd_ack:                  1;
-            uint32_t wr_retry_done:                1;
-            uint32_t tx_err_eof:                   1;
-            uint32_t cmd_dtc:                      1;
-            uint32_t rx_quick_eof:                 1;
-            uint32_t host_pop_eof_err:             1;
-            uint32_t reserved28:                   4;
+            uint32_t frhost_bit0                   :    1;
+            uint32_t frhost_bit1                   :    1;
+            uint32_t frhost_bit2                   :    1;
+            uint32_t frhost_bit3                   :    1;
+            uint32_t frhost_bit4                   :    1;
+            uint32_t frhost_bit5                   :    1;
+            uint32_t frhost_bit6                   :    1;
+            uint32_t frhost_bit7                   :    1;
+            uint32_t rx_start                      :    1;
+            uint32_t tx_start                      :    1;
+            uint32_t rx_udf                        :    1;
+            uint32_t tx_ovf                        :    1;
+            uint32_t token0_1to0                   :    1;
+            uint32_t token1_1to0                   :    1;
+            uint32_t tx_done                       :    1;
+            uint32_t tx_suc_eof                    :    1;
+            uint32_t rx_done                       :    1;
+            uint32_t rx_eof                        :    1;
+            uint32_t tohost                        :    1;
+            uint32_t tx_dscr_err                   :    1;
+            uint32_t rx_dscr_err                   :    1;
+            uint32_t tx_dscr_empty                 :    1;
+            uint32_t host_rd_ack                   :    1;
+            uint32_t wr_retry_done                 :    1;
+            uint32_t tx_err_eof                    :    1;
+            uint32_t cmd_dtc                       :    1;
+            uint32_t rx_quick_eof                  :    1;
+            uint32_t host_pop_eof_err              :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_st;
     union {
         struct {
-            uint32_t frhost_bit0:                   1;
-            uint32_t frhost_bit1:                   1;
-            uint32_t frhost_bit2:                   1;
-            uint32_t frhost_bit3:                   1;
-            uint32_t frhost_bit4:                   1;
-            uint32_t frhost_bit5:                   1;
-            uint32_t frhost_bit6:                   1;
-            uint32_t frhost_bit7:                   1;
-            uint32_t rx_start:                      1;
-            uint32_t tx_start:                      1;
-            uint32_t rx_udf:                        1;
-            uint32_t tx_ovf:                        1;
-            uint32_t token0_1to0:                   1;
-            uint32_t token1_1to0:                   1;
-            uint32_t tx_done:                       1;
-            uint32_t tx_suc_eof:                    1;
-            uint32_t rx_done:                       1;
-            uint32_t rx_eof:                        1;
-            uint32_t tohost:                        1;
-            uint32_t tx_dscr_err:                   1;
-            uint32_t rx_dscr_err:                   1;
-            uint32_t tx_dscr_empty:                 1;
-            uint32_t host_rd_ack:                   1;
-            uint32_t wr_retry_done:                 1;
-            uint32_t tx_err_eof:                    1;
-            uint32_t cmd_dtc:                       1;
-            uint32_t rx_quick_eof:                  1;
-            uint32_t host_pop_eof_err:              1;
-            uint32_t reserved28:                    4;
+            uint32_t frhost_bit0                   :    1;
+            uint32_t frhost_bit1                   :    1;
+            uint32_t frhost_bit2                   :    1;
+            uint32_t frhost_bit3                   :    1;
+            uint32_t frhost_bit4                   :    1;
+            uint32_t frhost_bit5                   :    1;
+            uint32_t frhost_bit6                   :    1;
+            uint32_t frhost_bit7                   :    1;
+            uint32_t rx_start                      :    1;
+            uint32_t tx_start                      :    1;
+            uint32_t rx_udf                        :    1;
+            uint32_t tx_ovf                        :    1;
+            uint32_t token0_1to0                   :    1;
+            uint32_t token1_1to0                   :    1;
+            uint32_t tx_done                       :    1;
+            uint32_t tx_suc_eof                    :    1;
+            uint32_t rx_done                       :    1;
+            uint32_t rx_eof                        :    1;
+            uint32_t tohost                        :    1;
+            uint32_t tx_dscr_err                   :    1;
+            uint32_t rx_dscr_err                   :    1;
+            uint32_t tx_dscr_empty                 :    1;
+            uint32_t host_rd_ack                   :    1;
+            uint32_t wr_retry_done                 :    1;
+            uint32_t tx_err_eof                    :    1;
+            uint32_t cmd_dtc                       :    1;
+            uint32_t rx_quick_eof                  :    1;
+            uint32_t host_pop_eof_err              :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_ena;
     union {
         struct {
-            uint32_t frhost_bit0:                   1;
-            uint32_t frhost_bit1:                   1;
-            uint32_t frhost_bit2:                   1;
-            uint32_t frhost_bit3:                   1;
-            uint32_t frhost_bit4:                   1;
-            uint32_t frhost_bit5:                   1;
-            uint32_t frhost_bit6:                   1;
-            uint32_t frhost_bit7:                   1;
-            uint32_t rx_start:                      1;
-            uint32_t tx_start:                      1;
-            uint32_t rx_udf:                        1;
-            uint32_t tx_ovf:                        1;
-            uint32_t token0_1to0:                   1;
-            uint32_t token1_1to0:                   1;
-            uint32_t tx_done:                       1;
-            uint32_t tx_suc_eof:                    1;
-            uint32_t rx_done:                       1;
-            uint32_t rx_eof:                        1;
-            uint32_t tohost:                        1;
-            uint32_t tx_dscr_err:                   1;
-            uint32_t rx_dscr_err:                   1;
-            uint32_t tx_dscr_empty:                 1;
-            uint32_t host_rd_ack:                   1;
-            uint32_t wr_retry_done:                 1;
-            uint32_t tx_err_eof:                    1;
-            uint32_t cmd_dtc:                       1;
-            uint32_t rx_quick_eof:                  1;
-            uint32_t host_pop_eof_err:              1;
-            uint32_t reserved28:                    4;
+            uint32_t frhost_bit0                   :    1;
+            uint32_t frhost_bit1                   :    1;
+            uint32_t frhost_bit2                   :    1;
+            uint32_t frhost_bit3                   :    1;
+            uint32_t frhost_bit4                   :    1;
+            uint32_t frhost_bit5                   :    1;
+            uint32_t frhost_bit6                   :    1;
+            uint32_t frhost_bit7                   :    1;
+            uint32_t rx_start                      :    1;
+            uint32_t tx_start                      :    1;
+            uint32_t rx_udf                        :    1;
+            uint32_t tx_ovf                        :    1;
+            uint32_t token0_1to0                   :    1;
+            uint32_t token1_1to0                   :    1;
+            uint32_t tx_done                       :    1;
+            uint32_t tx_suc_eof                    :    1;
+            uint32_t rx_done                       :    1;
+            uint32_t rx_eof                        :    1;
+            uint32_t tohost                        :    1;
+            uint32_t tx_dscr_err                   :    1;
+            uint32_t rx_dscr_err                   :    1;
+            uint32_t tx_dscr_empty                 :    1;
+            uint32_t host_rd_ack                   :    1;
+            uint32_t wr_retry_done                 :    1;
+            uint32_t tx_err_eof                    :    1;
+            uint32_t cmd_dtc                       :    1;
+            uint32_t rx_quick_eof                  :    1;
+            uint32_t host_pop_eof_err              :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_clr;
@@ -186,60 +186,60 @@ typedef volatile struct {
     uint32_t reserved_20;
     union {
         struct {
-            uint32_t slc0_rx_full:    1;
-            uint32_t slc0_rx_empty:   1;
-            uint32_t slc0_rx_buf_len: 12;
-            uint32_t reserved14:     18;
+            uint32_t rx_full                       :    1;
+            uint32_t rx_empty                      :    1;
+            uint32_t rx_buf_len                    :    12;
+            uint32_t reserved14                    :    18;
         };
         uint32_t val;
     } rx_status;
     union {
         struct {
-            uint32_t rxfifo_wdata:      9;
-            uint32_t reserved9:         7;
-            uint32_t rxfifo_push:       1;
-            uint32_t reserved17:       15;
+            uint32_t rxfifo_wdata                  :    9;
+            uint32_t reserved9                     :    7;
+            uint32_t rxfifo_push                   :    1;
+            uint32_t reserved17                    :    15;
         };
         uint32_t val;
     } slc0_rxfifo_push;
     uint32_t reserved_2c;
     union {
         struct {
-            uint32_t slc0_tx_full:  1;
-            uint32_t slc0_tx_empty: 1;
-            uint32_t reserved2:    30;
+            uint32_t tx_full                       :    1;
+            uint32_t tx_empty                      :    1;
+            uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } tx_status;
     union {
         struct {
-            uint32_t txfifo_rdata:     11;
-            uint32_t reserved11:        5;
-            uint32_t txfifo_pop:        1;
-            uint32_t reserved17:       15;
+            uint32_t txfifo_rdata                  :    11;
+            uint32_t reserved11                    :    5;
+            uint32_t txfifo_pop                    :    1;
+            uint32_t reserved17                    :    15;
         };
         uint32_t val;
     } slc0_txfifo_pop;
     uint32_t reserved_38;
     union {
         struct {
-            uint32_t addr:               20;
-            uint32_t reserved20:          8;
-            uint32_t stop:                1;
-            uint32_t start:               1;
-            uint32_t restart:             1;
-            uint32_t park:                1;
+            uint32_t addr                          :    20;
+            uint32_t reserved20                    :    8;
+            uint32_t stop                          :    1;
+            uint32_t start                         :    1;
+            uint32_t restart                       :    1;
+            uint32_t park                          :    1;
         };
         uint32_t val;
     } slc0_rx_link;
     union {
         struct {
-            uint32_t addr:               20;
-            uint32_t reserved20:          8;
-            uint32_t stop:                1;
-            uint32_t start:               1;
-            uint32_t restart:             1;
-            uint32_t park:                1;
+            uint32_t addr                          :    20;
+            uint32_t reserved20                    :    8;
+            uint32_t stop                          :    1;
+            uint32_t start                         :    1;
+            uint32_t restart                       :    1;
+            uint32_t park                          :    1;
         };
         uint32_t val;
     } slc0_tx_link;
@@ -247,32 +247,32 @@ typedef volatile struct {
     uint32_t reserved_48;
     union {
         struct {
-            uint32_t slc0_intvec:        8;
-            uint32_t reserved8:         24;
+            uint32_t tohost_intvec                 :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
-    } intvec_tohost;
+    } slcintvec_tohost;
     union {
         struct {
-            uint32_t wdata:               12;
-            uint32_t wr:                   1;
-            uint32_t inc:                  1;
-            uint32_t inc_more:             1;
-            uint32_t reserved15:           1;
-            uint32_t token0:              12;
-            uint32_t reserved28:           4;
+            uint32_t wdata                         :    12;
+            uint32_t wr                            :    1;
+            uint32_t inc                           :    1;
+            uint32_t inc_more                      :    1;
+            uint32_t reserved15                    :    1;
+            uint32_t token0                        :    12;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
-    } slc0_token0;
+    } slc0token0;
     union {
         struct {
-            uint32_t wdata:               12;
-            uint32_t wr:                   1;
-            uint32_t inc:                  1;
-            uint32_t inc_more:             1;
-            uint32_t reserved15:           1;
-            uint32_t token1:              12;
-            uint32_t reserved28:           4;
+            uint32_t wdata                         :    12;
+            uint32_t wr                            :    1;
+            uint32_t inc                           :    1;
+            uint32_t inc_more                      :    1;
+            uint32_t reserved15                    :    1;
+            uint32_t token1                        :    12;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_token1;
@@ -280,257 +280,257 @@ typedef volatile struct {
     uint32_t reserved_5c;
     union {
         struct {
-            uint32_t slc0_check_owner:     1;
-            uint32_t slc0_tx_check_sum_en: 1;
-            uint32_t slc0_rx_check_sum_en: 1;
-            uint32_t cmd_hold_en:          1;
-            uint32_t slc0_len_auto_clr:    1;
-            uint32_t slc0_tx_stitch_en:    1;
-            uint32_t slc0_rx_stitch_en:    1;
-            uint32_t reserved7:           12;
-            uint32_t host_int_level_sel:   1;
-            uint32_t reserved20:           2;
-            uint32_t clk_en:               1;
-            uint32_t reserved23:           9;
+            uint32_t check_owner                   :    1;
+            uint32_t tx_check_sum_en               :    1;
+            uint32_t rx_check_sum_en               :    1;
+            uint32_t reg_cmd_hold_en               :    1;
+            uint32_t len_auto_clr                  :    1;
+            uint32_t tx_stitch_en                  :    1;
+            uint32_t rx_stitch_en                  :    1;
+            uint32_t reserved7                     :    12;
+            uint32_t host_int_level_sel            :    1;
+            uint32_t reserved20                    :    2;
+            uint32_t reg_clk_en                    :    1;
+            uint32_t reserved23                    :    9;
         };
         uint32_t val;
-    } conf1;
-    uint32_t slc0_state0;                                 /**/
-    uint32_t slc0_state1;                                 /**/
+    } slcconf1;
+    uint32_t slc0_state0;
+    uint32_t slc0_state1;
     uint32_t reserved_6c;
     uint32_t reserved_70;
     union {
         struct {
-            uint32_t txeof_ena:          6;
-            uint32_t reserved6:          2;
-            uint32_t fifo_map_ena:       4;
-            uint32_t slc0_tx_dummy_mode: 1;
-            uint32_t hda_map_128k:       1;
-            uint32_t reserved14:         2;
-            uint32_t tx_push_idle_num:  16;
+            uint32_t txeof_ena                     :    6;
+            uint32_t reserved6                     :    2;
+            uint32_t fifo_map_ena                  :    4;
+            uint32_t tx_dummy_mode                 :    1;
+            uint32_t hda_map_128k                  :    1;
+            uint32_t reserved14                    :    2;
+            uint32_t tx_push_idle_num              :    16;
         };
         uint32_t val;
-    } bridge_conf;
-    uint32_t slc0_to_eof_des_addr;                        /**/
-    uint32_t slc0_tx_eof_des_addr;                        /**/
-    uint32_t slc0_to_eof_bfr_des_addr;                    /**/
+    } slcbridge_conf;
+    uint32_t slc0_to_eof_des_addr;
+    uint32_t slc0_tx_eof_des_addr;
+    uint32_t slc0_to_eof_bfr_des_addr;
     uint32_t reserved_84;
     uint32_t reserved_88;
     uint32_t reserved_8c;
     union {
         struct {
-            uint32_t mode:         3;
-            uint32_t reserved3:    1;
-            uint32_t addr:         2;
-            uint32_t reserved6:   26;
+            uint32_t mode                          :    3;
+            uint32_t reserved3                     :    1;
+            uint32_t addr                          :    2;
+            uint32_t reserved6                     :    26;
         };
         uint32_t val;
     } ahb_test;
     union {
         struct {
-            uint32_t cmd_st:          3;
-            uint32_t reserved3:       1;
-            uint32_t func_st:         4;
-            uint32_t sdio_wakeup:     1;
-            uint32_t reserved9:       3;
-            uint32_t bus_st:          3;
-            uint32_t reserved15:      1;
-            uint32_t func1_acc_state: 5;
-            uint32_t reserved21:     11;
+            uint32_t cmd_st                        :    3;
+            uint32_t reserved3                     :    1;
+            uint32_t func_st                       :    4;
+            uint32_t sdio_wakeup                   :    1;
+            uint32_t reserved9                     :    3;
+            uint32_t bus_st                        :    3;
+            uint32_t reserved15                    :    1;
+            uint32_t func1_acc_state               :    5;
+            uint32_t reserved21                    :    11;
         };
         uint32_t val;
     } sdio_st;
     union {
         struct {
-            uint32_t slc0_token_no_replace:   1;
-            uint32_t slc0_infor_no_replace:   1;
-            uint32_t slc0_rx_fill_mode:       1;
-            uint32_t slc0_rx_eof_mode:        1;
-            uint32_t slc0_rx_fill_en:         1;
-            uint32_t slc0_rd_retry_threshold: 11;
-            uint32_t reserved16:             16;
+            uint32_t token_no_replace              :    1;
+            uint32_t infor_no_replace              :    1;
+            uint32_t rx_fill_mode                  :    1;
+            uint32_t rx_eof_mode                   :    1;
+            uint32_t rx_fill_en                    :    1;
+            uint32_t rd_retry_threshold            :    11;
+            uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } rx_dscr_conf;
-    uint32_t slc0_txlink_dscr;                            /**/
-    uint32_t slc0_txlink_dscr_bf0;                        /**/
-    uint32_t slc0_txlink_dscr_bf1;                        /**/
-    uint32_t slc0_rxlink_dscr;                            /**/
-    uint32_t slc0_rxlink_dscr_bf0;                        /**/
-    uint32_t slc0_rxlink_dscr_bf1;                        /**/
+    uint32_t slc0_txlink_dscr;
+    uint32_t slc0_txlink_dscr_bf0;
+    uint32_t slc0_txlink_dscr_bf1;
+    uint32_t slc0_rxlink_dscr;
+    uint32_t slc0_rxlink_dscr_bf0;
+    uint32_t slc0_rxlink_dscr_bf1;
     uint32_t reserved_b4;
     uint32_t reserved_b8;
     uint32_t reserved_bc;
     uint32_t reserved_c0;
     uint32_t reserved_c4;
     uint32_t reserved_c8;
-    uint32_t slc0_tx_erreof_des_addr;                     /**/
+    uint32_t slc0_tx_erreof_des_addr;
     uint32_t reserved_d0;
     union {
         struct {
-            uint32_t slc0_token: 12;
-            uint32_t reserved12: 20;
+            uint32_t token                         :    12;
+            uint32_t reserved12                    :    20;
         };
         uint32_t val;
     } token_lat;
     union {
         struct {
-            uint32_t wr_retry_threshold: 11;
-            uint32_t reserved11:        21;
+            uint32_t wr_retry_threshold            :    11;
+            uint32_t reserved11                    :    21;
         };
         uint32_t val;
     } tx_dscr_conf;
-    uint32_t cmd_infor0;                                  /**/
-    uint32_t cmd_infor1;                                  /**/
+    uint32_t cmd_infor0;
+    uint32_t cmd_infor1;
     union {
         struct {
-            uint32_t len_wdata:             20;
-            uint32_t len_wr:                 1;
-            uint32_t len_inc:                1;
-            uint32_t len_inc_more:           1;
-            uint32_t rx_packet_load_en:      1;
-            uint32_t tx_packet_load_en:      1;
-            uint32_t rx_get_used_dscr:       1;
-            uint32_t tx_get_used_dscr:       1;
-            uint32_t rx_new_pkt_ind:         1;
-            uint32_t tx_new_pkt_ind:         1;
-            uint32_t reserved29:             3;
+            uint32_t len_wdata                     :    20;
+            uint32_t len_wr                        :    1;
+            uint32_t len_inc                       :    1;
+            uint32_t len_inc_more                  :    1;
+            uint32_t rx_packet_load_en             :    1;
+            uint32_t tx_packet_load_en             :    1;
+            uint32_t rx_get_used_dscr              :    1;
+            uint32_t tx_get_used_dscr              :    1;
+            uint32_t rx_new_pkt_ind                :    1;
+            uint32_t tx_new_pkt_ind                :    1;
+            uint32_t reserved29                    :    3;
         };
         uint32_t val;
     } slc0_len_conf;
     union {
         struct {
-            uint32_t len:       20;
-            uint32_t reserved20: 12;
+            uint32_t len                           :    20;
+            uint32_t reserved20                    :    12;
         };
         uint32_t val;
     } slc0_length;
-    uint32_t slc0_txpkt_h_dscr;                           /**/
-    uint32_t slc0_txpkt_e_dscr;                           /**/
-    uint32_t slc0_rxpkt_h_dscr;                           /**/
-    uint32_t slc0_rxpkt_e_dscr;                           /**/
-    uint32_t slc0_txpktu_h_dscr;                          /**/
-    uint32_t slc0_txpktu_e_dscr;                          /**/
-    uint32_t slc0_rxpktu_h_dscr;                          /**/
-    uint32_t slc0_rxpktu_e_dscr;                          /**/
+    uint32_t slc0_txpkt_h_dscr;
+    uint32_t slc0_txpkt_e_dscr;
+    uint32_t slc0_rxpkt_h_dscr;
+    uint32_t slc0_rxpkt_e_dscr;
+    uint32_t slc0_txpktu_h_dscr;
+    uint32_t slc0_txpktu_e_dscr;
+    uint32_t slc0_rxpktu_h_dscr;
+    uint32_t slc0_rxpktu_e_dscr;
     uint32_t reserved_10c;
     uint32_t reserved_110;
     union {
         struct {
-            uint32_t slc0_position:     8;
-            uint32_t reserved8:        24;
+            uint32_t seq_position                  :    8;
+            uint32_t reserved8                     :    24;
         };
         uint32_t val;
     } seq_position;
     union {
         struct {
-            uint32_t rx_dscr_rec_lim:     10;
-            uint32_t reserved10:          22;
+            uint32_t rx_dscr_rec_lim               :    10;
+            uint32_t reserved10                    :    22;
         };
         uint32_t val;
     } slc0_dscr_rec_conf;
     union {
         struct {
-            uint32_t dat0_crc_err_cnt: 8;
-            uint32_t dat1_crc_err_cnt: 8;
-            uint32_t dat2_crc_err_cnt: 8;
-            uint32_t dat3_crc_err_cnt: 8;
+            uint32_t dat0_crc_err_cnt              :    8;
+            uint32_t dat1_crc_err_cnt              :    8;
+            uint32_t dat2_crc_err_cnt              :    8;
+            uint32_t dat3_crc_err_cnt              :    8;
         };
         uint32_t val;
     } sdio_crc_st0;
     union {
         struct {
-            uint32_t cmd_crc_err_cnt: 8;
-            uint32_t reserved8:      23;
-            uint32_t err_cnt_clr:     1;
+            uint32_t cmd_crc_err_cnt               :    8;
+            uint32_t reserved8                     :    23;
+            uint32_t err_cnt_clr                   :    1;
         };
         uint32_t val;
     } sdio_crc_st1;
-    uint32_t slc0_eof_start_des;                          /**/
-    uint32_t slc0_push_dscr_addr;                         /**/
-    uint32_t slc0_done_dscr_addr;                         /**/
-    uint32_t slc0_sub_start_des;                          /**/
+    uint32_t slc0_eof_start_des;
+    uint32_t slc0_push_dscr_addr;
+    uint32_t slc0_done_dscr_addr;
+    uint32_t slc0_sub_start_des;
     union {
         struct {
-            uint32_t rx_dscr_cnt_lat:     10;
-            uint32_t reserved10:           6;
-            uint32_t rx_get_eof_occ:       1;
-            uint32_t reserved17:          15;
+            uint32_t rx_dscr_cnt_lat               :    10;
+            uint32_t reserved10                    :    6;
+            uint32_t rx_get_eof_occ                :    1;
+            uint32_t reserved17                    :    15;
         };
         uint32_t val;
     } slc0_dscr_cnt;
     union {
         struct {
-            uint32_t len_lim:     20;
-            uint32_t reserved20:  12;
+            uint32_t len_lim                       :    20;
+            uint32_t reserved20                    :    12;
         };
         uint32_t val;
     } slc0_len_lim_conf;
     union {
         struct {
-            uint32_t frhost_bit01:                  1;
-            uint32_t frhost_bit11:                  1;
-            uint32_t frhost_bit21:                  1;
-            uint32_t frhost_bit31:                  1;
-            uint32_t frhost_bit41:                  1;
-            uint32_t frhost_bit51:                  1;
-            uint32_t frhost_bit61:                  1;
-            uint32_t frhost_bit71:                  1;
-            uint32_t rx_start1:                     1;
-            uint32_t tx_start1:                     1;
-            uint32_t rx_udf1:                       1;
-            uint32_t tx_ovf1:                       1;
-            uint32_t token0_1to01:                  1;
-            uint32_t token1_1to01:                  1;
-            uint32_t tx_done1:                      1;
-            uint32_t tx_suc_eof1:                   1;
-            uint32_t rx_done1:                      1;
-            uint32_t rx_eof1:                       1;
-            uint32_t tohost1:                       1;
-            uint32_t tx_dscr_err1:                  1;
-            uint32_t rx_dscr_err1:                  1;
-            uint32_t tx_dscr_empty1:                1;
-            uint32_t host_rd_ack1:                  1;
-            uint32_t wr_retry_done1:                1;
-            uint32_t tx_err_eof1:                   1;
-            uint32_t cmd_dtc1:                      1;
-            uint32_t rx_quick_eof1:                 1;
-            uint32_t host_pop_eof_err1:             1;
-            uint32_t reserved28:                    4;
+            uint32_t frhost_bit01                  :    1;
+            uint32_t frhost_bit11                  :    1;
+            uint32_t frhost_bit21                  :    1;
+            uint32_t frhost_bit31                  :    1;
+            uint32_t frhost_bit41                  :    1;
+            uint32_t frhost_bit51                  :    1;
+            uint32_t frhost_bit61                  :    1;
+            uint32_t frhost_bit71                  :    1;
+            uint32_t rx_start1                     :    1;
+            uint32_t tx_start1                     :    1;
+            uint32_t rx_udf1                       :    1;
+            uint32_t tx_ovf1                       :    1;
+            uint32_t token0_1to01                  :    1;
+            uint32_t token1_1to01                  :    1;
+            uint32_t tx_done1                      :    1;
+            uint32_t tx_suc_eof1                   :    1;
+            uint32_t rx_done1                      :    1;
+            uint32_t rx_eof1                       :    1;
+            uint32_t tohost1                       :    1;
+            uint32_t tx_dscr_err1                  :    1;
+            uint32_t rx_dscr_err1                  :    1;
+            uint32_t tx_dscr_empty1                :    1;
+            uint32_t host_rd_ack1                  :    1;
+            uint32_t wr_retry_done1                :    1;
+            uint32_t tx_err_eof1                   :    1;
+            uint32_t cmd_dtc1                      :    1;
+            uint32_t rx_quick_eof1                 :    1;
+            uint32_t host_pop_eof_err1             :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_st1;
     union {
         struct {
-            uint32_t frhost_bit01:                   1;
-            uint32_t frhost_bit11:                   1;
-            uint32_t frhost_bit21:                   1;
-            uint32_t frhost_bit31:                   1;
-            uint32_t frhost_bit41:                   1;
-            uint32_t frhost_bit51:                   1;
-            uint32_t frhost_bit61:                   1;
-            uint32_t frhost_bit71:                   1;
-            uint32_t rx_start1:                      1;
-            uint32_t tx_start1:                      1;
-            uint32_t rx_udf1:                        1;
-            uint32_t tx_ovf1:                        1;
-            uint32_t token0_1to01:                   1;
-            uint32_t token1_1to01:                   1;
-            uint32_t tx_done1:                       1;
-            uint32_t tx_suc_eof1:                    1;
-            uint32_t rx_done1:                       1;
-            uint32_t rx_eof1:                        1;
-            uint32_t tohost1:                        1;
-            uint32_t tx_dscr_err1:                   1;
-            uint32_t rx_dscr_err1:                   1;
-            uint32_t tx_dscr_empty1:                 1;
-            uint32_t host_rd_ack1:                   1;
-            uint32_t wr_retry_done1:                 1;
-            uint32_t tx_err_eof1:                    1;
-            uint32_t cmd_dtc1:                       1;
-            uint32_t rx_quick_eof1:                  1;
-            uint32_t host_pop_eof_err1:              1;
-            uint32_t reserved28:                     4;
+            uint32_t frhost_bit01                  :    1;
+            uint32_t frhost_bit11                  :    1;
+            uint32_t frhost_bit21                  :    1;
+            uint32_t frhost_bit31                  :    1;
+            uint32_t frhost_bit41                  :    1;
+            uint32_t frhost_bit51                  :    1;
+            uint32_t frhost_bit61                  :    1;
+            uint32_t frhost_bit71                  :    1;
+            uint32_t rx_start1                     :    1;
+            uint32_t tx_start1                     :    1;
+            uint32_t rx_udf1                       :    1;
+            uint32_t tx_ovf1                       :    1;
+            uint32_t token0_1to01                  :    1;
+            uint32_t token1_1to01                  :    1;
+            uint32_t tx_done1                      :    1;
+            uint32_t tx_suc_eof1                   :    1;
+            uint32_t rx_done1                      :    1;
+            uint32_t rx_eof1                       :    1;
+            uint32_t tohost1                       :    1;
+            uint32_t tx_dscr_err1                  :    1;
+            uint32_t rx_dscr_err1                  :    1;
+            uint32_t tx_dscr_empty1                :    1;
+            uint32_t host_rd_ack1                  :    1;
+            uint32_t wr_retry_done1                :    1;
+            uint32_t tx_err_eof1                   :    1;
+            uint32_t cmd_dtc1                      :    1;
+            uint32_t rx_quick_eof1                 :    1;
+            uint32_t host_pop_eof_err1             :    1;
+            uint32_t reserved28                    :    4;
         };
         uint32_t val;
     } slc0_int_ena1;
@@ -579,12 +579,14 @@ typedef volatile struct {
     uint32_t reserved_1ec;
     uint32_t reserved_1f0;
     uint32_t reserved_1f4;
-    uint32_t date;                                     /**/
-    uint32_t id;                                       /**/
+    uint32_t date;
+    uint32_t id;
 } slc_dev_t;
-
 extern slc_dev_t SLC;
-
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_SLC_STRUCT_H_ */

components/soc/esp32s3/include/soc/soc.h

@@ -90,7 +90,7 @@
 #define DR_REG_I2S1_BASE                        0x6002D000
 #define DR_REG_UART2_BASE                       0x6002E000
 #define DR_REG_SPI4_BASE                        0x60037000
-#define DR_REG_USB_DEVICE_BASE                  0x60080000
+#define DR_REG_USB_DEVICE_BASE                  0x60038000
 #define DR_REG_USB_WRAP_BASE                    0x60039000
 #define DR_REG_APB_SARADC_BASE                  0x60040000
 #define DR_REG_LCD_CAM_BASE                     0x60041000
@@ -213,7 +213,7 @@
 
 //Periheral Clock {{
 #define  APB_CLK_FREQ_ROM                            (40*1000000)
-#define  CPU_CLK_FREQ_ROM                            (40*1000000)
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  UART_CLK_FREQ_ROM                           (40*1000000)
 #define  EFUSE_CLK_FREQ_ROM                          (20*1000000)
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
@@ -223,9 +223,9 @@
 #define  XTAL_CLK_FREQ                               (40*1000000)
 #define  UART_CLK_FREQ                               APB_CLK_FREQ
 #define  WDT_CLK_FREQ                                APB_CLK_FREQ
-#define  TIMER_CLK_FREQ                              (80000000>>4)
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
 #define  SPI_CLK_DIV                                 4
-#define  TICKS_PER_US_ROM                            40
+#define  TICKS_PER_US_ROM                            40              // CPU is 80MHz
 #define  GPIO_MATRIX_DELAY_NS                        0
 //}}
 

components/soc/esp32s3/include/soc/spi_mem_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SPI_MEM_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
 /* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
@@ -274,8 +274,8 @@ e low..*/
 #define SPI_MEM_RXFIFO_RST_V  0x1
 #define SPI_MEM_RXFIFO_RST_S  30
 /* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: Delay cycles of resume Flash when resume Flash from standby mode is enable by SP
-I_CLK..*/
+/*description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 4 or * 256) SPI_CLK cycles..*/
 #define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
 #define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
 #define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
@@ -371,31 +371,31 @@ CNT_N+1).*/
 
 #define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
 /* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the CMD phase of an operation..*/
+/*description: Set this bit to enable enable the CMD phase of an operation..*/
 #define SPI_MEM_USR_COMMAND    (BIT(31))
 #define SPI_MEM_USR_COMMAND_M  (BIT(31))
 #define SPI_MEM_USR_COMMAND_V  0x1
 #define SPI_MEM_USR_COMMAND_S  31
 /* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the ADDR phase of an operation..*/
+/*description: Set this bit to enable enable the ADDR phase of an operation..*/
 #define SPI_MEM_USR_ADDR    (BIT(30))
 #define SPI_MEM_USR_ADDR_M  (BIT(30))
 #define SPI_MEM_USR_ADDR_V  0x1
 #define SPI_MEM_USR_ADDR_S  30
 /* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the DUMMY phase of an operation..*/
+/*description: Set this bit to enable enable the DUMMY phase of an operation..*/
 #define SPI_MEM_USR_DUMMY    (BIT(29))
 #define SPI_MEM_USR_DUMMY_M  (BIT(29))
 #define SPI_MEM_USR_DUMMY_V  0x1
 #define SPI_MEM_USR_DUMMY_S  29
 /* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the DIN phase of a read-data operation..*/
+/*description: Set this bit to enable enable the DIN phase of a read-data operation..*/
 #define SPI_MEM_USR_MISO    (BIT(28))
 #define SPI_MEM_USR_MISO_M  (BIT(28))
 #define SPI_MEM_USR_MISO_V  0x1
 #define SPI_MEM_USR_MISO_S  28
 /* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the DOUT phase of an write-data operation..*/
+/*description: Set this bit to enable the DOUT phase of an write-data operation..*/
 #define SPI_MEM_USR_MOSI    (BIT(27))
 #define SPI_MEM_USR_MOSI_M  (BIT(27))
 #define SPI_MEM_USR_MOSI_V  0x1
@@ -565,28 +565,16 @@ dle..*/
 #define SPI_MEM_FSUB_PIN_M  (BIT(7))
 #define SPI_MEM_FSUB_PIN_V  0x1
 #define SPI_MEM_FSUB_PIN_S  7
-/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of SPI transmitting done..*/
-#define SPI_MEM_TRANS_END_INT_ENA    (BIT(4))
-#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_TRANS_END_INT_ENA_S  4
-/* SPI_MEM_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the transmitting is done..*/
-#define SPI_MEM_TRANS_END    (BIT(3))
-#define SPI_MEM_TRANS_END_M  (BIT(3))
-#define SPI_MEM_TRANS_END_V  0x1
-#define SPI_MEM_TRANS_END_S  3
 /* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
 /*description: Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM)
- connected to SPI_CS1 is inactive when SPI1 transfer starts..*/
+ connected to SPI_CS1 is in low level when SPI1 transfer starts..*/
 #define SPI_MEM_CS1_DIS    (BIT(1))
 #define SPI_MEM_CS1_DIS_M  (BIT(1))
 #define SPI_MEM_CS1_DIS_V  0x1
 #define SPI_MEM_CS1_DIS_S  1
 /* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co
-nnected to SPI_CS is inactive when SPI1 transfer starts..*/
+nnected to SPI_CS is in low level when SPI1 transfer starts..*/
 #define SPI_MEM_CS0_DIS    (BIT(0))
 #define SPI_MEM_CS0_DIS_M  (BIT(0))
 #define SPI_MEM_CS0_DIS_V  0x1
@@ -1033,19 +1021,19 @@ N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/
 
 #define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
 /* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when auto wait flash idle .*/
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
 #define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
 #define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
 /* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
-/*description: The command to auto wait idle.*/
+/*description: The command value of auto wait flash idle transfer(RDSR)..*/
 #define SPI_MEM_WAITI_CMD    0x000000FF
 #define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
 #define SPI_MEM_WAITI_CMD_V  0xFF
 #define SPI_MEM_WAITI_CMD_S  2
 /* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when auto wait flash idle.*/
+/*description: Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR)..*/
 #define SPI_MEM_WAITI_DUMMY    (BIT(1))
 #define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
 #define SPI_MEM_WAITI_DUMMY_V  0x1
@@ -1171,8 +1159,8 @@ ed when PER is sent. Only used in SPI1..*/
 
 #define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
 /* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc
-esses to flash. Active when SPI_MEM_TIMING_CALI bit is set..*/
+/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when S
+PI_MEM_TIMING_CALI bit is set..*/
 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
@@ -1184,7 +1172,7 @@ ns..*/
 #define SPI_MEM_TIMING_CALI_M  (BIT(1))
 #define SPI_MEM_TIMING_CALI_V  0x1
 #define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
 als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
 #define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
@@ -1438,7 +1426,7 @@ ns..*/
 #define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
 #define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
 #define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
-/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
 als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
 #define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
@@ -1737,7 +1725,7 @@ M_ECC_ERR_INT_CLR bit..*/
 #define SPI_MEM_ECC_DATA_ERR_BIT_S  6
 
 #define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
-/* SPI_MEM_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
 /*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
 sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
 SPI core clock cycles..*/
@@ -1825,7 +1813,7 @@ ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
 #define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
 /* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
 /*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses to flash or SPI1 accesses flash or sram..*/
+ccesses flash or SPI1 accesses flash or sram..*/
 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
 #define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
@@ -1892,13 +1880,13 @@ accesses to flash..*/
 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
 #define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
 /* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
 #define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
 /* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to swap TX data of a word in DDR mode..*/
+/*description: Set the bit to reorder TX data of the word in DDR mode..*/
 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
 #define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
@@ -1910,13 +1898,13 @@ accesses to flash..*/
 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
 #define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
 /* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in DDR mode..*/
+/*description: Set the bit to enable variable dummy cycle in DDRmode..*/
 #define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
 #define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
 /* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in ddr mode,  0 in sdr mode.*/
+/*description: 1: in DDR mode,  0: in SDR mode..*/
 #define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
 #define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
 #define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
@@ -2212,12 +2200,36 @@ mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
 #define SPI_MEM_PER_END_INT_ST_S  0
 
 #define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101040 ; */
+/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */
 /*description: SPI register version..*/
-#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE    0x007FFFFF
 #define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
+#define SPI_MEM_DATE_V  0x7FFFFF
+#define SPI_MEM_DATE_S  5
+/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled b
+y the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The
+ driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK
+ PAD..*/
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN    (BIT(4))
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M  (BIT(4))
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V  0x1
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S  4
+/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0
+] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV    0x00000003
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S))
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V  0x3
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S  2
+/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0
+] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RA
+M..*/
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV    0x00000003
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S))
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V  0x3
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S  0
 
 
 #ifdef __cplusplus

components/soc/esp32s3/include/soc/spi_mem_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,9 @@
 // limitations under the License.
 #ifndef _SOC_SPI_MEM_STRUCT_H_
 #define _SOC_SPI_MEM_STRUCT_H_
+
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -71,22 +74,22 @@ typedef volatile struct {
     union {
         struct {
             uint32_t clk_mode                      :    2;  /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*Delay cycles of resume Flash when resume Flash from standby mode is enable by SPI_CLK.*/
-            uint32_t reserved12                    :    18;  /*reserved*/
-			uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    18;  /*reserved*/
+            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
             uint32_t reserved31                    :    1;  /*reserved*/
         };
         uint32_t val;
     } ctrl1;
     union {
         struct {
-            uint32_t cs_setup_time:        5;                   /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t cs_hold_time:         5;                   /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t ecc_cs_hold_time:     3;                   /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner: 1;                   /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en:   1;                   /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15:          10;                   /*reserved*/
-            uint32_t cs_hold_delay:        6;                   /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t cs_hold_time                  :    5;  /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
+            uint32_t reserved15                    :    10;  /*reserved*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
             uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
         };
         uint32_t val;
@@ -95,18 +98,18 @@ typedef volatile struct {
         struct {
             uint32_t clkcnt_l                      :    8;  /*It must equal to the value of SPI_MEM_CLKCNT_N. */
             uint32_t clkcnt_h                      :    8;  /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
+            uint32_t clkcnt_n                      :    8;  /*When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
             uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t clk_equ_sysclk                :    1;  /*When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
+            uint32_t clk_equ_sysclk                :    1;  /*When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
         };
         uint32_t val;
     } clock;
     union {
         struct {
-            uint32_t reserved0:      6;                         /*reserved*/
-            uint32_t cs_hold:        1;                         /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
-            uint32_t cs_setup:       1;                         /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
-            uint32_t reserved8:      1;                         /*reserved*/
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
+            uint32_t cs_setup                      :    1;  /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
+            uint32_t reserved8                     :    1;  /*reserved*/
             uint32_t ck_out_edge                   :    1;  /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
             uint32_t reserved10                    :    2;  /*reserved*/
             uint32_t fwrite_dual                   :    1;  /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
@@ -117,11 +120,11 @@ typedef volatile struct {
             uint32_t usr_miso_highpart             :    1;  /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
             uint32_t usr_mosi_highpart             :    1;  /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
             uint32_t usr_dummy_idle                :    1;  /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the DOUT phase of an write-data operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the DIN phase of a read-data operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the DUMMY phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the ADDR phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the CMD phase of an operation.*/
+            uint32_t usr_mosi                      :    1;  /*Set this bit to enable the DOUT phase of an write-data operation.*/
+            uint32_t usr_miso                      :    1;  /*Set this bit to enable enable the DIN phase of a read-data operation.*/
+            uint32_t usr_dummy                     :    1;  /*Set this bit to enable enable the DUMMY phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*Set this bit to enable enable the ADDR phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*Set this bit to enable enable the CMD phase of an operation.*/
         };
         uint32_t val;
     } user;
@@ -143,45 +146,42 @@ typedef volatile struct {
     } user2;
     union {
         struct {
-            uint32_t usr_mosi_bit_len:10;                       /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10:      22;                       /*reserved*/
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of DOUT phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
         };
         uint32_t val;
     } mosi_dlen;
     union {
         struct {
-            uint32_t usr_miso_bit_len:10;                       /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10:      22;                       /*reserved*/
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of DIN phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
         };
         uint32_t val;
     } miso_dlen;
     union {
         struct {
-            uint32_t status:    16;                             /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode:    8;                             /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24: 8;                             /*reserved*/
+            uint32_t status                        :    16;  /*The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
         };
         uint32_t val;
     } rd_status;
-    uint32_t ext_addr;                                          /*The register are the higher 32bits in the 64 bits address mode.*/
+    uint32_t ext_addr;
     union {
         struct {
-            uint32_t cs0_dis:           1;                      /*SPI CS0 pin enable  1: disable CS0  0: spi_mem_cs0 signal is from/to CS0 pin*/
-            uint32_t cs1_dis:           1;                      /*SPI CS1 pin enable  1: disable CS1  0: spi_mem_cs1 signal is from/to CS1 pin*/
-            uint32_t reserved2:         1;                      /*reserved*/
-            uint32_t trans_end:         1;                      /*The bit is used to indicate the transimitting is done.*/
-            uint32_t trans_end_en:      1;                      /*The bit is used to enable the intterrupt of SPI transmitting done.*/
-            uint32_t reserved5:         2;                      /*reserved*/
-            uint32_t fsub_pin:          1;                      /*For SPI0   flash is connected to SUBPINs.*/
-            uint32_t ssub_pin:          1;                      /*For SPI0   sram is connected to SUBPINs.*/
-            uint32_t ck_idle_edge:      1;                      /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
-            uint32_t cs_keep_active:    1;                      /*spi cs line keep low when the bit is set.*/
-            uint32_t auto_per:          1;                      /*reserved*/
-            uint32_t reserved12:       20;                      /*reserved*/
+            uint32_t cs0_dis                       :    1;  /*Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.*/
+            uint32_t cs1_dis                       :    1;  /*Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.*/
+            uint32_t reserved0                     :    5;  /*reserved*/
+            uint32_t fsub_pin                      :    1;  /*Flash is connected to SPI SUBPIN bus.*/
+            uint32_t ssub_pin                      :    1;  /*Ext_RAM is connected to SPI SUBPIN bus.*/
+            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
+            uint32_t auto_per                      :    1;  /*Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
         };
         uint32_t val;
     } misc;
-    uint32_t tx_crc;                                            /*For SPI1  the value of crc32.*/
+    uint32_t tx_crc;
     union {
         struct {
             uint32_t req_en                        :    1;  /*Set this bit to enable Cache's access and SPI0's transfer.*/
@@ -264,7 +264,7 @@ typedef volatile struct {
     } sram_clk;
     union {
         struct {
-            uint32_t st                            :    3;  /*The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
+            uint32_t st                            :    3;  /*The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
             uint32_t reserved3                     :    29;  /*reserved*/
         };
         uint32_t val;
@@ -273,9 +273,9 @@ typedef volatile struct {
     union {
         struct {
             uint32_t waiti_en                      :    1;  /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when auto wait flash idle*/
-            uint32_t waiti_cmd                     :    8;  /*The command to auto wait idle*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when auto wait flash idle */
+            uint32_t waiti_dummy                   :    1;  /*Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).*/
+            uint32_t waiti_cmd                     :    8;  /*The command value of auto wait flash idle transfer(RDSR).*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
             uint32_t reserved16                    :    16;  /*reserved*/
         };
         uint32_t val;
@@ -316,10 +316,10 @@ typedef volatile struct {
     } sus_status;
     union {
         struct {
-            uint32_t timing_clk_ena:       1;                   /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali:          1;                   /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen: 3;                   /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reserved5:           27;
+            uint32_t timing_clk_ena                :    1;  /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
+            uint32_t timing_cali                   :    1;  /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
         };
         uint32_t val;
     } timing_cali;
@@ -512,15 +512,15 @@ typedef volatile struct {
     } spi_smem_ddr;
     union {
         struct {
-            uint32_t clk_en:     1;                             /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1: 31;                             /*reserved*/
+            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
         };
         uint32_t val;
     } clock_gate;
     union {
         struct {
-            uint32_t spi01_clk_sel: 2;                          /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
-            uint32_t reserved2:    30;                          /*reserved*/
+            uint32_t core_clk_sel                  :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. */
+            uint32_t reserved2                     :    30;  /*reserved*/
         };
         uint32_t val;
     } core_clk_sel;
@@ -761,7 +761,10 @@ typedef volatile struct {
     uint32_t reserved_3f8;
     union {
         struct {
-            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reg_smem_spiclk_fun_drv       :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM.*/
+            uint32_t fmem_spiclk_fun_drv           :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.*/
+            uint32_t reg_spiclk_pad_drv_ctl_en     :    1;  /*SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD.*/
+            uint32_t date                          :    23;  /*SPI register version.*/
             uint32_t reserved28                    :    4;  /*reserved*/
         };
         uint32_t val;
@@ -769,11 +772,10 @@ typedef volatile struct {
 } spi_mem_dev_t;
 extern spi_mem_dev_t SPIMEM0;
 extern spi_mem_dev_t SPIMEM1;
-
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* _SOC_SPI_MEM_STRUCT_H_ */
+
+
+#endif /*_SOC_SPI_MEM_STRUCT_H_ */

components/soc/esp32s3/include/soc/spi_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SPI_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
 /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
@@ -52,20 +52,20 @@ clock domain, which is only used in SPI master mode..*/
 #define SPI_USR_ADDR_VALUE_S  0
 
 #define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
 /*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
 figured in CONF state..*/
-#define SPI_WR_BIT_ORDER    (BIT(26))
-#define SPI_WR_BIT_ORDER_M  (BIT(26))
-#define SPI_WR_BIT_ORDER_V  0x1
-#define SPI_WR_BIT_ORDER_S  26
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
+#define SPI_WR_BIT_ORDER    0x00000003
+#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
+#define SPI_WR_BIT_ORDER_V  0x3
+#define SPI_WR_BIT_ORDER_S  25
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
 /*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
 tate..*/
-#define SPI_RD_BIT_ORDER    (BIT(25))
-#define SPI_RD_BIT_ORDER_M  (BIT(25))
-#define SPI_RD_BIT_ORDER_V  0x1
-#define SPI_RD_BIT_ORDER_S  25
+#define SPI_RD_BIT_ORDER    0x00000003
+#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
+#define SPI_RD_BIT_ORDER_V  0x3
+#define SPI_RD_BIT_ORDER_S  23
 /* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
 /*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
 an be configured in CONF state..*/
@@ -158,8 +158,8 @@ ONF state..*/
 #define SPI_FADDR_DUAL_V  0x1
 #define SPI_FADDR_DUAL_S  5
 /* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the dummy phase the signal level of spi is output by the spi controller. Can
-be configured in CONF state..*/
+/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
+e, the FSPI bus signals are output. Can be configured in CONF state..*/
 #define SPI_DUMMY_OUT    (BIT(3))
 #define SPI_DUMMY_OUT_M  (BIT(3))
 #define SPI_DUMMY_OUT_V  0x1
@@ -426,8 +426,8 @@ the configured bit length in slave mode DMA RX controlled transfer. The register
 
 #define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
 /* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configur
-ed in CONF state..*/
+/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
+:  spi quad input swap disable. Can be configured in CONF state..*/
 #define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
 #define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
 #define SPI_QUAD_DIN_PIN_SWAP_V  0x1
@@ -813,6 +813,20 @@ _vld is cleared by spi_trans_done..*/
 #define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
 #define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
 #define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
+a. 0: DMA RX FIFO is ready for receiving data..*/
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
+#define SPI_DMA_INFIFO_FULL_V  0x1
+#define SPI_DMA_INFIFO_FULL_S  1
+/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
+ 0: DMA TX FIFO is ready for sending data..*/
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
 
 #define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
 /* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
@@ -1726,7 +1740,7 @@ M. 0: XTAL CLK..*/
 #define SPI_CLK_EN_S  0
 
 #define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
-/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010110 ; */
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101190 ; */
 /*description: SPI register version..*/
 #define SPI_DATE    0x0FFFFFFF
 #define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))

components/soc/esp32s3/include/soc/spi_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -14,6 +14,8 @@
 #ifndef _SOC_SPI_STRUCT_H_
 #define _SOC_SPI_STRUCT_H_
 
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -33,7 +35,7 @@ typedef volatile struct {
     union {
         struct {
             uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t dummy_out                     :    1;  /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
+            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
             uint32_t reserved4                     :    1;  /*reserved*/
             uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
             uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
@@ -50,9 +52,9 @@ typedef volatile struct {
             uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
             uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
             uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    3;  /*reserved*/
-            uint32_t rd_bit_order                  :    1;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
-            uint32_t wr_bit_order                  :    1;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
             uint32_t reserved27                    :    5;  /*reserved*/
         };
         uint32_t val;
@@ -146,7 +148,7 @@ typedef volatile struct {
             uint32_t reserved25                    :    4;  /*reserved*/
             uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
             uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
-            uint32_t quad_din_pin_swap             :    1;  /*1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
         };
         uint32_t val;
     } misc;
@@ -196,7 +198,9 @@ typedef volatile struct {
     } dout_mode;
     union {
         struct {
-            uint32_t reserved0                     :    18;  /*reserved*/
+            uint32_t outfifo_empty                 :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
+            uint32_t infifo_full                   :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
+            uint32_t reserved2                     :    16;  /*reserved*/
             uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
             uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
             uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
@@ -365,7 +369,7 @@ typedef volatile struct {
     uint32_t reserved_8c;
     uint32_t reserved_90;
     uint32_t reserved_94;
-    uint32_t data_buf[16];
+    uint32_t data_buf[16];                                               /*SPI CPU-controlled buffer0*/
     uint32_t reserved_d8;
     uint32_t reserved_dc;
     union {
@@ -419,4 +423,6 @@ extern spi_dev_t GPSPI3;
 }
 #endif
 
+
+
 #endif /*_SOC_SPI_STRUCT_H_ */

components/soc/esp32s3/include/soc/syscon_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SYSCON_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */

components/soc/esp32s3/include/soc/syscon_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,6 +13,7 @@
 // limitations under the License.
 #ifndef _SOC_SYSCON_STRUCT_H_
 #define _SOC_SYSCON_STRUCT_H_
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/system_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SYSTEM_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SYSTEM_CORE_1_CONTROL_0_REG          (DR_REG_SYSTEM_BASE + 0x0)
 /* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */

components/soc/esp32s3/include/soc/system_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_SYSTEM_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {

components/soc/esp32s3/include/soc/systimer_struct.h

@@ -14,6 +14,7 @@
  */
 #pragma once
 
+#include <stdint.h>
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32s3/include/soc/timer_group_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,10 +11,11 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#ifndef _SOC_TIMG_REG_H_
-#define _SOC_TIMG_REG_H_
+#ifndef _SOC_TIMER_GROUP_REG_H_
+#define _SOC_TIMER_GROUP_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/timer_group_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,14 +11,15 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#ifndef _SOC_TIMG_STRUCT_H_
-#define _SOC_TIMG_STRUCT_H_
+#ifndef _SOC_TIMER_GROUP_STRUCT_H_
+#define _SOC_TIMER_GROUP_STRUCT_H_
+
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdint.h>
-
 typedef volatile struct {
     struct {
         union {
@@ -31,7 +32,7 @@ typedef volatile struct {
                 uint32_t divider                       :    16;
                 uint32_t autoreload                    :    1;
                 uint32_t increase                      :    1;
-                uint32_t enable                            :    1;
+                uint32_t enable                        :    1;
             };
             uint32_t val;
         } config;
@@ -213,4 +214,6 @@ extern timg_dev_t TIMERG1;
 }
 #endif
 
-#endif  /* _SOC_TIMG_STRUCT_H_ */
+
+
+#endif /*_SOC_TIMG_STRUCT_H_ */

components/soc/esp32s3/include/soc/twai_struct.h

@@ -14,6 +14,7 @@
 
 #pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/uart_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_UART_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
 /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */

components/soc/esp32s3/include/soc/uart_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_UART_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {

components/soc/esp32s3/include/soc/uhci_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_UHCI_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
 /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */

components/soc/esp32s3/include/soc/uhci_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_UHCI_STRUCT_H_
 
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct {
     union {

components/soc/esp32s3/include/soc/usb_device_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_USB_DEVICE_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define USB_DEVICE_EP1_REG          (DR_REG_USB_DEVICE_BASE + 0x0)
 /* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */

components/soc/esp32s3/include/soc/usb_reg.h

@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/usb_struct.h

@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include "usb_types.h"
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/usb_wrap_reg.h

@@ -1,252 +1,216 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_USB_WRAP_REG_H_
+#define _SOC_USB_WRAP_REG_H_
 
-#include <stdint.h>
-#include "soc/soc.h"
+
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/** USB_WRAP_OTG_CONF_REG register
- *  PAD/DFIFO/PHY configuration register.
- */
-#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
-/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
- *  This bit is used to enable the software override of srp session end signal.1'b0:
- *  the signal is controlled by the chip input.1'b1: the signal is controlled by the
- *  software.
- */
-#define USB_WRAP_SRP_SESSEND_OVERRIDE    (BIT(0))
-#define USB_WRAP_SRP_SESSEND_OVERRIDE_M  (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
-#define USB_WRAP_SRP_SESSEND_OVERRIDE_V  0x00000001
-#define USB_WRAP_SRP_SESSEND_OVERRIDE_S  0
-/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
- *  Software override value of srp session end signal.
- */
-#define USB_WRAP_SRP_SESSEND_VALUE    (BIT(1))
-#define USB_WRAP_SRP_SESSEND_VALUE_M  (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
-#define USB_WRAP_SRP_SESSEND_VALUE_V  0x00000001
-#define USB_WRAP_SRP_SESSEND_VALUE_S  1
-/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
- *  Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
- */
-#define USB_WRAP_PHY_SEL    (BIT(2))
-#define USB_WRAP_PHY_SEL_M  (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
-#define USB_WRAP_PHY_SEL_V  0x00000001
-#define USB_WRAP_PHY_SEL_S  2
-/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
- *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
- */
-#define USB_WRAP_DFIFO_FORCE_PD    (BIT(3))
-#define USB_WRAP_DFIFO_FORCE_PD_M  (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
-#define USB_WRAP_DFIFO_FORCE_PD_V  0x00000001
-#define USB_WRAP_DFIFO_FORCE_PD_S  3
-/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
- *  Bypass Debounce filters for avalid.
- */
-#define USB_WRAP_DBNCE_FLTR_BYPASS    (BIT(4))
-#define USB_WRAP_DBNCE_FLTR_BYPASS_M  (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
-#define USB_WRAP_DBNCE_FLTR_BYPASS_V  0x00000001
-#define USB_WRAP_DBNCE_FLTR_BYPASS_S  4
-/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
- *  Enable software to control USB D+ D- exchange
- */
-#define USB_WRAP_EXCHG_PINS_OVERRIDE    (BIT(5))
-#define USB_WRAP_EXCHG_PINS_OVERRIDE_M  (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
-#define USB_WRAP_EXCHG_PINS_OVERRIDE_V  0x00000001
-#define USB_WRAP_EXCHG_PINS_OVERRIDE_S  5
-/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
- *  USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
- */
-#define USB_WRAP_EXCHG_PINS    (BIT(6))
-#define USB_WRAP_EXCHG_PINS_M  (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
-#define USB_WRAP_EXCHG_PINS_V  0x00000001
-#define USB_WRAP_EXCHG_PINS_S  6
-/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
- *  Control single-end input high threshold.
- */
-#define USB_WRAP_VREFH    0x00000003
-#define USB_WRAP_VREFH_M  (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
-#define USB_WRAP_VREFH_V  0x00000003
-#define USB_WRAP_VREFH_S  7
-/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
- *  Control single-end input low threshold.
- */
-#define USB_WRAP_VREFL    0x00000003
-#define USB_WRAP_VREFL_M  (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
-#define USB_WRAP_VREFL_V  0x00000003
-#define USB_WRAP_VREFL_S  9
-/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
- *  Enable software to control input  threshold.
- */
-#define USB_WRAP_VREF_OVERRIDE    (BIT(11))
-#define USB_WRAP_VREF_OVERRIDE_M  (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
-#define USB_WRAP_VREF_OVERRIDE_V  0x00000001
-#define USB_WRAP_VREF_OVERRIDE_S  11
-/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
- *  Enable software to control USB pad in pullup or pulldown mode.
- */
-#define USB_WRAP_PAD_PULL_OVERRIDE    (BIT(12))
-#define USB_WRAP_PAD_PULL_OVERRIDE_M  (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
-#define USB_WRAP_PAD_PULL_OVERRIDE_V  0x00000001
-#define USB_WRAP_PAD_PULL_OVERRIDE_S  12
-/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
- *  Control USB D+ pullup.
- */
-#define USB_WRAP_DP_PULLUP    (BIT(13))
-#define USB_WRAP_DP_PULLUP_M  (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
-#define USB_WRAP_DP_PULLUP_V  0x00000001
-#define USB_WRAP_DP_PULLUP_S  13
-/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
- *  Control USB D+ pulldown.
- */
-#define USB_WRAP_DP_PULLDOWN    (BIT(14))
-#define USB_WRAP_DP_PULLDOWN_M  (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
-#define USB_WRAP_DP_PULLDOWN_V  0x00000001
-#define USB_WRAP_DP_PULLDOWN_S  14
-/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
- *  Control USB D+ pullup.
- */
-#define USB_WRAP_DM_PULLUP    (BIT(15))
-#define USB_WRAP_DM_PULLUP_M  (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
-#define USB_WRAP_DM_PULLUP_V  0x00000001
-#define USB_WRAP_DM_PULLUP_S  15
-/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
- *  Control USB D+ pulldown.
- */
-#define USB_WRAP_DM_PULLDOWN    (BIT(16))
-#define USB_WRAP_DM_PULLDOWN_M  (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
-#define USB_WRAP_DM_PULLDOWN_V  0x00000001
-#define USB_WRAP_DM_PULLDOWN_S  16
-/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
- *  Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
- */
-#define USB_WRAP_PULLUP_VALUE    (BIT(17))
-#define USB_WRAP_PULLUP_VALUE_M  (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
-#define USB_WRAP_PULLUP_VALUE_V  0x00000001
-#define USB_WRAP_PULLUP_VALUE_S  17
-/** USB_WRAP_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
- *  Enable USB pad function.
- */
-#define USB_WRAP_PAD_ENABLE    (BIT(18))
-#define USB_WRAP_PAD_ENABLE_M  (USB_WRAP_PAD_ENABLE_V << USB_WRAP_PAD_ENABLE_S)
-#define USB_WRAP_PAD_ENABLE_V  0x00000001
-#define USB_WRAP_PAD_ENABLE_S  18
-/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 1;
- *  Force AHB clock always on.
- */
-#define USB_WRAP_AHB_CLK_FORCE_ON    (BIT(19))
-#define USB_WRAP_AHB_CLK_FORCE_ON_M  (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
-#define USB_WRAP_AHB_CLK_FORCE_ON_V  0x00000001
-#define USB_WRAP_AHB_CLK_FORCE_ON_S  19
-/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
- *  Force PHY clock always on.
- */
-#define USB_WRAP_PHY_CLK_FORCE_ON    (BIT(20))
-#define USB_WRAP_PHY_CLK_FORCE_ON_M  (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
-#define USB_WRAP_PHY_CLK_FORCE_ON_V  0x00000001
-#define USB_WRAP_PHY_CLK_FORCE_ON_S  20
-/** USB_WRAP_PHY_TX_EDGE_SEL : R/W; bitpos: [21]; default: 0;
- *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
- */
-#define USB_WRAP_PHY_TX_EDGE_SEL    (BIT(21))
-#define USB_WRAP_PHY_TX_EDGE_SEL_M  (USB_WRAP_PHY_TX_EDGE_SEL_V << USB_WRAP_PHY_TX_EDGE_SEL_S)
-#define USB_WRAP_PHY_TX_EDGE_SEL_V  0x00000001
-#define USB_WRAP_PHY_TX_EDGE_SEL_S  21
-/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
- *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
- */
-#define USB_WRAP_DFIFO_FORCE_PU    (BIT(22))
-#define USB_WRAP_DFIFO_FORCE_PU_M  (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
-#define USB_WRAP_DFIFO_FORCE_PU_V  0x00000001
-#define USB_WRAP_DFIFO_FORCE_PU_S  22
-/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Disable auto clock gating of CSR registers.
- */
+#define USB_WRAP_OTG_CONF_REG          (DR_REG_USB_WRAP_BASE + 0x0)
+/* USB_WRAP_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Disable auto clock gating of CSR registers .*/
 #define USB_WRAP_CLK_EN    (BIT(31))
-#define USB_WRAP_CLK_EN_M  (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
-#define USB_WRAP_CLK_EN_V  0x00000001
+#define USB_WRAP_CLK_EN_M  (BIT(31))
+#define USB_WRAP_CLK_EN_V  0x1
 #define USB_WRAP_CLK_EN_S  31
+/* USB_WRAP_DFIFO_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Disable the dfifo to go into low power mode. The data in dfifo will not lost..*/
+#define USB_WRAP_DFIFO_FORCE_PU    (BIT(22))
+#define USB_WRAP_DFIFO_FORCE_PU_M  (BIT(22))
+#define USB_WRAP_DFIFO_FORCE_PU_V  0x1
+#define USB_WRAP_DFIFO_FORCE_PU_S  22
+/* USB_WRAP_PHY_TX_EDGE_SEL : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Select phy tx signal output clock edge.*/
+#define USB_WRAP_PHY_TX_EDGE_SEL    (BIT(21))
+#define USB_WRAP_PHY_TX_EDGE_SEL_M  (BIT(21))
+#define USB_WRAP_PHY_TX_EDGE_SEL_V  0x1
+#define USB_WRAP_PHY_TX_EDGE_SEL_S  21
+/* USB_WRAP_PHY_CLK_FORCE_ON : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: Force phy clock always on.*/
+#define USB_WRAP_PHY_CLK_FORCE_ON    (BIT(20))
+#define USB_WRAP_PHY_CLK_FORCE_ON_M  (BIT(20))
+#define USB_WRAP_PHY_CLK_FORCE_ON_V  0x1
+#define USB_WRAP_PHY_CLK_FORCE_ON_S  20
+/* USB_WRAP_AHB_CLK_FORCE_ON : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: Force ahb clock always on.*/
+#define USB_WRAP_AHB_CLK_FORCE_ON    (BIT(19))
+#define USB_WRAP_AHB_CLK_FORCE_ON_M  (BIT(19))
+#define USB_WRAP_AHB_CLK_FORCE_ON_V  0x1
+#define USB_WRAP_AHB_CLK_FORCE_ON_S  19
+/* USB_WRAP_USB_PAD_ENABLE : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: Enable USB pad function.*/
+#define USB_WRAP_USB_PAD_ENABLE    (BIT(18))
+#define USB_WRAP_USB_PAD_ENABLE_M  (BIT(18))
+#define USB_WRAP_USB_PAD_ENABLE_V  0x1
+#define USB_WRAP_USB_PAD_ENABLE_S  18
+/* USB_WRAP_PULLUP_VALUE : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Controlle pullup value.*/
+#define USB_WRAP_PULLUP_VALUE    (BIT(17))
+#define USB_WRAP_PULLUP_VALUE_M  (BIT(17))
+#define USB_WRAP_PULLUP_VALUE_V  0x1
+#define USB_WRAP_PULLUP_VALUE_S  17
+/* USB_WRAP_DM_PULLDOWN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Controlle USB D+ pulldown.*/
+#define USB_WRAP_DM_PULLDOWN    (BIT(16))
+#define USB_WRAP_DM_PULLDOWN_M  (BIT(16))
+#define USB_WRAP_DM_PULLDOWN_V  0x1
+#define USB_WRAP_DM_PULLDOWN_S  16
+/* USB_WRAP_DM_PULLUP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Controlle USB D+ pullup.*/
+#define USB_WRAP_DM_PULLUP    (BIT(15))
+#define USB_WRAP_DM_PULLUP_M  (BIT(15))
+#define USB_WRAP_DM_PULLUP_V  0x1
+#define USB_WRAP_DM_PULLUP_S  15
+/* USB_WRAP_DP_PULLDOWN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Controlle USB D+ pulldown.*/
+#define USB_WRAP_DP_PULLDOWN    (BIT(14))
+#define USB_WRAP_DP_PULLDOWN_M  (BIT(14))
+#define USB_WRAP_DP_PULLDOWN_V  0x1
+#define USB_WRAP_DP_PULLDOWN_S  14
+/* USB_WRAP_DP_PULLUP : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Controlle USB D+ pullup.*/
+#define USB_WRAP_DP_PULLUP    (BIT(13))
+#define USB_WRAP_DP_PULLUP_M  (BIT(13))
+#define USB_WRAP_DP_PULLUP_V  0x1
+#define USB_WRAP_DP_PULLUP_S  13
+/* USB_WRAP_PAD_PULL_OVERRIDE : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Enable software controlle USB D+ D- pullup pulldown.*/
+#define USB_WRAP_PAD_PULL_OVERRIDE    (BIT(12))
+#define USB_WRAP_PAD_PULL_OVERRIDE_M  (BIT(12))
+#define USB_WRAP_PAD_PULL_OVERRIDE_V  0x1
+#define USB_WRAP_PAD_PULL_OVERRIDE_S  12
+/* USB_WRAP_VREF_OVERRIDE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Enable software controlle input  threshold.*/
+#define USB_WRAP_VREF_OVERRIDE    (BIT(11))
+#define USB_WRAP_VREF_OVERRIDE_M  (BIT(11))
+#define USB_WRAP_VREF_OVERRIDE_V  0x1
+#define USB_WRAP_VREF_OVERRIDE_S  11
+/* USB_WRAP_VREFL : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
+/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
+#define USB_WRAP_VREFL    0x00000003
+#define USB_WRAP_VREFL_M  ((USB_WRAP_VREFL_V)<<(USB_WRAP_VREFL_S))
+#define USB_WRAP_VREFL_V  0x3
+#define USB_WRAP_VREFL_S  9
+/* USB_WRAP_VREFH : R/W ;bitpos:[8:7] ;default: 2'b0 ; */
+/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
+#define USB_WRAP_VREFH    0x00000003
+#define USB_WRAP_VREFH_M  ((USB_WRAP_VREFH_V)<<(USB_WRAP_VREFH_S))
+#define USB_WRAP_VREFH_V  0x3
+#define USB_WRAP_VREFH_S  7
+/* USB_WRAP_EXCHG_PINS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: USB D+ D- exchange.*/
+#define USB_WRAP_EXCHG_PINS    (BIT(6))
+#define USB_WRAP_EXCHG_PINS_M  (BIT(6))
+#define USB_WRAP_EXCHG_PINS_V  0x1
+#define USB_WRAP_EXCHG_PINS_S  6
+/* USB_WRAP_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Enable software controlle USB D+ D- exchange.*/
+#define USB_WRAP_EXCHG_PINS_OVERRIDE    (BIT(5))
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_M  (BIT(5))
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_V  0x1
+#define USB_WRAP_EXCHG_PINS_OVERRIDE_S  5
+/* USB_WRAP_DBNCE_FLTR_BYPASS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals.*/
+#define USB_WRAP_DBNCE_FLTR_BYPASS    (BIT(4))
+#define USB_WRAP_DBNCE_FLTR_BYPASS_M  (BIT(4))
+#define USB_WRAP_DBNCE_FLTR_BYPASS_V  0x1
+#define USB_WRAP_DBNCE_FLTR_BYPASS_S  4
+/* USB_WRAP_DFIFO_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Force the dfifo to go into low power mode. The data in dfifo will not lost..*/
+#define USB_WRAP_DFIFO_FORCE_PD    (BIT(3))
+#define USB_WRAP_DFIFO_FORCE_PD_M  (BIT(3))
+#define USB_WRAP_DFIFO_FORCE_PD_V  0x1
+#define USB_WRAP_DFIFO_FORCE_PD_S  3
+/* USB_WRAP_PHY_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Select internal external PHY.*/
+#define USB_WRAP_PHY_SEL    (BIT(2))
+#define USB_WRAP_PHY_SEL_M  (BIT(2))
+#define USB_WRAP_PHY_SEL_V  0x1
+#define USB_WRAP_PHY_SEL_S  2
+/* USB_WRAP_SRP_SESSEND_VALUE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Software over-ride value of srp session end signal..*/
+#define USB_WRAP_SRP_SESSEND_VALUE    (BIT(1))
+#define USB_WRAP_SRP_SESSEND_VALUE_M  (BIT(1))
+#define USB_WRAP_SRP_SESSEND_VALUE_V  0x1
+#define USB_WRAP_SRP_SESSEND_VALUE_S  1
+/* USB_WRAP_SRP_SESSEND_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit is used to enable the software over-ride of srp session end signal..*/
+#define USB_WRAP_SRP_SESSEND_OVERRIDE    (BIT(0))
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_M  (BIT(0))
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_V  0x1
+#define USB_WRAP_SRP_SESSEND_OVERRIDE_S  0
 
-/** USB_WRAP_TEST_CONF_REG register
- *  TEST relative configuration registers.
- */
-#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4)
-/** USB_WRAP_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable to test the USB pad.
- */
-#define USB_WRAP_TEST_ENABLE    (BIT(0))
-#define USB_WRAP_TEST_ENABLE_M  (USB_WRAP_TEST_ENABLE_V << USB_WRAP_TEST_ENABLE_S)
-#define USB_WRAP_TEST_ENABLE_V  0x00000001
-#define USB_WRAP_TEST_ENABLE_S  0
-/** USB_WRAP_TEST_USB_WRAP_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test.
- */
-#define USB_WRAP_TEST_USB_WRAP_OE    (BIT(1))
-#define USB_WRAP_TEST_USB_WRAP_OE_M  (USB_WRAP_TEST_USB_WRAP_OE_V << USB_WRAP_TEST_USB_WRAP_OE_S)
-#define USB_WRAP_TEST_USB_WRAP_OE_V  0x00000001
-#define USB_WRAP_TEST_USB_WRAP_OE_S  1
-/** USB_WRAP_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test.
- */
-#define USB_WRAP_TEST_TX_DP    (BIT(2))
-#define USB_WRAP_TEST_TX_DP_M  (USB_WRAP_TEST_TX_DP_V << USB_WRAP_TEST_TX_DP_S)
-#define USB_WRAP_TEST_TX_DP_V  0x00000001
-#define USB_WRAP_TEST_TX_DP_S  2
-/** USB_WRAP_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test.
- */
-#define USB_WRAP_TEST_TX_DM    (BIT(3))
-#define USB_WRAP_TEST_TX_DM_M  (USB_WRAP_TEST_TX_DM_V << USB_WRAP_TEST_TX_DM_S)
-#define USB_WRAP_TEST_TX_DM_V  0x00000001
-#define USB_WRAP_TEST_TX_DM_S  3
-/** USB_WRAP_TEST_RX_RCV : RO; bitpos: [4]; default: 0;
- *  USB differential rx value in test.
- */
-#define USB_WRAP_TEST_RX_RCV    (BIT(4))
-#define USB_WRAP_TEST_RX_RCV_M  (USB_WRAP_TEST_RX_RCV_V << USB_WRAP_TEST_RX_RCV_S)
-#define USB_WRAP_TEST_RX_RCV_V  0x00000001
-#define USB_WRAP_TEST_RX_RCV_S  4
-/** USB_WRAP_TEST_RX_DP : RO; bitpos: [5]; default: 0;
- *  USB D+ rx value in test.
- */
-#define USB_WRAP_TEST_RX_DP    (BIT(5))
-#define USB_WRAP_TEST_RX_DP_M  (USB_WRAP_TEST_RX_DP_V << USB_WRAP_TEST_RX_DP_S)
-#define USB_WRAP_TEST_RX_DP_V  0x00000001
-#define USB_WRAP_TEST_RX_DP_S  5
-/** USB_WRAP_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test.
- */
+#define USB_WRAP_TEST_CONF_REG          (DR_REG_USB_WRAP_BASE + 0x4)
+/* USB_WRAP_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: USB D- rx value in test.*/
 #define USB_WRAP_TEST_RX_DM    (BIT(6))
-#define USB_WRAP_TEST_RX_DM_M  (USB_WRAP_TEST_RX_DM_V << USB_WRAP_TEST_RX_DM_S)
-#define USB_WRAP_TEST_RX_DM_V  0x00000001
+#define USB_WRAP_TEST_RX_DM_M  (BIT(6))
+#define USB_WRAP_TEST_RX_DM_V  0x1
 #define USB_WRAP_TEST_RX_DM_S  6
+/* USB_WRAP_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: USB D+ rx value in test.*/
+#define USB_WRAP_TEST_RX_DP    (BIT(5))
+#define USB_WRAP_TEST_RX_DP_M  (BIT(5))
+#define USB_WRAP_TEST_RX_DP_V  0x1
+#define USB_WRAP_TEST_RX_DP_S  5
+/* USB_WRAP_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: USB differential rx value in test.*/
+#define USB_WRAP_TEST_RX_RCV    (BIT(4))
+#define USB_WRAP_TEST_RX_RCV_M  (BIT(4))
+#define USB_WRAP_TEST_RX_RCV_V  0x1
+#define USB_WRAP_TEST_RX_RCV_S  4
+/* USB_WRAP_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: USB D- tx value in test.*/
+#define USB_WRAP_TEST_TX_DM    (BIT(3))
+#define USB_WRAP_TEST_TX_DM_M  (BIT(3))
+#define USB_WRAP_TEST_TX_DM_V  0x1
+#define USB_WRAP_TEST_TX_DM_S  3
+/* USB_WRAP_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: USB D+ tx value in test.*/
+#define USB_WRAP_TEST_TX_DP    (BIT(2))
+#define USB_WRAP_TEST_TX_DP_M  (BIT(2))
+#define USB_WRAP_TEST_TX_DP_V  0x1
+#define USB_WRAP_TEST_TX_DP_S  2
+/* USB_WRAP_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: USB pad oen in test.*/
+#define USB_WRAP_TEST_USB_OE    (BIT(1))
+#define USB_WRAP_TEST_USB_OE_M  (BIT(1))
+#define USB_WRAP_TEST_USB_OE_V  0x1
+#define USB_WRAP_TEST_USB_OE_S  1
+/* USB_WRAP_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Enable test of the USB pad.*/
+#define USB_WRAP_TEST_ENABLE    (BIT(0))
+#define USB_WRAP_TEST_ENABLE_M  (BIT(0))
+#define USB_WRAP_TEST_ENABLE_V  0x1
+#define USB_WRAP_TEST_ENABLE_S  0
 
-/** USB_WRAP_DATE_REG register
- *  Version register.
- */
-#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
-/** USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 419631616;
- *  data register.
- */
+#define USB_WRAP_DATE_REG          (DR_REG_USB_WRAP_BASE + 0x3FC)
+/* USB_WRAP_DATE : R/W ;bitpos:[31:0] ;default: 32'h2102010 ; */
+/*description: Date register.*/
 #define USB_WRAP_DATE    0xFFFFFFFF
-#define USB_WRAP_DATE_M  (USB_WRAP_DATE_V << USB_WRAP_DATE_S)
+#define USB_WRAP_DATE_M  ((USB_WRAP_DATE_V)<<(USB_WRAP_DATE_S))
 #define USB_WRAP_DATE_V  0xFFFFFFFF
 #define USB_WRAP_DATE_S  0
 
+
 #ifdef __cplusplus
 }
 #endif
+
+
+
+#endif /*_SOC_USB_WRAP_REG_H_ */

components/soc/esp32s3/include/soc/usb_wrap_struct.h

@@ -14,6 +14,7 @@
  */
 #pragma once
 
+#include <stdint.h>
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32s3/include/soc/usbh_struct.h

@@ -14,6 +14,7 @@
 
 #pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32s3/include/soc/world_controller_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
 #define _SOC_WORLD_CONTROLLER_REG_H_
 
 
+#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define WORLD_CONTROLLER_WCL_CORE_0_ENTRY_1_ADDR_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x0)
 /* WORLD_CONTROLLER_CORE_0_ENTRY_1_ADDR : R/W ;bitpos:[31:0] ;default: 31'b0 ; */
@@ -411,8 +411,7 @@ extern "C" {
 #define WORLD_CONTROLLER_WCL_CORE_0_STATUSTABLE_CURRENT_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0xFC)
 /* WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */
 /*description: This field is used to quickly read and rewrite the current field of all STATUSTA
-BLE registers.For example,bit 1 represents the current field of STATUSTABLE1, bi
-t2 represents the current field of STATUSTABLE2, and so on..*/
+BLE registers.For example.*/
 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT    0x00001FFF
 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_M  ((WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_S))
 #define WORLD_CONTROLLER_CORE_0_STATUSTABLE_CURRENT_V  0x1FFF
@@ -420,15 +419,13 @@ t2 represents the current field of STATUSTABLE2, and so on..*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_MESSAGE_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x108)
 /* WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is
- checking address..*/
+/*description: If this bit is 1.*/
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE    (BIT(6))
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_M  (BIT(6))
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_V  0x1
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_ADDRESSPHASE_S  6
 /* WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is
- checking data..*/
+/*description: If this bit is 1.*/
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE    (BIT(5))
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_M  (BIT(5))
 #define WORLD_CONTROLLER_CORE_0_MESSAGE_DATAPHASE_V  0x1
@@ -448,8 +445,7 @@ t2 represents the current field of STATUSTABLE2, and so on..*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_TRIGGER_ADDR_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x140)
 /* WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to configure the entry address from WORLD0 to WORLD1, when th
-e CPU executes to this address, switch to WORLD1.*/
+/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/
 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_M  ((WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_S))
 #define WORLD_CONTROLLER_CORE_0_WORLD_TRIGGER_ADDR_V  0xFFFFFFFF
@@ -457,7 +453,7 @@ e CPU executes to this address, switch to WORLD1.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PREPARE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x144)
 /* WORLD_CONTROLLER_CORE_0_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1.*/
+/*description: This field to used to set world to enter.*/
 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE    0x00000003
 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_M  ((WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_S))
 #define WORLD_CONTROLLER_CORE_0_WORLD_PREPARE_V  0x3
@@ -465,9 +461,7 @@ e CPU executes to this address, switch to WORLD1.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_UPDATE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x148)
 /* WORLD_CONTROLLER_CORE_0_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to update configuration completed, can write any value, the h
-ardware only checks the write operation of this register and does not case about
- its value.*/
+/*description: This field is used to update configuration completed.*/
 #define WORLD_CONTROLLER_CORE_0_UPDATE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_UPDATE_M  ((WORLD_CONTROLLER_CORE_0_UPDATE_V)<<(WORLD_CONTROLLER_CORE_0_UPDATE_S))
 #define WORLD_CONTROLLER_CORE_0_UPDATE_V  0xFFFFFFFF
@@ -475,10 +469,7 @@ ardware only checks the write operation of this register and does not case about
 
 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_CANCEL_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x14C)
 /* WORLD_CONTROLLER_CORE_0_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to cancel switch world configuration, if the trigger address
-and update configuration complete, can use this register to cancel world switch.
- can write any value, the hardware only checks the write operation of this regis
-ter and does not case about its value.*/
+/*description: This field is used to cancel switch world configuration.*/
 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_M  ((WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_S))
 #define WORLD_CONTROLLER_CORE_0_WORLD_CANCEL_V  0xFFFFFFFF
@@ -502,7 +493,7 @@ ter and does not case about its value.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_WORLD_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x158)
 /* WORLD_CONTROLLER_CORE_0_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit indicates whether is preparing to switch to WORLD1, 1 means value..*/
+/*description: This bit indicates whether is preparing to switch to WORLD1.*/
 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE    (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_WORLD_PHASE_V  0x1
@@ -510,8 +501,7 @@ ter and does not case about its value.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_ENABLE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x180)
 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field is used to set NMI mask, it can write any value, when write this regi
-ster, the hardware start masking NMI interrupt.*/
+/*description: this field is used to set NMI mask.*/
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_M  ((WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_S))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_ENABLE_V  0xFFFFFFFF
@@ -519,8 +509,7 @@ ster, the hardware start masking NMI interrupt.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x184)
 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field to used to set trigger address, when CPU executes to this address, NM
-I mask automatically fails.*/
+/*description: this field to used to set trigger address.*/
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_M  ((WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_S))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_TRIGGER_ADDR_V  0xFFFFFFFF
@@ -528,8 +517,7 @@ I mask automatically fails.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_DISABLE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x188)
 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field is used to disable NMI mask, it will not take effect immediately, onl
-y when the CPU executes to the trigger address will it start to cancel NMI mask.*/
+/*description: this field is used to disable NMI mask.*/
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_M  ((WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_S))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_DISABLE_V  0xFFFFFFFF
@@ -545,7 +533,7 @@ y when the CPU executes to the trigger address will it start to cancel NMI mask.
 
 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x190)
 /* WORLD_CONTROLLER_CORE_0_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: this bit is used to mask NMI interrupt, it can directly mask NMI interrupt.*/
+/*description: this bit is used to mask NMI interrupt.*/
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK    (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_V  0x1
@@ -553,8 +541,7 @@ y when the CPU executes to the trigger address will it start to cancel NMI mask.
 
 #define WORLD_CONTROLLER_WCL_CORE_0_NMI_MASK_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x194)
 /* WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: this bit is used to indicates whether the NMI interrupt is being masked, 1 means
- NMI interrupt is being masked,.*/
+/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE    (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_0_NMI_MASK_PHASE_V  0x1
@@ -951,8 +938,7 @@ y when the CPU executes to the trigger address will it start to cancel NMI mask.
 #define WORLD_CONTROLLER_WCL_CORE_1_STATUSTABLE_CURRENT_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x4FC)
 /* WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT : R/W ;bitpos:[13:1] ;default: 13'b0 ; */
 /*description: This field is used to quickly read and rewrite the current field of all STATUSTA
-BLE registers.For example,bit 1 represents the current field of STATUSTABLE1, bi
-t2 represents the current field of STATUSTABLE2, and so on..*/
+BLE registers.For example.*/
 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT    0x00001FFF
 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_M  ((WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V)<<(WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_S))
 #define WORLD_CONTROLLER_CORE_1_STATUSTABLE_CURRENT_V  0x1FFF
@@ -960,15 +946,13 @@ t2 represents the current field of STATUSTABLE2, and so on..*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_MESSAGE_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x508)
 /* WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is
- checking address..*/
+/*description: If this bit is 1.*/
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE    (BIT(6))
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_M  (BIT(6))
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_V  0x1
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_ADDRESSPHASE_S  6
 /* WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: If this bit is 1, it means that is checking clear write_buffer operation, and is
- checking data..*/
+/*description: If this bit is 1.*/
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE    (BIT(5))
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_M  (BIT(5))
 #define WORLD_CONTROLLER_CORE_1_MESSAGE_DATAPHASE_V  0x1
@@ -988,8 +972,7 @@ t2 represents the current field of STATUSTABLE2, and so on..*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_TRIGGER_ADDR_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x540)
 /* WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR : RW ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to configure the entry address from WORLD0 to WORLD1, when th
-e CPU executes to this address, switch to WORLD1.*/
+/*description: This field is used to configure the entry address from WORLD0 to WORLD1.*/
 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_M  ((WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_S))
 #define WORLD_CONTROLLER_CORE_1_WORLD_TRIGGER_ADDR_V  0xFFFFFFFF
@@ -997,7 +980,7 @@ e CPU executes to this address, switch to WORLD1.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PREPARE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x544)
 /* WORLD_CONTROLLER_CORE_1_WORLD_PREPARE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1.*/
+/*description: This field to used to set world to enter.*/
 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE    0x00000003
 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_M  ((WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_S))
 #define WORLD_CONTROLLER_CORE_1_WORLD_PREPARE_V  0x3
@@ -1005,9 +988,7 @@ e CPU executes to this address, switch to WORLD1.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_UPDATE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x548)
 /* WORLD_CONTROLLER_CORE_1_UPDATE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to update configuration completed, can write any value, the h
-ardware only checks the write operation of this register and does not case about
- its value.*/
+/*description: This field is used to update configuration completed.*/
 #define WORLD_CONTROLLER_CORE_1_UPDATE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_UPDATE_M  ((WORLD_CONTROLLER_CORE_1_UPDATE_V)<<(WORLD_CONTROLLER_CORE_1_UPDATE_S))
 #define WORLD_CONTROLLER_CORE_1_UPDATE_V  0xFFFFFFFF
@@ -1015,10 +996,7 @@ ardware only checks the write operation of this register and does not case about
 
 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_CANCEL_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x54C)
 /* WORLD_CONTROLLER_CORE_1_WORLD_CANCEL : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: This field is used to cancel switch world configuration, if the trigger address
-and update configuration complete, can use this register to cancel world switch.
- can write any value, the hardware only checks the write operation of this regis
-ter and does not case about its value.*/
+/*description: This field is used to cancel switch world configuration.*/
 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_M  ((WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V)<<(WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_S))
 #define WORLD_CONTROLLER_CORE_1_WORLD_CANCEL_V  0xFFFFFFFF
@@ -1042,7 +1020,7 @@ ter and does not case about its value.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_WORLD_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x558)
 /* WORLD_CONTROLLER_CORE_1_WORLD_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit indicates whether is preparing to switch to WORLD1, 1 means value..*/
+/*description: This bit indicates whether is preparing to switch to WORLD1.*/
 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE    (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_WORLD_PHASE_V  0x1
@@ -1050,8 +1028,7 @@ ter and does not case about its value.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_ENABLE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x580)
 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field is used to set NMI mask, it can write any value, when write this regi
-ster, the hardware start masking NMI interrupt.*/
+/*description: this field is used to set NMI mask.*/
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_M  ((WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_S))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_ENABLE_V  0xFFFFFFFF
@@ -1059,8 +1036,7 @@ ster, the hardware start masking NMI interrupt.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x584)
 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field to used to set trigger address, when CPU executes to this address, NM
-I mask automatically fails.*/
+/*description: this field to used to set trigger address.*/
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_M  ((WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_S))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_TRIGGER_ADDR_V  0xFFFFFFFF
@@ -1068,8 +1044,7 @@ I mask automatically fails.*/
 
 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_DISABLE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x588)
 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE : WO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: this field is used to disable NMI mask, it will not take effect immediately, onl
-y when the CPU executes to the trigger address will it start to cancel NMI mask.*/
+/*description: this field is used to disable NMI mask.*/
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE    0xFFFFFFFF
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_M  ((WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V)<<(WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_S))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_DISABLE_V  0xFFFFFFFF
@@ -1085,7 +1060,7 @@ y when the CPU executes to the trigger address will it start to cancel NMI mask.
 
 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x590)
 /* WORLD_CONTROLLER_CORE_1_NMI_MASK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: this bit is used to mask NMI interrupt, it can directly mask NMI interrupt.*/
+/*description: this bit is used to mask NMI interrupt.*/
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK    (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_V  0x1
@@ -1093,220 +1068,12 @@ y when the CPU executes to the trigger address will it start to cancel NMI mask.
 
 #define WORLD_CONTROLLER_WCL_CORE_1_NMI_MASK_PHASE_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x594)
 /* WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: this bit is used to indicates whether the NMI interrupt is being masked, 1 means
- NMI interrupt is being masked,.*/
+/*description: this bit is used to indicates whether the NMI interrupt is being masked.*/
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE    (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_M  (BIT(0))
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_V  0x1
 #define WORLD_CONTROLLER_CORE_1_NMI_MASK_PHASE_S  0
 
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SPI2_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x800)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_SPI2, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI2_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SPI3_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x804)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_SPI3, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SPI3_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_UCHI0_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x808)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_UCHI0, 2'b01 means WORLD0, 2'b10 means WO
-RLD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_UCHI0_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_I2S0_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x80C)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_I2S0, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S0_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_I2S1_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x810)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_I2S1, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_I2S1_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_LCD_CAM_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x814)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_LCD_CAM, 2'b01 means WORLD0, 2'b10 means
-WORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LCD_CAM_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_AES_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x818)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_AES, 2'b01 means WORLD0, 2'b10 means WORL
-D1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_AES_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SHA_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x81C)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_SHA, 2'b01 means WORLD0, 2'b10 means WORL
-D1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SHA_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_ADC_DAC_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x820)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_ADC_DAC, 2'b01 means WORLD0, 2'b10 means
-WORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_ADC_DAC_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_USB_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x824)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_USB, 2'b01 means WORLD0, 2'b10 means WORL
-D1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_USB_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SDIO_HOST_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x828)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_SDIO_HOST, 2'b01 means WORLD0, 2'b10 mean
-s WORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SDIO_HOST_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_MAC_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x82C)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_MAC, 2'b01 means WORLD0, 2'b10 means WORL
-D1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_MAC_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_SLC_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x830)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_SLC, 2'b01 means WORLD0, 2'b10 means WORL
-D1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_SLC_S  0
-
-#define WORLD_CONTROLLER_WCL_DMA_APBPERI_LC_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x834)
-/* WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of DMA_LC, 2'b01 means WORLD0, 2'b10 means WORLD
-1 .*/
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC    0x00000003
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_M  ((WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_V)<<(WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_S))
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_V  0x3
-#define WORLD_CONTROLLER_WORLD_DMA_APBPERI_LC_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_SPI2_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x900)
-/* WORLD_CONTROLLER_WORLD_EDMA_SPI2 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_SPI2, 2'b01 means WORLD0, 2'b10 means WO
-RLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI2    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_M  ((WORLD_CONTROLLER_WORLD_EDMA_SPI2_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SPI2_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI2_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_SPI3_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x904)
-/* WORLD_CONTROLLER_WORLD_EDMA_SPI3 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_SPI3, 2'b01 means WORLD0, 2'b10 means WO
-RLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI3    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_M  ((WORLD_CONTROLLER_WORLD_EDMA_SPI3_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SPI3_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_SPI3_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_UCHI0_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x908)
-/* WORLD_CONTROLLER_WORLD_EDMA_UCHI0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_UCHI0, 2'b01 means WORLD0, 2'b10 means W
-ORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_M  ((WORLD_CONTROLLER_WORLD_EDMA_UCHI0_V)<<(WORLD_CONTROLLER_WORLD_EDMA_UCHI0_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_UCHI0_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_I2S0_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x90C)
-/* WORLD_CONTROLLER_WORLD_EDMA_I2S0 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_I2S0, 2'b01 means WORLD0, 2'b10 means WO
-RLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S0    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_M  ((WORLD_CONTROLLER_WORLD_EDMA_I2S0_V)<<(WORLD_CONTROLLER_WORLD_EDMA_I2S0_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S0_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_I2S1_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x910)
-/* WORLD_CONTROLLER_WORLD_EDMA_I2S1 : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_I2S1, 2'b01 means WORLD0, 2'b10 means WO
-RLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S1    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_M  ((WORLD_CONTROLLER_WORLD_EDMA_I2S1_V)<<(WORLD_CONTROLLER_WORLD_EDMA_I2S1_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_I2S1_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_LCD_CAM_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x914)
-/* WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_LCD_CAM, 2'b01 means WORLD0, 2'b10 means
- WORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_M  ((WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_V)<<(WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_LCD_CAM_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_AES_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x918)
-/* WORLD_CONTROLLER_WORLD_EDMA_AES : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_AES, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_AES    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_AES_M  ((WORLD_CONTROLLER_WORLD_EDMA_AES_V)<<(WORLD_CONTROLLER_WORLD_EDMA_AES_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_AES_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_AES_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_SHA_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x91C)
-/* WORLD_CONTROLLER_WORLD_EDMA_SHA : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_SHA, 2'b01 means WORLD0, 2'b10 means WOR
-LD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_SHA    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_SHA_M  ((WORLD_CONTROLLER_WORLD_EDMA_SHA_V)<<(WORLD_CONTROLLER_WORLD_EDMA_SHA_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_SHA_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_SHA_S  0
-
-#define WORLD_CONTROLLER_WCL_EDMA_ADC_DAC_REG          (DR_REG_WORLD_CONTROLLER_BASE + 0x920)
-/* WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This field is used to set world of EDMA_ADC_DAC, 2'b01 means WORLD0, 2'b10 means
- WORLD1 .*/
-#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC    0x00000003
-#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_M  ((WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_V)<<(WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_S))
-#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_V  0x3
-#define WORLD_CONTROLLER_WORLD_EDMA_ADC_DAC_S  0
-
 
 #ifdef __cplusplus
 }

components/soc/esp32s3/include/soc/world_controller_struct.h

@@ -0,0 +1,796 @@
+// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_WORLD_CONTROLLER_STRUCT_H_
+#define _SOC_WORLD_CONTROLLER_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t wcl_core_0_entry_1_addr;
+    uint32_t wcl_core_0_entry_2_addr;
+    uint32_t wcl_core_0_entry_3_addr;
+    uint32_t wcl_core_0_entry_4_addr;
+    uint32_t wcl_core_0_entry_5_addr;
+    uint32_t wcl_core_0_entry_6_addr;
+    uint32_t wcl_core_0_entry_7_addr;
+    uint32_t wcl_core_0_entry_8_addr;
+    uint32_t wcl_core_0_entry_9_addr;
+    uint32_t wcl_core_0_entry_10_addr;
+    uint32_t wcl_core_0_entry_11_addr;
+    uint32_t wcl_core_0_entry_12_addr;
+    uint32_t wcl_core_0_entry_13_addr;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t reg_core_0_entry_check        :    13;  /*This filed is used to enable entry address check */
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } wcl_core_0_entry_check;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t wcl_core_0_message_addr;
+    union {
+        struct {
+            uint32_t reg_core_0_message_max        :    4;  /*This filed is used to set the max value of clear write_buffer*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } wcl_core_0_message_max;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_1       :    1;  /*This bit is used to confirm world before enter entry 1 */
+            uint32_t reg_core_0_from_entry_1       :    4;  /*This filed is used to confirm in which entry before enter entry 1*/
+            uint32_t reg_core_0_current_1          :    1;  /*This bit is used to confirm whether the current state is in entry 1 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable1;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_2       :    1;  /*This bit is used to confirm world before enter entry 2 */
+            uint32_t reg_core_0_from_entry_2       :    4;  /*This filed is used to confirm in which entry before enter entry 2*/
+            uint32_t reg_core_0_current_2          :    1;  /*This bit is used to confirm whether the current state is in entry 2 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable2;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_3       :    1;  /*This bit is used to confirm world before enter entry 3 */
+            uint32_t reg_core_0_from_entry_3       :    4;  /*This filed is used to confirm in which entry before enter entry 3*/
+            uint32_t reg_core_0_current_3          :    1;  /*This bit is used to confirm whether the current state is in entry 3 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable3;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_4       :    1;  /*This bit is used to confirm world before enter entry 4 */
+            uint32_t reg_core_0_from_entry_4       :    4;  /*This filed is used to confirm in which entry before enter entry 4*/
+            uint32_t reg_core_0_current_4          :    1;  /*This bit is used to confirm whether the current state is in entry 4 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable4;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_5       :    1;  /*This bit is used to confirm world before enter entry 5 */
+            uint32_t reg_core_0_from_entry_5       :    4;  /*This filed is used to confirm in which entry before enter entry 5*/
+            uint32_t reg_core_0_current_5          :    1;  /*This bit is used to confirm whether the current state is in entry 5 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable5;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_6       :    1;  /*This bit is used to confirm world before enter entry 6 */
+            uint32_t reg_core_0_from_entry_6       :    4;  /*This filed is used to confirm in which entry before enter entry 6*/
+            uint32_t reg_core_0_current_6          :    1;  /*This bit is used to confirm whether the current state is in entry 6 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable6;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_7       :    1;  /*This bit is used to confirm world before enter entry 7 */
+            uint32_t reg_core_0_from_entry_7       :    4;  /*This filed is used to confirm in which entry before enter entry 7*/
+            uint32_t reg_core_0_current_7          :    1;  /*This bit is used to confirm whether the current state is in entry 7 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable7;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_8       :    1;  /*This bit is used to confirm world before enter entry 8 */
+            uint32_t reg_core_0_from_entry_8       :    4;  /*This filed is used to confirm in which entry before enter entry 8*/
+            uint32_t reg_core_0_current_8          :    1;  /*This bit is used to confirm whether the current state is in entry 8 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable8;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_9       :    1;  /*This bit is used to confirm world before enter entry 9 */
+            uint32_t reg_core_0_from_entry_9       :    4;  /*This filed is used to confirm in which entry before enter entry 9*/
+            uint32_t reg_core_0_current_9          :    1;  /*This bit is used to confirm whether the current state is in entry 9 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable9;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_10      :    1;  /*This bit is used to confirm world before enter entry 10 */
+            uint32_t reg_core_0_from_entry_10      :    4;  /*This filed is used to confirm in which entry before enter entry 10*/
+            uint32_t reg_core_0_current_10         :    1;  /*This bit is used to confirm whether the current state is in entry 10 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable10;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_11      :    1;  /*This bit is used to confirm world before enter entry 11 */
+            uint32_t reg_core_0_from_entry_11      :    4;  /*This filed is used to confirm in which entry before enter entry 11*/
+            uint32_t reg_core_0_current_11         :    1;  /*This bit is used to confirm whether the current state is in entry 11 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable11;
+    union {
+        struct {
+            uint32_t core_0_from_world_12          :    1;  /*This bit is used to confirm world before enter entry 12 */
+            uint32_t core_0_from_entry_12          :    4;  /*This filed is used to confirm in which entry before enter entry 12*/
+            uint32_t core_0_current_12             :    1;  /*This bit is used to confirm whether the current state is in entry 12 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable12;
+    union {
+        struct {
+            uint32_t reg_core_0_from_world_13      :    1;  /*This bit is used to confirm world before enter entry 13 */
+            uint32_t reg_core_0_from_entry_13      :    4;  /*This filed is used to confirm in which entry before enter entry 13*/
+            uint32_t reg_core_0_current_13         :    1;  /*This bit is used to confirm whether the current state is in entry 13 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable13;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t reg_core_0_statustable_current:    13;  /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } wcl_core_0_statustable_current;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    union {
+        struct {
+            uint32_t reg_core_0_message_match      :    1;  /*This bit indicates whether the check is successful*/
+            uint32_t reg_core_0_message_expect     :    4;  /*This field indicates the data to be written next time*/
+            uint32_t reg_core_0_message_dataphase  :    1;  /*If this bit is 1*/
+            uint32_t reg_core_0_message_addressphase:    1;  /*If this bit is 1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } wcl_core_0_message_phase;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t wcl_core_0_world_trigger_addr;
+    union {
+        struct {
+            uint32_t reg_core_0_world_prepare      :    2;  /*This field to used to set world to enter*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_0_world_prepare;
+    uint32_t wcl_core_0_world_update;
+    uint32_t wcl_core_0_world_cancel;
+    union {
+        struct {
+            uint32_t reg_core_0_world_iram0        :    2;  /*this field is used to read current world of Iram0 bus*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_0_world_iram0;
+    union {
+        struct {
+            uint32_t reg_core_0_world_dram0_pif    :    2;  /*this field is used to read current world of Dram0 bus and PIF bus*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_0_world_dram0_pif;
+    union {
+        struct {
+            uint32_t reg_core_0_world_phase        :    1;  /*This bit indicates whether is preparing to switch to WORLD1*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_0_world_phase;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t wcl_core_0_nmi_mask_enable;
+    uint32_t wcl_core_0_nmi_mask_trigger_addr;
+    uint32_t wcl_core_0_nmi_mask_disable;
+    uint32_t wcl_core_0_nmi_mask_cancle;
+    union {
+        struct {
+            uint32_t reg_core_0_nmi_mask           :    1;  /*this bit is used to mask NMI interrupt*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_0_nmi_mask;
+    union {
+        struct {
+            uint32_t reg_core_0_nmi_mask_phase     :    1;  /*this bit is used to indicates whether the NMI interrupt is being masked*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_0_nmi_mask_phase;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t wcl_core_1_entry_1_addr;
+    uint32_t wcl_core_1_entry_2_addr;
+    uint32_t wcl_core_1_entry_3_addr;
+    uint32_t wcl_core_1_entry_4_addr;
+    uint32_t wcl_core_1_entry_5_addr;
+    uint32_t wcl_core_1_entry_6_addr;
+    uint32_t wcl_core_1_entry_7_addr;
+    uint32_t wcl_core_1_entry_8_addr;
+    uint32_t wcl_core_1_entry_9_addr;
+    uint32_t wcl_core_1_entry_10_addr;
+    uint32_t wcl_core_1_entry_11_addr;
+    uint32_t wcl_core_1_entry_12_addr;
+    uint32_t wcl_core_1_entry_13_addr;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t reg_core_1_entry_check        :    13;  /*This filed is used to enable entry address check */
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } wcl_core_1_entry_check;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t wcl_core_1_message_addr;
+    union {
+        struct {
+            uint32_t reg_core_1_message_max        :    4;  /*This filed is used to set the max value of clear write_buffer*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } wcl_core_1_message_max;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_1       :    1;  /*This bit is used to confirm world before enter entry 1 */
+            uint32_t reg_core_1_from_entry_1       :    4;  /*This filed is used to confirm in which entry before enter entry 1*/
+            uint32_t reg_core_1_current_1          :    1;  /*This bit is used to confirm whether the current state is in entry 1 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable1;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_2       :    1;  /*This bit is used to confirm world before enter entry 2 */
+            uint32_t reg_core_1_from_entry_2       :    4;  /*This filed is used to confirm in which entry before enter entry 2*/
+            uint32_t reg_core_1_current_2          :    1;  /*This bit is used to confirm whether the current state is in entry 2 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable2;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_3       :    1;  /*This bit is used to confirm world before enter entry 3 */
+            uint32_t reg_core_1_from_entry_3       :    4;  /*This filed is used to confirm in which entry before enter entry 3*/
+            uint32_t reg_core_1_current_3          :    1;  /*This bit is used to confirm whether the current state is in entry 3 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable3;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_4       :    1;  /*This bit is used to confirm world before enter entry 4 */
+            uint32_t reg_core_1_from_entry_4       :    4;  /*This filed is used to confirm in which entry before enter entry 4*/
+            uint32_t reg_core_1_current_4          :    1;  /*This bit is used to confirm whether the current state is in entry 4 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable4;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_5       :    1;  /*This bit is used to confirm world before enter entry 5 */
+            uint32_t reg_core_1_from_entry_5       :    4;  /*This filed is used to confirm in which entry before enter entry 5*/
+            uint32_t reg_core_1_current_5          :    1;  /*This bit is used to confirm whether the current state is in entry 5 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable5;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_6       :    1;  /*This bit is used to confirm world before enter entry 6 */
+            uint32_t reg_core_1_from_entry_6       :    4;  /*This filed is used to confirm in which entry before enter entry 6*/
+            uint32_t reg_core_1_current_6          :    1;  /*This bit is used to confirm whether the current state is in entry 6 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable6;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_7       :    1;  /*This bit is used to confirm world before enter entry 7 */
+            uint32_t reg_core_1_from_entry_7       :    4;  /*This filed is used to confirm in which entry before enter entry 7*/
+            uint32_t reg_core_1_current_7          :    1;  /*This bit is used to confirm whether the current state is in entry 7 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable7;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_8       :    1;  /*This bit is used to confirm world before enter entry 8 */
+            uint32_t reg_core_1_from_entry_8       :    4;  /*This filed is used to confirm in which entry before enter entry 8*/
+            uint32_t reg_core_1_current_8          :    1;  /*This bit is used to confirm whether the current state is in entry 8 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable8;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_9       :    1;  /*This bit is used to confirm world before enter entry 9 */
+            uint32_t reg_core_1_from_entry_9       :    4;  /*This filed is used to confirm in which entry before enter entry 9*/
+            uint32_t reg_core_1_current_9          :    1;  /*This bit is used to confirm whether the current state is in entry 9 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable9;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_10      :    1;  /*This bit is used to confirm world before enter entry 10 */
+            uint32_t reg_core_1_from_entry_10      :    4;  /*This filed is used to confirm in which entry before enter entry 10*/
+            uint32_t reg_core_1_current_10         :    1;  /*This bit is used to confirm whether the current state is in entry 10 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable10;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_11      :    1;  /*This bit is used to confirm world before enter entry 11 */
+            uint32_t reg_core_1_from_entry_11      :    4;  /*This filed is used to confirm in which entry before enter entry 11*/
+            uint32_t reg_core_1_current_11         :    1;  /*This bit is used to confirm whether the current state is in entry 11 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable11;
+    union {
+        struct {
+            uint32_t core_1_from_world_12          :    1;  /*This bit is used to confirm world before enter entry 12 */
+            uint32_t core_1_from_entry_12          :    4;  /*This filed is used to confirm in which entry before enter entry 12*/
+            uint32_t core_1_current_12             :    1;  /*This bit is used to confirm whether the current state is in entry 12 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable12;
+    union {
+        struct {
+            uint32_t reg_core_1_from_world_13      :    1;  /*This bit is used to confirm world before enter entry 13 */
+            uint32_t reg_core_1_from_entry_13      :    4;  /*This filed is used to confirm in which entry before enter entry 13*/
+            uint32_t reg_core_1_current_13         :    1;  /*This bit is used to confirm whether the current state is in entry 13 */
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable13;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t reg_core_1_statustable_current:    13;  /*This field is used to quickly read and rewrite the current field of all STATUSTABLE registers.For example*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } wcl_core_1_statustable_current;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    union {
+        struct {
+            uint32_t reg_core_1_message_match      :    1;  /*This bit indicates whether the check is successful*/
+            uint32_t reg_core_1_message_expect     :    4;  /*This field indicates the data to be written next time*/
+            uint32_t reg_core_1_message_dataphase  :    1;  /*If this bit is 1*/
+            uint32_t reg_core_1_message_addressphase:    1;  /*If this bit is 1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } wcl_core_1_message_phase;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t wcl_core_1_world_trigger_addr;
+    union {
+        struct {
+            uint32_t reg_core_1_world_prepare      :    2;  /*This field to used to set world to enter*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_1_world_prepare;
+    uint32_t wcl_core_1_world_update;
+    uint32_t wcl_core_1_world_cancel;
+    union {
+        struct {
+            uint32_t reg_core_1_world_iram0        :    2;  /*this field is used to read current world of Iram0 bus*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_1_world_iram0;
+    union {
+        struct {
+            uint32_t reg_core_1_world_dram0_pif    :    2;  /*this field is used to read current world of Dram0 bus and PIF bus*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } wcl_core_1_world_dram0_pif;
+    union {
+        struct {
+            uint32_t reg_core_1_world_phase        :    1;  /*This bit indicates whether is preparing to switch to WORLD1*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_1_world_phase;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t wcl_core_1_nmi_mask_enable;
+    uint32_t wcl_core_1_nmi_mask_trigger_addr;
+    uint32_t wcl_core_1_nmi_mask_disable;
+    uint32_t wcl_core_1_nmi_mask_cancle;
+    union {
+        struct {
+            uint32_t reg_core_1_nmi_mask           :    1;  /*this bit is used to mask NMI interrupt*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_1_nmi_mask;
+    union {
+        struct {
+            uint32_t reg_core_1_nmi_mask_phase     :    1;  /*this bit is used to indicates whether the NMI interrupt is being masked*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } wcl_core_1_nmi_mask_phase;
+} world_controller_dev_t;
+extern world_controller_dev_t WORLD_CONTROLLER;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_WORLD_CONTROLLER_STRUCT_H_ */