Merge branch 'bugfix/update_config_in_esp32h2_chip' into 'master'

ble: update config in esp32h2 chip

See merge request espressif/esp-idf!22708

components/bt/controller/esp32h2/bt.c

@@ -659,7 +659,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
     // modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
     // esp_phy_modem_init();
     esp_phy_enable();
-    bt_bb_v2_init_cmplx(PHY_ENABLE_VERSION_PRINT);
     s_ble_active = true;
 
     if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {

components/bt/controller/lib_esp32h2/esp32h2-bt-lib

@@ -1 +1 @@
-Subproject commit 048df1c5932ee225cf93ae2def8946cee7ab6399
+Subproject commit 9b2aba2df8f7ca18995a1deeecfcae7575bb9cc9

components/bt/include/esp32h2/include/esp_bt.h

@@ -85,14 +85,17 @@ typedef enum {
     ESP_PWR_LVL_N6  = 6,              /*!< Corresponding to  -6dbm */
     ESP_PWR_LVL_N3  = 7,              /*!< Corresponding to  -3dbm */
     ESP_PWR_LVL_N0  = 8,              /*!< Corresponding to   0dbm */
-    ESP_PWR_LVL_P3  = 9,             /*!< Corresponding to  +3dbm */
+    ESP_PWR_LVL_P3  = 9,              /*!< Corresponding to  +3dbm */
     ESP_PWR_LVL_P6  = 10,             /*!< Corresponding to  +6dbm */
     ESP_PWR_LVL_P9  = 11,             /*!< Corresponding to  +9dbm */
     ESP_PWR_LVL_P12 = 12,             /*!< Corresponding to  +12dbm */
     ESP_PWR_LVL_P15 = 13,             /*!< Corresponding to  +15dbm */
-    ESP_PWR_LVL_P18 = 14,             /*!< Corresponding to  +18dbm */
-    ESP_PWR_LVL_P21 = 15,              /*!< Corresponding to  +21dbm */
-    ESP_PWR_LVL_INVALID = 0xFF,         /*!< Indicates an invalid value */
+    ESP_PWR_LVL_P16 = 14,             /*!< Corresponding to  +16dbm */
+    ESP_PWR_LVL_P17 = 15,             /*!< Corresponding to  +17dbm */
+    ESP_PWR_LVL_P18 = 16,             /*!< Corresponding to  +18dbm */
+    ESP_PWR_LVL_P19 = 17,             /*!< Corresponding to  +19dbm */
+    ESP_PWR_LVL_P20 = 18,             /*!< Corresponding to  +20dbm */
+    ESP_PWR_LVL_INVALID = 0xFF,       /*!< Indicates an invalid value */
 } esp_power_level_t;
 
 typedef enum {
@@ -145,7 +148,7 @@ esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type
  */
 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
 
-#define CONFIG_VERSION  0x20221220
+#define CONFIG_VERSION  0x20230113
 #define CONFIG_MAGIC    0x5A5AA5A5
 
 /**
@@ -203,9 +206,9 @@ typedef struct {
     uint8_t cca_drop_mode;
     int8_t cca_low_tx_pwr;
     uint8_t main_xtal_freq;
-    uint8_t version_num;
     uint8_t cpu_freq_mhz;
     uint8_t ignore_wl_for_direct_adv;
+    uint8_t enable_pcl;
     uint32_t config_magic;
 } esp_bt_controller_config_t;
 
@@ -257,9 +260,9 @@ typedef struct {
     .dis_scan_backoff           = NIMBLE_DISABLE_SCAN_BACKOFF,                          \
     .ble_scan_classify_filter_enable         = 0,                                       \
     .main_xtal_freq             = CONFIG_XTAL_FREQ,                                     \
-    .version_num                = 0,                                                    \
     .cpu_freq_mhz               = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,                      \
     .ignore_wl_for_direct_adv   = 0,                                                    \
+    .enable_pcl                 = 0,                                                    \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
 

components/bt/include/esp32h2/include/esp_bt_cfg.h

@@ -196,7 +196,7 @@ extern "C" {
 
 #define BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N     (3000)
 
-#define RTC_FREQ_N                          (160000) /* in Hz */
+#define RTC_FREQ_N                          (32768) /* in Hz */
 
 #define BLE_LL_TX_PWR_DBM_N                 (9)