i2s: correct soc info

1. remove non-exist I2S instance
2. update soc_caps.h, i2s_ll.h

components/hal/esp32/include/hal/i2s_ll.h

@@ -35,19 +35,54 @@ extern "C" {
 
 #define I2S_LL_AD_BCK_FACTOR           (2)
 #define I2S_LL_PDM_BCK_FACTOR          (64)
-#define I2S_LL_BASE_CLK                (2*APB_CLK_FREQ)
+#define I2S_LL_BASE_CLK                (2 * APB_CLK_FREQ)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (6)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
 
+#define I2S_LL_EVENT_TX_EOF       (1 << 12)
+#define I2S_LL_BCK_MAX_PRESCALE   (64)
+
 /* I2S clock configuration structure */
 typedef struct {
     uint16_t mclk_div; // I2S module clock devider, Fmclk = Fsclk /(mclk_div+b/a)
     uint16_t a;
     uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
-    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
 } i2s_ll_clk_cal_t;
 
+/**
+ * @brief Enable DMA descriptor owner check
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to enable owner check
+ */
+static inline void i2s_ll_dma_enable_owner_check(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.check_owner = en;
+}
+
+/**
+ * @brief Enable DMA descriptor write back
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to enable write back
+ */
+static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.out_auto_wrback = en;
+}
+
+/**
+ * @brief I2S DMA generate EOF event on data in FIFO poped out
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en True to enable, False to disable
+ */
+static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.out_eof_mode = en;
+}
+
 /**
  * @brief I2S module general init, enable I2S clock.
  *
@@ -218,6 +253,17 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->clkm_conf.clka_en = (src == I2S_CLK_APLL) ? 1 : 0;
 }
 
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.tx_bck_div_num = val;
+}
+
 /**
  * @brief Configure I2S TX clock devider
  *
@@ -229,7 +275,17 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
     hw->clkm_conf.clkm_div_num = set->mclk_div;
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
-    hw->sample_rate_conf.tx_bck_div_num = set->bck_div;
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.rx_bck_div_num = val;
 }
 
 /**
@@ -243,7 +299,22 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
     hw->clkm_conf.clkm_div_num = set->mclk_div;
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
-    hw->sample_rate_conf.rx_bck_div_num = set->bck_div;
+}
+
+/**
+ * @brief Enable interrupt by mask
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mask Interrupt event mask
+ * @param en true to enable, false to disable
+ */
+static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
+{
+    if (en) {
+        hw->int_ena.val |= mask;
+    } else {
+        hw->int_ena.val &= ~mask;
+    }
 }
 
 /**
@@ -290,6 +361,17 @@ static inline void i2s_ll_rx_disable_intr(i2s_dev_t *hw)
     hw->int_ena.in_dscr_err = 0;
 }
 
+/**
+ * @brief Get interrupt status register address
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return interrupt status register address
+ */
+static inline volatile void *i2s_ll_get_intr_status_reg(i2s_dev_t *hw)
+{
+    return &hw->int_st;
+}
+
 /**
  * @brief Get I2S interrupt status
  *
@@ -335,6 +417,27 @@ static inline void i2s_ll_rx_reset_dma(i2s_dev_t *hw)
     hw->lc_conf.in_rst = 0;
 }
 
+/**
+ * @brief Start out link
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_start_out_link(i2s_dev_t *hw)
+{
+    hw->out_link.start = 1;
+}
+
+/**
+ * @brief Set I2S out link address
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set out link address
+ */
+static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val)
+{
+    hw->out_link.addr = val;
+}
+
 /**
  * @brief Start TX module
  *
@@ -363,8 +466,8 @@ static inline void i2s_ll_rx_start(i2s_dev_t *hw)
  */
 static inline void i2s_ll_tx_start_link(i2s_dev_t *hw, uint32_t link_addr)
 {
-    hw->out_link.addr = link_addr;
-    hw->out_link.start = 1;
+    i2s_ll_set_out_link_addr(hw, link_addr);
+    i2s_ll_start_out_link(hw);
 }
 
 /**
@@ -453,6 +556,17 @@ static inline void i2s_ll_rx_set_eof_num(i2s_dev_t *hw, int eof_num)
     hw->rx_eof_num = eof_num / 4;
 }
 
+/**
+ * @brief Set I2S tx bits mod
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bits mod
+ */
+static inline void i2s_ll_tx_set_bits_mod(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.tx_bits_mod = val;
+}
+
 /**
  * @brief Congfigure TX chan bit and audio data bit, on ESP32, sample_bit should equals to data_bit
  *
@@ -479,6 +593,28 @@ static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int
     hw->sample_rate_conf.rx_bits_mod = data_bit;
 }
 
+/**
+ * @brief Set whether to continue I2S signal on bus when TX FIFO is empty
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to stop when tx fifo is empty
+ */
+static inline void i2s_ll_tx_stop_on_fifo_empty(i2s_dev_t *hw, bool en)
+{
+    hw->conf1.tx_stop_en = en;
+}
+
+/**
+ * @brief Set whether to bypass the internal PCM module
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param bypass whether to bypass the PCM module
+ */
+static inline void i2s_ll_tx_bypass_pcm(i2s_dev_t *hw, bool bypass)
+{
+    hw->conf1.tx_pcm_bypass = bypass;
+}
+
 /**
  * @brief Enable I2S DMA
  *
@@ -534,6 +670,17 @@ static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enab
     hw->conf.rx_msb_shift = msb_shift_enable;
 }
 
+/**
+ * @brief Set I2S tx chan mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx chan mode
+ */
+static inline void i2s_ll_tx_set_chan_mod(i2s_dev_t *hw, uint32_t val)
+{
+    hw->conf_chan.tx_chan_mod = val;
+}
+
 /**
  * @brief Enable TX mono mode
  *

components/hal/esp32c3/include/hal/i2s_ll.h

@@ -42,7 +42,6 @@ typedef struct {
     uint16_t mclk_div; // I2S module clock devider, Fmclk = Fsclk /(mclk_div+b/a)
     uint16_t a;
     uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
-    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
 } i2s_ll_clk_cal_t;
 
 /**
@@ -183,6 +182,17 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->rx_clkm_conf.rx_clk_sel = 2;
 }
 
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->tx_conf1.tx_bck_div_num = val - 1;
+}
+
 /**
  * @brief Configure I2S TX clock devider
  *
@@ -209,7 +219,17 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
-    hw->tx_conf1.tx_bck_div_num = set->bck_div - 1;
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->rx_conf1.rx_bck_div_num = val - 1;
 }
 
 /**
@@ -238,7 +258,6 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
-    hw->rx_conf1.rx_bck_div_num = set->bck_div - 1;
 }
 
 /**

components/hal/esp32h2/include/hal/i2s_ll.h

@@ -43,7 +43,6 @@ typedef struct {
     uint16_t mclk_div; // I2S module clock devider, Fmclk = Fsclk /(mclk_div+b/a)
     uint16_t a;
     uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
-    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
 } i2s_ll_clk_cal_t;
 
 /**
@@ -184,6 +183,17 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->rx_clkm_conf.rx_clk_sel = 2;
 }
 
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->tx_conf1.tx_bck_div_num = val - 1;
+}
+
 /**
  * @brief Configure I2S TX clock devider
  *
@@ -210,7 +220,17 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
-    hw->tx_conf1.tx_bck_div_num = set->bck_div - 1;
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->rx_conf1.rx_bck_div_num = val - 1;
 }
 
 /**
@@ -239,7 +259,6 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
-    hw->rx_conf1.rx_bck_div_num = set->bck_div - 1;
 }
 
 /**

components/hal/esp32s2/include/hal/clk_gate_ll.h

@@ -43,8 +43,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return DPORT_I2C_EXT1_CLK_EN;
     case PERIPH_I2S0_MODULE:
         return DPORT_I2S0_CLK_EN;
-    case PERIPH_I2S1_MODULE:
-        return DPORT_I2S1_CLK_EN;
     case PERIPH_TIMG0_MODULE:
         return DPORT_TIMERGROUP_CLK_EN;
     case PERIPH_TIMG1_MODULE:
@@ -115,8 +113,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return DPORT_I2C_EXT1_RST;
     case PERIPH_I2S0_MODULE:
         return DPORT_I2S0_RST;
-    case PERIPH_I2S1_MODULE:
-        return DPORT_I2S1_RST;
     case PERIPH_TIMG0_MODULE:
         return DPORT_TIMERGROUP_RST;
     case PERIPH_TIMG1_MODULE:

components/hal/esp32s2/include/hal/i2s_ll.h

@@ -33,7 +33,7 @@ extern "C" {
 // Get I2S hardware instance with giving i2s num
 #define I2S_LL_GET_HW(num)             (((num) == 0) ? (&I2S0) : NULL)
 
-#define I2S_LL_BASE_CLK                (2*APB_CLK_FREQ)
+#define I2S_LL_BASE_CLK                (2 * APB_CLK_FREQ)
 
 #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH  (6)
 #define I2S_LL_MCLK_DIVIDER_MAX        ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
@@ -43,9 +43,44 @@ typedef struct {
     uint16_t mclk_div; // I2S module clock devider, Fmclk = Fsclk /(mclk_div+b/a)
     uint16_t a;
     uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
-    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
 } i2s_ll_clk_cal_t;
 
+#define I2S_LL_EVENT_TX_EOF      (1 << 12)
+#define I2S_LL_BCK_MAX_PRESCALE  (64)
+
+/**
+ * @brief Enable DMA descriptor owner check
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to enable owner check
+ */
+static inline void i2s_ll_dma_enable_owner_check(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.check_owner = en;
+}
+
+/**
+ * @brief Enable DMA descriptor write back
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to enable write back
+ */
+static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.out_auto_wrback = en;
+}
+
+/**
+ * @brief I2S DMA generate EOF event on data in FIFO poped out
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en True to enable, False to disable
+ */
+static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
+{
+    hw->lc_conf.out_eof_mode = en;
+}
+
 /**
  * @brief I2S module general init, enable I2S clock.
  *
@@ -214,6 +249,17 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->clkm_conf.clk_sel = (src == I2S_CLK_APLL) ? 1 : 2;
 }
 
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.tx_bck_div_num = val;
+}
+
 /**
  * @brief Configure I2S TX clock devider
  *
@@ -225,7 +271,17 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
     hw->clkm_conf.clkm_div_num = set->mclk_div;
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
-    hw->sample_rate_conf.tx_bck_div_num = set->bck_div;
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.rx_bck_div_num = val;
 }
 
 /**
@@ -239,7 +295,22 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
     hw->clkm_conf.clkm_div_num = set->mclk_div;
     hw->clkm_conf.clkm_div_b = set->b;
     hw->clkm_conf.clkm_div_a = set->a;
-    hw->sample_rate_conf.rx_bck_div_num = set->bck_div;
+}
+
+/**
+ * @brief Enable interrupt by mask
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mask Interrupt event mask
+ * @param en true to enable, false to disable
+ */
+static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
+{
+    if (en) {
+        hw->int_ena.val |= mask;
+    } else {
+        hw->int_ena.val &= ~mask;
+    }
 }
 
 /**
@@ -286,6 +357,17 @@ static inline void i2s_ll_rx_disable_intr(i2s_dev_t *hw)
     hw->int_ena.in_dscr_err = 0;
 }
 
+/**
+ * @brief Get interrupt status register address
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return interrupt status register address
+ */
+static inline volatile void *i2s_ll_get_intr_status_reg(i2s_dev_t *hw)
+{
+    return &hw->int_st;
+}
+
 /**
  * @brief Get I2S interrupt status
  *
@@ -357,6 +439,27 @@ static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
     // Remain empty
 }
 
+/**
+ * @brief Start out link
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_start_out_link(i2s_dev_t *hw)
+{
+    hw->out_link.start = 1;
+}
+
+/**
+ * @brief Set I2S out link address
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set out link address
+ */
+static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val)
+{
+    hw->out_link.addr = val;
+}
+
 /**
  * @brief Start TX module
  *
@@ -385,8 +488,8 @@ static inline void i2s_ll_rx_start(i2s_dev_t *hw)
  */
 static inline void i2s_ll_tx_start_link(i2s_dev_t *hw, uint32_t link_addr)
 {
-    hw->out_link.addr = link_addr;
-    hw->out_link.start = 1;
+    i2s_ll_set_out_link_addr(hw, link_addr);
+    i2s_ll_start_out_link(hw);
 }
 
 /**
@@ -643,6 +746,39 @@ static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enab
     hw->conf.rx_msb_shift = msb_shift_enable;
 }
 
+/**
+ * @brief Set I2S tx chan mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx chan mode
+ */
+static inline void i2s_ll_tx_set_chan_mod(i2s_dev_t *hw, uint32_t val)
+{
+    hw->conf_chan.tx_chan_mod = val;
+}
+
+/**
+ * @brief Set I2S tx bits mod
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bits mod
+ */
+static inline void i2s_ll_tx_set_bits_mod(i2s_dev_t *hw, uint32_t val)
+{
+    hw->sample_rate_conf.tx_bits_mod = val;
+}
+
+/**
+ * @brief Set I2S tx dma equal
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx dma equal
+ */
+static inline void i2s_ll_tx_enable_dma_equal(i2s_dev_t *hw, bool en)
+{
+    hw->conf.tx_dma_equal = en;
+}
+
 /**
  * @brief Enable TX mono mode
  *
@@ -682,6 +818,39 @@ static inline void i2s_ll_enable_loop_back(i2s_dev_t *hw, bool loopback_en)
     hw->conf.sig_loopback = loopback_en;
 }
 
+/**
+ * @brief Enable I2S LCD mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param enable Set true to enable LCD mode.
+ */
+static inline void i2s_ll_enable_lcd(i2s_dev_t *hw, bool enable)
+{
+    hw->conf2.lcd_en = enable;
+}
+
+/**
+ * @brief Set whether to continue I2S signal on bus when TX FIFO is empty
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param en whether to stop when tx fifo is empty
+ */
+static inline void i2s_ll_tx_stop_on_fifo_empty(i2s_dev_t *hw, bool en)
+{
+    hw->conf1.tx_stop_en = en;
+}
+
+/**
+ * @brief Set whether to bypass the internal PCM module
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param bypass whether to bypass the PCM module
+ */
+static inline void i2s_ll_tx_bypass_pcm(i2s_dev_t *hw, bool bypass)
+{
+    hw->conf1.tx_pcm_bypass = bypass;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/i2s_ll.h

@@ -43,7 +43,6 @@ typedef struct {
     uint16_t mclk_div; // I2S module clock devider, Fmclk = Fsclk /(mclk_div+b/a)
     uint16_t a;
     uint16_t b;        // The decimal part of module clock devider, the decimal is: b/a
-    uint16_t bck_div;  // The BCK devider, Fbck = Fmclk / bck_div
 } i2s_ll_clk_cal_t;
 
 /**
@@ -186,6 +185,17 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->rx_clkm_conf.rx_clk_sel = 2;
 }
 
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->tx_conf1.tx_bck_div_num = val - 1;
+}
+
 /**
  * @brief Configure I2S TX clock devider
  *
@@ -212,7 +222,17 @@ static inline void i2s_ll_tx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->tx_clkm_conf.tx_clkm_div_num = set->mclk_div;
-    hw->tx_conf1.tx_bck_div_num = set->bck_div - 1;
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->rx_conf1.rx_bck_div_num = val - 1;
 }
 
 /**
@@ -241,7 +261,6 @@ static inline void i2s_ll_rx_set_clk(i2s_dev_t *hw, i2s_ll_clk_cal_t *set)
         }
     }
     hw->rx_clkm_conf.rx_clkm_div_num = set->mclk_div;
-    hw->rx_conf1.rx_bck_div_num = set->bck_div - 1;
 }
 
 /**

components/hal/i2s_hal.c

@@ -37,7 +37,6 @@ static void i2s_hal_clk_cal(uint32_t fsclk, uint32_t fbck, int bck_div, i2s_ll_c
     int mb = 0;
     uint32_t mclk = fbck * bck_div;
     cal->mclk_div = fsclk / mclk;
-    cal->bck_div = bck_div;
     cal->a = 1;
     cal->b = 0;
     uint32_t freq_diff = fsclk - mclk * cal->mclk_div;
@@ -74,6 +73,7 @@ void i2s_hal_tx_clock_config(i2s_hal_context_t *hal, uint32_t sclk, uint32_t fbc
     i2s_ll_clk_cal_t clk_set = {0};
     i2s_hal_clk_cal(sclk, fbck, factor, &clk_set);
     i2s_ll_tx_set_clk(hal->dev, &clk_set);
+    i2s_ll_tx_set_bck_div_num(hal->dev, factor);
 }
 
 void i2s_hal_rx_clock_config(i2s_hal_context_t *hal, uint32_t sclk, uint32_t fbck, int factor)
@@ -81,6 +81,7 @@ void i2s_hal_rx_clock_config(i2s_hal_context_t *hal, uint32_t sclk, uint32_t fbc
     i2s_ll_clk_cal_t clk_set = {0};
     i2s_hal_clk_cal(sclk, fbck, factor, &clk_set);
     i2s_ll_rx_set_clk(hal->dev, &clk_set);
+    i2s_ll_rx_set_bck_div_num(hal->dev, factor);
 }
 
 void i2s_hal_enable_master_fd_mode(i2s_hal_context_t *hal)

components/soc/esp32/include/soc/soc_caps.h

@@ -68,7 +68,6 @@
 #define SOC_SDIO_SLAVE_SUPPORTED    1
 #define SOC_TWAI_SUPPORTED          1
 #define SOC_EMAC_SUPPORTED          1
-#define SOC_RISCV_COPROC_SUPPORTED  0   //TODO: correct the caller and remove this line
 #define SOC_CPU_CORES_NUM           2
 #define SOC_ULP_SUPPORTED           1
 #define SOC_RTC_SLOW_MEM_SUPPORTED  1
@@ -144,6 +143,14 @@
 #define SOC_I2S_APLL_MIN_FREQ       (250000000)
 #define SOC_I2S_APLL_MAX_FREQ       (500000000)
 #define SOC_I2S_APLL_MIN_RATE       (10675) //in Hz, I2S Clock rate limited by hardware
+#define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word
+#define SOC_I2S_LCD_I80_VARIANT       (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing
+
+/*-------------------------- LCD CAPS ----------------------------------------*/
+/* Notes: On esp32, LCD intel 8080 timing is generated by I2S peripheral */
+#define SOC_LCD_I80_SUPPORTED      (1)  /*!< Intel 8080 LCD is supported */
+#define SOC_LCD_I80_BUSES          (1)  /*!< Only I2S0 has LCD mode */
+#define SOC_LCD_I80_BUS_WIDTH      (24) /*!< Intel 8080 bus width */
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_HS_MODE  (1)

components/soc/esp32h2/include/soc/i2s_caps.h

@@ -1,22 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#define SOC_I2S_APLL_MIN_FREQ                     (250000000)
-#define SOC_I2S_APLL_MAX_FREQ                     (500000000)
-#define SOC_I2S_APLL_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
-#define SOC_I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
-
-#define SOC_I2S_NUM            (1)

components/soc/esp32s2/include/soc/periph_defs.h

@@ -27,7 +27,6 @@ typedef enum {
     PERIPH_I2C0_MODULE,
     PERIPH_I2C1_MODULE,
     PERIPH_I2S0_MODULE,
-    PERIPH_I2S1_MODULE,
     PERIPH_TIMG0_MODULE,
     PERIPH_TIMG1_MODULE,
     PERIPH_UHCI0_MODULE,
@@ -93,8 +92,7 @@ typedef enum {
     ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
     ETS_SPI3_INTR_SOURCE,                       /**< interrupt of SPI3, level*/
     ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
-    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
+    ETS_UART0_INTR_SOURCE = 37,                 /**< interrupt of UART0, level*/
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
     ETS_UART2_INTR_SOURCE,                      /**< interrupt of UART2, level*/
     ETS_SDIO_HOST_INTR_SOURCE,                  /**< interrupt of SD/SDIO/MMC HOST, level*/

components/soc/esp32s2/include/soc/soc_caps.h

@@ -136,11 +136,19 @@
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // ESP32-S2 have 1 I2S
-#define SOC_I2S_NUM            (1)
-#define SOC_I2S_SUPPORTS_APLL  (1)// ESP32-S2 support APLL
-#define SOC_I2S_APLL_MIN_FREQ                     (250000000)
-#define SOC_I2S_APLL_MAX_FREQ                     (500000000)
-#define SOC_I2S_APLL_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
+#define SOC_I2S_NUM                (1)
+#define SOC_I2S_SUPPORTS_APLL      (1)// ESP32-S2 support APLL
+#define SOC_I2S_SUPPORTS_DMA_EQUAL (1)
+#define SOC_I2S_APLL_MIN_FREQ      (250000000)
+#define SOC_I2S_APLL_MAX_FREQ      (500000000)
+#define SOC_I2S_APLL_MIN_RATE      (10675) //in Hz, I2S Clock rate limited by hardware
+#define SOC_I2S_LCD_I80_VARIANT    (1)
+
+/*-------------------------- LCD CAPS ----------------------------------------*/
+/* Notes: On esp32-s2, LCD intel 8080 timing is generated by I2S peripheral */
+#define SOC_LCD_I80_SUPPORTED      (1)  /*!< Intel 8080 LCD is supported */
+#define SOC_LCD_I80_BUSES          (1)  /*!< Only I2S0 has LCD mode */
+#define SOC_LCD_I80_BUS_WIDTH      (24) /*!< Intel 8080 bus width */
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)