Merge branch 'bugfix/fix_bootloader_time_too_long_bug_v4.3' into 'release/v4.3'

esp32s2/esp32c3: decrease boot up and cpu start up time (backport v4.3)

See merge request espressif/esp-idf!12728

components/esp_hw_support/port/esp32c3/rtc_clk.c

@@ -121,27 +121,6 @@ bool rtc_clk_8md256_enabled(void)
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
 
-void rtc_clk_set_xtal_wait(void)
-{
-    /*
-     the `xtal_wait` time need 1ms, so we need calibrate slow clk period,
-     and `RTC_CNTL_XTL_BUF_WAIT` depend on it.
-    */
-    rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
-    rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
-    if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) {
-        cal_clk = RTC_CAL_32K_XTAL;
-    } else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) {
-        cal_clk  = RTC_CAL_8MD256;
-    }
-    uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000);
-    uint32_t xtal_wait_1ms = 100;
-    if (slow_clk_period) {
-        xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period;
-    }
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
-}
-
 static void wait_dig_dbias_valid(uint64_t rtc_cycles)
 {
     rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
@@ -168,7 +147,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
     so if the slow_clk is 8md256, clk_8m must be force power on
     */
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
-    rtc_clk_set_xtal_wait();
     esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
 }
 

components/esp_hw_support/port/esp32c3/rtc_init.c

@@ -38,7 +38,6 @@ void rtc_init(rtc_config_t cfg)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
 
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
-    rtc_clk_set_xtal_wait();
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
     REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);

components/esp_hw_support/port/esp32s2/rtc_clk.c

@@ -152,29 +152,6 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
     }
 }
 
-void rtc_clk_set_xtal_wait(void)
-{
-    /*
-     the `xtal_wait` time need 1ms, so we need calibrate slow clk period,
-     and `RTC_CNTL_XTL_BUF_WAIT` depend on it.
-    */
-    rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
-    rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
-    rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
-    rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
-    if (slow_clk_freq == (rtc_slow_freq_x32k)) {
-        cal_clk = RTC_CAL_32K_XTAL;
-    } else if (slow_clk_freq == rtc_slow_freq_8MD256) {
-        cal_clk  = RTC_CAL_8MD256;
-    }
-    uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000);
-    uint32_t xtal_wait_1ms = 100;
-    if (slow_clk_period) {
-        xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period;
-    }
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
-}
-
 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
 {
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
@@ -189,7 +166,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
     so if the slow_clk is 8md256, clk_8m must be force power on
     */
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
-    rtc_clk_set_xtal_wait();
     esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
 }
 

components/esp_hw_support/port/esp32s2/rtc_init.c

@@ -34,7 +34,6 @@ static void calibrate_ocode(void);
 void rtc_init(rtc_config_t cfg)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
-    rtc_clk_set_xtal_wait();
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
 

components/esp_hw_support/port/esp32s3/rtc_clk.c

@@ -126,29 +126,6 @@ bool rtc_clk_8md256_enabled(void)
     return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
 }
 
-void rtc_clk_set_xtal_wait(void)
-{
-    /*
-     the `xtal_wait` time need 1ms, so we need calibrate slow clk period,
-     and `RTC_CNTL_XTL_BUF_WAIT` depend on it.
-    */
-    rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
-    rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
-    rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
-    rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
-    if (slow_clk_freq == (rtc_slow_freq_x32k)) {
-        cal_clk = RTC_CAL_32K_XTAL;
-    } else if (slow_clk_freq == rtc_slow_freq_8MD256) {
-        cal_clk  = RTC_CAL_8MD256;
-    }
-    uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000);
-    uint32_t xtal_wait_1ms = 100;
-    if (slow_clk_period) {
-        xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period;
-    }
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
-}
-
 static void wait_dig_dbias_valid(uint64_t rtc_cycles)
 {
     rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
@@ -175,7 +152,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
     so if the slow_clk is 8md256, clk_8m must be force power on
     */
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
-    rtc_clk_set_xtal_wait();
     esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
 }
 

components/esp_hw_support/port/esp32s3/rtc_init.c

@@ -34,7 +34,6 @@ void rtc_init(rtc_config_t cfg)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
-    rtc_clk_set_xtal_wait();
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
 

components/soc/esp32c3/include/soc/rtc.h

@@ -376,11 +376,6 @@ bool rtc_clk_8md256_enabled(void);
  */
 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
 
-/**
- * @brief Set XTAL wait cycles by RTC slow clock's period
- */
-void rtc_clk_set_xtal_wait(void);
-
 /**
  * @brief Select source for RTC_SLOW_CLK
  * @param slow_freq clock source (one of rtc_slow_freq_t values)

components/soc/esp32s2/include/soc/rtc.h

@@ -406,11 +406,6 @@ bool rtc_clk_8md256_enabled(void);
  */
 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
 
-/**
- * @brief Set XTAL wait cycles by RTC slow clock's period
- */
-void rtc_clk_set_xtal_wait(void);
-
 /**
  * @brief Select source for RTC_SLOW_CLK
  * @param slow_freq clock source (one of rtc_slow_freq_t values)

components/soc/esp32s3/include/soc/rtc.h

@@ -376,11 +376,6 @@ bool rtc_clk_8md256_enabled(void);
  */
 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
 
-/**
- * @brief Set XTAL wait cycles by RTC slow clock's period
- */
-void rtc_clk_set_xtal_wait(void);
-
 /**
  * @brief Select source for RTC_SLOW_CLK
  * @param slow_freq clock source (one of rtc_slow_freq_t values)