Merge branch 'feature/support_efuse_for_esp32h2' into 'master'

efuse: Add support for esp32h2

Closes IDF-6252, IDF-4337, and IDF-6897

See merge request espressif/esp-idf!22393

.gitlab/ci/host-test.yml

@@ -203,7 +203,7 @@ test_idf_tools:
   script:
     - cd ${IDF_PATH}/components/efuse/
     - ./efuse_table_gen.py -t "${IDF_TARGET}" ${IDF_PATH}/components/efuse/${IDF_TARGET}/esp_efuse_table.csv
-    - git diff --exit-code -- ${IDF_TARGET}/esp_efuse_table.c || { echo 'Differences found for ${IDF_TARGET} target. Please run make efuse_common_table or idf.py efuse-common-table and commit the changes.'; exit 1; }
+    - git diff --exit-code -- ${IDF_TARGET}/esp_efuse_table.c || { echo 'Differences found for ${IDF_TARGET} target. Please run idf.py efuse-common-table and commit the changes.'; exit 1; }
     - cd ${IDF_PATH}/components/efuse/test_efuse_host
     - ./efuse_tests.py
 
@@ -225,6 +225,11 @@ test_efuse_table_on_host_esp32c3:
   variables:
     IDF_TARGET: esp32c3
 
+test_efuse_table_on_host_esp32h2:
+  extends: .test_efuse_table_on_host_template
+  variables:
+    IDF_TARGET: esp32h2
+
 test_efuse_table_on_host_esp32h4:
   extends: .test_efuse_table_on_host_template
   variables:

components/bootloader/Kconfig.projbuild

@@ -932,7 +932,7 @@ menu "Security features"
 
         config SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
             bool "Leave UART bootloader flash cache enabled"
-            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
+            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE) # NOERROR
             default N
             help
                 If not set (default), the bootloader will permanently disable UART bootloader flash cache access on

components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,13 +23,6 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
     ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
 #endif
 
-#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
-    ESP_LOGI(TAG, "Disable UART bootloader cache...");
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-#else
-    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
-#endif
-
 #ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
     ESP_LOGI(TAG, "Disable JTAG...");
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);

components/bootloader_support/src/flash_encrypt.c

@@ -134,18 +134,15 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
             if ( dis_dl_cache && dis_dl_enc && dis_dl_dec ) {
                 mode = ESP_FLASH_ENC_MODE_RELEASE;
             }
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-            bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
-            bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-            bool dis_dl_dcache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
-
-            if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
-                mode = ESP_FLASH_ENC_MODE_RELEASE;
-            }
-#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6
-            bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
-            bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
-            if (dis_dl_enc && dis_dl_icache) {
+#else
+            if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT)
+#if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+                && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE)
+#endif
+#if SOC_EFUSE_DIS_DOWNLOAD_DCACHE
+                && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE)
+#endif
+                ) {
                 mode = ESP_FLASH_ENC_MODE_RELEASE;
 #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
                 // This chip supports two types of key: AES128_DERIVED and AES128.
@@ -154,7 +151,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
                 mode = (xts_key_len_256_wr_dis) ? ESP_FLASH_ENC_MODE_RELEASE : ESP_FLASH_ENC_MODE_DEVELOPMENT;
 #endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
             }
-#endif
+#endif // !CONFIG_IDF_TARGET_ESP32
         }
     } else {
         mode = ESP_FLASH_ENC_MODE_DISABLED;
@@ -187,23 +184,21 @@ void esp_flash_encryption_set_release_mode(void)
     esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_CACHE);
     esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_ENCRYPT);
     esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT);
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#else
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
+#endif
+#if SOC_EFUSE_DIS_DOWNLOAD_DCACHE
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
-#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
+#endif
 #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
     // For AES128_DERIVED, FE key is 16 bytes and XTS_KEY_LENGTH_256 is 0.
     // It is important to protect XTS_KEY_LENGTH_256 from further changing it to 1. Set write protection for this bit.
     // Burning WR_DIS_CRYPT_CNT, blocks further changing of eFuses: DIS_DOWNLOAD_MANUAL_ENCRYPT, SPI_BOOT_CRYPT_CNT, [XTS_KEY_LENGTH_256], SECURE_BOOT_EN.
     esp_efuse_write_field_bit(WR_DIS_CRYPT_CNT);
 #endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
-#else
-    ESP_LOGE(TAG, "Flash Encryption support not added, abort..");
-    abort();
-#endif
+#endif // !CONFIG_IDF_TARGET_ESP32
 
 #if CONFIG_SOC_SUPPORTS_SECURE_DL_MODE
     esp_efuse_enable_rom_secure_download_mode();
@@ -325,11 +320,13 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
     }
 #endif
 
+#if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
     result &= secure;
     if (!secure) {
         ESP_LOGW(TAG, "Not disabled UART bootloader cache (set DIS_DOWNLOAD_ICACHE->1)");
     }
+#endif
 
 #if SOC_EFUSE_DIS_PAD_JTAG
     secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_PAD_JTAG);

components/efuse/efuse_table_gen.py

@@ -261,7 +261,11 @@ class FuseTable(list):
         last_field_name = ''
         for p in self:
             if (p.field_name != last_field_name):
-                rows += ['extern const esp_efuse_desc_t* ' + 'ESP_EFUSE_' + p.field_name.replace('.', '_') + '[];']
+                name = 'ESP_EFUSE_' + p.field_name.replace('.', '_')
+                rows += ['extern const esp_efuse_desc_t* ' + name + '[];']
+                for alt_name in p.get_alt_names():
+                    alt_name = 'ESP_EFUSE_' + alt_name.replace('.', '_')
+                    rows += ['#define ' + alt_name + ' ' + name]
                 last_field_name = p.field_name
 
         rows += ['',
@@ -434,6 +438,12 @@ class FuseDefinition(object):
                          str(self.bit_start),
                          str(self.get_bit_count()) + '}, \t // ' + self.comment])
 
+    def get_alt_names(self):
+        result = re.search(r'\[(.*?)\]', self.comment)
+        if result:
+            return result.group(1).split()
+        return []
+
 
 def process_input_file(file, type_table):
     status('Parsing efuse CSV input file ' + file.name + ' ...')
@@ -488,7 +498,7 @@ def main():
 
     parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
     parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
-                        'esp32h4', 'esp32c2', 'esp32c6'], default='esp32')
+                        'esp32h4', 'esp32c2', 'esp32c6', 'esp32h2'], default='esp32')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
     parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')

components/efuse/esp32h2/esp_efuse_table.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,1115 +9,1246 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-#include "esp_efuse.h"
-
-// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
+// md5_digest_table 910e196e9c9c5c052f1c57710fe3977c
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
 // To show efuse_table run the command 'show_efuse_table'.
 
 static const esp_efuse_desc_t WR_DIS[] = {
-    {EFUSE_BLK0, 0, 32}, 	 // Write protection,
+    {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
 };
 
 static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
-    {EFUSE_BLK0, 0, 1}, 	 // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
+    {EFUSE_BLK0, 0, 1}, 	 // [] wr_dis of RD_DIS,
 };
 
-static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = {
-    {EFUSE_BLK0, 1, 1}, 	 // Write protection for SWAP_UART_SDIO_EN,
+static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_ICACHE,
 };
 
-static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
-    {EFUSE_BLK0, 2, 1}, 	 // Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
+static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_USB_JTAG,
 };
 
-static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
-    {EFUSE_BLK0, 3, 1}, 	 // Write protection for WDT_DELAY_SEL,
+static const esp_efuse_desc_t WR_DIS_POWERGLITCH_EN[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of POWERGLITCH_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_FORCE_DOWNLOAD,
+};
+
+static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI,
+};
+
+static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of JTAG_SEL_ENABLE,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_PAD_JTAG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
+};
+
+static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
+    {EFUSE_BLK0, 3, 1}, 	 // [] wr_dis of WDT_DELAY_SEL,
 };
 
 static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
-    {EFUSE_BLK0, 4, 1}, 	 // Write protection for SPI_BOOT_CRYPT_CNT,
+    {EFUSE_BLK0, 4, 1}, 	 // [] wr_dis of SPI_BOOT_CRYPT_CNT,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
-    {EFUSE_BLK0, 5, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE0,
+    {EFUSE_BLK0, 5, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
-    {EFUSE_BLK0, 6, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE1,
+    {EFUSE_BLK0, 6, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
-    {EFUSE_BLK0, 7, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE2,
+    {EFUSE_BLK0, 7, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
-    {EFUSE_BLK0, 8, 1}, 	 // Write protection for key_purpose. KEY0,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
-    {EFUSE_BLK0, 9, 1}, 	 // Write protection for key_purpose. KEY1,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
-    {EFUSE_BLK0, 10, 1}, 	 // Write protection for key_purpose. KEY2,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
-    {EFUSE_BLK0, 11, 1}, 	 // Write protection for key_purpose. KEY3,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
-    {EFUSE_BLK0, 12, 1}, 	 // Write protection for key_purpose. KEY4,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
-    {EFUSE_BLK0, 13, 1}, 	 // Write protection for key_purpose. KEY5,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
 };
 
 static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
-    {EFUSE_BLK0, 14, 1}, 	 // Write protection for SEC_DPA_LEVEL,
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of SEC_DPA_LEVEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = {
+    {EFUSE_BLK0, 14, 1}, 	 // [] wr_dis of CRYPT_DPA_ENABLE,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
-    {EFUSE_BLK0, 15, 1}, 	 // Write protection for SECURE_BOOT_EN,
+    {EFUSE_BLK0, 15, 1}, 	 // [] wr_dis of SECURE_BOOT_EN,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    {EFUSE_BLK0, 16, 1}, 	 // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
+    {EFUSE_BLK0, 16, 1}, 	 // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
+};
+
+static const esp_efuse_desc_t WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
+    {EFUSE_BLK0, 17, 1}, 	 // [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FLASH_TPUW,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DIRECT_BOOT,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
+};
+
+static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of UART_PRINT_CONTROL,
 };
 
-static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
-    {EFUSE_BLK0, 18, 1}, 	 // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
+static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FORCE_SEND_RESUME,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of SECURE_VERSION,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
-    {EFUSE_BLK0, 19, 1}, 	 // Write protection for SECURE_BOOT_DISABLE_FAST_WAKE,
+    {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
+};
+
+static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD0[] = {
+    {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of HYS_EN_PAD0,
+};
+
+static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD1[] = {
+    {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of HYS_EN_PAD1,
 };
 
 static const esp_efuse_desc_t WR_DIS_BLK1[] = {
-    {EFUSE_BLK0, 20, 1}, 	 // Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS,
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLOCK1,
+};
+
+static const esp_efuse_desc_t WR_DIS_MAC[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
+};
+
+static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of MAC_EXT,
+};
+
+static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MINOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MAJOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_CAP,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_TEMP,
+};
+
+static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_VENDOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PKG_VERSION,
 };
 
 static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
-    {EFUSE_BLK0, 21, 1}, 	 // Write protection for EFUSE_BLK2.  SYS_DATA_PART1,
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
 };
 
-static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
-    {EFUSE_BLK0, 22, 1}, 	 // Write protection for EFUSE_BLK3.  USER_DATA,
+static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY0[] = {
-    {EFUSE_BLK0, 23, 1}, 	 // Write protection for EFUSE_BLK4.  KEY0,
+static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLK_VERSION_MINOR,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY1[] = {
-    {EFUSE_BLK0, 24, 1}, 	 // Write protection for EFUSE_BLK5.  KEY1,
+static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLK_VERSION_MAJOR,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY2[] = {
-    {EFUSE_BLK0, 25, 1}, 	 // Write protection for EFUSE_BLK6.  KEY2,
+static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY3[] = {
-    {EFUSE_BLK0, 26, 1}, 	 // Write protection for EFUSE_BLK7.  KEY3,
+static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY4[] = {
-    {EFUSE_BLK0, 27, 1}, 	 // Write protection for EFUSE_BLK8.  KEY4,
+static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY5[] = {
-    {EFUSE_BLK0, 28, 1}, 	 // Write protection for EFUSE_BLK9.  KEY5,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 23, 1}, 	 // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
 };
 
-static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
-    {EFUSE_BLK0, 29, 1}, 	 // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 24, 1}, 	 // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
 };
 
-static const esp_efuse_desc_t RD_DIS[] = {
-    {EFUSE_BLK0, 32, 7}, 	 // Read protection,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 25, 1}, 	 // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY0[] = {
-    {EFUSE_BLK0, 32, 1}, 	 // Read protection for EFUSE_BLK4.  KEY0,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 26, 1}, 	 // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY1[] = {
-    {EFUSE_BLK0, 33, 1}, 	 // Read protection for EFUSE_BLK5.  KEY1,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 27, 1}, 	 // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY2[] = {
-    {EFUSE_BLK0, 34, 1}, 	 // Read protection for EFUSE_BLK6.  KEY2,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 28, 1}, 	 // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY3[] = {
-    {EFUSE_BLK0, 35, 1}, 	 // Read protection for EFUSE_BLK7.  KEY3,
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY4[] = {
-    {EFUSE_BLK0, 36, 1}, 	 // Read protection for EFUSE_BLK8.  KEY4,
+static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 30, 1}, 	 // [] wr_dis of USB_EXCHG_PINS,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY5[] = {
-    {EFUSE_BLK0, 37, 1}, 	 // Read protection for EFUSE_BLK9.  KEY5,
+static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = {
+    {EFUSE_BLK0, 30, 1}, 	 // [] wr_dis of VDD_SPI_AS_GPIO,
 };
 
-static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
-    {EFUSE_BLK0, 38, 1}, 	 // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
+static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
+    {EFUSE_BLK0, 31, 1}, 	 // [] wr_dis of SOFT_DIS_JTAG,
 };
 
-static const esp_efuse_desc_t SWAP_UART_SDIO_EN[] = {
-    {EFUSE_BLK0, 39, 1}, 	 // Swap pad of uart and sdio.,
+static const esp_efuse_desc_t RD_DIS[] = {
+    {EFUSE_BLK0, 32, 7}, 	 // [] Disable reading from BlOCK4-10,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 32, 1}, 	 // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 33, 1}, 	 // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 34, 1}, 	 // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 35, 1}, 	 // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 36, 1}, 	 // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 37, 1}, 	 // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
 };
 
 static const esp_efuse_desc_t DIS_ICACHE[] = {
-    {EFUSE_BLK0, 40, 1}, 	 // Disable Icache,
+    {EFUSE_BLK0, 40, 1}, 	 // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_USB_JTAG[] = {
-    {EFUSE_BLK0, 41, 1}, 	 // Disable USB JTAG,
+    {EFUSE_BLK0, 41, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
-    {EFUSE_BLK0, 42, 1}, 	 // Disable Icache in download mode,
+static const esp_efuse_desc_t POWERGLITCH_EN[] = {
+    {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled,
 };
 
-static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = {
-    {EFUSE_BLK0, 43, 1}, 	 // Disable USB_SERIAL_JTAG,
+static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
-    {EFUSE_BLK0, 44, 1}, 	 // Disable force chip go to download mode function,
+static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 45, 1}, 	 // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_TWAI[] = {
-    {EFUSE_BLK0, 46, 1}, 	 // Disable TWAI function,
+    {EFUSE_BLK0, 46, 1}, 	 // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
-    {EFUSE_BLK0, 47, 1}, 	 // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.,
+    {EFUSE_BLK0, 47, 1}, 	 // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0,
 };
 
 static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
-    {EFUSE_BLK0, 48, 3}, 	 // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.,
+    {EFUSE_BLK0, 48, 3}, 	 // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
 };
 
 static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
-    {EFUSE_BLK0, 51, 1}, 	 // Disable JTAG in the hard way. JTAG is disabled permanently.,
+    {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    {EFUSE_BLK0, 52, 1}, 	 // Disable flash encryption when in download boot modes.,
-};
-
-static const esp_efuse_desc_t USB_DREFH[] = {
-    {EFUSE_BLK0, 53, 2}, 	 // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.,
-};
-
-static const esp_efuse_desc_t USB_DREFL[] = {
-    {EFUSE_BLK0, 55, 2}, 	 // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.,
+    {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
-    {EFUSE_BLK0, 57, 1}, 	 // Exchange D+ D- pins,
+    {EFUSE_BLK0, 57, 1}, 	 // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged,
 };
 
 static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
-    {EFUSE_BLK0, 58, 1}, 	 // Set this bit to vdd spi pin function as gpio,
+    {EFUSE_BLK0, 58, 1}, 	 // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned,
 };
 
 static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
-    {EFUSE_BLK0, 80, 2}, 	 // Select RTC WDT time out threshold,
+    {EFUSE_BLK0, 80, 2}, 	 // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
 };
 
 static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
-    {EFUSE_BLK0, 82, 3}, 	 // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
+    {EFUSE_BLK0, 82, 3}, 	 // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
-    {EFUSE_BLK0, 85, 1}, 	 // Enable revoke first secure boot key,
+    {EFUSE_BLK0, 85, 1}, 	 // [] Revoke 1st secure boot key,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
-    {EFUSE_BLK0, 86, 1}, 	 // Enable revoke second secure boot key,
+    {EFUSE_BLK0, 86, 1}, 	 // [] Revoke 2nd secure boot key,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
-    {EFUSE_BLK0, 87, 1}, 	 // Enable revoke third secure boot key,
+    {EFUSE_BLK0, 87, 1}, 	 // [] Revoke 3rd secure boot key,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
-    {EFUSE_BLK0, 88, 4}, 	 // Key0 purpose,
+    {EFUSE_BLK0, 88, 4}, 	 // [KEY0_PURPOSE] Represents the purpose of Key0,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
-    {EFUSE_BLK0, 92, 4}, 	 // Key1 purpose,
+    {EFUSE_BLK0, 92, 4}, 	 // [KEY1_PURPOSE] Represents the purpose of Key1,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
-    {EFUSE_BLK0, 96, 4}, 	 // Key2 purpose,
+    {EFUSE_BLK0, 96, 4}, 	 // [KEY2_PURPOSE] Represents the purpose of Key2,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
-    {EFUSE_BLK0, 100, 4}, 	 // Key3 purpose,
+    {EFUSE_BLK0, 100, 4}, 	 // [KEY3_PURPOSE] Represents the purpose of Key3,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
-    {EFUSE_BLK0, 104, 4}, 	 // Key4 purpose,
+    {EFUSE_BLK0, 104, 4}, 	 // [KEY4_PURPOSE] Represents the purpose of Key4,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
-    {EFUSE_BLK0, 108, 4}, 	 // Key5 purpose,
+    {EFUSE_BLK0, 108, 4}, 	 // [KEY5_PURPOSE] Represents the purpose of Key5,
 };
 
 static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
-    {EFUSE_BLK0, 112, 2}, 	 // Configures the clock random divide mode to determine the spa secure level,
+    {EFUSE_BLK0, 112, 2}, 	 // [] Represents the spa secure level by configuring the clock random divide mode,
+};
+
+static const esp_efuse_desc_t ECDSA_FORCE_USE_HARDWARE_K[] = {
+    {EFUSE_BLK0, 114, 1}, 	 // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used,
+};
+
+static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
+    {EFUSE_BLK0, 115, 1}, 	 // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
-    {EFUSE_BLK0, 116, 1}, 	 // Secure boot enable,
+    {EFUSE_BLK0, 116, 1}, 	 // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    {EFUSE_BLK0, 117, 1}, 	 // Enable aggressive secure boot revoke,
+    {EFUSE_BLK0, 117, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t FLASH_TPUW[] = {
-    {EFUSE_BLK0, 124, 4}, 	 // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
+    {EFUSE_BLK0, 124, 4}, 	 // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 128, 1}, 	 // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
+    {EFUSE_BLK0, 128, 1}, 	 // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
-    {EFUSE_BLK0, 129, 1}, 	 // Disable direct boot mode,
+    {EFUSE_BLK0, 129, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t DIS_USB_PRINT[] = {
-    {EFUSE_BLK0, 130, 1}, 	 // Disable USB Print,
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    {EFUSE_BLK0, 130, 1}, 	 // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot,
 };
 
-static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 132, 1}, 	 // Disable download through USB,
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 132, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
-    {EFUSE_BLK0, 133, 1}, 	 // Enable security download mode,
+    {EFUSE_BLK0, 133, 1}, 	 // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
-    {EFUSE_BLK0, 134, 2}, 	 // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.,
+    {EFUSE_BLK0, 134, 2}, 	 // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"},
 };
 
 static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
-    {EFUSE_BLK0, 141, 1}, 	 // Force ROM code to send a resume command during SPI boot,
+    {EFUSE_BLK0, 136, 1}, 	 // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
 };
 
 static const esp_efuse_desc_t SECURE_VERSION[] = {
-    {EFUSE_BLK0, 142, 16}, 	 // Secure version for anti-rollback,
+    {EFUSE_BLK0, 137, 16}, 	 // [] Represents the version used by ESP-IDF anti-rollback feature,
 };
 
-static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
-    {EFUSE_BLK0, 160, 1}, 	 // Disables check of wafer version major,
-};
-
-static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
-    {EFUSE_BLK0, 161, 1}, 	 // Disables check of blk version major,
+static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    {EFUSE_BLK0, 153, 1}, 	 // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t MAC_FACTORY[] = {
-    {EFUSE_BLK1, 40, 8}, 	 // Factory MAC addr [0],
-    {EFUSE_BLK1, 32, 8}, 	 // Factory MAC addr [1],
-    {EFUSE_BLK1, 24, 8}, 	 // Factory MAC addr [2],
-    {EFUSE_BLK1, 16, 8}, 	 // Factory MAC addr [3],
-    {EFUSE_BLK1, 8, 8}, 	 // Factory MAC addr [4],
-    {EFUSE_BLK1, 0, 8}, 	 // Factory MAC addr [5],
+static const esp_efuse_desc_t HYS_EN_PAD0[] = {
+    {EFUSE_BLK0, 154, 6}, 	 // [] Set bits to enable hysteresis function of PAD0~5,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
-    {EFUSE_BLK1, 48, 6}, 	 // SPI_PAD_configure CLK,
+static const esp_efuse_desc_t HYS_EN_PAD1[] = {
+    {EFUSE_BLK0, 160, 22}, 	 // [] Set bits to enable hysteresis function of PAD6~27,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
-    {EFUSE_BLK1, 54, 6}, 	 // SPI_PAD_configure Q(D1),
+static const esp_efuse_desc_t MAC[] = {
+    {EFUSE_BLK1, 40, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 32, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 24, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 16, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 8, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 0, 8}, 	 // [MAC_FACTORY] MAC address,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
-    {EFUSE_BLK1, 60, 6}, 	 // SPI_PAD_configure D(D0),
+static const esp_efuse_desc_t MAC_EXT[] = {
+    {EFUSE_BLK1, 48, 16}, 	 // [] Stores the extended bits of MAC address,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
-    {EFUSE_BLK1, 66, 6}, 	 // SPI_PAD_configure CS,
+static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
+    {EFUSE_BLK1, 114, 3}, 	 // [],
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
-    {EFUSE_BLK1, 72, 6}, 	 // SPI_PAD_configure HD(D3),
+static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 117, 2}, 	 // [],
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
-    {EFUSE_BLK1, 78, 6}, 	 // SPI_PAD_configure WP(D2),
+static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
+    {EFUSE_BLK1, 119, 1}, 	 // [] Disables check of wafer version major,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
-    {EFUSE_BLK1, 84, 6}, 	 // SPI_PAD_configure DQS,
+static const esp_efuse_desc_t FLASH_CAP[] = {
+    {EFUSE_BLK1, 120, 3}, 	 // [],
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
-    {EFUSE_BLK1, 90, 6}, 	 // SPI_PAD_configure D4,
+static const esp_efuse_desc_t FLASH_TEMP[] = {
+    {EFUSE_BLK1, 123, 2}, 	 // [],
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
-    {EFUSE_BLK1, 96, 6}, 	 // SPI_PAD_configure D5,
+static const esp_efuse_desc_t FLASH_VENDOR[] = {
+    {EFUSE_BLK1, 125, 3}, 	 // [],
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
-    {EFUSE_BLK1, 102, 6}, 	 // SPI_PAD_configure D6,
+static const esp_efuse_desc_t PKG_VERSION[] = {
+    {EFUSE_BLK1, 128, 3}, 	 // [] Package version,
 };
 
-static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
-    {EFUSE_BLK1, 108, 6}, 	 // SPI_PAD_configure D7,
+static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
+    {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
 };
 
-static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
-    {EFUSE_BLK1, 114, 3}, 	 // WAFER_VERSION_MINOR least significant bits,
-    {EFUSE_BLK1, 183, 1}, 	 // WAFER_VERSION_MINOR most significant bit,
+static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
+    {EFUSE_BLK2, 130, 3}, 	 // [] BLK_VERSION_MINOR of BLOCK2,
 };
 
-static const esp_efuse_desc_t PKG_VERSION[] = {
-    {EFUSE_BLK1, 117, 3}, 	 // Package version 0:ESP32C3,
+static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK2, 133, 2}, 	 // [] BLK_VERSION_MAJOR of BLOCK2,
 };
 
-static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
-    {EFUSE_BLK1, 120, 3}, 	 // BLK_VERSION_MINOR,
+static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
+    {EFUSE_BLK2, 135, 1}, 	 // [] Disables check of blk version major,
 };
 
-static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
-    {EFUSE_BLK1, 184, 2}, 	 // WAFER_VERSION_MAJOR,
+static const esp_efuse_desc_t USER_DATA[] = {
+    {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
 
-static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
-    {EFUSE_BLK2, 0, 128}, 	 // Optional unique 128-bit ID,
+static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
+    {EFUSE_BLK3, 200, 48}, 	 // [MAC_CUSTOM CUSTOM_MAC] Custom MAC,
 };
 
-static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
-    {EFUSE_BLK2, 128, 2}, 	 // BLK_VERSION_MAJOR of BLOCK2,
+static const esp_efuse_desc_t KEY0[] = {
+    {EFUSE_BLK4, 0, 256}, 	 // [BLOCK_KEY0] Key0 or user data,
 };
 
-static const esp_efuse_desc_t TEMP_CALIB[] = {
-    {EFUSE_BLK2, 131, 9}, 	 // Temperature calibration data,
+static const esp_efuse_desc_t KEY1[] = {
+    {EFUSE_BLK5, 0, 256}, 	 // [BLOCK_KEY1] Key1 or user data,
 };
 
-static const esp_efuse_desc_t OCODE[] = {
-    {EFUSE_BLK2, 140, 8}, 	 // ADC OCode,
+static const esp_efuse_desc_t KEY2[] = {
+    {EFUSE_BLK6, 0, 256}, 	 // [BLOCK_KEY2] Key2 or user data,
 };
 
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
-    {EFUSE_BLK2, 148, 10}, 	 // ADC1 init code at atten0,
+static const esp_efuse_desc_t KEY3[] = {
+    {EFUSE_BLK7, 0, 256}, 	 // [BLOCK_KEY3] Key3 or user data,
 };
 
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
-    {EFUSE_BLK2, 158, 10}, 	 // ADC1 init code at atten1,
+static const esp_efuse_desc_t KEY4[] = {
+    {EFUSE_BLK8, 0, 256}, 	 // [BLOCK_KEY4] Key4 or user data,
 };
 
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
-    {EFUSE_BLK2, 168, 10}, 	 // ADC1 init code at atten2,
+static const esp_efuse_desc_t KEY5[] = {
+    {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
 };
 
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
-    {EFUSE_BLK2, 178, 10}, 	 // ADC1 init code at atten3,
+static const esp_efuse_desc_t SYS_DATA_PART2[] = {
+    {EFUSE_BLK10, 0, 256}, 	 // [BLOCK_SYS_DATA2] System data part 2 (reserved),
 };
 
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
-    {EFUSE_BLK2, 188, 10}, 	 // ADC1 calibration voltage at atten0,
-};
 
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
-    {EFUSE_BLK2, 198, 10}, 	 // ADC1 calibration voltage at atten1,
-};
 
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
-    {EFUSE_BLK2, 208, 10}, 	 // ADC1 calibration voltage at atten2,
-};
 
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
-    {EFUSE_BLK2, 218, 10}, 	 // ADC1 calibration voltage at atten3,
-};
 
-static const esp_efuse_desc_t USER_DATA[] = {
-    {EFUSE_BLK3, 0, 256}, 	 // User data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
+    &WR_DIS[0],    		// [] Disable programming of individual eFuses
+    NULL
 };
 
-static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
-    {EFUSE_BLK3, 200, 48}, 	 // Custom MAC,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
+    &WR_DIS_RD_DIS[0],    		// [] wr_dis of RD_DIS
+    NULL
 };
 
-static const esp_efuse_desc_t KEY0[] = {
-    {EFUSE_BLK4, 0, 256}, 	 // Key0 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = {
+    &WR_DIS_DIS_ICACHE[0],    		// [] wr_dis of DIS_ICACHE
+    NULL
 };
 
-static const esp_efuse_desc_t KEY1[] = {
-    {EFUSE_BLK5, 0, 256}, 	 // Key1 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = {
+    &WR_DIS_DIS_USB_JTAG[0],    		// [] wr_dis of DIS_USB_JTAG
+    NULL
 };
 
-static const esp_efuse_desc_t KEY2[] = {
-    {EFUSE_BLK6, 0, 256}, 	 // Key2 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[] = {
+    &WR_DIS_POWERGLITCH_EN[0],    		// [] wr_dis of POWERGLITCH_EN
+    NULL
 };
 
-static const esp_efuse_desc_t KEY3[] = {
-    {EFUSE_BLK7, 0, 256}, 	 // Key3 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
+    &WR_DIS_DIS_FORCE_DOWNLOAD[0],    		// [] wr_dis of DIS_FORCE_DOWNLOAD
+    NULL
 };
 
-static const esp_efuse_desc_t KEY4[] = {
-    {EFUSE_BLK8, 0, 256}, 	 // Key4 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0],    		// [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
+    NULL
 };
 
-static const esp_efuse_desc_t KEY5[] = {
-    {EFUSE_BLK9, 0, 256}, 	 // Key5 or user data,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
+    &WR_DIS_DIS_TWAI[0],    		// [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
+    NULL
 };
 
-static const esp_efuse_desc_t SYS_DATA_PART2[] = {
-    {EFUSE_BLK10, 0, 256}, 	 // System configuration,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
+    &WR_DIS_JTAG_SEL_ENABLE[0],    		// [] wr_dis of JTAG_SEL_ENABLE
+    NULL
 };
 
-static const esp_efuse_desc_t K_RTC_LDO[] = {
-    {EFUSE_BLK1, 135, 7}, 	 // BLOCK1 K_RTC_LDO,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = {
+    &WR_DIS_DIS_PAD_JTAG[0],    		// [] wr_dis of DIS_PAD_JTAG
+    NULL
 };
 
-static const esp_efuse_desc_t K_DIG_LDO[] = {
-    {EFUSE_BLK1, 142, 7}, 	 // BLOCK1 K_DIG_LDO,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
+    NULL
 };
 
-static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
-    {EFUSE_BLK1, 149, 8}, 	 // BLOCK1 voltage of rtc dbias20,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
+    &WR_DIS_WDT_DELAY_SEL[0],    		// [] wr_dis of WDT_DELAY_SEL
+    NULL
 };
 
-static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
-    {EFUSE_BLK1, 157, 8}, 	 // BLOCK1 voltage of digital dbias20,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// [] wr_dis of SPI_BOOT_CRYPT_CNT
+    NULL
 };
 
-static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
-    {EFUSE_BLK1, 165, 5}, 	 // BLOCK1 digital dbias when hvt,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+    NULL
 };
 
-static const esp_efuse_desc_t THRES_HVT[] = {
-    {EFUSE_BLK1, 170, 10}, 	 // BLOCK1 pvt threshold when hvt,
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+    NULL
 };
 
-
-
-
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
-    &WR_DIS[0],    		// Write protection
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
-    &WR_DIS_RD_DIS[0],    		// Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
+    &WR_DIS_KEY_PURPOSE_0[0],    		// [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = {
-    &WR_DIS_SWAP_UART_SDIO_EN[0],    		// Write protection for SWAP_UART_SDIO_EN
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
+    &WR_DIS_KEY_PURPOSE_1[0],    		// [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
-    &WR_DIS_GROUP_1[0],    		// Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
+    &WR_DIS_KEY_PURPOSE_2[0],    		// [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
-    &WR_DIS_GROUP_2[0],    		// Write protection for WDT_DELAY_SEL
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
+    &WR_DIS_KEY_PURPOSE_3[0],    		// [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
-    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// Write protection for SPI_BOOT_CRYPT_CNT
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
+    &WR_DIS_KEY_PURPOSE_4[0],    		// [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
+    &WR_DIS_KEY_PURPOSE_5[0],    		// [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
+    &WR_DIS_SEC_DPA_LEVEL[0],    		// [] wr_dis of SEC_DPA_LEVEL
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = {
+    &WR_DIS_CRYPT_DPA_ENABLE[0],    		// [] wr_dis of CRYPT_DPA_ENABLE
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
-    &WR_DIS_KEY0_PURPOSE[0],    		// Write protection for key_purpose. KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
+    &WR_DIS_SECURE_BOOT_EN[0],    		// [] wr_dis of SECURE_BOOT_EN
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
-    &WR_DIS_KEY1_PURPOSE[0],    		// Write protection for key_purpose. KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
-    &WR_DIS_KEY2_PURPOSE[0],    		// Write protection for key_purpose. KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
+    &WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[0],    		// [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
-    &WR_DIS_KEY3_PURPOSE[0],    		// Write protection for key_purpose. KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
+    &WR_DIS_FLASH_TPUW[0],    		// [] wr_dis of FLASH_TPUW
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
-    &WR_DIS_KEY4_PURPOSE[0],    		// Write protection for key_purpose. KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = {
+    &WR_DIS_DIS_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_DOWNLOAD_MODE
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
-    &WR_DIS_KEY5_PURPOSE[0],    		// Write protection for key_purpose. KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = {
+    &WR_DIS_DIS_DIRECT_BOOT[0],    		// [] wr_dis of DIS_DIRECT_BOOT
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
-    &WR_DIS_SEC_DPA_LEVEL[0],    		// Write protection for SEC_DPA_LEVEL
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
-    &WR_DIS_SECURE_BOOT_EN[0],    		// Write protection for SECURE_BOOT_EN
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
+    &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0],    		// [] wr_dis of ENABLE_SECURITY_DOWNLOAD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
-    &WR_DIS_GROUP_3[0],    		// Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = {
+    &WR_DIS_UART_PRINT_CONTROL[0],    		// [] wr_dis of UART_PRINT_CONTROL
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
-    &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// Write protection for SECURE_BOOT_DISABLE_FAST_WAKE
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = {
+    &WR_DIS_FORCE_SEND_RESUME[0],    		// [] wr_dis of FORCE_SEND_RESUME
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
-    &WR_DIS_BLK1[0],    		// Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = {
+    &WR_DIS_SECURE_VERSION[0],    		// [] wr_dis of SECURE_VERSION
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
-    &WR_DIS_SYS_DATA_PART1[0],    		// Write protection for EFUSE_BLK2.  SYS_DATA_PART1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
-    &WR_DIS_USER_DATA[0],    		// Write protection for EFUSE_BLK3.  USER_DATA
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD0[] = {
+    &WR_DIS_HYS_EN_PAD0[0],    		// [] wr_dis of HYS_EN_PAD0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
-    &WR_DIS_KEY0[0],    		// Write protection for EFUSE_BLK4.  KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD1[] = {
+    &WR_DIS_HYS_EN_PAD1[0],    		// [] wr_dis of HYS_EN_PAD1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
-    &WR_DIS_KEY1[0],    		// Write protection for EFUSE_BLK5.  KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
+    &WR_DIS_BLK1[0],    		// [] wr_dis of BLOCK1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
-    &WR_DIS_KEY2[0],    		// Write protection for EFUSE_BLK6.  KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
+    &WR_DIS_MAC[0],    		// [WR_DIS.MAC_FACTORY] wr_dis of MAC
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
-    &WR_DIS_KEY3[0],    		// Write protection for EFUSE_BLK7.  KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
+    &WR_DIS_MAC_EXT[0],    		// [] wr_dis of MAC_EXT
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
-    &WR_DIS_KEY4[0],    		// Write protection for EFUSE_BLK8.  KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
+    &WR_DIS_WAFER_VERSION_MINOR[0],    		// [] wr_dis of WAFER_VERSION_MINOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
-    &WR_DIS_KEY5[0],    		// Write protection for EFUSE_BLK9.  KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
+    &WR_DIS_WAFER_VERSION_MAJOR[0],    		// [] wr_dis of WAFER_VERSION_MAJOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
-    &WR_DIS_SYS_DATA_PART2[0],    		// Write protection for EFUSE_BLK10. SYS_DATA_PART2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
+    &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
-    &RD_DIS[0],    		// Read protection
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
+    &WR_DIS_FLASH_CAP[0],    		// [] wr_dis of FLASH_CAP
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
-    &RD_DIS_KEY0[0],    		// Read protection for EFUSE_BLK4.  KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = {
+    &WR_DIS_FLASH_TEMP[0],    		// [] wr_dis of FLASH_TEMP
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
-    &RD_DIS_KEY1[0],    		// Read protection for EFUSE_BLK5.  KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
+    &WR_DIS_FLASH_VENDOR[0],    		// [] wr_dis of FLASH_VENDOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
-    &RD_DIS_KEY2[0],    		// Read protection for EFUSE_BLK6.  KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
+    &WR_DIS_PKG_VERSION[0],    		// [] wr_dis of PKG_VERSION
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
-    &RD_DIS_KEY3[0],    		// Read protection for EFUSE_BLK7.  KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
+    &WR_DIS_SYS_DATA_PART1[0],    		// [] wr_dis of BLOCK2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
-    &RD_DIS_KEY4[0],    		// Read protection for EFUSE_BLK8.  KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
+    &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
-    &RD_DIS_KEY5[0],    		// Read protection for EFUSE_BLK9.  KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
+    &WR_DIS_BLK_VERSION_MINOR[0],    		// [] wr_dis of BLK_VERSION_MINOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
-    &RD_DIS_SYS_DATA_PART2[0],    		// Read protection for EFUSE_BLK10. SYS_DATA_PART2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
+    &WR_DIS_BLK_VERSION_MAJOR[0],    		// [] wr_dis of BLK_VERSION_MAJOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[] = {
-    &SWAP_UART_SDIO_EN[0],    		// Swap pad of uart and sdio.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
+    &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_BLK_VERSION_MAJOR
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
-    &DIS_ICACHE[0],    		// Disable Icache
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
+    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
-    &DIS_USB_JTAG[0],    		// Disable USB JTAG
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
+    &WR_DIS_CUSTOM_MAC[0],    		// [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
-    &DIS_DOWNLOAD_ICACHE[0],    		// Disable Icache in download mode
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
+    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = {
-    &DIS_USB_SERIAL_JTAG[0],    		// Disable USB_SERIAL_JTAG
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
+    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
-    &DIS_FORCE_DOWNLOAD[0],    		// Disable force chip go to download mode function
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
+    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
-    &DIS_TWAI[0],    		// Disable TWAI function
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
+    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
-    &JTAG_SEL_ENABLE[0],    		// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
+    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
-    &SOFT_DIS_JTAG[0],    		// Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
+    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
-    &DIS_PAD_JTAG[0],    		// Disable JTAG in the hard way. JTAG is disabled permanently.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
+    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// Disable flash encryption when in download boot modes.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
+    &WR_DIS_USB_EXCHG_PINS[0],    		// [] wr_dis of USB_EXCHG_PINS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = {
-    &USB_DREFH[0],    		// Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = {
+    &WR_DIS_VDD_SPI_AS_GPIO[0],    		// [] wr_dis of VDD_SPI_AS_GPIO
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = {
-    &USB_DREFL[0],    		// Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
+    &WR_DIS_SOFT_DIS_JTAG[0],    		// [] wr_dis of SOFT_DIS_JTAG
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
-    &USB_EXCHG_PINS[0],    		// Exchange D+ D- pins
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
+    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
-    &VDD_SPI_AS_GPIO[0],    		// Set this bit to vdd spi pin function as gpio
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
+    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
-    &WDT_DELAY_SEL[0],    		// Select RTC WDT time out threshold
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
+    &RD_DIS_BLOCK_KEY1[0],    		// [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
-    &SPI_BOOT_CRYPT_CNT[0],    		// SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
+    &RD_DIS_BLOCK_KEY2[0],    		// [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
-    &SECURE_BOOT_KEY_REVOKE0[0],    		// Enable revoke first secure boot key
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
+    &RD_DIS_BLOCK_KEY3[0],    		// [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
-    &SECURE_BOOT_KEY_REVOKE1[0],    		// Enable revoke second secure boot key
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
+    &RD_DIS_BLOCK_KEY4[0],    		// [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
-    &SECURE_BOOT_KEY_REVOKE2[0],    		// Enable revoke third secure boot key
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
+    &RD_DIS_BLOCK_KEY5[0],    		// [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
-    &KEY_PURPOSE_0[0],    		// Key0 purpose
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
+    &RD_DIS_BLOCK_SYS_DATA2[0],    		// [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
-    &KEY_PURPOSE_1[0],    		// Key1 purpose
+const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
+    &DIS_ICACHE[0],    		// [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
-    &KEY_PURPOSE_2[0],    		// Key2 purpose
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
+    &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
-    &KEY_PURPOSE_3[0],    		// Key3 purpose
+const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
+    &POWERGLITCH_EN[0],    		// [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
-    &KEY_PURPOSE_4[0],    		// Key4 purpose
+const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
+    &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
-    &KEY_PURPOSE_5[0],    		// Key5 purpose
+const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
-    &SEC_DPA_LEVEL[0],    		// Configures the clock random divide mode to determine the spa secure level
+const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
+    &DIS_TWAI[0],    		// [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
-    &SECURE_BOOT_EN[0],    		// Secure boot enable
+const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
+    &JTAG_SEL_ENABLE[0],    		// [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Enable aggressive secure boot revoke
+const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
+    &SOFT_DIS_JTAG[0],    		// [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
-    &FLASH_TPUW[0],    		// Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
+const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
+    &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
-    &DIS_DOWNLOAD_MODE[0],    		// Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
-    &DIS_DIRECT_BOOT[0],    		// Disable direct boot mode
+const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
+    &USB_EXCHG_PINS[0],    		// [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[] = {
-    &DIS_USB_PRINT[0],    		// Disable USB Print
+const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
+    &VDD_SPI_AS_GPIO[0],    		// [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
-    &DIS_USB_DOWNLOAD_MODE[0],    		// Disable download through USB
+const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
+    &WDT_DELAY_SEL[0],    		// [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
-    &ENABLE_SECURITY_DOWNLOAD[0],    		// Enable security download mode
+const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
+    &SPI_BOOT_CRYPT_CNT[0],    		// [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
-    &UART_PRINT_CONTROL[0],    		// b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
+    &SECURE_BOOT_KEY_REVOKE0[0],    		// [] Revoke 1st secure boot key
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
-    &FORCE_SEND_RESUME[0],    		// Force ROM code to send a resume command during SPI boot
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
+    &SECURE_BOOT_KEY_REVOKE1[0],    		// [] Revoke 2nd secure boot key
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
-    &SECURE_VERSION[0],    		// Secure version for anti-rollback
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
+    &SECURE_BOOT_KEY_REVOKE2[0],    		// [] Revoke 3rd secure boot key
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
-    &DISABLE_WAFER_VERSION_MAJOR[0],    		// Disables check of wafer version major
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
+    &KEY_PURPOSE_0[0],    		// [KEY0_PURPOSE] Represents the purpose of Key0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
-    &DISABLE_BLK_VERSION_MAJOR[0],    		// Disables check of blk version major
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
+    &KEY_PURPOSE_1[0],    		// [KEY1_PURPOSE] Represents the purpose of Key1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
-    &MAC_FACTORY[0],    		// Factory MAC addr [0]
-    &MAC_FACTORY[1],    		// Factory MAC addr [1]
-    &MAC_FACTORY[2],    		// Factory MAC addr [2]
-    &MAC_FACTORY[3],    		// Factory MAC addr [3]
-    &MAC_FACTORY[4],    		// Factory MAC addr [4]
-    &MAC_FACTORY[5],    		// Factory MAC addr [5]
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
+    &KEY_PURPOSE_2[0],    		// [KEY2_PURPOSE] Represents the purpose of Key2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
-    &SPI_PAD_CONFIG_CLK[0],    		// SPI_PAD_configure CLK
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
+    &KEY_PURPOSE_3[0],    		// [KEY3_PURPOSE] Represents the purpose of Key3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
-    &SPI_PAD_CONFIG_Q_D1[0],    		// SPI_PAD_configure Q(D1)
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
+    &KEY_PURPOSE_4[0],    		// [KEY4_PURPOSE] Represents the purpose of Key4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
-    &SPI_PAD_CONFIG_D_D0[0],    		// SPI_PAD_configure D(D0)
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
+    &KEY_PURPOSE_5[0],    		// [KEY5_PURPOSE] Represents the purpose of Key5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
-    &SPI_PAD_CONFIG_CS[0],    		// SPI_PAD_configure CS
+const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
+    &SEC_DPA_LEVEL[0],    		// [] Represents the spa secure level by configuring the clock random divide mode
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
-    &SPI_PAD_CONFIG_HD_D3[0],    		// SPI_PAD_configure HD(D3)
+const esp_efuse_desc_t* ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K[] = {
+    &ECDSA_FORCE_USE_HARDWARE_K[0],    		// [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
-    &SPI_PAD_CONFIG_WP_D2[0],    		// SPI_PAD_configure WP(D2)
+const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
+    &CRYPT_DPA_ENABLE[0],    		// [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
-    &SPI_PAD_CONFIG_DQS[0],    		// SPI_PAD_configure DQS
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
+    &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
-    &SPI_PAD_CONFIG_D4[0],    		// SPI_PAD_configure D4
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
-    &SPI_PAD_CONFIG_D5[0],    		// SPI_PAD_configure D5
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
+    &FLASH_TPUW[0],    		// [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
-    &SPI_PAD_CONFIG_D6[0],    		// SPI_PAD_configure D6
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
+    &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
-    &SPI_PAD_CONFIG_D7[0],    		// SPI_PAD_configure D7
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
+    &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
-    &WAFER_VERSION_MINOR[0],    		// WAFER_VERSION_MINOR least significant bits
-    &WAFER_VERSION_MINOR[1],    		// WAFER_VERSION_MINOR most significant bit
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
-    &PKG_VERSION[0],    		// Package version 0:ESP32C3
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
-    &BLK_VERSION_MINOR[0],    		// BLK_VERSION_MINOR
+const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
-    &WAFER_VERSION_MAJOR[0],    		// WAFER_VERSION_MAJOR
+const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
+    &UART_PRINT_CONTROL[0],    		// [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
-    &OPTIONAL_UNIQUE_ID[0],    		// Optional unique 128-bit ID
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
+    &FORCE_SEND_RESUME[0],    		// [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
-    &BLK_VERSION_MAJOR[0],    		// BLK_VERSION_MAJOR of BLOCK2
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
+    &SECURE_VERSION[0],    		// [] Represents the version used by ESP-IDF anti-rollback feature
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
-    &TEMP_CALIB[0],    		// Temperature calibration data
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
-    &OCODE[0],    		// ADC OCode
+const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[] = {
+    &HYS_EN_PAD0[0],    		// [] Set bits to enable hysteresis function of PAD0~5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
-    &ADC1_INIT_CODE_ATTEN0[0],    		// ADC1 init code at atten0
+const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[] = {
+    &HYS_EN_PAD1[0],    		// [] Set bits to enable hysteresis function of PAD6~27
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
-    &ADC1_INIT_CODE_ATTEN1[0],    		// ADC1 init code at atten1
+const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
+    &MAC[0],    		// [MAC_FACTORY] MAC address
+    &MAC[1],    		// [MAC_FACTORY] MAC address
+    &MAC[2],    		// [MAC_FACTORY] MAC address
+    &MAC[3],    		// [MAC_FACTORY] MAC address
+    &MAC[4],    		// [MAC_FACTORY] MAC address
+    &MAC[5],    		// [MAC_FACTORY] MAC address
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
-    &ADC1_INIT_CODE_ATTEN2[0],    		// ADC1 init code at atten2
+const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
+    &MAC_EXT[0],    		// [] Stores the extended bits of MAC address
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
-    &ADC1_INIT_CODE_ATTEN3[0],    		// ADC1 init code at atten3
+const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
+    &WAFER_VERSION_MINOR[0],    		// []
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
-    &ADC1_CAL_VOL_ATTEN0[0],    		// ADC1 calibration voltage at atten0
+const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
+    &WAFER_VERSION_MAJOR[0],    		// []
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
-    &ADC1_CAL_VOL_ATTEN1[0],    		// ADC1 calibration voltage at atten1
+const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
+    &DISABLE_WAFER_VERSION_MAJOR[0],    		// [] Disables check of wafer version major
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
-    &ADC1_CAL_VOL_ATTEN2[0],    		// ADC1 calibration voltage at atten2
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
+    &FLASH_CAP[0],    		// []
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
-    &ADC1_CAL_VOL_ATTEN3[0],    		// ADC1 calibration voltage at atten3
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = {
+    &FLASH_TEMP[0],    		// []
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
-    &USER_DATA[0],    		// User data
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
+    &FLASH_VENDOR[0],    		// []
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
-    &USER_DATA_MAC_CUSTOM[0],    		// Custom MAC
+const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
+    &PKG_VERSION[0],    		// [] Package version
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
-    &KEY0[0],    		// Key0 or user data
+const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
+    &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
-    &KEY1[0],    		// Key1 or user data
+const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
+    &BLK_VERSION_MINOR[0],    		// [] BLK_VERSION_MINOR of BLOCK2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
-    &KEY2[0],    		// Key2 or user data
+const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
+    &BLK_VERSION_MAJOR[0],    		// [] BLK_VERSION_MAJOR of BLOCK2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
-    &KEY3[0],    		// Key3 or user data
+const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
+    &DISABLE_BLK_VERSION_MAJOR[0],    		// [] Disables check of blk version major
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
-    &KEY4[0],    		// Key4 or user data
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
+    &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
-    &KEY5[0],    		// Key5 or user data
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
+    &USER_DATA_MAC_CUSTOM[0],    		// [MAC_CUSTOM CUSTOM_MAC] Custom MAC
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
-    &SYS_DATA_PART2[0],    		// System configuration
+const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
+    &KEY0[0],    		// [BLOCK_KEY0] Key0 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
-    &K_RTC_LDO[0],    		// BLOCK1 K_RTC_LDO
+const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
+    &KEY1[0],    		// [BLOCK_KEY1] Key1 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
-    &K_DIG_LDO[0],    		// BLOCK1 K_DIG_LDO
+const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
+    &KEY2[0],    		// [BLOCK_KEY2] Key2 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
-    &V_RTC_DBIAS20[0],    		// BLOCK1 voltage of rtc dbias20
+const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
+    &KEY3[0],    		// [BLOCK_KEY3] Key3 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
-    &V_DIG_DBIAS20[0],    		// BLOCK1 voltage of digital dbias20
+const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
+    &KEY4[0],    		// [BLOCK_KEY4] Key4 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
-    &DIG_DBIAS_HVT[0],    		// BLOCK1 digital dbias when hvt
+const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
+    &KEY5[0],    		// [BLOCK_KEY5] Key5 or user data
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = {
-    &THRES_HVT[0],    		// BLOCK1 pvt threshold when hvt
+const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
+    &SYS_DATA_PART2[0],    		// [BLOCK_SYS_DATA2] System data part 2 (reserved)
     NULL
 };

components/efuse/esp32h2/esp_efuse_table.csv

@@ -1,178 +1,154 @@
+
 # field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1..-)     |        #
-#                   |     EFUSE_BLK1  |            |MAX_BLK_LEN*|        #
-#                   |        ...      |            |            |        #
-#                   |     EFUSE_BLK10)|            |            |        #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...)     |            |            |        #
 ##########################################################################
-# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
+# After editing this file, run the command manually "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# EFUSE_RD_REPEAT_DATA BLOCK #
-##############################
-    # EFUSE_RD_WR_DIS_REG #
-        WR_DIS,                           EFUSE_BLK0,   0,    32,     Write protection
-            WR_DIS.RD_DIS,                EFUSE_BLK0,   0,    1,      Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
-            WR_DIS.SWAP_UART_SDIO_EN,     EFUSE_BLK0,   1,    1,      Write protection for SWAP_UART_SDIO_EN
-            WR_DIS.GROUP_1,               EFUSE_BLK0,   2,    1,      Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
-            WR_DIS.GROUP_2,               EFUSE_BLK0,   3,    1,      Write protection for WDT_DELAY_SEL
-            WR_DIS.SPI_BOOT_CRYPT_CNT,    EFUSE_BLK0,   4,    1,      Write protection for SPI_BOOT_CRYPT_CNT
-            WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0,  5,    1,      Write protection for SECURE_BOOT_KEY_REVOKE0
-            WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0,  6,    1,      Write protection for SECURE_BOOT_KEY_REVOKE1
-            WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0,  7,    1,      Write protection for SECURE_BOOT_KEY_REVOKE2
-            WR_DIS.KEY0_PURPOSE,          EFUSE_BLK0,   8,    1,      Write protection for key_purpose. KEY0
-            WR_DIS.KEY1_PURPOSE,          EFUSE_BLK0,   9,    1,      Write protection for key_purpose. KEY1
-            WR_DIS.KEY2_PURPOSE,          EFUSE_BLK0,  10,    1,      Write protection for key_purpose. KEY2
-            WR_DIS.KEY3_PURPOSE,          EFUSE_BLK0,  11,    1,      Write protection for key_purpose. KEY3
-            WR_DIS.KEY4_PURPOSE,          EFUSE_BLK0,  12,    1,      Write protection for key_purpose. KEY4
-            WR_DIS.KEY5_PURPOSE,          EFUSE_BLK0,  13,    1,      Write protection for key_purpose. KEY5
-            WR_DIS.SEC_DPA_LEVEL,         EFUSE_BLK0,  14,    1,      Write protection for SEC_DPA_LEVEL
-            WR_DIS.SECURE_BOOT_EN,        EFUSE_BLK0,  15,    1,      Write protection for SECURE_BOOT_EN
-            WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1,   Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
-            WR_DIS.GROUP_3,               EFUSE_BLK0,  18,    1,      Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
-            WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,EFUSE_BLK0, 19, 1,   Write protection for SECURE_BOOT_DISABLE_FAST_WAKE
-            WR_DIS.BLK1,                  EFUSE_BLK0,  20,    1,      Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
-            WR_DIS.SYS_DATA_PART1,        EFUSE_BLK0,  21,    1,      Write protection for EFUSE_BLK2.  SYS_DATA_PART1
-            WR_DIS.USER_DATA,             EFUSE_BLK0,  22,    1,      Write protection for EFUSE_BLK3.  USER_DATA
-            WR_DIS.KEY0,                  EFUSE_BLK0,  23,    1,      Write protection for EFUSE_BLK4.  KEY0
-            WR_DIS.KEY1,                  EFUSE_BLK0,  24,    1,      Write protection for EFUSE_BLK5.  KEY1
-            WR_DIS.KEY2,                  EFUSE_BLK0,  25,    1,      Write protection for EFUSE_BLK6.  KEY2
-            WR_DIS.KEY3,                  EFUSE_BLK0,  26,    1,      Write protection for EFUSE_BLK7.  KEY3
-            WR_DIS.KEY4,                  EFUSE_BLK0,  27,    1,      Write protection for EFUSE_BLK8.  KEY4
-            WR_DIS.KEY5,                  EFUSE_BLK0,  28,    1,      Write protection for EFUSE_BLK9.  KEY5
-            WR_DIS.SYS_DATA_PART2,        EFUSE_BLK0,  29,    1,      Write protection for EFUSE_BLK10. SYS_DATA_PART2
-
-    # EFUSE_RD_REPEAT_DATA0_REG #
-        RD_DIS,                           EFUSE_BLK0,   32,    7,     Read protection
-            RD_DIS.KEY0,                  EFUSE_BLK0,   32,    1,     Read protection for EFUSE_BLK4.  KEY0
-            RD_DIS.KEY1,                  EFUSE_BLK0,   33,    1,     Read protection for EFUSE_BLK5.  KEY1
-            RD_DIS.KEY2,                  EFUSE_BLK0,   34,    1,     Read protection for EFUSE_BLK6.  KEY2
-            RD_DIS.KEY3,                  EFUSE_BLK0,   35,    1,     Read protection for EFUSE_BLK7.  KEY3
-            RD_DIS.KEY4,                  EFUSE_BLK0,   36,    1,     Read protection for EFUSE_BLK8.  KEY4
-            RD_DIS.KEY5,                  EFUSE_BLK0,   37,    1,     Read protection for EFUSE_BLK9.  KEY5
-            RD_DIS.SYS_DATA_PART2,        EFUSE_BLK0,   38,    1,     Read protection for EFUSE_BLK10. SYS_DATA_PART2
-        SWAP_UART_SDIO_EN,                EFUSE_BLK0,   39,    1,     Swap pad of uart and sdio.
-        DIS_ICACHE,                       EFUSE_BLK0,   40,    1,     Disable Icache
-        DIS_USB_JTAG,                     EFUSE_BLK0,   41,    1,     Disable USB JTAG
-        DIS_DOWNLOAD_ICACHE,              EFUSE_BLK0,   42,    1,     Disable Icache in download mode
-        DIS_USB_SERIAL_JTAG,              EFUSE_BLK0,   43,    1,     Disable USB_SERIAL_JTAG
-        DIS_FORCE_DOWNLOAD,               EFUSE_BLK0,   44,    1,     Disable force chip go to download mode function
-        DIS_TWAI,                         EFUSE_BLK0,   46,    1,     Disable TWAI function
-        JTAG_SEL_ENABLE,                  EFUSE_BLK0,   47,    1,     Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-        SOFT_DIS_JTAG,                    EFUSE_BLK0,   48,    3,     Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
-        DIS_PAD_JTAG,                     EFUSE_BLK0,   51,    1,     Disable JTAG in the hard way. JTAG is disabled permanently.
-        DIS_DOWNLOAD_MANUAL_ENCRYPT,      EFUSE_BLK0,   52,    1,     Disable flash encryption when in download boot modes.
-        USB_DREFH,                        EFUSE_BLK0,   53,    2,     Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
-        USB_DREFL,                        EFUSE_BLK0,   55,    2,     Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
-        USB_EXCHG_PINS,                   EFUSE_BLK0,   57,    1,     Exchange D+ D- pins
-        VDD_SPI_AS_GPIO,                  EFUSE_BLK0,   58,    1,     Set this bit to vdd spi pin function as gpio
-
-
-    # EFUSE_RD_REPEAT_DATA1_REG #
-        WDT_DELAY_SEL,                    EFUSE_BLK0,   80,    2,     Select RTC WDT time out threshold
-        SPI_BOOT_CRYPT_CNT,               EFUSE_BLK0,   82,    3,     SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
-        SECURE_BOOT_KEY_REVOKE0,          EFUSE_BLK0,   85,    1,     Enable revoke first secure boot key
-        SECURE_BOOT_KEY_REVOKE1,          EFUSE_BLK0,   86,    1,     Enable revoke second secure boot key
-        SECURE_BOOT_KEY_REVOKE2,          EFUSE_BLK0,   87,    1,     Enable revoke third secure boot key
-        KEY_PURPOSE_0,                    EFUSE_BLK0,   88,    4,     Key0 purpose
-        KEY_PURPOSE_1,                    EFUSE_BLK0,   92,    4,     Key1 purpose
-
-    # EFUSE_RD_REPEAT_DATA2_REG #
-        KEY_PURPOSE_2,                    EFUSE_BLK0,   96,    4,     Key2 purpose
-        KEY_PURPOSE_3,                    EFUSE_BLK0,  100,    4,     Key3 purpose
-        KEY_PURPOSE_4,                    EFUSE_BLK0,  104,    4,     Key4 purpose
-        KEY_PURPOSE_5,                    EFUSE_BLK0,  108,    4,     Key5 purpose
-        SEC_DPA_LEVEL,                    EFUSE_BLK0,  112,    2,     Configures the clock random divide mode to determine the spa secure level
-        SECURE_BOOT_EN,                   EFUSE_BLK0,  116,    1,     Secure boot enable
-        SECURE_BOOT_AGGRESSIVE_REVOKE,    EFUSE_BLK0,  117,    1,     Enable aggressive secure boot revoke
-        FLASH_TPUW,                       EFUSE_BLK0,  124,    4,     Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
-
-    # EFUSE_RD_REPEAT_DATA3_REG #
-        DIS_DOWNLOAD_MODE,                EFUSE_BLK0,  128,    1,     Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
-        DIS_DIRECT_BOOT,                  EFUSE_BLK0,  129,    1,     Disable direct boot mode
-        DIS_USB_PRINT,                    EFUSE_BLK0,  130,    1,     Disable USB Print
-        DIS_USB_DOWNLOAD_MODE,            EFUSE_BLK0,  132,    1,     Disable download through USB
-        ENABLE_SECURITY_DOWNLOAD,         EFUSE_BLK0,  133,    1,     Enable security download mode
-        UART_PRINT_CONTROL,               EFUSE_BLK0,  134,    2,     b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
-        FORCE_SEND_RESUME,                EFUSE_BLK0,  141,    1,     Force ROM code to send a resume command during SPI boot
-        SECURE_VERSION,                   EFUSE_BLK0,  142,   16,     Secure version for anti-rollback
-
-    # EFUSE_RD_REPEAT_DATA4_REG #
-        DISABLE_WAFER_VERSION_MAJOR,      EFUSE_BLK0,  160,    1,      Disables check of wafer version major
-        DISABLE_BLK_VERSION_MAJOR,        EFUSE_BLK0,  161,    1,      Disables check of blk version major
-
-# MAC_SPI_SYS BLOCK#
-#######################
-    # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
-        MAC_FACTORY,                          EFUSE_BLK1,   40,    8,     Factory MAC addr [0]
-        ,                                     EFUSE_BLK1,   32,    8,     Factory MAC addr [1]
-        ,                                     EFUSE_BLK1,   24,    8,     Factory MAC addr [2]
-        ,                                     EFUSE_BLK1,   16,    8,     Factory MAC addr [3]
-        ,                                     EFUSE_BLK1,    8,    8,     Factory MAC addr [4]
-        ,                                     EFUSE_BLK1,    0,    8,     Factory MAC addr [5]
-        SPI_PAD_CONFIG_CLK,                   EFUSE_BLK1,   48,    6,     SPI_PAD_configure CLK
-        SPI_PAD_CONFIG_Q_D1,                  EFUSE_BLK1,   54,    6,     SPI_PAD_configure Q(D1)
-        SPI_PAD_CONFIG_D_D0,                  EFUSE_BLK1,   60,    6,     SPI_PAD_configure D(D0)
-        SPI_PAD_CONFIG_CS,                    EFUSE_BLK1,   66,    6,     SPI_PAD_configure CS
-        SPI_PAD_CONFIG_HD_D3,                 EFUSE_BLK1,   72,    6,     SPI_PAD_configure HD(D3)
-        SPI_PAD_CONFIG_WP_D2,                 EFUSE_BLK1,   78,    6,     SPI_PAD_configure WP(D2)
-        SPI_PAD_CONFIG_DQS,                   EFUSE_BLK1,   84,    6,     SPI_PAD_configure DQS
-        SPI_PAD_CONFIG_D4,                    EFUSE_BLK1,   90,    6,     SPI_PAD_configure D4
-        SPI_PAD_CONFIG_D5,                    EFUSE_BLK1,   96,    6,     SPI_PAD_configure D5
-
-    # RD_MAC_SPI_SYS_3
-        SPI_PAD_CONFIG_D6,                    EFUSE_BLK1,  102,    6,     SPI_PAD_configure D6
-        SPI_PAD_CONFIG_D7,                    EFUSE_BLK1,  108,    6,     SPI_PAD_configure D7
-        WAFER_VERSION_MINOR,                  EFUSE_BLK1,  114,    3,     WAFER_VERSION_MINOR least significant bits
-        ,                                     EFUSE_BLK1,  183,    1,     WAFER_VERSION_MINOR most significant bit
-        # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
-        PKG_VERSION,                          EFUSE_BLK1,  117,    3,     Package version 0:ESP32C3
-        BLK_VERSION_MINOR,                    EFUSE_BLK1,  120,    3,     BLK_VERSION_MINOR
-
-    # RD_MAC_SPI_SYS_5
-        # WAFER_VERSION_MINOR most significant bit
-        WAFER_VERSION_MAJOR,                  EFUSE_BLK1,  184,    2,     WAFER_VERSION_MAJOR
-
-# SYS_DATA_PART1 BLOCK# - System configuration
-#######################
-    # RD_SYS_PART1_DATA0 - rd_sys_part1_data3
-        OPTIONAL_UNIQUE_ID,                   EFUSE_BLK2,    0,  128,     Optional unique 128-bit ID
-
-    # RD_SYS_PART1_DATA4
-        BLK_VERSION_MAJOR,                    EFUSE_BLK2,  128,    2,     BLK_VERSION_MAJOR of BLOCK2
-        TEMP_CALIB,                           EFUSE_BLK2,  131,    9,     Temperature calibration data
-        OCODE,                                EFUSE_BLK2,  140,    8,     ADC OCode
-        ADC1_INIT_CODE_ATTEN0,                EFUSE_BLK2,  148,   10,     ADC1 init code at atten0
-        ADC1_INIT_CODE_ATTEN1,                EFUSE_BLK2,  158,   10,     ADC1 init code at atten1
-
-    # RD_SYS_PART1_DATA5
-        ADC1_INIT_CODE_ATTEN2,                EFUSE_BLK2,  168,   10,     ADC1 init code at atten2
-        ADC1_INIT_CODE_ATTEN3,                EFUSE_BLK2,  178,   10,     ADC1 init code at atten3
-        ADC1_CAL_VOL_ATTEN0,                  EFUSE_BLK2,  188,   10,     ADC1 calibration voltage at atten0
-        ADC1_CAL_VOL_ATTEN1,                  EFUSE_BLK2,  198,   10,     ADC1 calibration voltage at atten1
-        ADC1_CAL_VOL_ATTEN2,                  EFUSE_BLK2,  208,   10,     ADC1 calibration voltage at atten2
-        ADC1_CAL_VOL_ATTEN3,                  EFUSE_BLK2,  218,   10,     ADC1 calibration voltage at atten3
-
-################
-USER_DATA,                                EFUSE_BLK3,    0,  256,     User data
-USER_DATA.MAC_CUSTOM,                     EFUSE_BLK3,  200,   48,     Custom MAC
-
-################
-KEY0,                                     EFUSE_BLK4,    0,  256,     Key0 or user data
-KEY1,                                     EFUSE_BLK5,    0,  256,     Key1 or user data
-KEY2,                                     EFUSE_BLK6,    0,  256,     Key2 or user data
-KEY3,                                     EFUSE_BLK7,    0,  256,     Key3 or user data
-KEY4,                                     EFUSE_BLK8,    0,  256,     Key4 or user data
-KEY5,                                     EFUSE_BLK9,    0,  256,     Key5 or user data
-SYS_DATA_PART2,                           EFUSE_BLK10,   0,  256,     System configuration
-
-# AUTO CONFIG DIG&RTC DBIAS#
-################
-K_RTC_LDO,                              EFUSE_BLK1,    135,    7,      BLOCK1 K_RTC_LDO
-K_DIG_LDO,                              EFUSE_BLK1,    142,    7,      BLOCK1 K_DIG_LDO
-V_RTC_DBIAS20,                          EFUSE_BLK1,    149,    8,      BLOCK1 voltage of rtc dbias20
-V_DIG_DBIAS20,                          EFUSE_BLK1,    157,    8,      BLOCK1 voltage of digital dbias20
-DIG_DBIAS_HVT,                          EFUSE_BLK1,    165,    5,      BLOCK1 digital dbias when hvt
-THRES_HVT,                              EFUSE_BLK1,    170,    10,     BLOCK1 pvt threshold when hvt
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 304372753f7bc2d7665354c487c05b4e
+
+WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
+WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
+WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
+WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
+WR_DIS.POWERGLITCH_EN,                           EFUSE_BLK0,   2,   1, [] wr_dis of POWERGLITCH_EN
+WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
+WR_DIS.SPI_DOWNLOAD_MSPI_DIS,                    EFUSE_BLK0,   2,   1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
+WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
+WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
+WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
+WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
+WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
+WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
+WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+WR_DIS.SEC_DPA_LEVEL,                            EFUSE_BLK0,  14,   1, [] wr_dis of SEC_DPA_LEVEL
+WR_DIS.CRYPT_DPA_ENABLE,                         EFUSE_BLK0,  14,   1, [] wr_dis of CRYPT_DPA_ENABLE
+WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
+WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
+WR_DIS.ECDSA_FORCE_USE_HARDWARE_K,               EFUSE_BLK0,  17,   1, [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K
+WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
+WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
+WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DIRECT_BOOT
+WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
+WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
+WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
+WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
+WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
+WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,            EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
+WR_DIS.HYS_EN_PAD0,                              EFUSE_BLK0,  19,   1, [] wr_dis of HYS_EN_PAD0
+WR_DIS.HYS_EN_PAD1,                              EFUSE_BLK0,  19,   1, [] wr_dis of HYS_EN_PAD1
+WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
+WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
+WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
+WR_DIS.WAFER_VERSION_MINOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR
+WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
+WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  20,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
+WR_DIS.FLASH_CAP,                                EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_CAP
+WR_DIS.FLASH_TEMP,                               EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_TEMP
+WR_DIS.FLASH_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_VENDOR
+WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
+WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
+WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
+WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MINOR
+WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MAJOR
+WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  21,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
+WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
+WR_DIS.VDD_SPI_AS_GPIO,                          EFUSE_BLK0,  30,   1, [] wr_dis of VDD_SPI_AS_GPIO
+WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
+RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
+RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
+DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
+POWERGLITCH_EN,                                  EFUSE_BLK0,  42,   1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
+DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
+USB_EXCHG_PINS,                                  EFUSE_BLK0,  57,   1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
+VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  58,   1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
+WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
+SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
+SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
+SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
+KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Represents the purpose of Key0
+KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Represents the purpose of Key1
+KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Represents the purpose of Key2
+KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Represents the purpose of Key3
+KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Represents the purpose of Key4
+KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Represents the purpose of Key5
+SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [] Represents the spa secure level by configuring the clock random divide mode
+ECDSA_FORCE_USE_HARDWARE_K,                      EFUSE_BLK0, 114,   1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
+CRYPT_DPA_ENABLE,                                EFUSE_BLK0, 115,   1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
+SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
+FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
+UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
+FORCE_SEND_RESUME,                               EFUSE_BLK0, 136,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
+SECURE_VERSION,                                  EFUSE_BLK0, 137,  16, [] Represents the version used by ESP-IDF anti-rollback feature
+SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 153,   1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
+HYS_EN_PAD0,                                     EFUSE_BLK0, 154,   6, [] Set bits to enable hysteresis function of PAD0~5
+HYS_EN_PAD1,                                     EFUSE_BLK0, 160,  22, [] Set bits to enable hysteresis function of PAD6~27
+MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  16,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   8,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   0,   8, [MAC_FACTORY] MAC address
+MAC_EXT,                                         EFUSE_BLK1,  48,  16, [] Stores the extended bits of MAC address
+WAFER_VERSION_MINOR,                             EFUSE_BLK1, 114,   3, []
+WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 117,   2, []
+DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK1, 119,   1, [] Disables check of wafer version major
+FLASH_CAP,                                       EFUSE_BLK1, 120,   3, []
+FLASH_TEMP,                                      EFUSE_BLK1, 123,   2, []
+FLASH_VENDOR,                                    EFUSE_BLK1, 125,   3, []
+PKG_VERSION,                                     EFUSE_BLK1, 128,   3, [] Package version
+OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
+BLK_VERSION_MINOR,                               EFUSE_BLK2, 130,   3, [] BLK_VERSION_MINOR of BLOCK2
+BLK_VERSION_MAJOR,                               EFUSE_BLK2, 133,   2, [] BLK_VERSION_MAJOR of BLOCK2
+DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK2, 135,   1, [] Disables check of blk version major
+USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
+USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
+KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
+KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
+KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
+KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
+KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
+KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
+SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

components/efuse/esp32h2/include/esp_efuse_table.h

@@ -1,17 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "esp_efuse.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "esp_efuse.h"
 
-// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
+// md5_digest_table 910e196e9c9c5c052f1c57710fe3977c
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -20,55 +19,115 @@ extern "C" {
 
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
+#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
 extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
@@ -77,68 +136,68 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
-extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
-extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
+#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
 
 #ifdef __cplusplus
 }

components/efuse/test_apps/main/Kconfig.projbuild

@@ -3,7 +3,7 @@ menu "eFuse Tests"
 
     config EFUSE_FPGA_TEST
         bool "Enable eFuse tests for FPGA (developers only, will PERMANENTLY burn efuses)"
-        default y if IDF_ENV_FPGA
+        default n
         help
             This includes eFuse tests for FPGA. These tests expect actual eFuse burning.
             Disable EFUSE_VIRTUAL to use real eFuse burning.

components/hal/esp32h2/efuse_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,7 +29,7 @@ uint32_t efuse_hal_get_minor_chip_version(void)
 void efuse_hal_set_timing(uint32_t apb_freq_hz)
 {
     (void) apb_freq_hz;
-    efuse_ll_set_pwr_off_num(0x190);
+    // keep the default values, no need to change
 }
 
 void efuse_hal_read(void)
@@ -78,16 +78,11 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
             }
         }
     } else if (block <= 10) {
-        // Fail bit (mask=0x8):
-        // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
-        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK9, BLOCK8
-        // Error num bits (mask=0x7):
         // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
-        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK10, BLOCK9
-        // BLOCK10 is not presented in the error regs.
-        uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
-        uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
-        return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
+        // EFUSE_RD_RS_ERR1_REG:                                                     BLOCK10, BLOCK9
+        block--;
+        uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
+        return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
     }
     return false;
 }

components/hal/esp32h2/include/hal/efuse_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,108 +18,106 @@ extern "C" {
 
 // Always inline these functions even no gcc optimization is applied.
 
-//// ESP32H2-TODO: efuse support IDF-6252
-
 /******************* eFuse fields *************************/
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
 {
-    return 0;//EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
+    return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
 {
-    return 0;//EFUSE.rd_repeat_data1.wdt_delay_sel;
+    return EFUSE.rd_repeat_data1.wdt_delay_sel;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
 {
-    return 0;//EFUSE.rd_mac_sys_0;
+    return EFUSE.rd_mac_sys_0.mac_0;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
 {
-    return 0;//EFUSE.rd_mac_sys_1.mac_1;
+    return EFUSE.rd_mac_sys_1.mac_1;
 }
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
 {
-    return 0;//EFUSE.rd_repeat_data2.secure_boot_en;
+    return EFUSE.rd_repeat_data2.secure_boot_en;
 }
 
 // use efuse_hal_get_major_chip_version() to get major chip version
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
 {
-    return 0;//EFUSE.rd_mac_sys_5.wafer_version_major;
+    return EFUSE.rd_mac_sys_3.wafer_version_major;
 }
 
 // use efuse_hal_get_minor_chip_version() to get minor chip version
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
 {
-    return 0;//(EFUSE.rd_mac_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_sys_3.wafer_version_minor_low;
+    return EFUSE.rd_mac_sys_3.wafer_version_minor;
 }
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
 {
-    return 0;//EFUSE.rd_repeat_data4.disable_wafer_version_major;
+    return EFUSE.rd_mac_sys_3.disable_wafer_version_major;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
 {
-    return 0;//EFUSE.rd_sys_part1_data4.blk_version_major;
+    return EFUSE.rd_sys_part1_data4.blk_version_major;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
 {
-    return 0;//EFUSE.rd_mac_sys_3.blk_version_minor;
+    return EFUSE.rd_sys_part1_data4.blk_version_minor;
 }
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
 {
-    return 0;//EFUSE.rd_repeat_data4.disable_blk_version_major;
+    return EFUSE.rd_sys_part1_data4.disable_blk_version_major;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
 {
-    return 0;//EFUSE.rd_mac_sys_3.pkg_version;
+    return EFUSE.rd_mac_sys_4.pkg_version;
 }
 
 /******************* eFuse control functions *************************/
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
 {
-    return 0;//EFUSE.cmd.read_cmd;
+    return EFUSE.cmd.read_cmd;
 }
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
 {
-    return 0;//EFUSE.cmd.pgm_cmd;
+    return EFUSE.cmd.pgm_cmd;
 }
 
 __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
 {
-    // EFUSE.cmd.read_cmd = 1;
+    EFUSE.cmd.read_cmd = 1;
 }
 
 __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
 {
-    // HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
-    // EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
+    HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
+    EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
 }
 
 __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
 {
-    // EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
+    EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
 }
 
 __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
 {
-    // EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
+    EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
 }
 
 __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
 {
-    // EFUSE.wr_tim_conf2.pwr_off_num = value;
+    EFUSE.wr_tim_conf2.pwr_off_num = value;
 }
 
 /******************* eFuse control functions *************************/

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -507,6 +507,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 1
 
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
 config SOC_EFUSE_DIS_PAD_JTAG
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -243,6 +243,7 @@
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (1U)
 
 /*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_PAD_JTAG 1
 #define SOC_EFUSE_DIS_DIRECT_BOOT 1
 

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -747,6 +747,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
     bool
     default y
 
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
 config SOC_EFUSE_DIS_PAD_JTAG
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -334,6 +334,7 @@
 #define SOC_TWAI_SUPPORTS_RX_STATUS     1
 
 /*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_PAD_JTAG 1
 #define SOC_EFUSE_DIS_USB_JTAG 1
 #define SOC_EFUSE_DIS_DIRECT_BOOT 1

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -895,6 +895,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
     bool
     default y
 
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
 config SOC_EFUSE_DIS_PAD_JTAG
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -374,6 +374,7 @@
 #define SOC_TWAI_SUPPORTS_RX_STATUS     1
 
 /*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_PAD_JTAG 1
 #define SOC_EFUSE_DIS_USB_JTAG 1
 #define SOC_EFUSE_DIS_DIRECT_BOOT 1

components/soc/esp32h2/include/soc/efuse_defs.h

@@ -0,0 +1,17 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_READ_OP_CODE 0x5aa5
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/soc/efuse_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
+#include "efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -220,17 +221,16 @@ extern "C" {
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0;
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
  *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
  */
-#define EFUSE_DIS_CAN    (BIT(14))
-#define EFUSE_DIS_CAN_M  (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S)
-#define EFUSE_DIS_CAN_V  0x00000001U
-#define EFUSE_DIS_CAN_S  14
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
+ *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
  */
 #define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
 #define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
@@ -481,14 +481,13 @@ extern "C" {
 #define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
 #define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
 #define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
- *  0: enabled.
- */
-#define EFUSE_DIS_USB_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_PRINT_M  (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S)
-#define EFUSE_DIS_USB_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_PRINT_S  2
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Set this bit to disable USB-Serial-JTAG print during rom boot.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
 /** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
  *  Reserved.
  */
@@ -545,8 +544,7 @@ extern "C" {
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
+ *  Set bits to enable hysteresis function of PAD0~5
  */
 #define EFUSE_HYS_EN_PAD0    0x0000003FU
 #define EFUSE_HYS_EN_PAD0_M  (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S)
@@ -558,8 +556,7 @@ extern "C" {
  */
 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
 /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
+ *  Set bits to enable hysteresis function of PAD6~27
  */
 #define EFUSE_HYS_EN_PAD1    0x003FFFFFU
 #define EFUSE_HYS_EN_PAD1_M  (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S)
@@ -641,25 +638,57 @@ extern "C" {
 #define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
 #define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
 #define EFUSE_MAC_RESERVED_2_S  0
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Stores the first 14 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [20:18]; default: 0; */
+#define EFUSE_WAFER_VERSION_MINOR    0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_S  18
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [22:21]; default: 0; */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  21
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [23]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(23))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  23
+/** EFUSE_FLASH_CAP : R; bitpos: [26:24]; default: 0; */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  24
+/** EFUSE_FLASH_TEMP : R; bitpos: [28:27]; default: 0; */
+#define EFUSE_FLASH_TEMP    0x00000003U
+#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
+#define EFUSE_FLASH_TEMP_V  0x00000003U
+#define EFUSE_FLASH_TEMP_S  27
+/** EFUSE_FLASH_VENDOR : R; bitpos: [31:29]; default: 0; */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  29
 
 /** EFUSE_RD_MAC_SYS_4_REG register
  *  BLOCK1 data register $n.
  */
 #define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of the zeroth part of system data.
+/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0;
+ *  Package version
  */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  0
+/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_131    0x1FFFFFFFU
+#define EFUSE_RESERVED_1_131_M  (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
+#define EFUSE_RESERVED_1_131_V  0x1FFFFFFFU
+#define EFUSE_RESERVED_1_131_S  3
 
 /** EFUSE_RD_MAC_SYS_5_REG register
  *  BLOCK1 data register $n.
@@ -677,61 +706,89 @@ extern "C" {
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of the first part of system data.
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
  */
-#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
-#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_S  0
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA1_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of the first part of system data.
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
  */
-#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
-#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_S  0
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA2_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the first part of system data.
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
  */
-#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
-#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_S  0
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA3_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of the first part of system data.
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
  */
-#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
-#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_S  0
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
 
 /** EFUSE_RD_SYS_PART1_DATA4_REG register
  *  Register $n of BLOCK2 (system).
  */
 #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_S  0
+/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_128    0x00000003U
+#define EFUSE_RESERVED_2_128_M  (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
+#define EFUSE_RESERVED_2_128_V  0x00000003U
+#define EFUSE_RESERVED_2_128_S  0
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  2
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  5
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_RESERVED_2_136 : R; bitpos: [31:8]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_136    0x00FFFFFFU
+#define EFUSE_RESERVED_2_136_M  (EFUSE_RESERVED_2_136_V << EFUSE_RESERVED_2_136_S)
+#define EFUSE_RESERVED_2_136_V  0x00FFFFFFU
+#define EFUSE_RESERVED_2_136_S  8
 
 /** EFUSE_RD_SYS_PART1_DATA5_REG register
  *  Register $n of BLOCK2 (system).
@@ -845,25 +902,39 @@ extern "C" {
  *  Register $n of BLOCK3 (user).
  */
 #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of BLOCK3 (user).
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
  */
-#define EFUSE_USR_DATA6    0xFFFFFFFFU
-#define EFUSE_USR_DATA6_M  (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
-#define EFUSE_USR_DATA6_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA6_S  0
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
 
 /** EFUSE_RD_USR_DATA7_REG register
  *  Register $n of BLOCK3 (user).
  */
 #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of BLOCK3 (user).
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
  */
-#define EFUSE_USR_DATA7    0xFFFFFFFFU
-#define EFUSE_USR_DATA7_M  (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
-#define EFUSE_USR_DATA7_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA7_S  0
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
 
 /** EFUSE_RD_KEY0_DATA0_REG register
  *  Register $n of BLOCK4 (KEY0).
@@ -2137,10 +2208,6 @@ extern "C" {
 #define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
 #define EFUSE_OP_CODE_V  0x0000FFFFU
 #define EFUSE_OP_CODE_S  0
-
-#define EFUSE_WRITE_OP_CODE 0x5a5a
-#define EFUSE_READ_OP_CODE 0x5aa5
-
 /** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
  *  Configures which block to use for ECDSA key output.
  */

components/soc/esp32h2/include/soc/efuse_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -155,7 +155,7 @@ typedef union {
 } efuse_pgm_check_value2_reg_t;
 
 
-/** Group: ******** Registers */
+/** Group: Read Data Register */
 /** Type of rd_wr_dis register
  *  BLOCK0 data register 0.
  */
@@ -211,14 +211,13 @@ typedef union {
          *  enabled. 1: disabled. 0: enabled.
          */
         uint32_t spi_download_mspi_dis:1;
-        /** dis_can : RO; bitpos: [14]; default: 0;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
          *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
          */
-        uint32_t dis_can:1;
+        uint32_t dis_twai:1;
         /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
          */
         uint32_t jtag_sel_enable:1;
         /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
@@ -385,11 +384,10 @@ typedef union {
          *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
          */
         uint32_t dis_direct_boot:1;
-        /** dis_usb_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
-         *  0: enabled.
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
          */
-        uint32_t dis_usb_print:1;
+        uint32_t dis_usb_serial_jtag_rom_print:1;
         /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
          *  Reserved.
          */
@@ -425,8 +423,7 @@ typedef union {
          */
         uint32_t secure_boot_disable_fast_wake:1;
         /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
+         *  Set bits to enable hysteresis function of PAD0~5
          */
         uint32_t hys_en_pad0:6;
     };
@@ -439,8 +436,7 @@ typedef union {
 typedef union {
     struct {
         /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
+         *  Set bits to enable hysteresis function of PAD6~27
          */
         uint32_t hys_en_pad1:22;
         /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0;
@@ -511,10 +507,20 @@ typedef union {
          *  Reserved.
          */
         uint32_t mac_reserved_2:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Stores the first 14 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
+        /** wafer_version_minor : R; bitpos: [20:18]; default: 0; */
+        uint32_t wafer_version_minor:3;
+        /** wafer_version_major : R; bitpos: [22:21]; default: 0; */
+        uint32_t wafer_version_major:2;
+        /** disable_wafer_version_major : R; bitpos: [23]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** flash_cap : R; bitpos: [26:24]; default: 0; */
+        uint32_t flash_cap:3;
+        /** flash_temp : R; bitpos: [28:27]; default: 0; */
+        uint32_t flash_temp:2;
+        /** flash_vendor : R; bitpos: [31:29]; default: 0; */
+        uint32_t flash_vendor:3;
     };
     uint32_t val;
 } efuse_rd_mac_sys_3_reg_t;
@@ -524,10 +530,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of the zeroth part of system data.
+        /** pkg_version : R; bitpos: [2:0]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** reserved_1_131 : R; bitpos: [31:3]; default: 0;
+         *  reserved
          */
-        uint32_t sys_data_part0_1:32;
+        uint32_t reserved_1_131:29;
     };
     uint32_t val;
 } efuse_rd_mac_sys_4_reg_t;
@@ -550,10 +560,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of the first part of system data.
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
          */
-        uint32_t sys_data_part1_0:32;
+        uint32_t optional_unique_id:32;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data0_reg_t;
@@ -563,10 +573,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of the first part of system data.
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
          */
-        uint32_t sys_data_part1_1:32;
+        uint32_t optional_unique_id_1:32;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data1_reg_t;
@@ -576,10 +586,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the first part of system data.
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
          */
-        uint32_t sys_data_part1_2:32;
+        uint32_t optional_unique_id_2:32;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data2_reg_t;
@@ -589,10 +599,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of the first part of system data.
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
          */
-        uint32_t sys_data_part1_3:32;
+        uint32_t optional_unique_id_3:32;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data3_reg_t;
@@ -602,10 +612,26 @@ typedef union {
  */
 typedef union {
     struct {
-        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of the first part of system data.
+        /** reserved_2_128 : R; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_128:2;
+        /** blk_version_minor : R; bitpos: [4:2]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [6:5]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
          */
-        uint32_t sys_data_part1_4:32;
+        uint32_t blk_version_major:2;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** reserved_2_136 : R; bitpos: [31:8]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_136:24;
     };
     uint32_t val;
 } efuse_rd_sys_part1_data4_reg_t;
@@ -732,10 +758,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** usr_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of BLOCK3 (user).
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
          */
-        uint32_t usr_data6:32;
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
     };
     uint32_t val;
 } efuse_rd_usr_data6_reg_t;
@@ -745,10 +775,14 @@ typedef union {
  */
 typedef union {
     struct {
-        /** usr_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of BLOCK3 (user).
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
          */
-        uint32_t usr_data7:32;
+        uint32_t reserved_3_248:8;
     };
     uint32_t val;
 } efuse_rd_usr_data7_reg_t;
@@ -1481,6 +1515,8 @@ typedef union {
     uint32_t val;
 } efuse_rd_sys_part2_data7_reg_t;
 
+
+/** Group: Report Register */
 /** Type of rd_repeat_err0 register
  *  Programming error record register 0 of BLOCK0.
  */
@@ -1847,6 +1883,8 @@ typedef union {
     uint32_t val;
 } efuse_rd_rs_err1_reg_t;
 
+
+/** Group: Configuration Register */
 /** Type of clk register
  *  eFuse clcok configuration register.
  */
@@ -1892,52 +1930,6 @@ typedef union {
     uint32_t val;
 } efuse_conf_reg_t;
 
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
 /** Type of cmd register
  *  eFuse command register.
  */
@@ -1961,78 +1953,6 @@ typedef union {
     uint32_t val;
 } efuse_cmd_reg_t;
 
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
 /** Type of dac_conf register
  *  Controls the eFuse programming voltage.
  */
@@ -2149,6 +2069,130 @@ typedef union {
     uint32_t val;
 } efuse_wr_tim_conf0_rs_bypass_reg_t;
 
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
 /** Type of date register
  *  eFuse version register.
  */

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -831,6 +831,10 @@ config SOC_AES_SUPPORT_GCM
     bool
     default y
 
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
 config SOC_EFUSE_DIS_DOWNLOAD_DCACHE
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -365,6 +365,7 @@
 #define SOC_AES_SUPPORT_GCM     (1)
 
 /*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
 #define SOC_EFUSE_HARD_DIS_JTAG 1
 #define SOC_EFUSE_SOFT_DIS_JTAG 1

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -1039,6 +1039,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
 
+config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
+    bool
+    default y
+
 config SOC_EFUSE_DIS_DOWNLOAD_DCACHE
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -425,6 +425,7 @@
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 
 /*-------------------------- eFuse CAPS----------------------------*/
+#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
 #define SOC_EFUSE_HARD_DIS_JTAG 1
 #define SOC_EFUSE_DIS_USB_JTAG 1

examples/system/efuse/pytest_system_efuse_example.py

@@ -71,7 +71,8 @@ def test_examples_efuse_with_virt_flash_enc(dut: Dut) -> None:
         else:
             dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4')
         dut.expect('Not disabling UART bootloader encryption')
-        dut.expect('Disable UART bootloader cache...')
+        if dut.app.target != 'esp32h2':
+            dut.expect('Disable UART bootloader cache...')
         dut.expect('Disable JTAG...')
     dut.expect('bootloader encrypted successfully')
     dut.expect('partition table encrypted and loaded successfully')
@@ -113,7 +114,8 @@ def test_examples_efuse_with_virt_flash_enc_aes_256(dut: Dut) -> None:
     dut.expect('Writing EFUSE_BLK_KEY0 with purpose 2')
     dut.expect('Writing EFUSE_BLK_KEY1 with purpose 3')
     dut.expect('Not disabling UART bootloader encryption')
-    dut.expect('Disable UART bootloader cache...')
+    if dut.app.target != 'esp32h2':
+        dut.expect('Disable UART bootloader cache...')
     dut.expect('Disable JTAG...')
 
     dut.expect('bootloader encrypted successfully')
@@ -182,7 +184,8 @@ def test_examples_efuse_with_virt_flash_enc_pre_loaded(dut: Dut) -> None:
         dut.expect('Disable ROM BASIC interpreter fallback...')
     else:
         dut.expect('Not disabling UART bootloader encryption')
-        dut.expect('Disable UART bootloader cache...')
+        if dut.app.target != 'esp32h2':
+            dut.expect('Disable UART bootloader cache...')
         dut.expect('Disable JTAG...')
     dut.expect('bootloader encrypted successfully')
     dut.expect('partition table encrypted and loaded successfully')
@@ -235,7 +238,8 @@ def test_examples_efuse_with_virt_flash_enc_release(dut: Dut) -> None:
         else:
             dut.expect('Writing EFUSE_BLK_KEY0 with purpose 4')
         dut.expect('Disable UART bootloader encryption')
-        dut.expect('Disable UART bootloader cache...')
+        if dut.app.target != 'esp32h2':
+            dut.expect('Disable UART bootloader cache...')
         dut.expect('Disable JTAG...')
     dut.expect('bootloader encrypted successfully')
     dut.expect('partition table encrypted and loaded successfully')
@@ -917,7 +921,8 @@ def test_examples_efuse_with_virt_sb_v2_and_fe_esp32xx(dut: Dut) -> None:
         dut.expect('Writing EFUSE_BLK_KEY1 with purpose 4')
 
     dut.expect('Not disabling UART bootloader encryption')
-    dut.expect('Disable UART bootloader cache...')
+    if dut.app.target != 'esp32h2':
+        dut.expect('Disable UART bootloader cache...')
     dut.expect('Disable JTAG...')
 
     if dut.app.target == 'esp32c2':