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@@ -91,9 +91,7 @@ bool esp_spiram_test()
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}
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}
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-
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-
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-esp_err_t esp_spiram_init()
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+void IRAM_ATTR esp_spiram_init_cache()
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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@@ -102,7 +100,11 @@ esp_err_t esp_spiram_init()
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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#endif
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+}
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+
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+esp_err_t esp_spiram_init()
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+{
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esp_err_t r;
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r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
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if (r != ESP_OK) {
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@@ -202,4 +204,4 @@ void IRAM_ATTR esp_spiram_writeback_cache()
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-#endif
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+#endif
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