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@@ -118,6 +118,29 @@ static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg)
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return src_clk_freq;
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}
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+/* Retrieve the clock frequency for global clocks only */
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+static uint32_t ledc_get_glb_clk_freq(ledc_slow_clk_sel_t clk_cfg)
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+{
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+ uint32_t src_clk_freq = 0;
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+
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+ switch (clk_cfg) {
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+ case LEDC_SLOW_CLK_APB:
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+ src_clk_freq = LEDC_APB_CLK_HZ;
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+ break;
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+ case LEDC_SLOW_CLK_RTC8M:
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+ src_clk_freq = s_ledc_slow_clk_8M;
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+ break;
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+#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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+ case LEDC_SLOW_CLK_XTAL:
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+ src_clk_freq = rtc_clk_xtal_freq_get() * 1000000;
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+ break;
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+#endif
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+ }
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+
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+ return src_clk_freq;
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+}
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+
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+
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static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_intr_type_t type)
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{
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portENTER_CRITICAL(&ledc_spinlock);
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@@ -283,24 +306,29 @@ static inline uint32_t ledc_calculate_divisor(uint32_t src_clk_freq, int freq_hz
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* a 80MHz clock (APB).
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* If the precision is 1024 (10 bits), the resulted multiplier is:
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* (80000000 << 8) / (5000 * 1024) = 4000 (0xfa0)
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- * Let's ignore the fractional part to simplify the exaplanation, so we get
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+ * Let's ignore the fractional part to simplify the explanation, so we get
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* a result of 15 (0xf).
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* This can be interpreted as: every 15 "precision" ticks, the resulted
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* clock will go high, where one precision tick is made out of 1024 source
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* clock ticks.
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* Thus, every `15 * 1024` source clock ticks, the resulted clock will go
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- * high. */
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- return ( (uint64_t) src_clk_freq << LEDC_LL_FRACTIONAL_BITS ) / (freq_hz * precision);
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+ * high.
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+ *
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+ * NOTE: We are also going to round up the value when necessary, thanks to:
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+ * (freq_hz * precision) / 2
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+ */
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+ return ( ( (uint64_t) src_clk_freq << LEDC_LL_FRACTIONAL_BITS ) + ((freq_hz * precision) / 2 ) )
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+ / (freq_hz * precision);
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}
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-static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precision, ledc_clk_cfg_t* clk_target)
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+static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precision, ledc_slow_clk_sel_t* clk_target)
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{
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uint32_t div_param = 0;
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uint32_t i = 0;
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uint32_t clk_freq = 0;
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/* This function will go through all the following clock sources to look
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* for a valid divisor which generates the requested frequency. */
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- const ledc_clk_cfg_t glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
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+ const ledc_slow_clk_sel_t glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
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for (i = 0; i < DIM(glb_clks); i++) {
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/* Before calculating the divisor, we need to have the RTC frequency.
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@@ -310,7 +338,7 @@ static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precis
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continue;
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}
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- clk_freq = ledc_get_src_clk_freq(glb_clks[i]);
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+ clk_freq = ledc_get_glb_clk_freq(glb_clks[i]);
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div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
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/* If the divisor is valid, we can return this value. */
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@@ -368,7 +396,7 @@ static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mo
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* by the caller.
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*/
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static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
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- ledc_clk_src_t* clk_source, ledc_clk_cfg_t* clk_target)
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+ ledc_clk_src_t* clk_source, ledc_slow_clk_sel_t* clk_target)
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{
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uint32_t div_param = 0;
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@@ -393,6 +421,35 @@ static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint3
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return div_param;
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}
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+static ledc_slow_clk_sel_t ledc_clk_cfg_to_global_clk(const ledc_clk_cfg_t clk_cfg)
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+{
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+ /* Initialization required for preventing a compiler warning */
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+ ledc_slow_clk_sel_t glb_clk = LEDC_SLOW_CLK_APB;
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+
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+ switch (clk_cfg) {
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+ case LEDC_USE_APB_CLK:
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+ glb_clk = LEDC_SLOW_CLK_APB;
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+ break;
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+ case LEDC_USE_RTC8M_CLK:
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+ glb_clk = LEDC_SLOW_CLK_RTC8M;
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+ break;
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+#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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+ case LEDC_USE_XTAL_CLK:
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+ glb_clk = LEDC_SLOW_CLK_XTAL;
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+ break;
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+#endif
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+#if SOC_LEDC_SUPPORT_REF_TICK
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+ case LEDC_USE_REF_TICK:
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+#endif
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+ default:
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+ /* We should not get here, REF_TICK is NOT a global clock,
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+ * it is a timer-specific clock. */
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+ assert(false);
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+ }
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+
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+ return glb_clk;
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+}
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+
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/**
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* @brief Function setting the LEDC timer divisor with the given source clock,
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* frequency and resolution. If the clock configuration passed is
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@@ -405,11 +462,13 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
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/* This variable represents the timer's mux value. It will be overwritten
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* if a timer-specific clock is used. */
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ledc_clk_src_t timer_clk_src = LEDC_SCLK;
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+ /* Store the global clock. */
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+ ledc_slow_clk_sel_t glb_clk = LEDC_SLOW_CLK_APB;
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uint32_t src_clk_freq = 0;
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if (clk_cfg == LEDC_AUTO_CLK) {
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/* User hasn't specified the speed, we should try to guess it. */
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- div_param = ledc_auto_clk_divisor(speed_mode, freq_hz, precision, &timer_clk_src, &clk_cfg);
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+ div_param = ledc_auto_clk_divisor(speed_mode, freq_hz, precision, &timer_clk_src, &glb_clk);
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} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
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/* User specified source clock(RTC8M_CLK) for low speed channel.
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@@ -425,17 +484,24 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
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/* We have the RTC clock frequency now. */
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div_param = ledc_calculate_divisor(s_ledc_slow_clk_8M, freq_hz, precision);
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+ /* Set the global clock source */
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+ glb_clk = LEDC_SLOW_CLK_RTC8M;
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+
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} else {
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#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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if (LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(speed_mode, clk_cfg)) {
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- /* Currently we can convert a timer specific clock to a source clock that
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+ /* Currently we can convert a timer-specific clock to a source clock that
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* easily because their values are identical in the enumerations (on purpose)
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* If we decide to change the values in the future, we should consider defining
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* a macro/function to convert timer-specific clock to clock source .*/
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timer_clk_src = (ledc_clk_src_t) clk_cfg;
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- }
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+ } else
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#endif
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+ {
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+ glb_clk = ledc_clk_cfg_to_global_clk(clk_cfg);
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+ }
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+
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src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
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div_param = ledc_calculate_divisor(src_clk_freq, freq_hz, precision);
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}
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@@ -462,9 +528,9 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
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#else
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if (timer_clk_src == LEDC_SCLK) {
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#endif
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- ESP_LOGD(LEDC_TAG, "In slow speed mode, using clock %d", clk_cfg);
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+ ESP_LOGD(LEDC_TAG, "In slow speed mode, using clock %d", glb_clk);
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portENTER_CRITICAL(&ledc_spinlock);
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- ledc_hal_set_slow_clk(&(p_ledc_obj[speed_mode]->ledc_hal), clk_cfg);
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+ ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);
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portEXIT_CRITICAL(&ledc_spinlock);
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}
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Omar Chebib