esp32s2: fix "loadable ELF" build

Closes IDF-1346

components/esp32s2/ld/esp32s2.ld

@@ -46,6 +46,7 @@ MEMORY
   /* IRAM for CPU.*/
   iram0_0_seg (RX) :                 org = IRAM_ORG, len = IRAM_SIZE
 
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Even though the segment name is iram, it is actually mapped to flash
   */
   iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20
@@ -57,15 +58,18 @@ MEMORY
     header. Setting this offset makes it simple to meet the flash cache MMU's
     constraint that (paddr % 64KB == vaddr % 64KB).)
   */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
 
   /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
   dram0_0_seg (RW) :                 org = DRAM_ORG, len = DRAM_SIZE
 
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
   drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20
 
   /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
   /* RTC fast memory (executable). Persists over deep sleep.
    */
@@ -101,3 +105,15 @@ REGION_ALIAS("rtc_data_location", rtc_slow_seg );
 #else
 REGION_ALIAS("rtc_data_location", rtc_data_seg );
 #endif
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  REGION_ALIAS("default_code_seg", iram0_2_seg);
+#else
+  REGION_ALIAS("default_code_seg", iram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+#else
+  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

components/esp32s2/ld/esp32s2.project.ld.in

@@ -307,7 +307,7 @@ SECTIONS
     *(.tbss.*)
     _thread_local_end = ABSOLUTE(.);
     . = ALIGN(4);
-  } >drom0_0_seg
+  } >default_rodata_seg
 
   .flash.text :
   {
@@ -329,5 +329,25 @@ SECTIONS
        the flash.text segment.
     */
     _flash_cache_start = ABSOLUTE(0);
-  } >iram0_2_seg
+  } >default_code_seg
+
+  /* Marks the end of IRAM code segment */
+  .iram0.text_end (NOLOAD) :
+  {
+    . = ALIGN (4);
+    _iram_end = ABSOLUTE(.);
+  } > iram0_0_seg
+
+  /* Marks the end of data, bss and possibly rodata  */
+  .dram0.heap_start (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _heap_start = ABSOLUTE(.);
+  } > dram0_0_seg
 }
+
+ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
+          "IRAM0 segment data does not fit.")
+
+ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
+          "DRAM segment data does not fit.")