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@@ -395,8 +395,12 @@ static void IRAM_ATTR flush_uarts(void)
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}
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}
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-static void IRAM_ATTR suspend_uarts(void)
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+/**
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+ * Suspend enabled uarts and return suspended uarts bit map
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+ */
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+static uint32_t IRAM_ATTR suspend_uarts(void)
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{
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+ uint32_t suspended_uarts_bmap = 0;
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for (int i = 0; i < SOC_UART_NUM; ++i) {
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#ifndef CONFIG_IDF_TARGET_ESP32
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if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
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@@ -404,6 +408,7 @@ static void IRAM_ATTR suspend_uarts(void)
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}
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#endif
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uart_ll_force_xoff(i);
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+ suspended_uarts_bmap |= BIT(i);
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#if SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
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uint32_t uart_fsm = 0;
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do {
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@@ -413,17 +418,16 @@ static void IRAM_ATTR suspend_uarts(void)
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while (uart_ll_get_fsm_status(i) != 0) {}
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#endif
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}
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+ return suspended_uarts_bmap;
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}
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-static void IRAM_ATTR resume_uarts(void)
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+static void IRAM_ATTR resume_uarts(uint32_t uarts_resume_bmap)
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{
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for (int i = 0; i < SOC_UART_NUM; ++i) {
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-#ifndef CONFIG_IDF_TARGET_ESP32
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- if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
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- continue;
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+ if (uarts_resume_bmap & 0x1) {
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+ uart_ll_force_xon(i);
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}
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-#endif
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- uart_ll_force_xon(i);
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+ uarts_resume_bmap >>= 1;
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}
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}
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@@ -488,6 +492,8 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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bool deep_sleep = (mode == ESP_SLEEP_MODE_DEEP_SLEEP);
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bool should_skip_sleep = false;
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+ uint32_t suspended_uarts_bmap = 0;
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+
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#if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
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//Keep the RTC8M_CLK on if RTC clock is rc_fast_d256.
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@@ -639,7 +645,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
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} else
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#endif
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{
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- suspend_uarts();
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+ suspended_uarts_bmap = suspend_uarts();
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}
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}
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@@ -730,7 +736,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
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}
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// re-enable UART output
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- resume_uarts();
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+ resume_uarts(suspended_uarts_bmap);
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s_lightsleep_cnt++;
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return result;
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}
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