driver: Add adc_digi single conversion mode

- add lock for single read and continuous read APIs
- update onetime read start singal delay for hardware limitation[*]
- move adc_caps to soc_caps.h
- update license dates

[*] There is a hardware limitation. If the APB clock frequency is high, the
step of this reg signal: ``onetime_start`` may not be captured by the
ADC digital controller (when its clock frequency is too slow). A rough
estimate for this step should be at least 3 ADC digital controller
clock cycle.

components/driver/esp32c3/adc.c

@@ -1,4 +1,4 @@
-// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,22 +15,22 @@
 #include <esp_types.h>
 #include <stdlib.h>
 #include <ctype.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "esp_intr_alloc.h"
 #include "esp_log.h"
 #include "sys/lock.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/timers.h"
-#include "esp_intr_alloc.h"
+#include "freertos/ringbuf.h"
+#include "esp32c3/rom/ets_sys.h"
 #include "driver/periph_ctrl.h"
-#include "driver/rtc_io.h"
-#include "driver/rtc_cntl.h"
 #include "driver/gpio.h"
 #include "driver/adc.h"
-#include "sdkconfig.h"
-
-#include "esp32c3/rom/ets_sys.h"
 #include "hal/adc_types.h"
 #include "hal/adc_hal.h"
+#include "hal/dma_types.h"
 
 #define ADC_CHECK_RET(fun_ret) ({                  \
     if (fun_ret != ESP_OK) {                                \
@@ -57,15 +57,472 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
 #define ADC_EXIT_CRITICAL()  portEXIT_CRITICAL(&rtc_spinlock)
 
 /*---------------------------------------------------------------
-                    Digital controller setting
+                    Digital Controller Context
 ---------------------------------------------------------------*/
-esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
+/**
+ * 1. adc_digi_mutex: this mutex lock is used for ADC digital controller. On ESP32-C3, the ADC single read APIs (unit1 & unit2)
+ * and ADC DMA continuous read APIs share the ``apb_saradc_struct.h`` regs.
+ *
+ * 2. sar_adc_mutex: this mutex lock is used for SARADC2 module. On ESP32C-C3, the ADC single read APIs (unit2), ADC DMA
+ * continuous read APIs and WIFI share the SARADC2 analog IP.
+ *
+ * Sequence:
+ *          Acquire: 1. sar_adc_mutex;  2. adc_digi_mutex;
+ *          Release: 1. adc_digi_mutex; 2. sar_adc_mutex;
+ */
+static _lock_t adc_digi_mutex;
+#define ADC_DIGI_LOCK_ACQUIRE()     _lock_acquire(&adc_digi_mutex)
+#define ADC_DIGI_LOCK_RELEASE()     _lock_release(&adc_digi_mutex)
+static _lock_t sar_adc2_mutex;
+#define SAC_ADC2_LOCK_ACQUIRE()     _lock_acquire(&sar_adc2_mutex)
+#define SAC_ADC2_LOCK_RELEASE()     _lock_release(&sar_adc2_mutex)
+
+#define INTERNAL_BUF_NUM 5
+#define IN_SUC_EOF_BIT GDMA_LL_EVENT_RX_SUC_EOF
+
+typedef struct adc_digi_context_t {
+    intr_handle_t           dma_intr_hdl;               //MD interrupt handle
+    uint32_t                bytes_between_intr;         //bytes between in suc eof intr
+    uint8_t                 *rx_dma_buf;                //dma buffer
+    adc_dma_hal_context_t   hal_dma;                    //dma context (hal)
+    adc_dma_hal_config_t    hal_dma_config;             //dma config (hal)
+    RingbufHandle_t         ringbuf_hdl;                //RX ringbuffer handler
+    bool                    ringbuf_overflow_flag;      //1: ringbuffer overflow
+    bool                    driver_start_flag;          //1: driver is started; 0: driver is stoped
+    bool                    use_adc2;                   //1: ADC unit2 will be used; 0: ADC unit2 won't be used. This determines whether to acquire sar_adc2_mutex lock or not.
+    adc_digi_config_t       digi_controller_config;     //Digital Controller Configuration
+} adc_digi_context_t;
+
+static const char* ADC_DMA_TAG = "ADC_DMA:";
+static adc_digi_context_t *s_adc_digi_ctx = NULL;
+
+
+/*---------------------------------------------------------------
+                   ADC Continuous Read Mode (via DMA)
+---------------------------------------------------------------*/
+static void adc_dma_intr(void* arg);
+
+static int8_t adc_digi_get_io_num(uint8_t adc_unit, uint8_t adc_channel)
+{
+    return adc_channel_io_map[adc_unit][adc_channel];
+}
+
+static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
 {
     esp_err_t ret = ESP_OK;
-    ADC_ENTER_CRITICAL();
-    adc_hal_digi_controller_config(config);
-    ADC_EXIT_CRITICAL();
+    uint64_t gpio_mask = 0;
+    uint32_t n = 0;
+    int8_t io = 0;
+
+    while (channel_mask) {
+        if (channel_mask & 0x1) {
+            io = adc_digi_get_io_num(adc_unit, n);
+            if (io < 0) {
+                return ESP_ERR_INVALID_ARG;
+            }
+            gpio_mask |= BIT64(io);
+        }
+        channel_mask = channel_mask >> 1;
+        n++;
+    }
+
+    gpio_config_t cfg = {
+        .pin_bit_mask = gpio_mask,
+        .mode = GPIO_MODE_DISABLE,
+    };
+    ret = gpio_config(&cfg);
+
+    return ret;
+}
+
+esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
+{
+    esp_err_t ret = ESP_OK;
+
+    s_adc_digi_ctx = calloc(1, sizeof(adc_digi_context_t));
+    if (s_adc_digi_ctx == NULL) {
+        ret = ESP_ERR_NO_MEM;
+        goto cleanup;
+    }
+
+    ret = esp_intr_alloc(SOC_GDMA_ADC_INTR_SOURCE, 0, adc_dma_intr, (void *)s_adc_digi_ctx, &s_adc_digi_ctx->dma_intr_hdl);
+    if (ret != ESP_OK) {
+        goto cleanup;
+    }
+
+    //ringbuffer
+    s_adc_digi_ctx->ringbuf_hdl = xRingbufferCreate(init_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF);
+    if (!s_adc_digi_ctx->ringbuf_hdl) {
+        ret = ESP_ERR_NO_MEM;
+        goto cleanup;
+    }
+
+    //malloc internal buffer
+    s_adc_digi_ctx->bytes_between_intr = init_config->conv_num_each_intr;
+    s_adc_digi_ctx->rx_dma_buf = heap_caps_calloc(1, s_adc_digi_ctx->bytes_between_intr * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL);
+    if (!s_adc_digi_ctx->rx_dma_buf) {
+        ret = ESP_ERR_NO_MEM;
+        goto cleanup;
+    }
+
+    //malloc dma descriptor
+    s_adc_digi_ctx->hal_dma_config.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_DMA);
+    if (!s_adc_digi_ctx->hal_dma_config.rx_desc) {
+        ret = ESP_ERR_NO_MEM;
+        goto cleanup;
+    }
+    s_adc_digi_ctx->hal_dma_config.desc_max_num = INTERNAL_BUF_NUM;
+    s_adc_digi_ctx->hal_dma_config.dma_chan = init_config->dma_chan;
+
+    //malloc pattern table
+    s_adc_digi_ctx->digi_controller_config.adc_pattern = calloc(1, SOC_ADC_PATT_LEN_MAX * sizeof(adc_digi_pattern_table_t));
+    if (!s_adc_digi_ctx->digi_controller_config.adc_pattern) {
+        ret = ESP_ERR_NO_MEM;
+        goto cleanup;
+    }
+
+    if (init_config->adc1_chan_mask) {
+        ret = adc_digi_gpio_init(ADC_NUM_1, init_config->adc1_chan_mask);
+        if (ret != ESP_OK) {
+            goto cleanup;
+        }
+    }
+    if (init_config->adc2_chan_mask) {
+        ret = adc_digi_gpio_init(ADC_NUM_2, init_config->adc2_chan_mask);
+        if (ret != ESP_OK) {
+            goto cleanup;
+        }
+    }
+
+    periph_module_enable(PERIPH_SARADC_MODULE);
+    periph_module_enable(PERIPH_GDMA_MODULE);
+
+    return ret;
+
+cleanup:
+    adc_digi_deinitialize();
     return ret;
+
+}
+
+static IRAM_ATTR void adc_dma_intr(void *arg)
+{
+    portBASE_TYPE taskAwoken = 0;
+    BaseType_t ret;
+
+    //clear the in suc eof interrupt
+    adc_hal_digi_clr_intr(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
+
+    while (s_adc_digi_ctx->hal_dma_config.cur_desc_ptr->dw0.owner == 0) {
+
+        dma_descriptor_t *current_desc = s_adc_digi_ctx->hal_dma_config.cur_desc_ptr;
+        ret = xRingbufferSendFromISR(s_adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken);
+        if (ret == pdFALSE) {
+            //ringbuffer overflow
+            s_adc_digi_ctx->ringbuf_overflow_flag = 1;
+        }
+
+        s_adc_digi_ctx->hal_dma_config.desc_cnt += 1;
+        //cycle the dma descriptor and buffers
+        s_adc_digi_ctx->hal_dma_config.cur_desc_ptr = s_adc_digi_ctx->hal_dma_config.cur_desc_ptr->next;
+        if (!s_adc_digi_ctx->hal_dma_config.cur_desc_ptr) {
+            break;
+        }
+    }
+
+    if (!s_adc_digi_ctx->hal_dma_config.cur_desc_ptr) {
+
+        assert(s_adc_digi_ctx->hal_dma_config.desc_cnt == s_adc_digi_ctx->hal_dma_config.desc_max_num);
+        //reset the current descriptor status
+        s_adc_digi_ctx->hal_dma_config.cur_desc_ptr = s_adc_digi_ctx->hal_dma_config.rx_desc;
+        s_adc_digi_ctx->hal_dma_config.desc_cnt = 0;
+
+        //start next turns of dma operation
+        adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+    }
+
+    if(taskAwoken == pdTRUE) {
+        portYIELD_FROM_ISR();
+    }
+}
+
+esp_err_t adc_digi_start(void)
+{
+    if (s_adc_digi_ctx->driver_start_flag != 0) {
+        ESP_LOGE(ADC_TAG, "The driver is already started");
+        return ESP_ERR_INVALID_STATE;
+    }
+    //reset flags
+    s_adc_digi_ctx->ringbuf_overflow_flag = 0;
+    s_adc_digi_ctx->driver_start_flag = 1;
+
+    //When using SARADC2 module, this task needs to be protected from WIFI
+    if (s_adc_digi_ctx->use_adc2) {
+        SAC_ADC2_LOCK_ACQUIRE();
+    }
+    ADC_DIGI_LOCK_ACQUIRE();
+
+    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
+    adc_hal_init();
+    adc_hal_arbiter_config(&config);
+    adc_hal_digi_init(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+    adc_hal_digi_controller_config(&s_adc_digi_ctx->digi_controller_config);
+
+    //create dma descriptors
+    adc_hal_digi_dma_multi_descriptor(&s_adc_digi_ctx->hal_dma_config, s_adc_digi_ctx->rx_dma_buf, s_adc_digi_ctx->bytes_between_intr, s_adc_digi_ctx->hal_dma_config.desc_max_num);
+    adc_hal_digi_set_eof_num(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, (s_adc_digi_ctx->bytes_between_intr)/4);
+    //set the current descriptor pointer
+    s_adc_digi_ctx->hal_dma_config.cur_desc_ptr = s_adc_digi_ctx->hal_dma_config.rx_desc;
+    s_adc_digi_ctx->hal_dma_config.desc_cnt = 0;
+
+    //enable in suc eof intr
+    adc_hal_digi_ena_intr(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
+    //start DMA
+    adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+    //start ADC
+    adc_hal_digi_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+
+    return ESP_OK;
+}
+
+esp_err_t adc_digi_stop(void)
+{
+    if (s_adc_digi_ctx->driver_start_flag != 1) {
+        ESP_LOGE(ADC_TAG, "The driver is already stopped");
+        return ESP_ERR_INVALID_STATE;
+    }
+    s_adc_digi_ctx->driver_start_flag = 0;
+
+    //disable the in suc eof intrrupt
+    adc_hal_digi_dis_intr(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
+    //clear the in suc eof interrupt
+    adc_hal_digi_clr_intr(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
+    //stop DMA
+    adc_hal_digi_rxdma_stop(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+    //stop ADC
+    adc_hal_digi_stop(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config);
+    adc_hal_digi_deinit();
+
+    ADC_DIGI_LOCK_RELEASE();
+    //When using SARADC2 module, this task needs to be protected from WIFI
+    if (s_adc_digi_ctx->use_adc2) {
+        SAC_ADC2_LOCK_RELEASE();
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms)
+{
+    TickType_t ticks_to_wait;
+    esp_err_t ret = ESP_OK;
+    uint8_t *data = NULL;
+    size_t size = 0;
+
+    ticks_to_wait = timeout_ms / portTICK_RATE_MS;
+    if (timeout_ms == ADC_MAX_DELAY) {
+        ticks_to_wait = portMAX_DELAY;
+    }
+
+    data = xRingbufferReceiveUpTo(s_adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max);
+    if (!data) {
+        ESP_LOGW(ADC_DMA_TAG, "No data, increase timeout or reduce conv_num_each_intr");
+        ret = ESP_ERR_TIMEOUT;
+        *out_length = 0;
+        return ret;
+    }
+
+    memcpy(buf, data, size);
+    vRingbufferReturnItem(s_adc_digi_ctx->ringbuf_hdl, data);
+    assert((size % 4) == 0);
+    *out_length = size;
+
+    if (s_adc_digi_ctx->ringbuf_overflow_flag) {
+        ret = ESP_ERR_INVALID_STATE;
+    }
+    return ret;
+}
+
+esp_err_t adc_digi_deinitialize(void)
+{
+    if (!s_adc_digi_ctx) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    if (s_adc_digi_ctx->driver_start_flag != 0) {
+        ESP_LOGE(ADC_TAG, "The driver is not stopped");
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    if (s_adc_digi_ctx->dma_intr_hdl) {
+        esp_intr_free(s_adc_digi_ctx->dma_intr_hdl);
+    }
+
+    if(s_adc_digi_ctx->ringbuf_hdl) {
+        vRingbufferDelete(s_adc_digi_ctx->ringbuf_hdl);
+        s_adc_digi_ctx->ringbuf_hdl = NULL;
+    }
+
+    free(s_adc_digi_ctx->hal_dma_config.rx_desc);
+    free(s_adc_digi_ctx->digi_controller_config.adc_pattern);
+    free(s_adc_digi_ctx);
+    s_adc_digi_ctx = NULL;
+
+    periph_module_disable(PERIPH_SARADC_MODULE);
+    periph_module_disable(PERIPH_GDMA_MODULE);
+
+    return ESP_OK;
+}
+
+/*---------------------------------------------------------------
+                    ADC Single Read Mode
+---------------------------------------------------------------*/
+static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX];    //Array saving attenuate of each channel of ADC1, used by single read API
+static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX];    //Array saving attenuate of each channel of ADC2, used by single read API
+
+esp_err_t adc1_config_width(adc_bits_width_t width_bit)
+{
+    //On ESP32C3, the data width is always 13-bits.
+    if (width_bit != ADC_WIDTH_BIT_13) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
+{
+    ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
+    ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG);
+
+    esp_err_t ret = ESP_OK;
+    s_atten1_single[channel] = atten;
+    ret = adc_digi_gpio_init(ADC_NUM_1, BIT(channel));
+
+    return ret;
+}
+
+int adc1_get_raw(adc1_channel_t channel)
+{
+    int result = 0;
+    adc_digi_config_t dig_cfg = {
+        .conv_limit_en = 0,
+        .conv_limit_num = 250,
+        .interval = 40,
+        .dig_clk.use_apll = 0,
+        .dig_clk.div_num = 1,
+        .dig_clk.div_a = 0,
+        .dig_clk.div_b = 1,
+    };
+
+    ADC_DIGI_LOCK_ACQUIRE();
+
+    adc_hal_digi_controller_config(&dig_cfg);
+
+    adc_hal_intr_clear(ADC_EVENT_ADC1_DONE);
+
+    adc_hal_onetime_channel(ADC_NUM_1, channel);
+    adc_hal_set_onetime_atten(s_atten1_single[channel]);
+
+    adc_hal_adc1_onetime_sample_enable(true);
+    //Trigger single read.
+    adc_hal_onetime_start(&dig_cfg);
+
+    while (!adc_hal_intr_get_raw(ADC_EVENT_ADC1_DONE));
+    adc_hal_intr_clear(ADC_EVENT_ADC1_DONE);
+    adc_hal_adc1_onetime_sample_enable(false);
+
+    result = adc_hal_adc1_read();
+    adc_hal_digi_deinit();
+
+    ADC_DIGI_LOCK_RELEASE();
+
+    return result;
+}
+
+esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
+{
+    ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
+    ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG);
+
+    esp_err_t ret = ESP_OK;
+    s_atten2_single[channel] = atten;
+    ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel));
+
+    return ret;
+}
+
+esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
+{
+    //On ESP32C3, the data width is always 13-bits.
+    if (width_bit != ADC_WIDTH_BIT_13) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    adc_digi_config_t dig_cfg = {
+        .conv_limit_en = 0,
+        .conv_limit_num = 250,
+        .interval = 40,
+        .dig_clk.use_apll = 0,
+        .dig_clk.div_num = 1,
+        .dig_clk.div_a = 0,
+        .dig_clk.div_b = 1,
+    };
+
+    SAC_ADC2_LOCK_ACQUIRE();
+    ADC_DIGI_LOCK_ACQUIRE();
+
+    adc_hal_digi_controller_config(&dig_cfg);
+
+    adc_hal_intr_clear(ADC_EVENT_ADC2_DONE);
+
+    adc_hal_onetime_channel(ADC_NUM_2, channel);
+    adc_hal_set_onetime_atten(s_atten2_single[channel]);
+
+    adc_hal_adc2_onetime_sample_enable(true);
+    //Trigger single read.
+    adc_hal_onetime_start(&dig_cfg);
+
+    while (!adc_hal_intr_get_raw(ADC_EVENT_ADC2_DONE));
+    adc_hal_intr_clear(ADC_EVENT_ADC2_DONE);
+    adc_hal_adc2_onetime_sample_enable(false);
+
+    *raw_out = adc_hal_adc2_read();
+    adc_hal_digi_deinit();
+
+    ADC_DIGI_LOCK_RELEASE();
+    SAC_ADC2_LOCK_RELEASE();
+
+    return ESP_OK;
+}
+
+
+/*---------------------------------------------------------------
+                    Digital controller setting
+---------------------------------------------------------------*/
+esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
+{
+    if (!s_adc_digi_ctx) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    s_adc_digi_ctx->digi_controller_config.conv_limit_en = config->conv_limit_en;
+    s_adc_digi_ctx->digi_controller_config.conv_limit_num = config->conv_limit_num;
+    s_adc_digi_ctx->digi_controller_config.adc_pattern_len = config->adc_pattern_len;
+    s_adc_digi_ctx->digi_controller_config.interval =  config->interval;
+    s_adc_digi_ctx->digi_controller_config.dig_clk = config-> dig_clk;
+    s_adc_digi_ctx->digi_controller_config.dma_eof_num = config->dma_eof_num;
+    memcpy(s_adc_digi_ctx->digi_controller_config.adc_pattern, config->adc_pattern, config->adc_pattern_len * sizeof(adc_digi_pattern_table_t));
+
+    //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
+    s_adc_digi_ctx->use_adc2 = 0;
+    for (int i = 0; i < config->adc_pattern_len; i++) {
+        if (config->adc_pattern->unit == ADC_NUM_2) {
+            s_adc_digi_ctx->use_adc2 = 1;
+        }
+    }
+
+    return ESP_OK;
 }
 
 esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config)
@@ -176,7 +633,6 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
  * @brief Get the filtered data of adc digital controller filter. For debug.
  *        The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API.
  *
- * @note For ESP32S2, The filter will filter all the enabled channel data of the each ADC unit at the same time.
  * @param idx Filter index.
  * @return Filtered data. if <0, the read data invalid.
  */
@@ -270,7 +726,7 @@ uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit)
     return ret;
 }
 
-static uint8_t s_isr_registered = 0;
+static bool s_isr_registered = 0;
 static intr_handle_t s_adc_isr_handle = NULL;
 
 esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags)
@@ -300,291 +756,3 @@ esp_err_t adc_digi_isr_deregister(void)
 /*---------------------------------------------------------------
                     RTC controller setting
 ---------------------------------------------------------------*/
-
-
-//This feature is currently supported on ESP32C3, will be supported on other chips soon
-/*---------------------------------------------------------------
-                    DMA setting
----------------------------------------------------------------*/
-#include "soc/system_reg.h"
-#include "hal/dma_types.h"
-#include "hal/gdma_ll.h"
-#include "hal/adc_hal.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/ringbuf.h"
-#include <string.h>
-
-#define INTERNAL_BUF_NUM 5
-#define IN_SUC_EOF_BIT GDMA_LL_EVENT_RX_SUC_EOF
-
-typedef struct adc_digi_context_t {
-    intr_handle_t           dma_intr_hdl;           //MD interrupt handle
-    uint32_t                bytes_between_intr;     //bytes between in suc eof intr
-    uint8_t                 *rx_dma_buf;            //dma buffer
-    adc_dma_hal_context_t   hal_dma;                //dma context (hal)
-    adc_dma_hal_config_t    hal_dma_config;         //dma config (hal)
-    RingbufHandle_t         ringbuf_hdl;            //RX ringbuffer handler
-    bool                    ringbuf_overflow_flag;  //1: ringbuffer overflow
-    bool                    driver_state_flag;      //1: driver is started; 2: driver is stoped
-} adc_digi_context_t;
-
-
-static const char* ADC_DMA_TAG = "ADC_DMA:";
-static adc_digi_context_t *adc_digi_ctx = NULL;
-
-static void adc_dma_intr(void* arg);
-
-static int8_t adc_digi_get_io_num(uint8_t adc_unit, uint8_t adc_channel)
-{
-    return adc_channel_io_map[adc_unit][adc_channel];
-}
-
-static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
-{
-    esp_err_t ret = ESP_OK;
-    uint64_t gpio_mask = 0;
-    uint32_t n = 0;
-    int8_t io = 0;
-
-    while (channel_mask) {
-        if (channel_mask & 0x1) {
-            io = adc_digi_get_io_num(adc_unit, n);
-            if (io < 0) {
-                return ESP_ERR_INVALID_ARG;
-            }
-            gpio_mask |= BIT64(io);
-        }
-        channel_mask = channel_mask >> 1;
-        n++;
-    }
-
-    gpio_config_t cfg = {
-        .pin_bit_mask = gpio_mask,
-        .mode = GPIO_MODE_DISABLE,
-    };
-    gpio_config(&cfg);
-
-    return ret;
-}
-
-esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
-{
-    esp_err_t ret = ESP_OK;
-
-    adc_digi_ctx = calloc(1, sizeof(adc_digi_context_t));
-    if (adc_digi_ctx == NULL) {
-        ret = ESP_ERR_NO_MEM;
-        goto cleanup;
-    }
-
-    ret = esp_intr_alloc(SOC_GDMA_ADC_INTR_SOURCE, 0, adc_dma_intr, (void *)adc_digi_ctx, &adc_digi_ctx->dma_intr_hdl);
-    if (ret != ESP_OK) {
-        goto cleanup;
-    }
-
-    //ringbuffer
-    adc_digi_ctx->ringbuf_hdl = xRingbufferCreate(init_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF);
-    if (!adc_digi_ctx->ringbuf_hdl) {
-        ret = ESP_ERR_NO_MEM;
-        goto cleanup;
-    }
-
-    //malloc internal buffer
-    adc_digi_ctx->bytes_between_intr = init_config->conv_num_each_intr;
-    adc_digi_ctx->rx_dma_buf = heap_caps_calloc(1, adc_digi_ctx->bytes_between_intr * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL);
-    if (!adc_digi_ctx->rx_dma_buf) {
-        ret = ESP_ERR_NO_MEM;
-        goto cleanup;
-    }
-
-    //malloc dma descriptor
-    adc_digi_ctx->hal_dma_config.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_DMA);
-    if (!adc_digi_ctx->hal_dma_config.rx_desc) {
-        ret = ESP_ERR_NO_MEM;
-        goto cleanup;
-    }
-    adc_digi_ctx->hal_dma_config.desc_max_num = INTERNAL_BUF_NUM;
-    adc_digi_ctx->hal_dma_config.dma_chan = init_config->dma_chan;
-
-    if (init_config->adc1_chan_mask) {
-        ret = adc_digi_gpio_init(ADC_NUM_1, init_config->adc1_chan_mask);
-        if (ret != ESP_OK) {
-            goto cleanup;
-        }
-    }
-    if (init_config->adc2_chan_mask) {
-        ret = adc_digi_gpio_init(ADC_NUM_2, init_config->adc2_chan_mask);
-        if (ret != ESP_OK) {
-            goto cleanup;
-        }
-    }
-
-    periph_module_enable(PERIPH_SARADC_MODULE);
-    periph_module_enable(PERIPH_GDMA_MODULE);
-    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
-    ADC_ENTER_CRITICAL();
-    adc_hal_init();
-    adc_hal_arbiter_config(&config);
-    adc_hal_digi_init(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-    ADC_EXIT_CRITICAL();
-
-    return ret;
-
-cleanup:
-    adc_digi_deinitialize();
-    return ret;
-
-}
-
-static IRAM_ATTR void adc_dma_intr(void *arg)
-{
-    portBASE_TYPE taskAwoken = 0;
-    BaseType_t ret;
-
-    //clear the in suc eof interrupt
-    adc_hal_digi_clr_intr(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
-
-    while (adc_digi_ctx->hal_dma_config.cur_desc_ptr->dw0.owner == 0) {
-
-        dma_descriptor_t *current_desc = adc_digi_ctx->hal_dma_config.cur_desc_ptr;
-        ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken);
-        if (ret == pdFALSE) {
-            //ringbuffer overflow
-            adc_digi_ctx->ringbuf_overflow_flag = 1;
-        }
-
-        adc_digi_ctx->hal_dma_config.desc_cnt += 1;
-        //cycle the dma descriptor and buffers
-        adc_digi_ctx->hal_dma_config.cur_desc_ptr = adc_digi_ctx->hal_dma_config.cur_desc_ptr->next;
-        if (!adc_digi_ctx->hal_dma_config.cur_desc_ptr) {
-            break;
-        }
-    }
-
-    if (!adc_digi_ctx->hal_dma_config.cur_desc_ptr) {
-
-        assert(adc_digi_ctx->hal_dma_config.desc_cnt == adc_digi_ctx->hal_dma_config.desc_max_num);
-        //reset the current descriptor status
-        adc_digi_ctx->hal_dma_config.cur_desc_ptr = adc_digi_ctx->hal_dma_config.rx_desc;
-        adc_digi_ctx->hal_dma_config.desc_cnt = 0;
-
-        //start next turns of dma operation
-        adc_hal_digi_rxdma_start(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-    }
-
-    if(taskAwoken == pdTRUE) {
-        portYIELD_FROM_ISR();
-    }
-}
-
-esp_err_t adc_digi_start(void)
-{
-    assert(adc_digi_ctx->driver_state_flag == 0 && "the driver is already started");
-    //reset flags
-    adc_digi_ctx->ringbuf_overflow_flag = 0;
-    adc_digi_ctx->driver_state_flag = 1;
-
-    //create dma descriptors
-    adc_hal_digi_dma_multi_descriptor(&adc_digi_ctx->hal_dma_config, adc_digi_ctx->rx_dma_buf, adc_digi_ctx->bytes_between_intr, adc_digi_ctx->hal_dma_config.desc_max_num);
-    adc_hal_digi_set_eof_num(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config, (adc_digi_ctx->bytes_between_intr)/4);
-    //set the current descriptor pointer
-    adc_digi_ctx->hal_dma_config.cur_desc_ptr = adc_digi_ctx->hal_dma_config.rx_desc;
-    adc_digi_ctx->hal_dma_config.desc_cnt = 0;
-
-    //enable in suc eof intr
-    adc_hal_digi_ena_intr(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config, GDMA_LL_EVENT_RX_SUC_EOF);
-    //start DMA
-    adc_hal_digi_rxdma_start(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-    //start ADC
-    adc_hal_digi_start(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-
-    return ESP_OK;
-}
-
-esp_err_t adc_digi_stop(void)
-{
-    assert(adc_digi_ctx->driver_state_flag == 1 && "the driver is already stoped");
-    adc_digi_ctx->driver_state_flag = 0;
-
-    //disable the in suc eof intrrupt
-    adc_hal_digi_dis_intr(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
-    //clear the in suc eof interrupt
-    adc_hal_digi_clr_intr(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT);
-    //stop DMA
-    adc_hal_digi_rxdma_stop(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-    //stop ADC
-    adc_hal_digi_stop(&adc_digi_ctx->hal_dma, &adc_digi_ctx->hal_dma_config);
-
-    return ESP_OK;
-}
-
-esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms)
-{
-    TickType_t ticks_to_wait;
-    esp_err_t ret = ESP_OK;
-    uint8_t *data = NULL;
-    size_t size = 0;
-
-    ticks_to_wait = timeout_ms / portTICK_RATE_MS;
-    if (timeout_ms == ADC_MAX_DELAY) {
-        ticks_to_wait = portMAX_DELAY;
-    }
-
-    data = xRingbufferReceiveUpTo(adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max);
-    if (!data) {
-        ESP_EARLY_LOGW(ADC_DMA_TAG, "No data, increase timeout or reduce conv_num_each_intr");
-        ret = ESP_ERR_TIMEOUT;
-        *out_length = 0;
-        return ret;
-    }
-
-    memcpy(buf, data, size);
-    vRingbufferReturnItem(adc_digi_ctx->ringbuf_hdl, data);
-    assert((size % 4) == 0);
-    *out_length = size;
-
-    if (adc_digi_ctx->ringbuf_overflow_flag) {
-        ret = ESP_ERR_INVALID_STATE;
-    }
-    return ret;
-}
-
-static esp_err_t adc_digi_deinit(void)
-{
-    ADC_ENTER_CRITICAL();
-    adc_hal_digi_deinit();
-    ADC_EXIT_CRITICAL();
-    return ESP_OK;
-}
-
-esp_err_t adc_digi_deinitialize(void)
-{
-    assert(adc_digi_ctx->driver_state_flag == 0 && "the driver is not stoped");
-
-    if (adc_digi_ctx == NULL) {
-        return ESP_ERR_INVALID_STATE;
-    }
-
-    if (adc_digi_ctx->dma_intr_hdl) {
-        esp_intr_free(adc_digi_ctx->dma_intr_hdl);
-    }
-
-    if(adc_digi_ctx->ringbuf_hdl) {
-        vRingbufferDelete(adc_digi_ctx->ringbuf_hdl);
-        adc_digi_ctx->ringbuf_hdl = NULL;
-    }
-
-    if (adc_digi_ctx->hal_dma_config.rx_desc) {
-        free(adc_digi_ctx->hal_dma_config.rx_desc);
-    }
-
-    free(adc_digi_ctx);
-    adc_digi_ctx = NULL;
-
-    adc_digi_deinit();
-    periph_module_disable(PERIPH_SARADC_MODULE);
-    periph_module_disable(PERIPH_GDMA_MODULE);
-
-    return ESP_OK;
-}

components/driver/esp32c3/include/driver/adc.h

@@ -1,4 +1,4 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -57,8 +57,6 @@ esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx);
 /**
  * @brief Set adc digital controller filter configuration.
  *
- * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
- *
  * @param idx Filter index.
  * @param config See ``adc_digi_filter_t``.
  *
@@ -70,8 +68,6 @@ esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_
 /**
  * @brief Get adc digital controller filter configuration.
  *
- * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
- *
  * @param idx Filter index.
  * @param config See ``adc_digi_filter_t``.
  *
@@ -84,8 +80,6 @@ esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_
  * @brief Enable/disable adc digital controller filter.
  *        Filtering the ADC data to obtain smooth data at higher sampling rates.
  *
- * @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
- *
  * @param idx Filter index.
  * @param enable Enable/Disable filter.
  *
@@ -101,8 +95,6 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable);
 /**
  * @brief Config monitor of adc digital controller.
  *
- * @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
- *
  * @param idx Monitor index.
  * @param config See ``adc_digi_monitor_t``.
  *
@@ -114,8 +106,6 @@ esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monit
 /**
  * @brief Enable/disable monitor of adc digital controller.
  *
- * @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
- *
  * @param idx Monitor index.
  * @param enable True or false enable monitor.
  *

components/driver/include/driver/adc_common.h

@@ -307,10 +307,8 @@ esp_err_t adc_set_clk_div(uint8_t clk_div);
 /**
  * @brief Configure ADC capture width.
  *
- * @note  ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
- *
  * @param adc_unit ADC unit index
- * @param width_bit Bit capture width for ADC unit. ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
+ * @param width_bit Bit capture width for ADC unit.
  *
  * @return
  *     - ESP_OK success
@@ -397,7 +395,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
  *       the low priority controller will read the invalid ADC2 data. Default priority: Wi-Fi > RTC > Digital;
  *
  * @param channel ADC2 channel to read
- * @param width_bit Bit capture width for ADC2. ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
+ * @param width_bit Bit capture width for ADC2
  * @param raw_out the variable to hold the output data.
  *
  * @return
@@ -466,7 +464,8 @@ esp_err_t adc_digi_deinit(void);
  * @param config Pointer to digital controller paramter. Refer to ``adc_digi_config_t``.
  *
  * @return
- *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_STATE Driver state is invalid.
+ *      - ESP_OK                On success
  */
 esp_err_t adc_digi_controller_config(const adc_digi_config_t *config);
 
@@ -492,6 +491,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config);
  * @brief Start the Digital ADC and DMA peripherals. After this, the hardware starts working.
  *
  * @return
+ *         - ESP_ERR_INVALID_STATE Driver state is invalid.
  *         - ESP_OK                On success
  */
 esp_err_t adc_digi_start(void);
@@ -500,6 +500,7 @@ esp_err_t adc_digi_start(void);
  * @brief Stop the Digital ADC and DMA peripherals. After this, the hardware stops working.
  *
  * @return
+ *         - ESP_ERR_INVALID_STATE Driver state is invalid.
  *         - ESP_OK                On success
  */
 esp_err_t adc_digi_stop(void);

components/hal/adc_hal.c

@@ -1,4 +1,4 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,8 +13,11 @@
 // limitations under the License.
 
 #include "hal/adc_hal.h"
-#if !CONFIG_IDF_TARGET_ESP32C3
 #include "hal/adc_hal_conf.h"
+
+#if CONFIG_IDF_TARGET_ESP32C3
+#include "soc/soc.h"
+#include "esp_rom_sys.h"
 #endif
 
 void adc_hal_init(void)
@@ -122,4 +125,109 @@ void adc_hal_digi_init(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t
     gdma_ll_clear_interrupt_status(adc_dma_ctx->dev, dma_config->dma_chan, UINT32_MAX);
     gdma_ll_rx_connect_to_periph(adc_dma_ctx->dev, dma_config->dma_chan, GDMA_LL_TRIG_SRC_ADC_DAC);
 }
+
+/*---------------------------------------------------------------
+                    Single Read
+---------------------------------------------------------------*/
+void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config)
+{
+    /**
+     * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
+     * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller
+     * clock cycle.
+     *
+     * This limitation will be removed in hardware future versions.
+     *
+     */
+    uint32_t digi_clk = APB_CLK_FREQ / (adc_digi_config->dig_clk.div_num + adc_digi_config->dig_clk.div_a / adc_digi_config->dig_clk.div_b + 1);
+    //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough.
+    uint32_t delay = (1000 * 1000) / digi_clk + 1;
+    //3 ADC digital controller clock cycle
+    delay = delay * 3;
+    //This coefficient (8) is got from test. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
+    if (digi_clk >= APB_CLK_FREQ/8) {
+        delay = 0;
+    }
+
+    adc_ll_onetime_start(false);
+    esp_rom_delay_us(delay);
+    adc_ll_onetime_start(true);
+    //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
+}
+
+void adc_hal_adc1_onetime_sample_enable(bool enable)
+{
+    if (enable) {
+        adc_ll_adc1_onetime_sample_ena();
+    } else {
+        adc_ll_adc1_onetime_sample_dis();
+    }
+}
+
+void adc_hal_adc2_onetime_sample_enable(bool enable)
+{
+    if (enable) {
+        adc_ll_adc2_onetime_sample_ena();
+    } else {
+        adc_ll_adc2_onetime_sample_dis();
+    }
+}
+
+void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel)
+{
+    adc_ll_onetime_set_channel(unit, channel);
+}
+
+void adc_hal_set_onetime_atten(adc_atten_t atten)
+{
+    adc_ll_onetime_set_atten(atten);
+}
+
+uint32_t adc_hal_adc1_read(void)
+{
+    return adc_ll_adc1_read();
+}
+
+uint32_t adc_hal_adc2_read(void)
+{
+    return adc_ll_adc2_read();
+}
+
+//--------------------INTR-------------------------------
+static adc_ll_intr_t get_event_intr(adc_event_t event)
+{
+    adc_ll_intr_t intr_mask = 0;
+    if (event & ADC_EVENT_ADC1_DONE) {
+        intr_mask |= ADC_LL_INTR_ADC1_DONE;
+    }
+    if (event & ADC_EVENT_ADC2_DONE) {
+        intr_mask |= ADC_LL_INTR_ADC2_DONE;
+    }
+    return intr_mask;
+}
+
+void adc_hal_intr_enable(adc_event_t event)
+{
+    adc_ll_intr_enable(get_event_intr(event));
+}
+
+void adc_hal_intr_disable(adc_event_t event)
+{
+    adc_ll_intr_disable(get_event_intr(event));
+}
+
+void adc_hal_intr_clear(adc_event_t event)
+{
+    adc_ll_intr_clear(get_event_intr(event));
+}
+
+bool adc_hal_intr_get_raw(adc_event_t event)
+{
+    return adc_ll_intr_get_raw(get_event_intr(event));
+}
+
+bool adc_hal_intr_get_status(adc_event_t event)
+{
+    return adc_ll_intr_get_status(get_event_intr(event));
+}
 #endif

components/soc/esp32c3/include/soc/adc_caps.h → components/hal/esp32c3/include/hal/adc_hal_conf.h

@@ -11,13 +11,8 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-#pragma once
-
-#define SOC_ADC_PERIPH_NUM              (2)
-#define SOC_ADC_PATT_LEN_MAX            (16)
 
-#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
-#define SOC_ADC_MAX_CHANNEL_NUM         (10)
+#pragma once
 
 #define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
 #define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
@@ -29,14 +24,6 @@
 #define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
 #define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
 
-/**
- * Check if adc support digital controller (DMA) mode.
- * @value
- *      - 1 : support;
- *      - 0 : not support;
- */
-#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
-
 #define SOC_ADC_PWDET_CCT_DEFAULT           (4)
 
 #define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)

components/hal/esp32c3/include/hal/adc_ll.h

@@ -22,6 +22,8 @@
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "regi2c_ctrl.h"
+#include "esp_attr.h"
+
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,6 +49,12 @@ typedef enum {
     ADC_RTC_DATA_FAIL = -1,
 } adc_ll_rtc_raw_data_t;
 
+typedef enum {
+    ADC_LL_INTR_ADC2_DONE = BIT(30),
+    ADC_LL_INTR_ADC1_DONE = BIT(31),
+} adc_ll_intr_t;
+FLAG_ATTR(adc_ll_intr_t)
+
 #ifdef _MSC_VER
 #pragma pack(push, 1)
 #endif /* _MSC_VER */
@@ -927,6 +935,87 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
     abort(); // TODO ESP32-C3 IDF-2526
 }
 
+/*---------------------------------------------------------------
+                    Single Read
+---------------------------------------------------------------*/
+/**
+ * Trigger single read
+ *
+ * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle,
+ *            otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow.
+ *            This hardware limitation will be removed in future versions.
+ */
+static inline void adc_ll_onetime_start(bool val)
+{
+    APB_SARADC.onetime_sample.onetime_start = val;
+}
+
+static inline void adc_ll_onetime_set_channel(adc_ll_num_t unit, adc_channel_t channel)
+{
+    APB_SARADC.onetime_sample.onetime_channel = ((unit << 3) | channel);
+}
+
+static inline void adc_ll_onetime_set_atten(adc_atten_t atten)
+{
+    APB_SARADC.onetime_sample.onetime_atten = atten;
+}
+
+static inline void adc_ll_intr_enable(adc_ll_intr_t mask)
+{
+    APB_SARADC.int_ena.val |= mask;
+}
+
+static inline void adc_ll_intr_disable(adc_ll_intr_t mask)
+{
+    APB_SARADC.int_ena.val &= ~mask;
+}
+
+static inline void adc_ll_intr_clear(adc_ll_intr_t mask)
+{
+    APB_SARADC.int_clr.val |= mask;
+}
+
+static inline bool adc_ll_intr_get_raw(adc_ll_intr_t mask)
+{
+    return (APB_SARADC.int_raw.val & mask);
+}
+
+static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
+{
+    return (APB_SARADC.int_st.val & mask);
+}
+
+//--------------------------------adc1------------------------------//
+static inline void adc_ll_adc1_onetime_sample_ena(void)
+{
+    APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
+}
+
+static inline void adc_ll_adc1_onetime_sample_dis(void)
+{
+    APB_SARADC.onetime_sample.adc1_onetime_sample = 0;
+}
+
+static inline uint32_t adc_ll_adc1_read(void)
+{
+    return APB_SARADC.apb_saradc1_data_status.adc1_data;
+}
+
+//--------------------------------adc2------------------------------//
+static inline void adc_ll_adc2_onetime_sample_ena(void)
+{
+    APB_SARADC.onetime_sample.adc2_onetime_sample = 1;
+}
+
+static inline void adc_ll_adc2_onetime_sample_dis(void)
+{
+    APB_SARADC.onetime_sample.adc2_onetime_sample = 0;
+}
+
+static inline uint32_t adc_ll_adc2_read(void)
+{
+    return APB_SARADC.apb_saradc2_data_status.adc2_data;
+}
 #ifdef __cplusplus
 }
 #endif

components/hal/include/hal/adc_hal.h

@@ -245,4 +245,32 @@ void adc_hal_digi_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t
 void adc_hal_digi_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config);
 
 void adc_hal_digi_init(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config);
+
+/*---------------------------------------------------------------
+                    Single Read
+---------------------------------------------------------------*/
+void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config);
+
+void adc_hal_adc1_onetime_sample_enable(bool enable);
+
+void adc_hal_adc2_onetime_sample_enable(bool enable);
+
+void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel);
+
+void adc_hal_set_onetime_atten(adc_atten_t atten);
+
+uint32_t adc_hal_adc1_read(void);
+
+uint32_t adc_hal_adc2_read(void);
+
+void adc_hal_intr_enable(adc_event_t event);
+
+void adc_hal_intr_disable(adc_event_t event);
+
+void adc_hal_intr_clear(adc_event_t event);
+
+bool adc_hal_intr_get_raw(adc_event_t event);
+
+bool adc_hal_intr_get_status(adc_event_t event);
+
 #endif  //#if CONFIG_IDF_TARGET_ESP32C3

components/hal/include/hal/adc_types.h

@@ -81,16 +81,15 @@ typedef enum {
 /**
  * @brief ADC resolution setting option.
  *
- * @note  For ESP32-S2. Only 13 bit resolution is supported.
- *        For ESP32.   13 bit resolution is not supported.
  */
 typedef enum {
-    ADC_WIDTH_BIT_9  = 0, /*!< ADC capture width is 9Bit. Only ESP32 is supported. */
-    ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */
-    ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */
-    ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */
-#if !CONFIG_IDF_TARGET_ESP32
-    ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32-S2 is supported. */
+#if CONFIG_IDF_TARGET_ESP32
+    ADC_WIDTH_BIT_9  = 0, /*!< ADC capture width is 9Bit. */
+    ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. */
+    ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. */
+    ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. */
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+    ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. */
 #endif
     ADC_WIDTH_MAX,
 } adc_bits_width_t;
@@ -196,7 +195,7 @@ typedef struct {
                                         If (channel > ADC_CHANNEL_MAX), The data is invalid. */
             uint32_t unit:      1;  /*!<ADC unit index info. 0: ADC1; 1: ADC2.  */
             uint32_t reserved: 15;
-        };
+        } type2;
         uint32_t val;
     };
 } adc_digi_output_data_t;
@@ -412,3 +411,10 @@ typedef struct {
 } adc_digi_monitor_t;
 
 #endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+
+#if CONFIG_IDF_TARGET_ESP32C3
+typedef enum {
+    ADC_EVENT_ADC1_DONE = BIT(0),
+    ADC_EVENT_ADC2_DONE = BIT(1),
+} adc_event_t;
+#endif

components/soc/esp32c3/include/soc/soc_caps.h

@@ -24,7 +24,6 @@
 #define SOC_GDMA_ADC_INTR_SOURCE    ETS_DMA_CH0_INTR_SOURCE
 
 #include "rmt_caps.h"
-#include "adc_caps.h"
 #include "dac_caps.h"
 #include "i2c_caps.h"
 #include "mpu_caps.h"
@@ -57,3 +56,18 @@
 
 #define SOC_AES_SUPPORT_AES_128 (1)
 #define SOC_AES_SUPPORT_AES_256 (1)
+
+/*-------------------------- ADC CAPS -------------------------------*/
+#define SOC_ADC_PERIPH_NUM              (2)
+#define SOC_ADC_PATT_LEN_MAX            (16)
+
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
+#define SOC_ADC_MAX_CHANNEL_NUM         (10)
+
+/**
+ * Check if adc support digital controller (DMA) mode.
+ * @value
+ *      - 1 : support;
+ *      - 0 : not support;
+ */
+#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1