ext_mem: make memory region check strict

components/esp_psram/include/esp_private/esp_psram_extram.h

@@ -20,6 +20,8 @@ extern "C" {
  * @param[out] out_vstart PSRAM virtual address start
  * @param[out] out_vend   PSRAM virtual address end
  *
+ * @note [out_vstart, out_vend), `out_vend` isn't included.
+ *
  * @return
  *        - ESP_OK                  On success
  *        - ESP_ERR_INVALID_STATE   PSRAM is not initialized successfully
@@ -32,6 +34,8 @@ esp_err_t esp_psram_extram_get_mapped_range(intptr_t *out_vstart, intptr_t *out_
  * @param[out] out_vstart PSRAM virtual address start
  * @param[out] out_vend   PSRAM virtual address end
  *
+ * @note [out_vstart, out_vend), `out_vend` isn't included.
+ *
  * @return
  *        - ESP_OK                  On success
  *        - ESP_ERR_INVALID_STATE   PSRAM is not initialized successfully

components/hal/esp32/include/hal/cache_ll.h

@@ -37,7 +37,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0 || cache_id == 1);
     cache_bus_mask_t mask = 0;
 
-    uint32_t vaddr_end = vaddr_start + len;
+    uint32_t vaddr_end = vaddr_start + len - 1;
     if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) {
         HAL_ASSERT(false);      //out of range
     } else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) {
@@ -50,10 +50,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
         mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
         mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
     } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end <= DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS1;
     } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end <= DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(false);

components/hal/esp32c2/include/hal/cache_ll.h

@@ -53,10 +53,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0);
     cache_bus_mask_t mask = 0;
 
-    uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
         mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(0);      //Out of region

components/hal/esp32c3/include/hal/cache_ll.h

@@ -53,10 +53,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0);
     cache_bus_mask_t mask = 0;
 
-    uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(0);          //Out of region

components/hal/esp32h2/include/hal/cache_ll.h

@@ -52,10 +52,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0);
     cache_bus_mask_t mask = 0;
 
-    uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(0);      //Out of region

components/hal/esp32s2/include/hal/cache_ll.h

@@ -41,7 +41,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0);
 
     cache_bus_mask_t mask = 0;
-    uint32_t vaddr_end = vaddr_start + len;
+    uint32_t vaddr_end = vaddr_start + len - 1;
     if (vaddr_start >= IRAM1_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS1;
     } else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {

components/hal/esp32s2/include/hal/mmu_ll.h

@@ -60,14 +60,15 @@ __attribute__((always_inline))
 static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
 {
     (void)mmu_id;
-    uint32_t vaddr_end = vaddr_start + len;
-
-    return (ADDRESS_IN_DROM0(vaddr_start) && ADDRESS_IN_DROM0(vaddr_end)) ||
-           (ADDRESS_IN_IRAM1(vaddr_start) && ADDRESS_IN_IRAM1(vaddr_end)) ||
-           (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
-           (ADDRESS_IN_DPORT_CACHE(vaddr_start) && ADDRESS_IN_DPORT_CACHE(vaddr_end)) ||
-           (ADDRESS_IN_DRAM1(vaddr_start) && ADDRESS_IN_DRAM1(vaddr_end)) ||
-           (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+    uint32_t vaddr_end = vaddr_start + len - 1;
+
+    //DROM0 is an alias of the IBUS2
+    bool on_ibus = ((vaddr_start >= DROM0_ADDRESS_LOW) && (vaddr_end < DROM0_ADDRESS_HIGH)) ||
+                   ((vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < IRAM1_ADDRESS_HIGH));
+
+    bool on_dbus = (vaddr_start >= DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < DRAM0_CACHE_ADDRESS_HIGH);
+
+    return (on_ibus || on_dbus);
 }
 
 /**

components/hal/esp32s3/include/hal/cache_ll.h

@@ -56,10 +56,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     HAL_ASSERT(cache_id == 0 || cache_id == 1);
 
     cache_bus_mask_t mask = 0;
-    uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;    //Both cores have their own IBUS0
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;    //Both cores have their own DBUS0
     } else {
         HAL_ASSERT(0);      //Out of region

components/soc/esp32/include/soc/ext_mem_defs.h

@@ -29,7 +29,7 @@ extern "C" {
 #define DROM0_CACHE_ADDRESS_HIGH    0x3F800000
 
 
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
 #define ADDRESS_IN_IRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
 #define ADDRESS_IN_IROM0_CACHE(vaddr)      ADDRESS_IN_BUS(IROM0_CACHE, vaddr)

components/soc/esp32c2/include/soc/ext_mem_defs.h

@@ -29,7 +29,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name, page_size)                 (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH(page_size))
+#define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size))
 
 #define ADDRESS_IN_IRAM0(vaddr, page_size)            ADDRESS_IN_BUS(IRAM0, vaddr, page_size)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size)

components/soc/esp32c3/include/soc/ext_mem_defs.h

@@ -27,7 +27,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -27,7 +27,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)

components/soc/esp32s2/include/soc/ext_mem_defs.h

@@ -43,7 +43,7 @@ extern "C" {
 #define DPORT_CACHE_ADDRESS_HIGH      	0x3f800000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)

components/soc/esp32s3/include/soc/ext_mem_defs.h

@@ -26,7 +26,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C800000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)