Merge branch 'bugfix/s3_uart_reg_update' into 'master'

uart: S3 7.2.8 bringup

Closes IDF-3227 and IDF-3304

See merge request espressif/esp-idf!14009

components/driver/uart.c

@@ -509,7 +509,7 @@ esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_c
     at_cmd.gap_tout = chr_tout * uart_div;
     at_cmd.pre_idle = pre_idle * uart_div;
     at_cmd.post_idle = post_idle * uart_div;
-#elif CONFIG_IDF_TARGET_ESP32S2
+#else
     at_cmd.gap_tout = chr_tout;
     at_cmd.pre_idle = pre_idle;
     at_cmd.post_idle = post_idle;

components/hal/esp32s3/include/hal/uart_ll.h

@@ -144,8 +144,8 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
     uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
     // The baud rate configuration register is divided into
     // an integer part and a fractional part.
-    hw->clk_div.div_int = clk_div >> 4;
-    hw->clk_div.div_frag = clk_div &  0xf;
+    hw->clkdiv.clkdiv = clk_div >> 4;
+    hw->clkdiv.clkdiv_frag = clk_div &  0xf;
     hw->clk_conf.sclk_div_num = sclk_div - 1;
 #undef DIV_UP
 }
@@ -160,8 +160,8 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
 FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw)
 {
     uint32_t sclk_freq = uart_ll_get_sclk_freq(hw);
-    typeof(hw->clk_div) div_reg = hw->clk_div;
-    return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1));
+    uart_clkdiv_reg_t div_reg = hw->clkdiv;
+    return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (hw->clk_conf.sclk_div_num + 1));
 }
 
 /**
@@ -239,7 +239,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
 FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
 {
     for (int i = 0; i < (int)rd_len; i++) {
-        buf[i] = hw->ahb_fifo.rw_byte;
+        buf[i] = hw->fifo.rxfifo_rd_byte;
     }
 }
 
@@ -255,7 +255,7 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
 FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
 {
     for (int i = 0; i < (int)wr_len; i++) {
-        hw->ahb_fifo.rw_byte = buf[i];
+        hw->fifo.rxfifo_rd_byte = buf[i];
     }
 }
 
@@ -523,7 +523,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
  */
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    hw->at_cmd_char.data = cmd_char->cmd_char;
+    hw->at_cmd_char.at_cmd_char = cmd_char->cmd_char;
     hw->at_cmd_char.char_num = cmd_char->char_num;
     hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
     hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
@@ -593,9 +593,9 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t
  */
 FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
 {
-    hw->rs485_conf.en = 0;
-    hw->rs485_conf.tx_rx_en = 0;
-    hw->rs485_conf.rx_busy_tx_en = 0;
+    hw->rs485_conf.rs485_en = 0;
+    hw->rs485_conf.rs485tx_rx_en= 0;
+    hw->rs485_conf.rs485rxby_tx_en = 0;
     hw->conf0.irda_en = 0;
 }
 
@@ -609,11 +609,11 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
 FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
 {
     // Application software control, remove echo
-    hw->rs485_conf.rx_busy_tx_en = 1;
+    hw->rs485_conf.rs485rxby_tx_en = 1;
     hw->conf0.irda_en = 0;
     hw->conf0.sw_rts = 0;
     hw->conf0.irda_en = 0;
-    hw->rs485_conf.en = 1;
+    hw->rs485_conf.rs485_en = 1;
 }
 
 /**
@@ -628,11 +628,11 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
     // Enable receiver, sw_rts = 1  generates low level on RTS pin
     hw->conf0.sw_rts = 1;
     // Must be set to 0 to automatically remove echo
-    hw->rs485_conf.tx_rx_en = 0;
+    hw->rs485_conf.rs485tx_rx_en = 0;
     // This is to void collision
-    hw->rs485_conf.rx_busy_tx_en = 1;
+    hw->rs485_conf.rs485rxby_tx_en = 1;
     hw->conf0.irda_en = 0;
-    hw->rs485_conf.en = 1;
+    hw->rs485_conf.rs485_en= 1;
 }
 
 /**
@@ -646,11 +646,11 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
 {
     hw->conf0.irda_en = 0;
     // Transmitters output signal loop back to the receivers input signal
-    hw->rs485_conf.tx_rx_en = 1 ;
+    hw->rs485_conf.rs485tx_rx_en = 1 ;
     // Transmitter should send data when the receiver is busy
-    hw->rs485_conf.rx_busy_tx_en = 1;
+    hw->rs485_conf.rs485rxby_tx_en = 1;
     hw->conf0.sw_rts = 0;
-    hw->rs485_conf.en = 1;
+    hw->rs485_conf.rs485_en = 1;
 }
 
 /**
@@ -662,9 +662,9 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
 {
-    hw->rs485_conf.en = 0;
-    hw->rs485_conf.tx_rx_en = 0;
-    hw->rs485_conf.rx_busy_tx_en = 0;
+    hw->rs485_conf.rs485_en = 0;
+    hw->rs485_conf.rs485tx_rx_en = 0;
+    hw->rs485_conf.rs485rxby_tx_en = 0;
     hw->conf0.sw_rts = 0;
     hw->conf0.irda_en = 1;
 }
@@ -710,7 +710,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = hw->at_cmd_char.data;
+    *cmd_char = hw->at_cmd_char.at_cmd_char;
     *char_num = hw->at_cmd_char.char_num;
 }
 
@@ -799,7 +799,7 @@ FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
  */
 FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
 {
-    typeof(hw->conf0) conf0_reg = hw->conf0;
+    uart_conf0_reg_t conf0_reg = hw->conf0;
     conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
     conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
     conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;

components/soc/esp32s3/include/soc/uart_reg.h

@@ -1,1263 +1,1532 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UART_REG_H_
-#define _SOC_UART_REG_H_
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
-
-#include "soc.h"
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
-/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: UART $n accesses FIFO via this register..*/
-#define UART_RXFIFO_RD_BYTE    0x000000FF
-#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
-#define UART_RXFIFO_RD_BYTE_V  0xFF
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART(i) accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
 #define UART_RXFIFO_RD_BYTE_S  0
 
-#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
-/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when input rxd edge changes more time
-s than what reg_active_threshold specifies in light sleeping mode..*/
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (BIT(19))
-#define UART_WAKEUP_INT_RAW_V  0x1
-#define UART_WAKEUP_INT_RAW_S  19
-/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the configured
-at_cmd char..*/
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when detects a clash between transmit
-ter and receiver in rs485 mode..*/
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_V  0x1
-#define UART_RS485_CLASH_INT_RAW_S  17
-/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
-ror from the echo of transmitter in rs485 mode..*/
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a parity error
-from the echo of transmitter in rs485 mode..*/
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has send out all dat
-a in FIFO..*/
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (BIT(14))
-#define UART_TX_DONE_INT_RAW_V  0x1
-#define UART_TX_DONE_INT_RAW_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has kept the shortes
-t duration after sending the  last data..*/
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter completes  sending
-NULL characters, after all data in Tx-FIFO are sent..*/
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a glitch in the
- middle of a start bit..*/
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_V  0x1
-#define UART_GLITCH_DET_INT_RAW_S  11
-/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives Xoff char when
- uart_sw_flow_con_en is set to 1..*/
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_V  0x1
-#define UART_SW_XOFF_INT_RAW_S  10
-/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when
-uart_sw_flow_con_en is set to 1..*/
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (BIT(9))
-#define UART_SW_XON_INT_RAW_V  0x1
-#define UART_SW_XON_INT_RAW_S  9
-/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver takes more time than rx
-_tout_thrhd to receive a byte..*/
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a 0 after the s
-top bit..*/
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (BIT(7))
-#define UART_BRK_DET_INT_RAW_V  0x1
-#define UART_BRK_DET_INT_RAW_S  7
-/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the edge change
- of CTSn signal..*/
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_V  0x1
-#define UART_CTS_CHG_INT_RAW_S  6
-/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the edge change
- of DSRn signal..*/
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_V  0x1
-#define UART_DSR_CHG_INT_RAW_S  5
-/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives more data than
- the FIFO can store..*/
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_V  0x1
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
-ror ..*/
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_V  0x1
-#define UART_FRM_ERR_INT_RAW_S  3
-/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a parity error
-in the data..*/
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_V  0x1
-#define UART_PARITY_ERR_INT_RAW_S  2
-/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
-/*description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- less than what txfifo_empty_thrhd specifies ..*/
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives more data than
- what rxfifo_full_thrhd specifies..*/
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
 #define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
 #define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters, after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
 
-#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
-/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set t
-o 1..*/
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (BIT(19))
-#define UART_WAKEUP_INT_ST_V  0x1
-#define UART_WAKEUP_INT_ST_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is se
-t to 1..*/
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set t
-o 1..*/
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_V  0x1
-#define UART_RS485_CLASH_INT_ST_S  17
-/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is se
-t to 1..*/
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_V  0x1
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- set to 1..*/
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1..*/
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (BIT(14))
-#define UART_TX_DONE_INT_ST_V  0x1
-#define UART_TX_DONE_INT_ST_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
-a is set to 1..*/
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set t
-o 1..*/
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-1..*/
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_V  0x1
-#define UART_GLITCH_DET_INT_ST_S  11
-/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1..*/
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (BIT(10))
-#define UART_SW_XOFF_INT_ST_V  0x1
-#define UART_SW_XOFF_INT_ST_S  10
-/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1..*/
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (BIT(9))
-#define UART_SW_XON_INT_ST_V  0x1
-#define UART_SW_XON_INT_ST_S  9
-/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set t
-o 1..*/
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_V  0x1
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1..*/
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (BIT(7))
-#define UART_BRK_DET_INT_ST_V  0x1
-#define UART_BRK_DET_INT_ST_S  7
-/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1..*/
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (BIT(6))
-#define UART_CTS_CHG_INT_ST_V  0x1
-#define UART_CTS_CHG_INT_ST_S  6
-/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1..*/
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (BIT(5))
-#define UART_DSR_CHG_INT_ST_V  0x1
-#define UART_DSR_CHG_INT_ST_S  5
-/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-1..*/
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_V  0x1
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1..*/
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (BIT(3))
-#define UART_FRM_ERR_INT_ST_V  0x1
-#define UART_FRM_ERR_INT_ST_S  3
-/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-1..*/
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_V  0x1
-#define UART_PARITY_ERR_INT_ST_S  2
-/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is s
-et to 1..*/
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set t
-o 1..*/
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
 #define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
 #define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
 
-#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
-/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the enable bit for uart_wakeup_int_st register..*/
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (BIT(19))
-#define UART_WAKEUP_INT_ENA_V  0x1
-#define UART_WAKEUP_INT_ENA_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the enable bit for at_cmd_char_det_int_st register..*/
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_clash_int_st register..*/
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_V  0x1
-#define UART_RS485_CLASH_INT_ENA_S  17
-/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register..*/
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register..*/
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_done_int_st register..*/
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (BIT(14))
-#define UART_TX_DONE_INT_ENA_V  0x1
-#define UART_TX_DONE_INT_ENA_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_idle_done_int_st register..*/
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_done_int_st register..*/
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the enable bit for glitch_det_int_st register..*/
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_V  0x1
-#define UART_GLITCH_DET_INT_ENA_S  11
-/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xoff_int_st register..*/
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_V  0x1
-#define UART_SW_XOFF_INT_ENA_S  10
-/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xon_int_st register..*/
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (BIT(9))
-#define UART_SW_XON_INT_ENA_V  0x1
-#define UART_SW_XON_INT_ENA_S  9
-/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_tout_int_st register..*/
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the enable bit for brk_det_int_st register..*/
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (BIT(7))
-#define UART_BRK_DET_INT_ENA_V  0x1
-#define UART_BRK_DET_INT_ENA_S  7
-/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the enable bit for cts_chg_int_st register..*/
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_V  0x1
-#define UART_CTS_CHG_INT_ENA_S  6
-/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the enable bit for dsr_chg_int_st register..*/
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_V  0x1
-#define UART_DSR_CHG_INT_ENA_S  5
-/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_ovf_int_st register..*/
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_V  0x1
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the enable bit for frm_err_int_st register..*/
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_V  0x1
-#define UART_FRM_ERR_INT_ENA_S  3
-/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the enable bit for parity_err_int_st register..*/
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_V  0x1
-#define UART_PARITY_ERR_INT_ENA_S  2
-/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the enable bit for txfifo_empty_int_st register..*/
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_full_int_st register..*/
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
 #define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
 #define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
 
-#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
-/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to clear the uart_wakeup_int_raw interrupt..*/
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (BIT(19))
-#define UART_WAKEUP_INT_CLR_V  0x1
-#define UART_WAKEUP_INT_CLR_S  19
-/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt..*/
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_clash_int_raw interrupt..*/
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_V  0x1
-#define UART_RS485_CLASH_INT_CLR_S  17
-/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt..*/
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt..*/
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_done_int_raw interrupt..*/
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (BIT(14))
-#define UART_TX_DONE_INT_CLR_V  0x1
-#define UART_TX_DONE_INT_CLR_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt..*/
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_done_int_raw interrupt...*/
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the glitch_det_int_raw interrupt..*/
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_V  0x1
-#define UART_GLITCH_DET_INT_CLR_S  11
-/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xoff_int_raw interrupt..*/
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_V  0x1
-#define UART_SW_XOFF_INT_CLR_S  10
-/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xon_int_raw interrupt..*/
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (BIT(9))
-#define UART_SW_XON_INT_CLR_V  0x1
-#define UART_SW_XON_INT_CLR_S  9
-/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt..*/
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the brk_det_int_raw interrupt..*/
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (BIT(7))
-#define UART_BRK_DET_INT_CLR_V  0x1
-#define UART_BRK_DET_INT_CLR_S  7
-/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the cts_chg_int_raw interrupt..*/
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_V  0x1
-#define UART_CTS_CHG_INT_CLR_S  6
-/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the dsr_chg_int_raw interrupt..*/
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_V  0x1
-#define UART_DSR_CHG_INT_CLR_S  5
-/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt..*/
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_V  0x1
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear frm_err_int_raw interrupt..*/
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_V  0x1
-#define UART_FRM_ERR_INT_CLR_S  3
-/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear parity_err_int_raw interrupt..*/
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_V  0x1
-#define UART_PARITY_ERR_INT_CLR_S  2
-/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear txfifo_empty_int_raw interrupt..*/
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_full_int_raw interrupt..*/
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
 #define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
 #define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
 
-#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
-/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
-/*description: The decimal part of the frequency divider factor..*/
-#define UART_CLKDIV_FRAG    0x0000000F
-#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
-#define UART_CLKDIV_FRAG_V  0xF
-#define UART_CLKDIV_FRAG_S  20
-/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2b6 ; */
-/*description: The integral part of the frequency divider factor..*/
-#define UART_CLKDIV    0x00000FFF
-#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
-#define UART_CLKDIV_V  0xFFF
+/** UART_CLKDIV_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
 #define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
 
-#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
-/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enable Rx signal filter..*/
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value, the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
 #define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (BIT(8))
-#define UART_GLITCH_FILT_EN_V  0x1
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
 #define UART_GLITCH_FILT_EN_S  8
-/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
-/*description: when input pulse width is lower than this value, the pulse is ignored..*/
-#define UART_GLITCH_FILT    0x000000FF
-#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
-#define UART_GLITCH_FILT_V  0xFF
-#define UART_GLITCH_FILT_S  0
 
-#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
-/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
-/*description: This bit represents the  level of the internal uart txd signal..*/
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (BIT(31))
-#define UART_TXD_V  0x1
-#define UART_TXD_S  31
-/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart rts signal..*/
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (BIT(30))
-#define UART_RTSN_V  0x1
-#define UART_RTSN_S  30
-/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart dtr signal..*/
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (BIT(29))
-#define UART_DTRN_V  0x1
-#define UART_DTRN_S  29
-/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
-/*description: Stores the byte number of data in Tx-FIFO..*/
-#define UART_TXFIFO_CNT    0x000003FF
-#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
-#define UART_TXFIFO_CNT_V  0x3FF
-#define UART_TXFIFO_CNT_S  16
-/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: This register represent the  level value of the internal uart rxd signal..*/
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (BIT(15))
-#define UART_RXD_V  0x1
-#define UART_RXD_S  15
-/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
-/*description: This register represent the level value of the internal uart cts signal..*/
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (BIT(14))
-#define UART_CTSN_V  0x1
-#define UART_CTSN_S  14
-/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The register represent the level value of the internal uart dsr signal..*/
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [9:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000003FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000003FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
 #define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (BIT(13))
-#define UART_DSRN_V  0x1
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
 #define UART_DSRN_S  13
-/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: Stores the byte number of valid data in Rx-FIFO..*/
-#define UART_RXFIFO_CNT    0x000003FF
-#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
-#define UART_RXFIFO_CNT_V  0x3FF
-#define UART_RXFIFO_CNT_S  0
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [25:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000003FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000003FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
 
-#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
-/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
-/*description: UART memory clock gate enable signal..*/
-#define UART_MEM_CLK_EN    (BIT(28))
-#define UART_MEM_CLK_EN_M  (BIT(28))
-#define UART_MEM_CLK_EN_V  0x1
-#define UART_MEM_CLK_EN_S  28
-/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This is the enable bit for detecting baudrate..*/
-#define UART_AUTOBAUD_EN    (BIT(27))
-#define UART_AUTOBAUD_EN_M  (BIT(27))
-#define UART_AUTOBAUD_EN_V  0x1
-#define UART_AUTOBAUD_EN_S  27
-/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver s
-tores the data even if the  received data is wrong..*/
-#define UART_ERR_WR_MASK    (BIT(26))
-#define UART_ERR_WR_MASK_M  (BIT(26))
-#define UART_ERR_WR_MASK_V  0x1
-#define UART_ERR_WR_MASK_S  26
-/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
-tes registers..*/
-#define UART_CLK_EN    (BIT(25))
-#define UART_CLK_EN_M  (BIT(25))
-#define UART_CLK_EN_V  0x1
-#define UART_CLK_EN_S  25
-/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dtr signal..*/
-#define UART_DTR_INV    (BIT(24))
-#define UART_DTR_INV_M  (BIT(24))
-#define UART_DTR_INV_V  0x1
-#define UART_DTR_INV_S  24
-/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rts signal..*/
-#define UART_RTS_INV    (BIT(23))
-#define UART_RTS_INV_M  (BIT(23))
-#define UART_RTS_INV_V  0x1
-#define UART_RTS_INV_S  23
-/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart txd signal..*/
-#define UART_TXD_INV    (BIT(22))
-#define UART_TXD_INV_M  (BIT(22))
-#define UART_TXD_INV_V  0x1
-#define UART_TXD_INV_S  22
-/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dsr signal..*/
-#define UART_DSR_INV    (BIT(21))
-#define UART_DSR_INV_M  (BIT(21))
-#define UART_DSR_INV_V  0x1
-#define UART_DSR_INV_S  21
-/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart cts signal..*/
-#define UART_CTS_INV    (BIT(20))
-#define UART_CTS_INV_M  (BIT(20))
-#define UART_CTS_INV_V  0x1
-#define UART_CTS_INV_S  20
-/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rxd signal..*/
-#define UART_RXD_INV    (BIT(19))
-#define UART_RXD_INV_M  (BIT(19))
-#define UART_RXD_INV_V  0x1
-#define UART_RXD_INV_S  19
-/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart transmit-FIFO..*/
-#define UART_TXFIFO_RST    (BIT(18))
-#define UART_TXFIFO_RST_M  (BIT(18))
-#define UART_TXFIFO_RST_V  0x1
-#define UART_TXFIFO_RST_S  18
-/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart receive-FIFO..*/
-#define UART_RXFIFO_RST    (BIT(17))
-#define UART_RXFIFO_RST_M  (BIT(17))
-#define UART_RXFIFO_RST_V  0x1
-#define UART_RXFIFO_RST_S  17
-/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to enable IrDA protocol..*/
-#define UART_IRDA_EN    (BIT(16))
-#define UART_IRDA_EN_M  (BIT(16))
-#define UART_IRDA_EN_V  0x1
-#define UART_IRDA_EN_S  16
-/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable flow control function for transmitter..*/
-#define UART_TX_FLOW_EN    (BIT(15))
-#define UART_TX_FLOW_EN_M  (BIT(15))
-#define UART_TX_FLOW_EN_V  0x1
-#define UART_TX_FLOW_EN_S  15
-/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart loopback test mode..*/
-#define UART_LOOPBACK    (BIT(14))
-#define UART_LOOPBACK_M  (BIT(14))
-#define UART_LOOPBACK_V  0x1
-#define UART_LOOPBACK_S  14
-/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of IrDA receiver..*/
-#define UART_IRDA_RX_INV    (BIT(13))
-#define UART_IRDA_RX_INV_M  (BIT(13))
-#define UART_IRDA_RX_INV_V  0x1
-#define UART_IRDA_RX_INV_S  13
-/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of  IrDA transmitter..*/
-#define UART_IRDA_TX_INV    (BIT(12))
-#define UART_IRDA_TX_INV_M  (BIT(12))
-#define UART_IRDA_TX_INV_V  0x1
-#define UART_IRDA_TX_INV_S  12
-/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA tr
-ansmitter's 11th bit to 0..*/
-#define UART_IRDA_WCTL    (BIT(11))
-#define UART_IRDA_WCTL_M  (BIT(11))
-#define UART_IRDA_WCTL_V  0x1
-#define UART_IRDA_WCTL_S  11
-/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the start enable bit for IrDA transmitter..*/
-#define UART_IRDA_TX_EN    (BIT(10))
-#define UART_IRDA_TX_EN_M  (BIT(10))
-#define UART_IRDA_TX_EN_V  0x1
-#define UART_IRDA_TX_EN_S  10
-/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable IrDA loopback mode..*/
-#define UART_IRDA_DPLX    (BIT(9))
-#define UART_IRDA_DPLX_M  (BIT(9))
-#define UART_IRDA_DPLX_V  0x1
-#define UART_IRDA_DPLX_S  9
-/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enbale transmitter to  send NULL when the process of sending dat
-a is done..*/
-#define UART_TXD_BRK    (BIT(8))
-#define UART_TXD_BRK_M  (BIT(8))
-#define UART_TXD_BRK_V  0x1
-#define UART_TXD_BRK_S  8
-/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This register is used to configure the software dtr signal which is used in soft
-ware flow control..*/
-#define UART_SW_DTR    (BIT(7))
-#define UART_SW_DTR_M  (BIT(7))
-#define UART_SW_DTR_V  0x1
-#define UART_SW_DTR_S  7
-/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This register is used to configure the software rts signal which is used in soft
-ware flow control..*/
-#define UART_SW_RTS    (BIT(6))
-#define UART_SW_RTS_M  (BIT(6))
-#define UART_SW_RTS_V  0x1
-#define UART_SW_RTS_S  6
-/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
-/*description: This register is used to set the length of  stop bit..*/
-#define UART_STOP_BIT_NUM    0x00000003
-#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
-#define UART_STOP_BIT_NUM_V  0x3
-#define UART_STOP_BIT_NUM_S  4
-/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
-/*description: This register is used to set the length of data..*/
-#define UART_BIT_NUM    0x00000003
-#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
-#define UART_BIT_NUM_V  0x3
-#define UART_BIT_NUM_S  2
-/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart parity check..*/
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (BIT(1))
-#define UART_PARITY_EN_V  0x1
-#define UART_PARITY_EN_S  1
-/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This register is used to configure the parity check mode..*/
+/** UART_CONF0_REG register
+ *  a
+ */
+#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
 #define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (BIT(0))
-#define UART_PARITY_V  0x1
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
 #define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_SW_RTS : R/W; bitpos: [6]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(6))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  6
+/** UART_SW_DTR : R/W; bitpos: [7]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(7))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  7
+/** UART_TXD_BRK : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(8))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  8
+/** UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(9))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  9
+/** UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(10))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  10
+/** UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(11))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  11
+/** UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(12))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  12
+/** UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(13))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  13
+/** UART_LOOPBACK : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(14))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  14
+/** UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(15))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  15
+/** UART_IRDA_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(16))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  16
+/** UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(17))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  17
+/** UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(18))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  18
+/** UART_RXD_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(19))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  19
+/** UART_CTS_INV : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(20))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  20
+/** UART_DSR_INV : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(21))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  21
+/** UART_TXD_INV : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(22))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  22
+/** UART_RTS_INV : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(23))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  23
+/** UART_DTR_INV : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(24))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  24
+/** UART_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(25))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  25
+/** UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(26))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  26
+/** UART_AUTOBAUD_EN : R/W; bitpos: [27]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(27))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  27
+/** UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(28))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  28
 
-#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
-/* UART_RX_TOUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This is the enble bit for uart receiver's timeout function..*/
-#define UART_RX_TOUT_EN    (BIT(23))
-#define UART_RX_TOUT_EN_M  (BIT(23))
-#define UART_RX_TOUT_EN_V  0x1
-#define UART_RX_TOUT_EN_S  23
-/* UART_RX_FLOW_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: This is the flow enable bit for UART receiver..*/
-#define UART_RX_FLOW_EN    (BIT(22))
-#define UART_RX_FLOW_EN_M  (BIT(22))
-#define UART_RX_FLOW_EN_V  0x1
-#define UART_RX_FLOW_EN_S  22
-/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/
-#define UART_RX_TOUT_FLOW_DIS    (BIT(21))
-#define UART_RX_TOUT_FLOW_DIS_M  (BIT(21))
-#define UART_RX_TOUT_FLOW_DIS_V  0x1
-#define UART_RX_TOUT_FLOW_DIS_S  21
-/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: Disable UART Rx data overflow detect. .*/
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [9:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000003FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000003FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [19:10]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000003FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000003FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  10
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [20]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
 #define UART_DIS_RX_DAT_OVF    (BIT(20))
-#define UART_DIS_RX_DAT_OVF_M  (BIT(20))
-#define UART_DIS_RX_DAT_OVF_V  0x1
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
 #define UART_DIS_RX_DAT_OVF_S  20
-/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[19:10] ;default: 10'h60 ; */
-/*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le
-ss than this register value..*/
-#define UART_TXFIFO_EMPTY_THRHD    0x000003FF
-#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
-#define UART_TXFIFO_EMPTY_THRHD_V  0x3FF
-#define UART_TXFIFO_EMPTY_THRHD_S  10
-/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[9:0] ;default: 10'h60 ; */
-/*description: It will produce rxfifo_full_int interrupt when receiver receives more data than
-this register value..*/
-#define UART_RXFIFO_FULL_THRHD    0x000003FF
-#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
-#define UART_RXFIFO_FULL_THRHD_V  0x3FF
-#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(21))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  21
+/** UART_RX_FLOW_EN : R/W; bitpos: [22]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(22))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  22
+/** UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0;
+ *  This is the enble bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(23))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  23
 
-#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
-/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the value of the minimum duration time of the low level pul
-se. It is used in baud rate-detect process..*/
-#define UART_LOWPULSE_MIN_CNT    0x00000FFF
-#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
-#define UART_LOWPULSE_MIN_CNT_V  0xFFF
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
 #define UART_LOWPULSE_MIN_CNT_S  0
 
-#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
-/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores  the value of the maxinum duration time for the high level
-pulse. It is used in baud rate-detect process..*/
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFF
-#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
-#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maxinum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
 #define UART_HIGHPULSE_MIN_CNT_S  0
 
-#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
-/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the count of rxd edge change. It is used in baud rate-detec
-t process..*/
-#define UART_RXD_EDGE_CNT    0x000003FF
-#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
-#define UART_RXD_EDGE_CNT_V  0x3FF
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
 #define UART_RXD_EDGE_CNT_S  0
 
-#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
-/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to send Xoff char. It is cleared by hardware automatically..*/
-#define UART_SEND_XOFF    (BIT(5))
-#define UART_SEND_XOFF_M  (BIT(5))
-#define UART_SEND_XOFF_V  0x1
-#define UART_SEND_XOFF_S  5
-/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to send Xon char. It is cleared by hardware automatically..*/
-#define UART_SEND_XON    (BIT(4))
-#define UART_SEND_XON_M  (BIT(4))
-#define UART_SEND_XON_V  0x1
-#define UART_SEND_XON_S  4
-/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to stop the  transmitter from sending data..*/
-#define UART_FORCE_XOFF    (BIT(3))
-#define UART_FORCE_XOFF_M  (BIT(3))
-#define UART_FORCE_XOFF_V  0x1
-#define UART_FORCE_XOFF_S  3
-/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable the transmitter to go on sending data..*/
-#define UART_FORCE_XON    (BIT(2))
-#define UART_FORCE_XON_M  (BIT(2))
-#define UART_FORCE_XON_V  0x1
-#define UART_FORCE_XON_S  2
-/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to remove flow control char from the received data..*/
-#define UART_XONOFF_DEL    (BIT(1))
-#define UART_XONOFF_DEL_M  (BIT(1))
-#define UART_XONOFF_DEL_V  0x1
-#define UART_XONOFF_DEL_S  1
-/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable software flow control. It is used with register sw_xon or
- sw_xoff..*/
+/** UART_FLOW_CONF_REG register
+ *  Software flow-control configuration
+ */
+#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
 #define UART_SW_FLOW_CON_EN    (BIT(0))
-#define UART_SW_FLOW_CON_EN_M  (BIT(0))
-#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
 #define UART_SW_FLOW_CON_EN_S  0
+/** UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(1))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  1
+/** UART_FORCE_XON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(2))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  2
+/** UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(3))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  3
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [4]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(4))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  4
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(5))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  5
 
-#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
-/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
-/*description: The uart is activated from light sleeping mode when the input rxd edge changes m
-ore times than this register value..*/
-#define UART_ACTIVE_THRESHOLD    0x000003FF
-#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
-#define UART_ACTIVE_THRESHOLD_V  0x3FF
+/** UART_SLEEP_CONF_REG register
+ *  Sleep-mode configuration
+ */
+#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
 #define UART_ACTIVE_THRESHOLD_S  0
 
-#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
-/* UART_XOFF_CHAR : R/W ;bitpos:[17:10] ;default: 8'h13 ; */
-/*description: This register stores the Xoff flow control char..*/
-#define UART_XOFF_CHAR    0x000000FF
-#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
-#define UART_XOFF_CHAR_V  0xFF
-#define UART_XOFF_CHAR_S  10
-/* UART_XOFF_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'he0 ; */
-/*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl
-ow_con_en set to 1, it will send a Xoff char..*/
-#define UART_XOFF_THRESHOLD    0x000003FF
-#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
-#define UART_XOFF_THRESHOLD_V  0x3FF
+/** UART_SWFC_CONF0_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [9:0]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000003FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000003FFU
 #define UART_XOFF_THRESHOLD_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [17:10]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  10
 
-#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
-/* UART_XON_CHAR : R/W ;bitpos:[17:10] ;default: 8'h11 ; */
-/*description: This register stores the Xon flow control char..*/
-#define UART_XON_CHAR    0x000000FF
-#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
-#define UART_XON_CHAR_V  0xFF
-#define UART_XON_CHAR_S  10
-/* UART_XON_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl
-ow_con_en set to 1, it will send a Xon char..*/
-#define UART_XON_THRESHOLD    0x000003FF
-#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
-#define UART_XON_THRESHOLD_V  0x3FF
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [9:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1, it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000003FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000003FFU
 #define UART_XON_THRESHOLD_S  0
+/** UART_XON_CHAR : R/W; bitpos: [17:10]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  10
 
-#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
-/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
-/*description: This register is used to configure the number of 0 to be sent after the process
-of sending data is done. It is active when txd_brk is set to 1..*/
-#define UART_TX_BRK_NUM    0x000000FF
-#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
-#define UART_TX_BRK_NUM_V  0xFF
+/** UART_TXBRK_CONF_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
 #define UART_TX_BRK_NUM_S  0
 
-#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
-/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
-/*description: This register is used to configure the duration time between transfers..*/
-#define UART_TX_IDLE_NUM    0x000003FF
-#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
-#define UART_TX_IDLE_NUM_V  0x3FF
-#define UART_TX_IDLE_NUM_S  10
-/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: It will produce frame end signal when receiver takes more time to receive one by
-te data than this register value..*/
-#define UART_RX_IDLE_THRHD    0x000003FF
-#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
-#define UART_RX_IDLE_THRHD_V  0x3FF
+/** UART_IDLE_CONF_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
 #define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
 
-#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4C)
-/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
-/*description: This register is used to delay the transmitter's internal data signal..*/
-#define UART_RS485_TX_DLY_NUM    0x0000000F
-#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
-#define UART_RS485_TX_DLY_NUM_V  0xF
-#define UART_RS485_TX_DLY_NUM_S  6
-/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This register is used to delay the receiver's internal data signal..*/
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_V  0x1
-#define UART_RS485_RX_DLY_NUM_S  5
-/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. .*/
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (BIT(4))
-#define UART_RS485RXBY_TX_EN_V  0x1
-#define UART_RS485RXBY_TX_EN_S  4
-/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable receiver could receive data when the transmitter is trans
-mitting data in rs485 mode.  .*/
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (BIT(3))
-#define UART_RS485TX_RX_EN_V  0x1
-#define UART_RS485TX_RX_EN_S  3
-/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit..*/
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (BIT(2))
-#define UART_DL1_EN_V  0x1
-#define UART_DL1_EN_S  2
-/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit..*/
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (BIT(1))
-#define UART_DL0_EN_V  0x1
-#define UART_DL0_EN_S  1
-/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to choose the rs485 mode..*/
+/** UART_RS485_CONF_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
 #define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (BIT(0))
-#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
 #define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
 
-#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
-/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the idle duration time before the first at_cm
-d is received by receiver. .*/
-#define UART_PRE_IDLE_NUM    0x0000FFFF
-#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
-#define UART_PRE_IDLE_NUM_V  0xFFFF
+/** UART_AT_CMD_PRECNT_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
 #define UART_PRE_IDLE_NUM_S  0
 
-#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
-/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the duration time between the last at_cmd and
- the next data..*/
-#define UART_POST_IDLE_NUM    0x0000FFFF
-#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
-#define UART_POST_IDLE_NUM_V  0xFFFF
+/** UART_AT_CMD_POSTCNT_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
 #define UART_POST_IDLE_NUM_S  0
 
-#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
-/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
-/*description: This register is used to configure the duration time between the at_cmd chars..*/
-#define UART_RX_GAP_TOUT    0x0000FFFF
-#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
-#define UART_RX_GAP_TOUT_V  0xFFFF
+/** UART_AT_CMD_GAPTOUT_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
 #define UART_RX_GAP_TOUT_S  0
 
-#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5C)
-/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
-/*description: This register is used to configure the num of continuous at_cmd chars received b
-y receiver..*/
-#define UART_CHAR_NUM    0x000000FF
-#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
-#define UART_CHAR_NUM_V  0xFF
-#define UART_CHAR_NUM_S  8
-/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
-/*description: This register is used to configure the content of at_cmd char..*/
-#define UART_AT_CMD_CHAR    0x000000FF
-#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
-#define UART_AT_CMD_CHAR_V  0xFF
+/** UART_AT_CMD_CHAR_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
 #define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
 
-#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
-/* UART_MEM_FORCE_PU : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to force power up UART memory..*/
-#define UART_MEM_FORCE_PU    (BIT(28))
-#define UART_MEM_FORCE_PU_M  (BIT(28))
-#define UART_MEM_FORCE_PU_V  0x1
-#define UART_MEM_FORCE_PU_S  28
-/* UART_MEM_FORCE_PD : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to force power down UART memory..*/
+/** UART_MEM_CONF_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_RX_SIZE : R/W; bitpos: [3:1]; default: 1;
+ *  This register is used to configure the amount of mem allocated for receive-FIFO.
+ *  The default number is 128 bytes.
+ */
+#define UART_RX_SIZE    0x00000007U
+#define UART_RX_SIZE_M  (UART_RX_SIZE_V << UART_RX_SIZE_S)
+#define UART_RX_SIZE_V  0x00000007U
+#define UART_RX_SIZE_S  1
+/** UART_TX_SIZE : R/W; bitpos: [6:4]; default: 1;
+ *  This register is used to configure the amount of mem allocated for transmit-FIFO.
+ *  The default number is 128 bytes.
+ */
+#define UART_TX_SIZE    0x00000007U
+#define UART_TX_SIZE_M  (UART_TX_SIZE_V << UART_TX_SIZE_S)
+#define UART_TX_SIZE_V  0x00000007U
+#define UART_TX_SIZE_S  4
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [16:7]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000003FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000003FFU
+#define UART_RX_FLOW_THRHD_S  7
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [26:17]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  17
+/** UART_MEM_FORCE_PD : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
 #define UART_MEM_FORCE_PD    (BIT(27))
-#define UART_MEM_FORCE_PD_M  (BIT(27))
-#define UART_MEM_FORCE_PD_V  0x1
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
 #define UART_MEM_FORCE_PD_S  27
-/* UART_RX_TOUT_THRHD : R/W ;bitpos:[26:17] ;default: 10'ha ; */
-/*description: This register is used to configure the threshold time that receiver takes to rec
-eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t
-akes more time to receive one byte with rx_tout_en set to 1..*/
-#define UART_RX_TOUT_THRHD    0x000003FF
-#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
-#define UART_RX_TOUT_THRHD_V  0x3FF
-#define UART_RX_TOUT_THRHD_S  17
-/* UART_RX_FLOW_THRHD : R/W ;bitpos:[16:7] ;default: 10'h0 ; */
-/*description: This register is used to configure the maximum amount of data that can be receiv
-ed  when hardware flow control works..*/
-#define UART_RX_FLOW_THRHD    0x000003FF
-#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
-#define UART_RX_FLOW_THRHD_V  0x3FF
-#define UART_RX_FLOW_THRHD_S  7
-/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
-/*description: This register is used to configure the amount of mem allocated for transmit-FIFO
-. The default number is 128 bytes..*/
-#define UART_TX_SIZE    0x00000007
-#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
-#define UART_TX_SIZE_V  0x7
-#define UART_TX_SIZE_S  4
-/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
-/*description: This register is used to configure the amount of mem allocated for receive-FIFO.
- The default number is 128 bytes..*/
-#define UART_RX_SIZE    0x00000007
-#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
-#define UART_RX_SIZE_V  0x7
-#define UART_RX_SIZE_S  1
+/** UART_MEM_FORCE_PU : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(28))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  28
 
-#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
-/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx
--FIFO_Ctrl..*/
-#define UART_TX_RADDR    0x000003FF
-#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
-#define UART_TX_RADDR_V  0x3FF
-#define UART_TX_RADDR_S  11
-/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-via APB..*/
-#define UART_APB_TX_WADDR    0x000003FF
-#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
-#define UART_APB_TX_WADDR_V  0x3FF
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-FIFO write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_APB_TX_WADDR : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
+ *  APB.
+ */
+#define UART_APB_TX_WADDR    0x000003FFU
+#define UART_APB_TX_WADDR_M  (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S)
+#define UART_APB_TX_WADDR_V  0x000003FFU
 #define UART_APB_TX_WADDR_S  0
+/** UART_TX_RADDR : RO; bitpos: [20:11]; default: 0;
+ *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+ *  Tx-FIFO_Ctrl.
+ */
+#define UART_TX_RADDR    0x000003FFU
+#define UART_TX_RADDR_M  (UART_TX_RADDR_V << UART_TX_RADDR_S)
+#define UART_TX_RADDR_V  0x000003FFU
+#define UART_TX_RADDR_S  11
 
-#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
-/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h200 ; */
-/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-F
-IFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300..*/
-#define UART_RX_WADDR    0x000003FF
-#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
-#define UART_RX_WADDR_V  0x3FF
-#define UART_RX_WADDR_S  11
-/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h200 ; */
-/*description: This register stores the offset address in RX-FIFO when software reads data from
- Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300..*/
-#define UART_APB_RX_RADDR    0x000003FF
-#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
-#define UART_APB_RX_RADDR_V  0x3FF
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-FIFO write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_APB_RX_RADDR : RO; bitpos: [9:0]; default: 512;
+ *  This register stores the offset address in RX-FIFO when software reads data from
+ *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+ */
+#define UART_APB_RX_RADDR    0x000003FFU
+#define UART_APB_RX_RADDR_M  (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S)
+#define UART_APB_RX_RADDR_V  0x000003FFU
 #define UART_APB_RX_RADDR_S  0
+/** UART_RX_WADDR : RO; bitpos: [20:11]; default: 512;
+ *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+ *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+ */
+#define UART_RX_WADDR    0x000003FFU
+#define UART_RX_WADDR_M  (UART_RX_WADDR_V << UART_RX_WADDR_S)
+#define UART_RX_WADDR_V  0x000003FFU
+#define UART_RX_WADDR_S  11
 
-#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6C)
-/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: This is the status register of transmitter..*/
-#define UART_ST_UTX_OUT    0x0000000F
-#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
-#define UART_ST_UTX_OUT_V  0xF
-#define UART_ST_UTX_OUT_S  4
-/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: This is the status register of receiver..*/
-#define UART_ST_URX_OUT    0x0000000F
-#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
-#define UART_ST_URX_OUT_V  0xF
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
 #define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
 
-#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
-/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the minimal input clock count between two positive edges. I
-t is used in boudrate-detect process..*/
-#define UART_POSEDGE_MIN_CNT    0x00000FFF
-#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
-#define UART_POSEDGE_MIN_CNT_V  0xFFF
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
 #define UART_POSEDGE_MIN_CNT_S  0
 
-#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
-/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the minimal input clock count between two negative edges. I
-t is used in boudrate-detect process..*/
-#define UART_NEGEDGE_MIN_CNT    0x00000FFF
-#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
-#define UART_NEGEDGE_MIN_CNT_V  0xFFF
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
 #define UART_NEGEDGE_MIN_CNT_S  0
 
-#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
-/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Rx..*/
-#define UART_RX_RST_CORE    (BIT(27))
-#define UART_RX_RST_CORE_M  (BIT(27))
-#define UART_RX_RST_CORE_V  0x1
-#define UART_RX_RST_CORE_S  27
-/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Tx..*/
-#define UART_TX_RST_CORE    (BIT(26))
-#define UART_TX_RST_CORE_M  (BIT(26))
-#define UART_TX_RST_CORE_V  0x1
-#define UART_TX_RST_CORE_S  26
-/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Rx clock..*/
-#define UART_RX_SCLK_EN    (BIT(25))
-#define UART_RX_SCLK_EN_M  (BIT(25))
-#define UART_RX_SCLK_EN_V  0x1
-#define UART_RX_SCLK_EN_S  25
-/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx clock..*/
-#define UART_TX_SCLK_EN    (BIT(24))
-#define UART_TX_SCLK_EN_M  (BIT(24))
-#define UART_TX_SCLK_EN_V  0x1
-#define UART_TX_SCLK_EN_S  24
-/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Tx/Rx..*/
-#define UART_RST_CORE    (BIT(23))
-#define UART_RST_CORE_M  (BIT(23))
-#define UART_RST_CORE_V  0x1
-#define UART_RST_CORE_S  23
-/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx/Rx clock..*/
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_B    0x0000003FU
+#define UART_SCLK_DIV_B_M  (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S)
+#define UART_SCLK_DIV_B_V  0x0000003FU
+#define UART_SCLK_DIV_B_S  0
+/** UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_A    0x0000003FU
+#define UART_SCLK_DIV_A_M  (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S)
+#define UART_SCLK_DIV_A_V  0x0000003FU
+#define UART_SCLK_DIV_A_S  6
+/** UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_NUM    0x000000FFU
+#define UART_SCLK_DIV_NUM_M  (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S)
+#define UART_SCLK_DIV_NUM_V  0x000000FFU
+#define UART_SCLK_DIV_NUM_S  12
+/** UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+ */
+#define UART_SCLK_SEL    0x00000003U
+#define UART_SCLK_SEL_M  (UART_SCLK_SEL_V << UART_SCLK_SEL_S)
+#define UART_SCLK_SEL_V  0x00000003U
+#define UART_SCLK_SEL_S  20
+/** UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set this bit to enable UART Tx/Rx clock.
+ */
 #define UART_SCLK_EN    (BIT(22))
-#define UART_SCLK_EN_M  (BIT(22))
-#define UART_SCLK_EN_V  0x1
+#define UART_SCLK_EN_M  (UART_SCLK_EN_V << UART_SCLK_EN_S)
+#define UART_SCLK_EN_V  0x00000001U
 #define UART_SCLK_EN_S  22
-/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
-/*description: UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL..*/
-#define UART_SCLK_SEL    0x00000003
-#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
-#define UART_SCLK_SEL_V  0x3
-#define UART_SCLK_SEL_S  20
-/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
-/*description: The integral part of the frequency divider factor..*/
-#define UART_SCLK_DIV_NUM    0x000000FF
-#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
-#define UART_SCLK_DIV_NUM_V  0xFF
-#define UART_SCLK_DIV_NUM_S  12
-/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
-/*description: The numerator of the frequency divider factor..*/
-#define UART_SCLK_DIV_A    0x0000003F
-#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
-#define UART_SCLK_DIV_A_V  0x3F
-#define UART_SCLK_DIV_A_S  6
-/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: The  denominator of the frequency divider factor..*/
-#define UART_SCLK_DIV_B    0x0000003F
-#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
-#define UART_SCLK_DIV_B_V  0x3F
-#define UART_SCLK_DIV_B_S  0
+/** UART_RST_CORE : R/W; bitpos: [23]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+ */
+#define UART_RST_CORE    (BIT(23))
+#define UART_RST_CORE_M  (UART_RST_CORE_V << UART_RST_CORE_S)
+#define UART_RST_CORE_V  0x00000001U
+#define UART_RST_CORE_S  23
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
 
-#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7C)
-/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
-/*description: This is the version register..*/
-#define UART_DATE    0xFFFFFFFF
-#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
-#define UART_DATE_V  0xFFFFFFFF
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 33587824;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
 #define UART_DATE_S  0
 
-#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
-/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Software write 1 would synchronize registers into UART Core clock domain and wou
-ld be cleared by hardware after synchronization is done..*/
-#define UART_UPDATE    (BIT(31))
-#define UART_UPDATE_M  (BIT(31))
-#define UART_UPDATE_V  0x1
-#define UART_UPDATE_S  31
-/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit used to select synchronize mode. 1: Registers are auto synchronized int
-o UART Core clock and UART core should be keep the same with APB clock. 0: After
- configure registers, software needs to write 1 to UART_REG_UPDATE to synchroniz
-e registers. .*/
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_ID : R/W; bitpos: [29:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0x3FFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0x3FFFFFFFU
+#define UART_ID_S  0
+/** UART_HIGH_SPEED : R/W; bitpos: [30]; default: 1;
+ *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
+ *  UART Core clock and UART core should be keep the same with APB clock. 0: After
+ *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
+ *  registers.
+ */
 #define UART_HIGH_SPEED    (BIT(30))
-#define UART_HIGH_SPEED_M  (BIT(30))
-#define UART_HIGH_SPEED_V  0x1
+#define UART_HIGH_SPEED_M  (UART_HIGH_SPEED_V << UART_HIGH_SPEED_S)
+#define UART_HIGH_SPEED_V  0x00000001U
 #define UART_HIGH_SPEED_S  30
-/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
-/*description: This register is used to configure the uart_id..*/
-#define UART_ID    0x3FFFFFFF
-#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
-#define UART_ID_V  0x3FFFFFFF
-#define UART_ID_S  0
-
+/** UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(31))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  31
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_UART_REG_H_ */

components/soc/esp32s3/include/soc/uart_struct.h

@@ -1,412 +1,1213 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UART_STRUCT_H_
-#define _SOC_UART_STRUCT_H_
-
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t rw_byte                       ;  /*UART $n accesses FIFO via this register.*/
-        };
-        uint32_t val;
-    } ahb_fifo;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
-            uint32_t txfifo_empty                  :    1;  /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
-            uint32_t parity_err                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
-            uint32_t frm_err                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
-            uint32_t rxfifo_ovf                    :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
-            uint32_t dsr_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
-            uint32_t cts_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
-            uint32_t brk_det                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
-            uint32_t rxfifo_tout                   :    1;  /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
-            uint32_t sw_xon                        :    1;  /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t sw_xoff                       :    1;  /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t glitch_det                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
-            uint32_t tx_brk_done                   :    1;  /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
-            uint32_t tx_done                       :    1;  /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
-            uint32_t rs485_parity_err              :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_frm_err                 :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_clash                   :    1;  /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
-            uint32_t at_cmd_char_det               :    1;  /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
-            uint32_t wakeup                        :    1;  /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
-            uint32_t txfifo_empty                  :    1;  /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
-            uint32_t parity_err                    :    1;  /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
-            uint32_t frm_err                       :    1;  /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
-            uint32_t rxfifo_ovf                    :    1;  /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
-            uint32_t dsr_chg                       :    1;  /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-            uint32_t cts_chg                       :    1;  /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-            uint32_t brk_det                       :    1;  /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-            uint32_t rxfifo_tout                   :    1;  /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
-            uint32_t sw_xon                        :    1;  /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-            uint32_t sw_xoff                       :    1;  /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-            uint32_t glitch_det                    :    1;  /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
-            uint32_t tx_brk_done                   :    1;  /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
-            uint32_t tx_done                       :    1;  /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-            uint32_t rs485_parity_err              :    1;  /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
-            uint32_t rs485_frm_err                 :    1;  /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
-            uint32_t rs485_clash                   :    1;  /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
-            uint32_t at_cmd_char_det               :    1;  /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
-            uint32_t wakeup                        :    1;  /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This is the enable bit for rxfifo_full_int_st register.*/
-            uint32_t txfifo_empty                  :    1;  /*This is the enable bit for txfifo_empty_int_st register.*/
-            uint32_t parity_err                    :    1;  /*This is the enable bit for parity_err_int_st register.*/
-            uint32_t frm_err                       :    1;  /*This is the enable bit for frm_err_int_st register.*/
-            uint32_t rxfifo_ovf                    :    1;  /*This is the enable bit for rxfifo_ovf_int_st register.*/
-            uint32_t dsr_chg                       :    1;  /*This is the enable bit for dsr_chg_int_st register.*/
-            uint32_t cts_chg                       :    1;  /*This is the enable bit for cts_chg_int_st register.*/
-            uint32_t brk_det                       :    1;  /*This is the enable bit for brk_det_int_st register.*/
-            uint32_t rxfifo_tout                   :    1;  /*This is the enable bit for rxfifo_tout_int_st register.*/
-            uint32_t sw_xon                        :    1;  /*This is the enable bit for sw_xon_int_st register.*/
-            uint32_t sw_xoff                       :    1;  /*This is the enable bit for sw_xoff_int_st register.*/
-            uint32_t glitch_det                    :    1;  /*This is the enable bit for glitch_det_int_st register.*/
-            uint32_t tx_brk_done                   :    1;  /*This is the enable bit for tx_brk_done_int_st register.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This is the enable bit for tx_brk_idle_done_int_st register.*/
-            uint32_t tx_done                       :    1;  /*This is the enable bit for tx_done_int_st register.*/
-            uint32_t rs485_parity_err              :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_frm_err                 :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_clash                   :    1;  /*This is the enable bit for rs485_clash_int_st register.*/
-            uint32_t at_cmd_char_det               :    1;  /*This is the enable bit for at_cmd_char_det_int_st register.*/
-            uint32_t wakeup                        :    1;  /*This is the enable bit for uart_wakeup_int_st register.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-            uint32_t txfifo_empty                  :    1;  /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
-            uint32_t parity_err                    :    1;  /*Set this bit to clear parity_err_int_raw interrupt.*/
-            uint32_t frm_err                       :    1;  /*Set this bit to clear frm_err_int_raw interrupt.*/
-            uint32_t rxfifo_ovf                    :    1;  /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-            uint32_t dsr_chg                       :    1;  /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
-            uint32_t cts_chg                       :    1;  /*Set this bit to clear the cts_chg_int_raw interrupt.*/
-            uint32_t brk_det                       :    1;  /*Set this bit to clear the brk_det_int_raw interrupt.*/
-            uint32_t rxfifo_tout                   :    1;  /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-            uint32_t sw_xon                        :    1;  /*Set this bit to clear the sw_xon_int_raw interrupt.*/
-            uint32_t sw_xoff                       :    1;  /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
-            uint32_t glitch_det                    :    1;  /*Set this bit to clear the glitch_det_int_raw interrupt.*/
-            uint32_t tx_brk_done                   :    1;  /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-            uint32_t tx_brk_idle_done              :    1;  /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-            uint32_t tx_done                       :    1;  /*Set this bit to clear the tx_done_int_raw interrupt.*/
-            uint32_t rs485_parity_err              :    1;  /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-            uint32_t rs485_frm_err                 :    1;  /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-            uint32_t rs485_clash                   :    1;  /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
-            uint32_t at_cmd_char_det               :    1;  /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-            uint32_t wakeup                        :    1;  /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t div_int                       :    12;  /*The integral part of the frequency divider factor.*/
-            uint32_t reserved12                    :    8;
-            uint32_t div_frag                      :    4;  /*The decimal part of the frequency divider factor.*/
-            uint32_t reserved24                    :    8;  /*Reserved*/
-        };
-        uint32_t val;
-    } clk_div;
-    union {
-        struct {
-            uint32_t glitch_filt                   :    8;  /*when input pulse width is lower than this value, the pulse is ignored.*/
-            uint32_t glitch_filt_en                :    1;  /*Set this bit to enable Rx signal filter.*/
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } rx_filt;
-    union {
-        struct {
-            uint32_t rxfifo_cnt                    :    10;  /*Stores the byte number of valid data in Rx-FIFO.*/
-            uint32_t reserved10                    :    3;
-            uint32_t dsrn                          :    1;  /*The register represent the level value of the internal uart dsr signal.*/
-            uint32_t ctsn                          :    1;  /*This register represent the level value of the internal uart cts signal.*/
-            uint32_t rxd                           :    1;  /*This register represent the  level value of the internal uart rxd signal.*/
-            uint32_t txfifo_cnt                    :    10;  /*Stores the byte number of data in Tx-FIFO.*/
-            uint32_t reserved26                    :    3;  /*Reserved*/
-            uint32_t dtrn                          :    1;  /*This bit represents the level of the internal uart dtr signal.*/
-            uint32_t rtsn                          :    1;  /*This bit represents the level of the internal uart rts signal.*/
-            uint32_t txd                           :    1;  /*This bit represents the  level of the internal uart txd signal.*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t parity                        :    1;  /*This register is used to configure the parity check mode.*/
-            uint32_t parity_en                     :    1;  /*Set this bit to enable uart parity check.*/
-            uint32_t bit_num                       :    2;  /*This register is used to set the length of data.*/
-            uint32_t stop_bit_num                  :    2;  /*This register is used to set the length of  stop bit.*/
-            uint32_t sw_rts                        :    1;  /*This register is used to configure the software rts signal which is used in software flow control.*/
-            uint32_t sw_dtr                        :    1;  /*This register is used to configure the software dtr signal which is used in software flow control.*/
-            uint32_t txd_brk                       :    1;  /*Set this bit to enbale transmitter to  send NULL when the process of sending data is done.*/
-            uint32_t irda_dplx                     :    1;  /*Set this bit to enable IrDA loopback mode.*/
-            uint32_t irda_tx_en                    :    1;  /*This is the start enable bit for IrDA transmitter.*/
-            uint32_t irda_wctl                     :    1;  /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
-            uint32_t irda_tx_inv                   :    1;  /*Set this bit to invert the level of  IrDA transmitter.*/
-            uint32_t irda_rx_inv                   :    1;  /*Set this bit to invert the level of IrDA receiver.*/
-            uint32_t loopback                      :    1;  /*Set this bit to enable uart loopback test mode.*/
-            uint32_t tx_flow_en                    :    1;  /*Set this bit to enable flow control function for transmitter.*/
-            uint32_t irda_en                       :    1;  /*Set this bit to enable IrDA protocol.*/
-            uint32_t rxfifo_rst                    :    1;  /*Set this bit to reset the uart receive-FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*Set this bit to reset the uart transmit-FIFO.*/
-            uint32_t rxd_inv                       :    1;  /*Set this bit to inverse the level value of uart rxd signal.*/
-            uint32_t cts_inv                       :    1;  /*Set this bit to inverse the level value of uart cts signal.*/
-            uint32_t dsr_inv                       :    1;  /*Set this bit to inverse the level value of uart dsr signal.*/
-            uint32_t txd_inv                       :    1;  /*Set this bit to inverse the level value of uart txd signal.*/
-            uint32_t rts_inv                       :    1;  /*Set this bit to inverse the level value of uart rts signal.*/
-            uint32_t dtr_inv                       :    1;  /*Set this bit to inverse the level value of uart dtr signal.*/
-            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-            uint32_t err_wr_mask                   :    1;  /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
-            uint32_t autobaud_en                   :    1;  /*This is the enable bit for detecting baudrate.*/
-            uint32_t mem_clk_en                    :    1;  /*UART memory clock gate enable signal.*/
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t rxfifo_full_thrhd             :    10;  /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
-            uint32_t txfifo_empty_thrhd            :    10;  /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
-            uint32_t dis_rx_dat_ovf                :    1;  /*Disable UART Rx data overflow detect. */
-            uint32_t rx_tout_flow_dis              :    1;  /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
-            uint32_t rx_flow_en                    :    1;  /*This is the flow enable bit for UART receiver.*/
-            uint32_t rx_tout_en                    :    1;  /*This is the enble bit for uart receiver's timeout function.*/
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } conf1;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } lowpulse;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } highpulse;
-    union {
-        struct {
-            uint32_t edge_cnt                      :    10;  /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } rxd_cnt;
-    union {
-        struct {
-            uint32_t sw_flow_con_en                :    1;  /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
-            uint32_t xonoff_del                    :    1;  /*Set this bit to remove flow control char from the received data.*/
-            uint32_t force_xon                     :    1;  /*Set this bit to enable the transmitter to go on sending data.*/
-            uint32_t force_xoff                    :    1;  /*Set this bit to stop the  transmitter from sending data.*/
-            uint32_t send_xon                      :    1;  /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
-            uint32_t send_xoff                     :    1;  /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
-            uint32_t reserved6                     :    26;  /*Reserved*/
-        };
-        uint32_t val;
-    } flow_conf;
-    union {
-        struct {
-            uint32_t active_threshold              :    10;  /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } sleep_conf;
-    union {
-        struct {
-            uint32_t xoff_threshold                :    10;  /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
-            uint32_t xoff_char                     :    8;  /*This register stores the Xoff flow control char.*/
-            uint32_t reserved18                    :    14;  /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf0;
-    union {
-        struct {
-            uint32_t xon_threshold                 :    10;  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
-            uint32_t xon_char                      :    8;  /*This register stores the Xon flow control char.*/
-            uint32_t reserved18                    :    14;  /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf1;
-    union {
-        struct {
-            uint32_t tx_brk_num                    :    8;  /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } txbrk_conf;
-    union {
-        struct {
-            uint32_t rx_idle_thrhd                 :    10;  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
-            uint32_t tx_idle_num                   :    10;  /*This register is used to configure the duration time between transfers.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } idle_conf;
-    union {
-        struct {
-            uint32_t en                            :    1;  /*Set this bit to choose the rs485 mode.*/
-            uint32_t dl0_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t dl1_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t tx_rx_en                      :    1;  /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.  */
-            uint32_t rx_busy_tx_en                 :    1;  /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
-            uint32_t rx_dly_num                    :    1;  /*This register is used to delay the receiver's internal data signal.*/
-            uint32_t tx_dly_num                    :    4;  /*This register is used to delay the transmitter's internal data signal.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } rs485_conf;
-    union {
-        struct {
-            uint32_t pre_idle_num                  :    16;  /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_precnt;
-    union {
-        struct {
-            uint32_t post_idle_num                 :    16;  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_postcnt;
-    union {
-        struct {
-            uint32_t rx_gap_tout                   :    16;  /*This register is used to configure the duration time between the at_cmd chars.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_gaptout;
-    union {
-        struct {
-            uint32_t data                          :    8;  /*This register is used to configure the content of at_cmd char.*/
-            uint32_t char_num                      :    8;  /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_char;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;
-            uint32_t rx_size                       :    3;  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
-            uint32_t tx_size                       :    3;  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
-            uint32_t rx_flow_thrhd                 :    10;  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
-            uint32_t rx_tout_thrhd                 :    10;  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
-            uint32_t force_pd                      :    1;  /*Set this bit to force power down UART memory.*/
-            uint32_t force_pu                      :    1;  /*Set this bit to force power up UART memory.*/
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } mem_conf;
-    union {
-        struct {
-            uint32_t apb_tx_waddr                  :    10;  /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
-            uint32_t reserved10                    :    1;  /*Reserved*/
-            uint32_t tx_raddr                      :    10;  /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } mem_tx_status;
-    union {
-        struct {
-            uint32_t apb_rx_raddr                  :    10;  /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/
-            uint32_t reserved10                    :    1;  /*Reserved*/
-            uint32_t rx_waddr                      :    10;  /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } mem_rx_status;
-    union {
-        struct {
-            uint32_t st_urx_out                    :    4;  /*This is the status register of receiver.*/
-            uint32_t st_utx_out                    :    4;  /*This is the status register of transmitter.*/
-            uint32_t reserved8                     :    24;  /*Reserved*/
-        };
-        uint32_t val;
-    } fsm_status;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } pospulse;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } negpulse;
-    union {
-        struct {
-            uint32_t sclk_div_b                    :    6;  /*The  denominator of the frequency divider factor.*/
-            uint32_t sclk_div_a                    :    6;  /*The numerator of the frequency divider factor.*/
-            uint32_t sclk_div_num                  :    8;  /*The integral part of the frequency divider factor.*/
-            uint32_t sclk_sel                      :    2;  /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
-            uint32_t sclk_en                       :    1;  /*Set this bit to enable UART Tx/Rx clock.*/
-            uint32_t rst_core                      :    1;  /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
-            uint32_t tx_sclk_en                    :    1;  /*Set this bit to enable UART Tx clock.*/
-            uint32_t rx_sclk_en                    :    1;  /*Set this bit to enable UART Rx clock.*/
-            uint32_t tx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Tx.*/
-            uint32_t rx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Rx.*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } clk_conf;
-    uint32_t date;
-    union {
-        struct {
-            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
-            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
-            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
-        };
-        uint32_t val;
-    } id;
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         *  Must be a unit32_t not a bitfield as to avoid
+         *  a read->write operation during writing. Reading
+         *  during writing would impact RX fifo
+         */
+        uint32_t rxfifo_rd_byte;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** rx_size : R/W; bitpos: [3:1]; default: 1;
+         *  This register is used to configure the amount of mem allocated for receive-FIFO.
+         *  The default number is 128 bytes.
+         */
+        uint32_t rx_size:3;
+        /** tx_size : R/W; bitpos: [6:4]; default: 1;
+         *  This register is used to configure the amount of mem allocated for transmit-FIFO.
+         *  The default number is 128 bytes.
+         */
+        uint32_t tx_size:3;
+        /** rx_flow_thrhd : R/W; bitpos: [16:7]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:10;
+        /** rx_tout_thrhd : R/W; bitpos: [26:17]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        /** mem_force_pd : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters, after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value, the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0 register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** sw_rts : R/W; bitpos: [6]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** sw_dtr : R/W; bitpos: [7]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** txd_brk : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [10]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [11]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxfifo_rst : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        /** rxd_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** cts_inv : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** txd_inv : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** rts_inv : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** clk_en : R/W; bitpos: [25]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        /** err_wr_mask : R/W; bitpos: [26]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [27]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [28]; default: 1;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} uart_conf0_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [9:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:10;
+        /** txfifo_empty_thrhd : R/W; bitpos: [19:10]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:10;
+        /** dis_rx_dat_ovf : R/W; bitpos: [20]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_flow_en : R/W; bitpos: [22]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        /** rx_tout_en : R/W; bitpos: [23]; default: 0;
+         *  This is the enble bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of flow_conf register
+ *  Software flow-control configuration
+ */
+typedef union {
+    struct {
+        /** sw_flow_con_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [4]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [5]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} uart_flow_conf_reg_t;
+
+/** Type of sleep_conf register
+ *  Sleep-mode configuration
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_sleep_conf_reg_t;
+
+/** Type of swfc_conf0 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xoff_threshold : R/W; bitpos: [9:0]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:10;
+        /** xoff_char : R/W; bitpos: [17:10]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} uart_swfc_conf0_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [9:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1, it will send a Xon char.
+         */
+        uint32_t xon_threshold:10;
+        /** xon_char : R/W; bitpos: [17:10]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_reg_t;
+
+/** Type of idle_conf register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_reg_t;
+
+/** Type of rs485_conf register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+         */
+        uint32_t sclk_sel:2;
+        /** sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set this bit to enable UART Tx/Rx clock.
+         */
+        uint32_t sclk_en:1;
+        /** rst_core : R/W; bitpos: [23]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+         */
+        uint32_t rst_core:1;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [9:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:10;
+        uint32_t reserved_10:3;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [25:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:10;
+        uint32_t reserved_26:3;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-FIFO write and read offset address.
+ */
+typedef union {
+    struct {
+        /** apb_tx_waddr : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
+         *  APB.
+         */
+        uint32_t apb_tx_waddr:10;
+        uint32_t reserved_10:1;
+        /** tx_raddr : RO; bitpos: [20:11]; default: 0;
+         *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+         *  Tx-FIFO_Ctrl.
+         */
+        uint32_t tx_raddr:10;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-FIFO write and read offset address.
+ */
+typedef union {
+    struct {
+        /** apb_rx_raddr : RO; bitpos: [9:0]; default: 512;
+         *  This register stores the offset address in RX-FIFO when software reads data from
+         *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+         */
+        uint32_t apb_rx_raddr:10;
+        uint32_t reserved_10:1;
+        /** rx_waddr : RO; bitpos: [20:11]; default: 512;
+         *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+         *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+         */
+        uint32_t rx_waddr:10;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maxinum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_reg_t;
+
+/** Type of at_cmd_postcnt register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_reg_t;
+
+/** Type of at_cmd_gaptout register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_reg_t;
+
+/** Type of at_cmd_char register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33587824;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [29:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:30;
+        /** high_speed : R/W; bitpos: [30]; default: 1;
+         *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
+         *  UART Core clock and UART core should be keep the same with APB clock. 0: After
+         *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
+         *  registers.
+         */
+        uint32_t high_speed:1;
+        /** reg_update : R/W/SC; bitpos: [31]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_reg_t clkdiv;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_reg_t conf0;
+    volatile uart_conf1_reg_t conf1;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_flow_conf_reg_t flow_conf;
+    volatile uart_sleep_conf_reg_t sleep_conf;
+    volatile uart_swfc_conf0_reg_t swfc_conf0;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_reg_t txbrk_conf;
+    volatile uart_idle_conf_reg_t idle_conf;
+    volatile uart_rs485_conf_reg_t rs485_conf;
+    volatile uart_at_cmd_precnt_reg_t at_cmd_precnt;
+    volatile uart_at_cmd_postcnt_reg_t at_cmd_postcnt;
+    volatile uart_at_cmd_gaptout_reg_t at_cmd_gaptout;
+    volatile uart_at_cmd_char_reg_t at_cmd_char;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_id_reg_t id;
 } uart_dev_t;
+
 extern uart_dev_t UART0;
 extern uart_dev_t UART1;
 extern uart_dev_t UART2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0x84, "Invalid size of uart_dev_t structure");
+_Static_assert(sizeof(UART0.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+_Static_assert(sizeof(UART1.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+_Static_assert(sizeof(UART2.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_UART_STRUCT_H_ */

components/vfs/vfs_uart.c

@@ -28,6 +28,7 @@
 #include "driver/uart_select.h"
 #include "esp_rom_uart.h"
 #include "soc/soc_caps.h"
+#include "hal/uart_ll.h"
 
 // TODO: make the number of UARTs chip dependent
 #define UART_NUM SOC_UART_NUM
@@ -158,14 +159,13 @@ static int uart_open(const char * path, int flags, int mode)
 static void uart_tx_char(int fd, int c)
 {
     uart_dev_t* uart = s_ctx[fd]->uart;
-    while (uart->status.txfifo_cnt >= 127) {
+    const uint8_t ch = (uint8_t) c;
+
+    while (uart_ll_get_txfifo_len(uart) < 2) {
         ;
     }
-#if CONFIG_IDF_TARGET_ESP32
-    uart->fifo.rw_byte = c;
-#else // CONFIG_IDF_TARGET_ESP32
-    uart->ahb_fifo.rw_byte = c;
-#endif
+
+    uart_ll_write_txfifo(uart, &ch, 1);
 }
 
 static void uart_tx_char_via_driver(int fd, int c)
@@ -177,14 +177,13 @@ static void uart_tx_char_via_driver(int fd, int c)
 static int uart_rx_char(int fd)
 {
     uart_dev_t* uart = s_ctx[fd]->uart;
-    if (uart->status.rxfifo_cnt == 0) {
+    uint8_t ch;
+    if (uart_ll_get_rxfifo_len(uart) == 0) {
         return NONE;
     }
-#if CONFIG_IDF_TARGET_ESP32
-    return uart->fifo.rw_byte;
-#else // CONFIG_IDF_TARGET_ESP32
-    return READ_PERI_REG(UART_FIFO_AHB_REG(fd));
-#endif
+    uart_ll_read_rxfifo(uart, &ch, 1);
+
+    return ch;
 }
 
 static int uart_rx_char_via_driver(int fd)

docs/en/api-reference/peripherals/uart.rst

@@ -1,20 +1,20 @@
 UART
 ====
 
-{IDF_TARGET_UART_NUM:default = "UART_NUM_1", esp32 = "UART_NUM_2", esp32s2 = "UART_NUM_1"}
+{IDF_TARGET_UART_NUM:default = "UART_NUM_1", esp32 = "UART_NUM_2", esp32s3 = "UART_NUM_2"}
 
 Overview
 --------
 
 A Universal Asynchronous Receiver/Transmitter (UART) is a hardware feature that handles communication (i.e., timing requirements and data framing) using widely-adopted asynchronous serial communication interfaces, such as RS232, RS422, RS485. A UART provides a widely adopted and cheap method to realize full-duplex or half-duplex data exchange among different devices.
 
-.. only:: esp32
+.. only:: esp32 or esp32s3
 
-    The ESP32 chip has three UART controllers (UART0, UART1, and UART2) that feature an identical set of registers for ease of programming and flexibility.
+    The {IDF_TARGET_NAME} chip has three UART controllers (UART0, UART1, and UART2), each featuring an identical set of registers to simplify programming and for more flexibility.
 
 .. only:: esp32s2 or esp32c3
 
-    The {IDF_TARGET_NAME} chip has two UART controllers (UART0 and UART1) that feature an identical set of registers for ease of programming and flexibility.
+    The {IDF_TARGET_NAME} chip has two UART controllers (UART0 and UART1), each featuring an identical set of registers to simplify programming and for more flexibility.
 
 Each UART controller is independently configurable with parameters such as baud rate, data bit length, bit ordering, number of stop bits, parity bit etc. All the controllers are compatible with UART-enabled devices from various manufacturers and can also support Infrared Data Association protocols (IrDA).
 
@@ -99,28 +99,10 @@ After setting communication parameters, configure the physical GPIO pins to whic
 
 The same macro should be specified for pins that will not be used.
 
+.. code-block:: c
 
-
-.. only:: esp32
-
-  .. code-block:: c
-
-    // Set UART pins(TX: IO17 (UART2 default), RX: IO16 (UART2 default), RTS: IO18, CTS: IO19)
-    ESP_ERROR_CHECK(uart_set_pin(UART_NUM_2, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, 18, 19));
-
-.. only:: esp32s2
-
-  .. code-block:: c
-
-    // Set UART pins(TX: IO17 (UART1 default), RX: IO18 (UART1 default), RTS: IO19, CTS: IO20)
-    ESP_ERROR_CHECK(uart_set_pin(UART_NUM_1, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, 19, 20));
-
-.. only:: esp32c3
-
-  .. code-block:: c
-  
-    // Set UART pins(TX: IO4, RX: IO5, RTS: IO19, CTS: IO20)
-    ESP_ERROR_CHECK(uart_set_pin(UART_NUM_1, 4, 5, 19, 20));
+  // Set UART pins(TX: IO4, RX: IO5, RTS: IO18, CTS: IO19)
+  ESP_ERROR_CHECK(uart_set_pin({IDF_TARGET_UART_NUM}, 4, 5, 18, 19));
 
 .. _uart-api-driver-installation:
 

examples/peripherals/uart/nmea0183_parser/README.md

@@ -12,7 +12,7 @@ For the convenience of the presentation, this example will only parse the follow
 * RMC
 * GLL
 * VTG
-  
+
 See [Limitation for multiple navigation system](#Limitation) for more information about this example.
 
 Usually, modules will also output some vendor specific statements which common nmea library can not cover. In this example, the NMEA Parser will propagate all unknown statements to the user, where a custom handler can parse information from it.
@@ -21,20 +21,19 @@ Usually, modules will also output some vendor specific statements which common n
 
 ### Hardware Required
 
-To run this example, you need an ESP32 dev board (e.g. ESP32-WROVER Kit) or ESP32 core board (e.g. ESP32-DevKitC). For test purpose, you also need a GPS module. Here we take the [ATGM332D-5N](http://www.icofchina.com/pro/mokuai/2016-08-01/5.html) as an example to show how to parse the NMEA statements and output common information such as UTC time, latitude, longitude, altitude, speed and so on.
+To run this example, you need an ESP32, ESP32-S or ESP32-C series dev board (e.g. ESP32-WROVER Kit). For test purpose, you also need a GPS module. Here we take the [ATGM332D-5N](http://www.icofchina.com/pro/mokuai/2016-08-01/5.html) as an example to show how to parse the NMEA statements and output common information such as UTC time, latitude, longitude, altitude, speed and so on.
 
 #### Pin Assignment:
 
 **Note:** The following pin assignments are used by default which can be changed in `nmea_parser_config_t` structure.
 
-| ESP32            | GPS             |
-| ---------------- | --------------- |
-| UART-TX (option) | GPS-RX (option) |
-| UART-RX          | GPS-TX          |
-| GND              | GND             |
-| 5V               | VCC             |
+| ESP                        | GPS             |
+| -------------------------- | --------------- |
+| UART-RX (GPIO5 by default) | GPS-TX          |
+| GND                        | GND             |
+| 5V                         | VCC             |
 
-**Note:** UART TX pin in ESP32 is not necessary if you only use uart to receive data.
+**Note:** UART TX pin is not necessary if you only use UART to receive data.
 
 
 ### Configure the project
@@ -60,38 +59,38 @@ See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/l
 I (0) cpu_start: Starting scheduler on APP CPU.
 I (317) uart: queue free spaces: 16
 I (317) nmea_parser: NMEA Parser init OK
-I (1067) gps_demo: 2018/12/4 13:59:34 => 
+I (1067) gps_demo: 2018/12/4 13:59:34 =>
 						latitude   = 31.20177°N
 						longitude = 121.57933°E
 						altitude   = 17.30m
 						speed      = 0.370400m/s
 W (1177) gps_demo: Unknown statement:$GPTXT,01,01,01,ANTENNA OK*35
-I (2067) gps_demo: 2018/12/4 13:59:35 => 
+I (2067) gps_demo: 2018/12/4 13:59:35 =>
 						latitude   = 31.20177°N
 						longitude  = 121.57933°E
 						altitude   = 17.30m
 						speed      = 0.000000m/s
 W (2177) gps_demo: Unknown statement:$GPTXT,01,01,01,ANTENNA OK*35
-I (3067) gps_demo: 2018/12/4 13:59:36 => 
+I (3067) gps_demo: 2018/12/4 13:59:36 =>
 						latitude   = 31.20178°N
 						longitude  = 121.57933°E
 						altitude   = 17.30m
 						speed      = 0.000000m/s
 W (3177) gps_demo: Unknown statement:$GPTXT,01,01,01,ANTENNA OK*35
-I (4067) gps_demo: 2018/12/4 13:59:37 => 
+I (4067) gps_demo: 2018/12/4 13:59:37 =>
 						latitude   = 31.20178°N
 						longitude  = 121.57933°E
 						altitude   = 17.30m
 						speed      = 0.000000m/s
 W (4177) gps_demo: Unknown statement:$GPTXT,01,01,01,ANTENNA OK*35
-I (5067) gps_demo: 2018/12/4 13:59:38 => 
+I (5067) gps_demo: 2018/12/4 13:59:38 =>
 						latitude   = 31.20178°N
 						longitude  = 121.57933°E
 						altitude   = 17.30m
 						speed      = 0.685240m/s
 W (5177) gps_demo: Unknown statement:$GPTXT,01,01,01,ANTENNA OK*35
 ```
-As shown above, ESP32 finally got the information after parsed the NMEA0183 format statements. But as we didn't add `GPTXT` type statement in the library (that means it is UNKNOWN to NMEA Parser library), so it was propagated to user without any process.
+As shown above, the ESP board finally got the information after parsed the NMEA0183 format statements. But as we didn't add `GPTXT` type statement in the library (that means it is UNKNOWN to NMEA Parser library), so it was propagated to user without any process.
 
 ## Troubleshooting
 
@@ -99,7 +98,7 @@ As shown above, ESP32 finally got the information after parsed the NMEA0183 form
    * Test your GPS via other terminal (e.g. minicom, putty) to check the right communication parameters (e.g. baudrate supported by GPS).
 
 ## Limitation
-If the GPS module supports multiple satellite navigation system (e.g. GPS, BDS), then the satellite ids and descriptions may be delivered in different statements (e.g. GPGSV, BDGSV, GPGSA, BDGSA), depend on the version of NMEA protocol used by the GPS module. This example currently can only record id and description of satellites from one navigation system. 
+If the GPS module supports multiple satellite navigation system (e.g. GPS, BDS), then the satellite ids and descriptions may be delivered in different statements (e.g. GPGSV, BDGSV, GPGSA, BDGSA), depend on the version of NMEA protocol used by the GPS module. This example currently can only record id and description of satellites from one navigation system.
 However, for other statements, this example can parse them correctly whatever the navigation system is.
 
 ### Steps to skip the limitation

examples/peripherals/uart/nmea0183_parser/main/Kconfig.projbuild

@@ -1,5 +1,16 @@
 menu "Example Configuration"
 
+    config NMEA_PARSER_UART_RXD
+        int "UART RXD pin number"
+        range 0 34 if IDF_TARGET_ESP32
+        range 0 46 if IDF_TARGET_ESP32S2
+        range 0 48 if IDF_TARGET_ESP32S3
+        range 0 19 if IDF_TARGET_ESP32C3
+        default 5
+        help
+            GPIO number for UART RX pin. See UART documentation for more information
+            about available pin numbers for UART.
+
     config NMEA_PARSER_RING_BUFFER_SIZE
         int "NMEA Parser Ring Buffer Size"
         range 0 2048

examples/peripherals/uart/uart_async_rxtxtasks/README.md

@@ -13,7 +13,7 @@ The example starts two FreeRTOS tasks:
 
 ### Hardware Required
 
-The example can be run on any commonly available ESP32 development board. You will need a USB cable to connect the
+The example can be run on any commonly available ESP32, ESP32-S and ESP32-C series based development board. You will need a USB cable to connect the
 development board to a computer, and a simple one-wire cable for shorting two pins of the board.
 
 ### Setup the Hardware

examples/peripherals/uart/uart_echo/README.md

@@ -9,23 +9,23 @@ configured UART.
 
 ### Hardware Required
 
-The example can be run on any ESP32 or ESP32-S2 based development board connected to a PC with a single USB cable for flashing and
+The example can be run on any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a single USB cable for flashing and
 monitoring. The external interface should have 3.3V outputs. You may use e.g. 3.3V compatible USB-to-Serial dongle.
 
 ### Setup the Hardware
 
-Connect the external serial interface to the ESP32(S2) board as follows.
-  
+Connect the external serial interface to the board as follows.
+
 ```
   ---------------------------------------------------------------------------------------
-  | Target chip Interface | #define          | Default ESP32(S2) Pin| External UART Pin |
+  | Target chip Interface | #define          | Default ESP Pin      | External UART Pin |
   | ----------------------|------------------|----------------------|--------------------
   | Transmit Data (TxD)   | EXAMPLE_UART_TXD | GPIO4                | RxD               |
   | Receive Data (RxD)    | EXAMPLE_UART_RXD | GPIO5                | TxD               |
   | Ground                | n/a              | GND                  | GND               |
   ---------------------------------------------------------------------------------------
 ```
-Note: The GPIO22 - GPIO25 can not be used with ESP32-S2 chip because they are reserved for internal use. Please refer to UART documentation for selected target.
+Note: Some GPIOs can not be used with certain chips because they are reserved for internal use. Please refer to UART documentation for selected target.
 
 Optionally, you can set-up and use a serial interface that has RTS and CTS signals in order to verify that the
 hardware control flow works. Connect the extra signals according to the following table, configure both extra pins in
@@ -35,7 +35,7 @@ UART1 driver to use the hardware flow control by setting `.flow_ctrl = UART_HW_F
 
 ```
   --------------------------------------------------------------------------------------
-  | Target chip Interface | #define         | Default ESP32(S2) Pin| External UART Pin |
+  | Target chip Interface | #define         | Default ESP Pin      | External UART Pin |
   | ----------------------|-----------------|----------------------|--------------------
   | Transmit Data (TxD)   | ECHO_TEST_RTS   | GPIO18               | CTS               |
   | Receive Data (RxD)    | ECHO_TEST_CTS   | GPIO19               | RTS               |
@@ -65,8 +65,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui
 
 ## Example Output
 
-Type some characters in the terminal connected to the external serial interface. As result you should see echo in the
-terminal which is used for flashing and monitoring. You can verify if the echo indeed comes from ESP32(S2) board by
+Type some characters in the terminal connected to the external serial interface. As result you should see echo in the same terminal which you used for typing the characters. You can verify if the echo indeed comes from ESP board by
 disconnecting either `TxD` or `RxD` pin: no characters will appear when typing.
 
 ## Troubleshooting

examples/peripherals/uart/uart_echo/main/Kconfig.projbuild

@@ -2,9 +2,9 @@ menu "Echo Example Configuration"
 
     config EXAMPLE_UART_PORT_NUM
         int "UART port number"
-        range 0 2 if IDF_TARGET_ESP32
+        range 0 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
         range 0 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3
-        default 2 if IDF_TARGET_ESP32
+        default 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
         default 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3
         help
             UART communication port number for the example.
@@ -20,7 +20,7 @@ menu "Echo Example Configuration"
     config EXAMPLE_UART_RXD
         int "UART RXD pin number"
         range 0 34 if IDF_TARGET_ESP32
-        range 0 46 if IDF_TARGET_ESP32S2
+        range 0 46 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
         range 0 19 if IDF_TARGET_ESP32C3
         default 5
         help
@@ -30,7 +30,7 @@ menu "Echo Example Configuration"
     config EXAMPLE_UART_TXD
         int "UART TXD pin number"
         range 0 34 if IDF_TARGET_ESP32
-        range 0 46 if IDF_TARGET_ESP32S2
+        range 0 46 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
         range 0 19 if IDF_TARGET_ESP32C3
         default 4
         help

examples/peripherals/uart/uart_echo_rs485/README.md

@@ -9,7 +9,7 @@ The approach demonstrated in this example can be used in user application to tra
 ## How to use example
 
 ### Hardware Required
-PC + USB Serial adapter connected to USB port + RS485 line drivers + ESP32-WROVER-KIT board.
+PC + USB Serial adapter connected to USB port + RS485 line drivers + ESP32, ESP32-S or ESP32-C series based board.
 The MAX485 line driver is used for example below but other similar chips can be used as well.
 
 #### RS485 example connection circuit schematic:
@@ -20,7 +20,7 @@ The MAX485 line driver is used for example below but other similar chips can be
          RXD <------| RO            |               |             RO|-----> RXD
                     |              B|---------------|B              |
          TXD ------>| DI  MAX485    |    \  /       |    MAX485   DI|<----- TXD
-ESP32-WROVER-KIT    |               |   RS-485 side |               |  SERIAL ADAPTER SIDE
+ESP dev kit         |               |   RS-485 side |               |  SERIAL ADAPTER SIDE
          RTS --+--->| DE            |    /  \       |             DE|---+
                |    |              A|---------------|A              |   |
                +----| /RE           |               |            /RE|---+-- RTS
@@ -29,19 +29,19 @@ ESP32-WROVER-KIT    |               |   RS-485 side |               |  SERIAL AD
                            ---                             ---
 ```
 
-#### Connect an external RS485 serial interface to an ESP32 board
-Connect USB to RS485 adapter to computer and connect its D+, D- output lines with the D+, D- lines of RS485 line driver connected to ESP32 (See picture above).
+#### Connect an external RS485 serial interface to an ESP board
+Connect USB to RS485 adapter to computer and connect its D+, D- output lines with the D+, D- lines of RS485 line driver connected to the ESP board (See picture above). To view or adjust default pins please see the `Echo RS485 Example Configuration` submenu in `idf.py menuconfig`.
 ```
-  --------------------------------------------------------------------------------------------------------------------------
-  | ESP32 Interface       | #define            | Default ESP32 Pin     | Default ESP32-S2 Pins | External RS485 Driver Pin |
-  | ----------------------|--------------------|-----------------------|-----------------------|---------------------------|
-  | Transmit Data (TxD)   | CONFIG_MB_UART_TXD | GPIO23                | GPIO20                | DI                        |
-  | Receive Data (RxD)    | CONFIG_MB_UART_RXD | GPIO22                | GPIO19                | RO                        |
-  | Request To Send (RTS) | CONFIG_MB_UART_RTS | GPIO18                | GPIO18                | ~RE/DE                    |
-  | Ground                | n/a                | GND                   | GND                   | GND                       |
-  --------------------------------------------------------------------------------------------------------------------------
+  --------------------------------------------------------------------------------------------------
+  | ESP Interface         | #define            | Default ESP Pin       | External RS485 Driver Pin |
+  | ----------------------|--------------------|-----------------------|---------------------------|
+  | Transmit Data (TxD)   | CONFIG_MB_UART_TXD | CONFIG_ECHO_UART_TXD  | DI                        |
+  | Receive Data (RxD)    | CONFIG_MB_UART_RXD | CONFIG_ECHO_UART_RXD  | RO                        |
+  | Request To Send (RTS) | CONFIG_MB_UART_RTS | CONFIG_ECHO_UART_RTS  | ~RE/DE                    |
+  | Ground                | n/a                | GND                   | GND                       |
+  --------------------------------------------------------------------------------------------------
 ```
-Note: The GPIO22 - GPIO25 can not be used with ESP32-S2 chip because they are used for flash chip connection. Please refer to UART documentation for selected target.
+Note: Some GPIOs can not be used with some chip because they are used for flash chip connection. Please refer to UART documentation for selected target.
 
 ### Configure the project
 ```
@@ -62,7 +62,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui
 Refer to the example and set up a serial terminal program to the same settings as of UART in ESP32-WROVER-KIT board.
 Open the external serial interface in the terminal. By default if no any symbols are received, the application sends character `.` to check transmission side.
 When typing message and push send button in the terminal you should see the message `RS485 Received: [ your message ]`, where "your message" is the message you sent from terminal.
-Verify if echo indeed comes from ESP32 by disconnecting either `TxD` or `RxD` pin. Once done there should be no any `.` displayed.
+Verify if echo indeed comes from your board by disconnecting either `TxD` or `RxD` pin. Once done there should be no any `.` displayed.
 
 ## Example Output
 Example output of the application:

examples/peripherals/uart/uart_echo_rs485/main/Kconfig.projbuild

@@ -2,9 +2,9 @@ menu "Echo RS485 Example Configuration"
 
     config ECHO_UART_PORT_NUM
         int "UART port number"
-        range 0 2 if IDF_TARGET_ESP32
+        range 0 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
         range 0 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3
-        default 2 if IDF_TARGET_ESP32
+        default 2 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
         default 1 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3
         help
             UART communication port number for the example.
@@ -23,8 +23,9 @@ menu "Echo RS485 Example Configuration"
         default 22 if IDF_TARGET_ESP32
         range 0 46 if IDF_TARGET_ESP32S2
         default 19 if IDF_TARGET_ESP32S2
+        range 0 48 if IDF_TARGET_ESP32S3
         range 0 19 if IDF_TARGET_ESP32C3
-        default 5  if IDF_TARGET_ESP32C3
+        default 5  if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
         help
             GPIO number for UART RX pin. See UART documentation for more information
             about available pin numbers for UART.
@@ -35,8 +36,9 @@ menu "Echo RS485 Example Configuration"
         default 23 if IDF_TARGET_ESP32
         range 0 46 if IDF_TARGET_ESP32S2
         default 20 if IDF_TARGET_ESP32S2
+        range 0 48 if IDF_TARGET_ESP32S3
         range 0 19 if IDF_TARGET_ESP32C3
-        default 4  if IDF_TARGET_ESP32C3
+        default 4  if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
         help
             GPIO number for UART TX pin. See UART documentation for more information
             about available pin numbers for UART.
@@ -45,6 +47,7 @@ menu "Echo RS485 Example Configuration"
         int "UART RTS pin number"
         range 0 34 if IDF_TARGET_ESP32
         range 0 46 if IDF_TARGET_ESP32S2
+        range 0 48 if IDF_TARGET_ESP32S3
         range 0 19 if IDF_TARGET_ESP32C3
         default 18
         help

examples/peripherals/uart/uart_events/README.md

@@ -9,7 +9,7 @@ and echoes it back to the monitoring console.
 
 ### Hardware Required
 
-The example can be used with any ESP32 development board connected to a computer with a USB cable.
+The example can be used with any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a USB cable.
 
 ### Configure the project
 

examples/peripherals/uart/uart_select/README.md

@@ -20,7 +20,7 @@ For a more comprehensive example please refer to `system/select`.
 
 ### Hardware Required
 
-The example can be run on any ESP32 development board connected to a PC with a single USB cable for communication
+The example can be run on any ESP32, ESP32-S and ESP32-C series based development board connected to a computer with a single USB cable for communication
 through UART.
 
 ### Configure the project