Merge branch 'feature/add_esp32p4_hello_world' into 'master'

esp32p4: introduced new chip ESP32P4: Hello World! :earth_asia:

Closes IDF-7523

See merge request espressif/esp-idf!25013

.gitlab/ci/dependencies/dependencies.yml

@@ -6,6 +6,7 @@
   - esp32c2
   - esp32c6
   - esp32h2
+  - esp32p4
 
 .target_test: &target_test
   - example_test

.gitlab/ci/rules.yml

@@ -509,6 +509,9 @@
 .if-label-component_ut_esp32h2: &if-label-component_ut_esp32h2
   if: '$BOT_LABEL_COMPONENT_UT_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h2(?:,[^,\n\r]+)*$/i'
 
+.if-label-component_ut_esp32p4: &if-label-component_ut_esp32p4
+  if: '$BOT_LABEL_COMPONENT_UT_ESP32P4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32p4(?:,[^,\n\r]+)*$/i'
+
 .if-label-component_ut_esp32s2: &if-label-component_ut_esp32s2
   if: '$BOT_LABEL_COMPONENT_UT_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32s2(?:,[^,\n\r]+)*$/i'
 
@@ -533,6 +536,9 @@
 .if-label-custom_test_esp32h2: &if-label-custom_test_esp32h2
   if: '$BOT_LABEL_CUSTOM_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h2(?:,[^,\n\r]+)*$/i'
 
+.if-label-custom_test_esp32p4: &if-label-custom_test_esp32p4
+  if: '$BOT_LABEL_CUSTOM_TEST_ESP32P4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32p4(?:,[^,\n\r]+)*$/i'
+
 .if-label-custom_test_esp32s2: &if-label-custom_test_esp32s2
   if: '$BOT_LABEL_CUSTOM_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32s2(?:,[^,\n\r]+)*$/i'
 
@@ -560,6 +566,9 @@
 .if-label-example_test_esp32h2: &if-label-example_test_esp32h2
   if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h2(?:,[^,\n\r]+)*$/i'
 
+.if-label-example_test_esp32p4: &if-label-example_test_esp32p4
+  if: '$BOT_LABEL_EXAMPLE_TEST_ESP32P4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32p4(?:,[^,\n\r]+)*$/i'
+
 .if-label-example_test_esp32s2: &if-label-example_test_esp32s2
   if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s2(?:,[^,\n\r]+)*$/i'
 
@@ -614,6 +623,9 @@
 .if-label-unit_test_esp32h2: &if-label-unit_test_esp32h2
   if: '$BOT_LABEL_UNIT_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h2(?:,[^,\n\r]+)*$/i'
 
+.if-label-unit_test_esp32p4: &if-label-unit_test_esp32p4
+  if: '$BOT_LABEL_UNIT_TEST_ESP32P4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32p4(?:,[^,\n\r]+)*$/i'
+
 .if-label-unit_test_esp32s2: &if-label-unit_test_esp32s2
   if: '$BOT_LABEL_UNIT_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s2(?:,[^,\n\r]+)*$/i'
 
@@ -660,6 +672,7 @@
     - <<: *if-label-component_ut_esp32c3
     - <<: *if-label-component_ut_esp32c6
     - <<: *if-label-component_ut_esp32h2
+    - <<: *if-label-component_ut_esp32p4
     - <<: *if-label-component_ut_esp32s2
     - <<: *if-label-component_ut_esp32s3
     - <<: *if-label-lan8720
@@ -670,6 +683,7 @@
     - <<: *if-label-unit_test_esp32c3
     - <<: *if-label-unit_test_esp32c6
     - <<: *if-label-unit_test_esp32h2
+    - <<: *if-label-unit_test_esp32p4
     - <<: *if-label-unit_test_esp32s2
     - <<: *if-label-unit_test_esp32s3
     - <<: *if-dev-push
@@ -962,6 +976,7 @@
     - <<: *if-label-custom_test_esp32c3
     - <<: *if-label-custom_test_esp32c6
     - <<: *if-label-custom_test_esp32h2
+    - <<: *if-label-custom_test_esp32p4
     - <<: *if-label-custom_test_esp32s2
     - <<: *if-label-custom_test_esp32s3
     - <<: *if-label-target_test
@@ -1541,6 +1556,7 @@
     - <<: *if-label-component_ut_esp32c3
     - <<: *if-label-component_ut_esp32c6
     - <<: *if-label-component_ut_esp32h2
+    - <<: *if-label-component_ut_esp32p4
     - <<: *if-label-component_ut_esp32s2
     - <<: *if-label-component_ut_esp32s3
     - <<: *if-label-custom_test
@@ -1549,6 +1565,7 @@
     - <<: *if-label-custom_test_esp32c3
     - <<: *if-label-custom_test_esp32c6
     - <<: *if-label-custom_test_esp32h2
+    - <<: *if-label-custom_test_esp32p4
     - <<: *if-label-custom_test_esp32s2
     - <<: *if-label-custom_test_esp32s3
     - <<: *if-label-example_test
@@ -1557,6 +1574,7 @@
     - <<: *if-label-example_test_esp32c3
     - <<: *if-label-example_test_esp32c6
     - <<: *if-label-example_test_esp32h2
+    - <<: *if-label-example_test_esp32p4
     - <<: *if-label-example_test_esp32s2
     - <<: *if-label-example_test_esp32s3
     - <<: *if-label-integration_test
@@ -1570,6 +1588,7 @@
     - <<: *if-label-unit_test_esp32c3
     - <<: *if-label-unit_test_esp32c6
     - <<: *if-label-unit_test_esp32h2
+    - <<: *if-label-unit_test_esp32p4
     - <<: *if-label-unit_test_esp32s2
     - <<: *if-label-unit_test_esp32s3
     - <<: *if-dev-push
@@ -1645,6 +1664,7 @@
     - <<: *if-label-unit_test_esp32c3
     - <<: *if-label-unit_test_esp32c6
     - <<: *if-label-unit_test_esp32h2
+    - <<: *if-label-unit_test_esp32p4
     - <<: *if-label-unit_test_esp32s2
     - <<: *if-label-unit_test_esp32s3
     - <<: *if-dev-push

components/bootloader/Kconfig.projbuild

@@ -5,6 +5,8 @@ menu "Bootloader config"
     config BOOTLOADER_OFFSET_IN_FLASH
         hex
         default 0x1000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
+        # the first 2 sectors are reserved for the key manager with AES-XTS (flash encryption) purpose
+        default 0x2000 if IDF_TARGET_ESP32P4
         default 0x0
         help
             Offset address that 2nd bootloader will be flashed to.
@@ -867,7 +869,9 @@ menu "Security features"
         default y if (SOC_EFUSE_DIS_ICACHE || IDF_TARGET_ESP32) && SECURE_FLASH_ENC_ENABLED
 
     menu "Potentially insecure options"
-        visible if SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT || SECURE_BOOT_INSECURE || SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT # NOERROR
+        visible if (SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT || \
+            SECURE_BOOT_INSECURE || \
+            SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT) # NOERROR
 
         # NOTE: Options in this menu NEED to have SECURE_BOOT_INSECURE
         # and/or SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT in "depends on", as the menu
@@ -971,7 +975,8 @@ menu "Security features"
 
         config SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
             bool "Leave UART bootloader flash cache enabled"
-            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE) # NOERROR
+            depends on SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && \
+                (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE) # NOERROR
             default N
             select SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE if SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE
             help

components/bootloader/subproject/main/ld/esp32p4/bootloader.ld

@@ -0,0 +1,250 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/**
+ * TODO: IDF-8002
+ * Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  ESP32-P4 ROM static data usage is as follows:
+ *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4087c610 - 0x4087e610: CPU1 stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087c610).
+ */
+
+/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4ff3abd0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x4000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2000;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32p4/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4FF2DBD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ * 0x4086ad08 ------------------> _dram0_0_start
+ *            |               |
+ *            |               |
+ *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *            |               |
+ *            |               |
+ * 0x4087c610 ------------------> __stack_sentry
+ *            |               |
+ *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *            |               |
+ * 0x4087e610 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |
+ *            |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *            |               |      (can be freed when IDF runs)
+ *            |               |
+ *            |               |
+ * 0x4087f564 ------------------> _dram0_rtos_reserved_start
+ *            |               |
+ *            |               |
+ *            |               |   4. Shared memory used in startup code and when IDF runs
+ *            |               |
+ *            |               |
+ * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
+ *            |               |
+ * 0x4087fce8 ------------------> _data_start_interface
+ *            |               |
+ *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *            |               |
+ * 0x40880000 ------------------> _data_end_interface
+ */

components/bootloader/subproject/main/ld/esp32p4/bootloader.rom.ld

@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-P4 target */

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -12,6 +12,10 @@
 #include "soc/soc_caps.h"
 #include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"
+#if CONFIG_IDF_TARGET_ESP32P4
+//TODO: IDF-7516
+#include "esp32p4/rom/cache.h"
+#endif
 
 #if CONFIG_IDF_TARGET_ESP32
 #   include "soc/spi_struct.h"
@@ -145,7 +149,12 @@ static const char *TAG = "bootloader_flash";
    63th block for bootloader_flash_read
 */
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
+#if CONFIG_IDF_TARGET_ESP32P4
+//TODO: IDF-7918
+#define MMAP_MMU_SIZE     (DRAM_FLASH_ADDRESS_HIGH - DRAM_FLASH_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#else
 #define MMAP_MMU_SIZE     (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#endif
 #define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE - SPI_FLASH_MMU_PAGE_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK63_VADDR
 #endif
@@ -229,6 +238,14 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
 #else
+#if CONFIG_IDF_TARGET_ESP32P4
+    /**
+     * TODO: IDF-7516
+     * we need to invalidate l1 dcache to make each mmap clean
+     * to that vaddr
+     */
+    Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE, MMU_BLOCK0_VADDR, actual_mapped_len);
+#endif
     cache_hal_enable(CACHE_TYPE_ALL);
 #endif
 
@@ -324,6 +341,10 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
 #if CONFIG_IDF_TARGET_ESP32
             Cache_Read_Enable(0);
 #else
+#if CONFIG_IDF_TARGET_ESP32P4
+            //TODO: IDF-7516
+            Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE, FLASH_READ_VADDR, actual_mapped_len);
+#endif
             cache_hal_enable(CACHE_TYPE_ALL);
 #endif
         }

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c

@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_rom_gpio.h"
+#include "soc/gpio_periph.h"
+#include "soc/spi_mem_reg.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_init.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/mmu_ll.h"
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+static const char *TAG = "boot.esp32p4";
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    cache_hal_disable(CACHE_TYPE_ALL);
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+    cache_hal_enable(CACHE_TYPE_ALL);
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        str = "20MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        str = "80MHz";
+        break;
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
+    switch (spi_mode) {
+    case ESP_ROM_SPIFLASH_QIO_MODE:
+        str = "QIO";
+        break;
+    case ESP_ROM_SPIFLASH_QOUT_MODE:
+        str = "QOUT";
+        break;
+    case ESP_ROM_SPIFLASH_DIO_MODE:
+        str = "DIO";
+        break;
+    case ESP_ROM_SPIFLASH_DOUT_MODE:
+        str = "DOUT";
+        break;
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        str = "FAST READ";
+        break;
+    default:
+        str = "SLOW READ";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+esp_err_t bootloader_init_spi_flash(void)
+{
+    bootloader_init_flash_configure();
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+    update_flash_config(&bootloader_image_hdr);
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}

components/bootloader_support/include/bootloader_memory_utils.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -164,6 +164,20 @@ inline static void * esp_ptr_diram_iram_to_dram(const void *p) {
 #endif
 }
 
+#if SOC_MEM_TCM_SUPPORTED
+/**
+ * @brief Check if the pointer is in TCM
+ *
+ * @param p pointer
+ *
+ * @return true: is in TCM; false: not in TCM
+ */
+__attribute__((always_inline))
+inline static bool esp_ptr_in_tcm(const void *p) {
+    return ((intptr_t)p >= SOC_TCM_LOW && (intptr_t)p < SOC_TCM_HIGH);
+}
+#endif  //#if SOC_MEM_TCM_SUPPORTED
+
 /** End of the common section that has to be in sync with esp_memory_utils.h **/
 /** Don't add new functions below **/
 

components/bootloader_support/private_include/bootloader_signature.h

@@ -23,6 +23,8 @@
 #include "esp32c6/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/secure_boot.h"
 #endif
 
 #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300

components/bootloader_support/src/bootloader_clock_init.c

@@ -9,7 +9,7 @@
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4// TODO: IDF-5645
 #include "soc/rtc_cntl_reg.h"
 #else
 #include "soc/lp_wdt_reg.h"
@@ -86,7 +86,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     }
 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
 
-// TODO: IDF-5645
 #if CONFIG_IDF_TARGET_ESP32C6
     // CLR ENA
     CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA);                                      /* SWD */
@@ -113,6 +112,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR);                                           /* WDT */
     SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR);                                          /* SLP_REJECT */
     SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR);                                    /* SLP_WAKEUP */
+#elif CONFIG_IDF_TARGET_ESP32P4
+// TODO: IDF-8008
 #else
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);

components/bootloader_support/src/bootloader_efuse.c

@@ -34,6 +34,9 @@ int bootloader_clock_get_rated_freq_mhz(void)
     //IDF-6570
     return 96;
 
+#elif CONFIG_IDF_TARGET_ESP32P4
+    return 400;
+
 #elif CONFIG_IDF_TARGET_ESP32S2
     return 240;
 

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
+#include "esp_log.h"
+
+static const char *TAG = "bootloader_random";
+
+void bootloader_random_enable(void)
+{
+    // TODO: IDF-6522
+    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+}
+
+void bootloader_random_disable(void)
+{
+    // TODO: IDF-6522
+    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+}

components/bootloader_support/src/bootloader_utility.c

@@ -45,6 +45,7 @@
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/rom/uart.h"
 #include "esp32h2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
 
 #else // CONFIG_IDF_TARGET_*
 #error "Unsupported IDF_TARGET"

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -0,0 +1,171 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_efuse.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_spiflash.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/cache_reg.h"
+#include "soc/io_mux_reg.h"
+#include "esp32p4/rom/efuse.h"
+#include "esp32p4/rom/ets_sys.h"
+#include "esp32p4/rom/spi_flash.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
+#include "esp_private/bootloader_flash_internal.h"
+#include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/lp_wdt_reg.h"
+#include "hal/efuse_hal.h"
+
+static const char *TAG = "boot.esp32p4";
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    //TODO: IDF-7688
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
+    REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+    REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
+}
+
+static inline void bootloader_hardware_init(void)
+{
+    //TODO: IDF-7528
+    // /* Enable analog i2c master clock */
+    // SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    // SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+}
+
+static inline void bootloader_ana_reset_config(void)
+{
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    bootloader_hardware_init();
+    bootloader_ana_reset_config();
+    bootloader_super_wdt_auto_feed();
+
+// In RAM_APP, memory will be initialized in `call_start_cpu0`
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    //init cache hal
+    cache_hal_init();
+    //reset mmu
+    mmu_hal_init();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
+        ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
+        return ret;
+    }
+#if !CONFIG_APP_BUILD_TYPE_RAM
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        return ret;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        return ret;
+    }
+#endif // !CONFIG_APP_BUILD_TYPE_RAM
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        return ret;
+    }
+#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+
+    // check whether a WDT reset happend
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+
+    return ret;
+}

components/bootloader_support/src/esp32p4/bootloader_sha.c

@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp32p4/rom/sha.h"
+
+static SHA_CTX ctx;
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    /* P4 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key.
+     * While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes.
+     * ets_sha_update handles it cleanly so we can safely remove the check:
+     * assert(data_len % 4) == 0
+     */
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}

components/bootloader_support/src/esp32p4/bootloader_soc.c

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    //TODO: IDF-7514
+}
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+    //TODO: IDF-7514
+}
+
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+    //TODO: IDF-7514
+}

components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c

@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "flash_encrypt";
+
+esp_err_t esp_flash_encryption_enable_secure_features(void)
+{
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
+    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
+    // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
+    // otherwise the Flash Encryption key cannot be read protected
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+#endif
+
+    return ESP_OK;
+}

components/bootloader_support/src/esp32p4/secure_boot_secure_features.c

@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "secure_boot";
+
+esp_err_t esp_secure_boot_enable_secure_features(void)
+{
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Enabling Security download mode...");
+    esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not enable Security download mode...");
+        return err;
+    }
+#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Disable ROM Download mode...");
+    esp_err_t err = esp_efuse_disable_rom_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not disable ROM Download mode...");
+        return err;
+    }
+#else
+    ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable hardware & software JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+    esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
+
+#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
+    bool rd_dis_now = true;
+#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
+    /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
+       when Flash Encryption is being enabled */
+    rd_dis_now = esp_flash_encryption_enabled();
+#endif
+    if (rd_dis_now) {
+        ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+    }
+#else
+    ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
+#endif
+
+    return ESP_OK;
+}

components/bootloader_support/src/esp_image_format.c

@@ -38,6 +38,10 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rtc.h"
+#include "esp32p4/rom/secure_boot.h"
+#include "esp32p4/rom/cache.h"
 #endif
 
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
@@ -232,6 +236,10 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
                 }
             }
         }
+#if CONFIG_IDF_TARGET_ESP32P4
+        //TODO: IDF-7516
+        Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
+#endif
     }
 #endif // BOOTLOADER_BUILD
 
@@ -459,6 +467,12 @@ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_
     }
 #endif
 
+#if SOC_MEM_TCM_SUPPORTED
+    else if (esp_ptr_in_tcm(load_addr_p) && esp_ptr_in_tcm(load_inclusive_end_p)) {
+        return true;
+    }
+#endif
+
     else { /* Not a DRAM or an IRAM or RTC Fast IRAM, RTC Fast DRAM or RTC Slow address */
         reason = "bad load address range";
         goto invalid;
@@ -661,6 +675,12 @@ static esp_err_t process_segment_data(intptr_t load_addr, uint32_t data_addr, ui
                                    MIN(SHA_CHUNK, data_len - i));
         }
     }
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7516
+    if (do_load && esp_ptr_in_diram_iram((uint32_t *)load_addr)) {
+        Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
+    }
+#endif
 
     bootloader_munmap(data);
 

components/bootloader_support/src/flash_encrypt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -137,11 +137,16 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
             }
 #else
             if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT)
+#if CONFIG_IDF_TARGET_ESP32P4
+                //TODO: IDF-7545
+                && esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS)
+#else
 #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
                 && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE)
 #endif
 #if SOC_EFUSE_DIS_DOWNLOAD_DCACHE
                 && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE)
+#endif
 #endif
                 ) {
                 mode = ESP_FLASH_ENC_MODE_RELEASE;
@@ -187,12 +192,17 @@ void esp_flash_encryption_set_release_mode(void)
     esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT);
 #else
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7545
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+#else
 #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
 #endif
 #if SOC_EFUSE_DIS_DOWNLOAD_DCACHE
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
 #endif
+#endif
 #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
     // For AES128_DERIVED, FE key is 16 bytes and XTS_KEY_LENGTH_256 is 0.
     // It is important to protect XTS_KEY_LENGTH_256 from further changing it to 1. Set write protection for this bit.
@@ -335,6 +345,14 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
     }
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7545
+    secure = esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
+    result &= secure;
+    if (!secure) {
+        ESP_LOGW(TAG, "Not disabled UART bootloader download mspi (set DIS_DOWNLOAD_MSPI->1)");
+    }
+#else
 #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
     result &= secure;
@@ -342,6 +360,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
         ESP_LOGW(TAG, "Not disabled UART bootloader cache (set DIS_DOWNLOAD_ICACHE->1)");
     }
 #endif
+#endif
 
 #if SOC_EFUSE_DIS_PAD_JTAG
     secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_PAD_JTAG);

components/driver/deprecated/adc_legacy.c

@@ -23,6 +23,7 @@
 #include "esp_private/sar_periph_ctrl.h"
 #include "adc1_private.h"
 #include "hal/adc_types.h"
+#include "hal/adc_hal.h"
 #include "hal/adc_ll.h"
 #include "hal/adc_hal_common.h"
 #include "esp_private/periph_ctrl.h"

components/driver/gpio/gpio.c

@@ -582,7 +582,11 @@ esp_err_t gpio_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags,
 {
     GPIO_CHECK(fn, "GPIO ISR null", ESP_ERR_INVALID_ARG);
     gpio_isr_alloc_t p;
+#if !CONFIG_IDF_TARGET_ESP32P4  //TODO: IDF-7995
     p.source = ETS_GPIO_INTR_SOURCE;
+#else
+    p.source = ETS_GPIO_INTR0_SOURCE;
+#endif
     p.intr_alloc_flags = intr_alloc_flags;
 #if SOC_ANA_CMPR_SUPPORTED
     p.intr_alloc_flags |= ESP_INTR_FLAG_SHARED;

components/efuse/efuse_table_gen.py

@@ -498,7 +498,7 @@ def main():
 
     parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
     parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
-                        'esp32c2', 'esp32c6', 'esp32h2'], default='esp32')
+                        'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4'], default='esp32')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
     parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')

components/efuse/esp32p4/esp_efuse_fields.c

@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_efuse.h"
+#include "esp_efuse_utility.h"
+#include "esp_efuse_table.h"
+#include "stdlib.h"
+#include "esp_types.h"
+#include "esp32p4/rom/efuse.h"
+#include "assert.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "soc/efuse_periph.h"
+#include "bootloader_random.h"
+#include "sys/param.h"
+
+static __attribute__((unused)) const char *TAG = "efuse";
+
+// Contains functions that provide access to efuse fields which are often used in IDF.
+
+// Returns chip package from efuse
+uint32_t esp_efuse_get_pkg_ver(void)
+{
+    uint32_t pkg_ver = 0;
+    return pkg_ver;
+}
+
+
+esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
+{
+    int cur_log_scheme = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
+    if (!cur_log_scheme) { // not burned yet
+        return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
+    } else {
+        return ESP_ERR_INVALID_STATE;
+    }
+}
+
+esp_err_t esp_efuse_disable_rom_download_mode(void)
+{
+    return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
+}
+
+esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
+{
+    if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
+}

components/efuse/esp32p4/esp_efuse_rtc_calib.c

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_bit_defs.h>
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+
+int esp_efuse_rtc_calib_get_ver(void)
+{
+    //TODO: IDF-7467, eFuses are not defined yet
+    return 0;
+}
+
+uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
+{
+    //TODO: IDF-7467, check below, eFuses are not defined yet
+    (void) version;
+    (void) adc_unit;
+    (void) atten;
+    return 0;
+}
+
+esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
+{
+    //TODO: IDF-7467, check below, eFuses are not defined yet
+    (void) version;
+    (void) atten;
+    (void) out_digi;
+    (void) out_vol_mv;
+    return ESP_ERR_NOT_SUPPORTED;
+}
+
+esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
+{
+    //TODO: IDF-7482
+    *tsens_cal = 0;
+    return ESP_ERR_NOT_SUPPORTED;
+}

components/efuse/esp32p4/esp_efuse_table.c

@@ -0,0 +1,986 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include "esp_efuse.h"
+#include <assert.h>
+#include "esp_efuse_table.h"
+
+// md5_digest_table 78dff63df528392f0f37f4880b83c6db
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+static const esp_efuse_desc_t WR_DIS[] = {
+    {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
+};
+
+static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
+    {EFUSE_BLK0, 0, 1}, 	 // [] wr_dis of RD_DIS,
+};
+
+static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 4, 1}, 	 // [] wr_dis of SPI_BOOT_CRYPT_CNT,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 5, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 6, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 7, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 15, 1}, 	 // [] wr_dis of SECURE_BOOT_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLK1[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLOCK1,
+};
+
+static const esp_efuse_desc_t WR_DIS_MAC[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
+};
+
+static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of MAC_EXT,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 23, 1}, 	 // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 24, 1}, 	 // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 25, 1}, 	 // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 26, 1}, 	 // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 27, 1}, 	 // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 28, 1}, 	 // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
+};
+
+static const esp_efuse_desc_t RD_DIS[] = {
+    {EFUSE_BLK0, 32, 7}, 	 // [] Disable reading from BlOCK4-10,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 32, 1}, 	 // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 33, 1}, 	 // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 34, 1}, 	 // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 35, 1}, 	 // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 36, 1}, 	 // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 37, 1}, 	 // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
+};
+
+static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
+};
+
+static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 39, 1}, 	 // [] Enable usb device exchange pins of D+ and D-,
+};
+
+static const esp_efuse_desc_t USB_OTG11_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 40, 1}, 	 // [] Enable usb otg11 exchange pins of D+ and D-,
+};
+
+static const esp_efuse_desc_t DIS_USB_JTAG[] = {
+    {EFUSE_BLK0, 41, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t POWERGLITCH_EN[] = {
+    {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 45, 1}, 	 // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download,
+};
+
+static const esp_efuse_desc_t DIS_TWAI[] = {
+    {EFUSE_BLK0, 46, 1}, 	 // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
+    {EFUSE_BLK0, 47, 1}, 	 // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
+    {EFUSE_BLK0, 48, 3}, 	 // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
+};
+
+static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
+    {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t USB_PHY_SEL[] = {
+    {EFUSE_BLK0, 57, 1}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t KM_HUK_GEN_STATE_LOW[] = {
+    {EFUSE_BLK0, 58, 6}, 	 // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
+};
+
+static const esp_efuse_desc_t KM_HUK_GEN_STATE_HIGH[] = {
+    {EFUSE_BLK0, 64, 3}, 	 // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
+};
+
+static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = {
+    {EFUSE_BLK0, 67, 2}, 	 // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles,
+};
+
+static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = {
+    {EFUSE_BLK0, 69, 4}, 	 // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
+};
+
+static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = {
+    {EFUSE_BLK0, 73, 4}, 	 // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
+};
+
+static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = {
+    {EFUSE_BLK0, 77, 1}, 	 // [] Set this bit to disable software written init key; and force use efuse_init_key,
+};
+
+static const esp_efuse_desc_t XTS_KEY_LENGTH_256[] = {
+    {EFUSE_BLK0, 78, 1}, 	 // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key,
+};
+
+static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
+    {EFUSE_BLK0, 80, 2}, 	 // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
+};
+
+static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 82, 3}, 	 // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 85, 1}, 	 // [] Revoke 1st secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 86, 1}, 	 // [] Revoke 2nd secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 87, 1}, 	 // [] Revoke 3rd secure boot key,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 88, 4}, 	 // [KEY0_PURPOSE] Represents the purpose of Key0,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 92, 4}, 	 // [KEY1_PURPOSE] Represents the purpose of Key1,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 96, 4}, 	 // [KEY2_PURPOSE] Represents the purpose of Key2,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 100, 4}, 	 // [KEY3_PURPOSE] Represents the purpose of Key3,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 104, 4}, 	 // [KEY4_PURPOSE] Represents the purpose of Key4,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 108, 4}, 	 // [KEY5_PURPOSE] Represents the purpose of Key5,
+};
+
+static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
+    {EFUSE_BLK0, 112, 2}, 	 // [] Represents the spa secure level by configuring the clock random divide mode,
+};
+
+static const esp_efuse_desc_t ECDSA_ENABLE_SOFT_K[] = {
+    {EFUSE_BLK0, 114, 1}, 	 // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used,
+};
+
+static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
+    {EFUSE_BLK0, 115, 1}, 	 // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 116, 1}, 	 // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    {EFUSE_BLK0, 117, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t FLASH_TYPE[] = {
+    {EFUSE_BLK0, 119, 1}, 	 // [] The type of interfaced flash. 0: four data lines; 1: eight data lines,
+};
+
+static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
+    {EFUSE_BLK0, 120, 2}, 	 // [] Set flash page size,
+};
+
+static const esp_efuse_desc_t FLASH_ECC_EN[] = {
+    {EFUSE_BLK0, 122, 1}, 	 // [] Set this bit to enable ecc for flash boot,
+};
+
+static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 123, 1}, 	 // [] Set this bit to disable download via USB-OTG,
+};
+
+static const esp_efuse_desc_t FLASH_TPUW[] = {
+    {EFUSE_BLK0, 124, 4}, 	 // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 128, 1}, 	 // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
+    {EFUSE_BLK0, 129, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    {EFUSE_BLK0, 130, 1}, 	 // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t LOCK_KM_KEY[] = {
+    {EFUSE_BLK0, 131, 1}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 132, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
+    {EFUSE_BLK0, 133, 1}, 	 // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
+};
+
+static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
+    {EFUSE_BLK0, 134, 2}, 	 // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing,
+};
+
+static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
+    {EFUSE_BLK0, 136, 1}, 	 // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
+};
+
+static const esp_efuse_desc_t SECURE_VERSION[] = {
+    {EFUSE_BLK0, 137, 16}, 	 // [] Represents the version used by ESP-IDF anti-rollback feature,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    {EFUSE_BLK0, 153, 1}, 	 // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t HYS_EN_PAD[] = {
+    {EFUSE_BLK0, 154, 1}, 	 // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled,
+};
+
+static const esp_efuse_desc_t DCDC_VSET[] = {
+    {EFUSE_BLK0, 155, 5}, 	 // [] Set the dcdc voltage default,
+};
+
+static const esp_efuse_desc_t PXA0_TIEH_SEL_0[] = {
+    {EFUSE_BLK0, 160, 2}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t PXA0_TIEH_SEL_1[] = {
+    {EFUSE_BLK0, 162, 2}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t PXA0_TIEH_SEL_2[] = {
+    {EFUSE_BLK0, 164, 2}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t PXA0_TIEH_SEL_3[] = {
+    {EFUSE_BLK0, 166, 2}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = {
+    {EFUSE_BLK0, 168, 4}, 	 // [] TBD,
+};
+
+static const esp_efuse_desc_t HP_PWR_SRC_SEL[] = {
+    {EFUSE_BLK0, 178, 1}, 	 // [] HP system power source select. 0:LDO. 1: DCDC,
+};
+
+static const esp_efuse_desc_t DCDC_VSET_EN[] = {
+    {EFUSE_BLK0, 179, 1}, 	 // [] Select dcdc vset use efuse_dcdc_vset,
+};
+
+static const esp_efuse_desc_t DIS_WDT[] = {
+    {EFUSE_BLK0, 180, 1}, 	 // [] Set this bit to disable watch dog,
+};
+
+static const esp_efuse_desc_t DIS_SWD[] = {
+    {EFUSE_BLK0, 181, 1}, 	 // [] Set this bit to disable super-watchdog,
+};
+
+static const esp_efuse_desc_t MAC[] = {
+    {EFUSE_BLK1, 40, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 32, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 24, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 16, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 8, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 0, 8}, 	 // [MAC_FACTORY] MAC address,
+};
+
+static const esp_efuse_desc_t MAC_EXT[] = {
+    {EFUSE_BLK1, 48, 8}, 	 // [] Stores the extended bits of MAC address [0],
+    {EFUSE_BLK1, 56, 8}, 	 // [] Stores the extended bits of MAC address [1],
+};
+
+static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = {
+    {EFUSE_BLK2, 0, 256}, 	 // [SYS_DATA_PART1] System data part 1,
+};
+
+static const esp_efuse_desc_t USER_DATA[] = {
+    {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
+};
+
+static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
+    {EFUSE_BLK3, 200, 48}, 	 // [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO,
+};
+
+static const esp_efuse_desc_t KEY0[] = {
+    {EFUSE_BLK4, 0, 256}, 	 // [BLOCK_KEY0] Key0 or user data,
+};
+
+static const esp_efuse_desc_t KEY1[] = {
+    {EFUSE_BLK5, 0, 256}, 	 // [BLOCK_KEY1] Key1 or user data,
+};
+
+static const esp_efuse_desc_t KEY2[] = {
+    {EFUSE_BLK6, 0, 256}, 	 // [BLOCK_KEY2] Key2 or user data,
+};
+
+static const esp_efuse_desc_t KEY3[] = {
+    {EFUSE_BLK7, 0, 256}, 	 // [BLOCK_KEY3] Key3 or user data,
+};
+
+static const esp_efuse_desc_t KEY4[] = {
+    {EFUSE_BLK8, 0, 256}, 	 // [BLOCK_KEY4] Key4 or user data,
+};
+
+static const esp_efuse_desc_t KEY5[] = {
+    {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
+};
+
+static const esp_efuse_desc_t SYS_DATA_PART2[] = {
+    {EFUSE_BLK10, 0, 256}, 	 // [BLOCK_SYS_DATA2] System data part 2 (reserved),
+};
+
+
+
+
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
+    &WR_DIS[0],    		// [] Disable programming of individual eFuses
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
+    &WR_DIS_RD_DIS[0],    		// [] wr_dis of RD_DIS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// [] wr_dis of SPI_BOOT_CRYPT_CNT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
+    &WR_DIS_KEY_PURPOSE_0[0],    		// [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
+    &WR_DIS_KEY_PURPOSE_1[0],    		// [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
+    &WR_DIS_KEY_PURPOSE_2[0],    		// [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
+    &WR_DIS_KEY_PURPOSE_3[0],    		// [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
+    &WR_DIS_KEY_PURPOSE_4[0],    		// [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
+    &WR_DIS_KEY_PURPOSE_5[0],    		// [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
+    &WR_DIS_SECURE_BOOT_EN[0],    		// [] wr_dis of SECURE_BOOT_EN
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
+    &WR_DIS_BLK1[0],    		// [] wr_dis of BLOCK1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
+    &WR_DIS_MAC[0],    		// [WR_DIS.MAC_FACTORY] wr_dis of MAC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
+    &WR_DIS_MAC_EXT[0],    		// [] wr_dis of MAC_EXT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = {
+    &WR_DIS_BLOCK_SYS_DATA1[0],    		// [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
+    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
+    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
+    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
+    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
+    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
+    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
+    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
+    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
+    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
+    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
+    &RD_DIS_BLOCK_KEY1[0],    		// [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
+    &RD_DIS_BLOCK_KEY2[0],    		// [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
+    &RD_DIS_BLOCK_KEY3[0],    		// [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
+    &RD_DIS_BLOCK_KEY4[0],    		// [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
+    &RD_DIS_BLOCK_KEY5[0],    		// [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
+    &RD_DIS_BLOCK_SYS_DATA2[0],    		// [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = {
+    &USB_DEVICE_EXCHG_PINS[0],    		// [] Enable usb device exchange pins of D+ and D-
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[] = {
+    &USB_OTG11_EXCHG_PINS[0],    		// [] Enable usb otg11 exchange pins of D+ and D-
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
+    &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
+    &POWERGLITCH_EN[0],    		// [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
+    &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
+    &DIS_TWAI[0],    		// [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
+    &JTAG_SEL_ENABLE[0],    		// [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
+    &SOFT_DIS_JTAG[0],    		// [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
+    &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = {
+    &USB_PHY_SEL[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[] = {
+    &KM_HUK_GEN_STATE_LOW[0],    		// [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[] = {
+    &KM_HUK_GEN_STATE_HIGH[0],    		// [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = {
+    &KM_RND_SWITCH_CYCLE[0],    		// [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = {
+    &KM_DEPLOY_ONLY_ONCE[0],    		// [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = {
+    &FORCE_USE_KEY_MANAGER_KEY[0],    		// [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = {
+    &FORCE_DISABLE_SW_INIT_KEY[0],    		// [] Set this bit to disable software written init key; and force use efuse_init_key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[] = {
+    &XTS_KEY_LENGTH_256[0],    		// [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
+    &WDT_DELAY_SEL[0],    		// [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
+    &SPI_BOOT_CRYPT_CNT[0],    		// [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
+    &SECURE_BOOT_KEY_REVOKE0[0],    		// [] Revoke 1st secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
+    &SECURE_BOOT_KEY_REVOKE1[0],    		// [] Revoke 2nd secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
+    &SECURE_BOOT_KEY_REVOKE2[0],    		// [] Revoke 3rd secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
+    &KEY_PURPOSE_0[0],    		// [KEY0_PURPOSE] Represents the purpose of Key0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
+    &KEY_PURPOSE_1[0],    		// [KEY1_PURPOSE] Represents the purpose of Key1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
+    &KEY_PURPOSE_2[0],    		// [KEY2_PURPOSE] Represents the purpose of Key2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
+    &KEY_PURPOSE_3[0],    		// [KEY3_PURPOSE] Represents the purpose of Key3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
+    &KEY_PURPOSE_4[0],    		// [KEY4_PURPOSE] Represents the purpose of Key4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
+    &KEY_PURPOSE_5[0],    		// [KEY5_PURPOSE] Represents the purpose of Key5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
+    &SEC_DPA_LEVEL[0],    		// [] Represents the spa secure level by configuring the clock random divide mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[] = {
+    &ECDSA_ENABLE_SOFT_K[0],    		// [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
+    &CRYPT_DPA_ENABLE[0],    		// [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
+    &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
+    &FLASH_TYPE[0],    		// [] The type of interfaced flash. 0: four data lines; 1: eight data lines
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
+    &FLASH_PAGE_SIZE[0],    		// [] Set flash page size
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
+    &FLASH_ECC_EN[0],    		// [] Set this bit to enable ecc for flash boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = {
+    &DIS_USB_OTG_DOWNLOAD_MODE[0],    		// [] Set this bit to disable download via USB-OTG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
+    &FLASH_TPUW[0],    		// [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
+    &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
+    &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
+    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = {
+    &LOCK_KM_KEY[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
+    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
+    &UART_PRINT_CONTROL[0],    		// [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
+    &FORCE_SEND_RESUME[0],    		// [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
+    &SECURE_VERSION[0],    		// [] Represents the version used by ESP-IDF anti-rollback feature
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
+    &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = {
+    &HYS_EN_PAD[0],    		// [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[] = {
+    &DCDC_VSET[0],    		// [] Set the dcdc voltage default
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[] = {
+    &PXA0_TIEH_SEL_0[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[] = {
+    &PXA0_TIEH_SEL_1[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[] = {
+    &PXA0_TIEH_SEL_2[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[] = {
+    &PXA0_TIEH_SEL_3[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = {
+    &KM_DISABLE_DEPLOY_MODE[0],    		// [] TBD
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[] = {
+    &HP_PWR_SRC_SEL[0],    		// [] HP system power source select. 0:LDO. 1: DCDC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[] = {
+    &DCDC_VSET_EN[0],    		// [] Select dcdc vset use efuse_dcdc_vset
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[] = {
+    &DIS_WDT[0],    		// [] Set this bit to disable watch dog
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[] = {
+    &DIS_SWD[0],    		// [] Set this bit to disable super-watchdog
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
+    &MAC[0],    		// [MAC_FACTORY] MAC address
+    &MAC[1],    		// [MAC_FACTORY] MAC address
+    &MAC[2],    		// [MAC_FACTORY] MAC address
+    &MAC[3],    		// [MAC_FACTORY] MAC address
+    &MAC[4],    		// [MAC_FACTORY] MAC address
+    &MAC[5],    		// [MAC_FACTORY] MAC address
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
+    &MAC_EXT[0],    		// [] Stores the extended bits of MAC address [0]
+    &MAC_EXT[1],    		// [] Stores the extended bits of MAC address [1]
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = {
+    &BLOCK_SYS_DATA1[0],    		// [SYS_DATA_PART1] System data part 1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
+    &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
+    &USER_DATA_MAC_CUSTOM[0],    		// [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
+    &KEY0[0],    		// [BLOCK_KEY0] Key0 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
+    &KEY1[0],    		// [BLOCK_KEY1] Key1 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
+    &KEY2[0],    		// [BLOCK_KEY2] Key2 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
+    &KEY3[0],    		// [BLOCK_KEY3] Key3 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
+    &KEY4[0],    		// [BLOCK_KEY4] Key4 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
+    &KEY5[0],    		// [BLOCK_KEY5] Key5 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
+    &SYS_DATA_PART2[0],    		// [BLOCK_SYS_DATA2] System data part 2 (reserved)
+    NULL
+};

components/efuse/esp32p4/esp_efuse_table.csv

@@ -0,0 +1,125 @@
+
+# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...)     |            |            |        #
+##########################################################################
+# !!!!!!!!!!! #
+# After editing this file, run the command manually "idf.py efuse-common-table"
+# this will generate new source files, next rebuild all the sources.
+# !!!!!!!!!!! #
+
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 552d7a824581925566213ca4f4d488dc
+
+WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
+WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
+WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
+WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
+WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
+WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
+WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
+WR_DIS.BLOCK_SYS_DATA1,                          EFUSE_BLK0,  21,   1, [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1
+WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
+RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+USB_DEVICE_EXCHG_PINS,                           EFUSE_BLK0,  39,   1, [] Enable usb device exchange pins of D+ and D-
+USB_OTG11_EXCHG_PINS,                            EFUSE_BLK0,  40,   1, [] Enable usb otg11 exchange pins of D+ and D-
+DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
+POWERGLITCH_EN,                                  EFUSE_BLK0,  42,   1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
+DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
+SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
+USB_PHY_SEL,                                     EFUSE_BLK0,  57,   1, [] TBD
+KM_HUK_GEN_STATE_LOW,                            EFUSE_BLK0,  58,   6, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+KM_HUK_GEN_STATE_HIGH,                           EFUSE_BLK0,  64,   3, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+KM_RND_SWITCH_CYCLE,                             EFUSE_BLK0,  67,   2, [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+KM_DEPLOY_ONLY_ONCE,                             EFUSE_BLK0,  69,   4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+FORCE_USE_KEY_MANAGER_KEY,                       EFUSE_BLK0,  73,   4, [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+FORCE_DISABLE_SW_INIT_KEY,                       EFUSE_BLK0,  77,   1, [] Set this bit to disable software written init key; and force use efuse_init_key
+XTS_KEY_LENGTH_256,                              EFUSE_BLK0,  78,   1, [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
+WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
+SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
+SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
+SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
+KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Represents the purpose of Key0
+KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Represents the purpose of Key1
+KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Represents the purpose of Key2
+KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Represents the purpose of Key3
+KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Represents the purpose of Key4
+KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Represents the purpose of Key5
+SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [] Represents the spa secure level by configuring the clock random divide mode
+ECDSA_ENABLE_SOFT_K,                             EFUSE_BLK0, 114,   1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
+CRYPT_DPA_ENABLE,                                EFUSE_BLK0, 115,   1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
+SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
+FLASH_TYPE,                                      EFUSE_BLK0, 119,   1, [] The type of interfaced flash. 0: four data lines; 1: eight data lines
+FLASH_PAGE_SIZE,                                 EFUSE_BLK0, 120,   2, [] Set flash page size
+FLASH_ECC_EN,                                    EFUSE_BLK0, 122,   1, [] Set this bit to enable ecc for flash boot
+DIS_USB_OTG_DOWNLOAD_MODE,                       EFUSE_BLK0, 123,   1, [] Set this bit to disable download via USB-OTG
+FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
+LOCK_KM_KEY,                                     EFUSE_BLK0, 131,   1, [] TBD
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
+UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
+FORCE_SEND_RESUME,                               EFUSE_BLK0, 136,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
+SECURE_VERSION,                                  EFUSE_BLK0, 137,  16, [] Represents the version used by ESP-IDF anti-rollback feature
+SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 153,   1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
+HYS_EN_PAD,                                      EFUSE_BLK0, 154,   1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
+DCDC_VSET,                                       EFUSE_BLK0, 155,   5, [] Set the dcdc voltage default
+PXA0_TIEH_SEL_0,                                 EFUSE_BLK0, 160,   2, [] TBD
+PXA0_TIEH_SEL_1,                                 EFUSE_BLK0, 162,   2, [] TBD
+PXA0_TIEH_SEL_2,                                 EFUSE_BLK0, 164,   2, [] TBD
+PXA0_TIEH_SEL_3,                                 EFUSE_BLK0, 166,   2, [] TBD
+KM_DISABLE_DEPLOY_MODE,                          EFUSE_BLK0, 168,   4, [] TBD
+HP_PWR_SRC_SEL,                                  EFUSE_BLK0, 178,   1, [] HP system power source select. 0:LDO. 1: DCDC
+DCDC_VSET_EN,                                    EFUSE_BLK0, 179,   1, [] Select dcdc vset use efuse_dcdc_vset
+DIS_WDT,                                         EFUSE_BLK0, 180,   1, [] Set this bit to disable watch dog
+DIS_SWD,                                         EFUSE_BLK0, 181,   1, [] Set this bit to disable super-watchdog
+MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  16,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   8,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   0,   8, [MAC_FACTORY] MAC address
+MAC_EXT,                                         EFUSE_BLK1,  48,   8, [] Stores the extended bits of MAC address [0]
+,                                                EFUSE_BLK1,  56,   8, [] Stores the extended bits of MAC address [1]
+BLOCK_SYS_DATA1,                                 EFUSE_BLK2,   0, 256, [SYS_DATA_PART1] System data part 1
+USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
+USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO, not defined yet)
+KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
+KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
+KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
+KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
+KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
+KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
+SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

components/efuse/esp32p4/esp_efuse_utility.c

@@ -0,0 +1,201 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/param.h>
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "assert.h"
+#include "esp_efuse_utility.h"
+#include "soc/efuse_periph.h"
+#include "hal/efuse_hal.h"
+
+static const char *TAG = "efuse";
+
+#ifdef CONFIG_EFUSE_VIRTUAL
+extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
+#endif // CONFIG_EFUSE_VIRTUAL
+
+/*Range addresses to read blocks*/
+const esp_efuse_range_addr_t range_read_addr_blocks[] = {
+    {EFUSE_RD_WR_DIS_REG,       EFUSE_RD_REPEAT_DATA4_REG},      // range address of EFUSE_BLK0  REPEAT
+    {EFUSE_RD_MAC_SYS_0_REG,    EFUSE_RD_MAC_SYS_5_REG},      // range address of EFUSE_BLK1  MAC_SPI_8M
+    {EFUSE_RD_SYS_PART1_DATA0_REG,    EFUSE_RD_SYS_PART1_DATA7_REG},         // range address of EFUSE_BLK2  SYS_DATA
+    {EFUSE_RD_USR_DATA0_REG,    EFUSE_RD_USR_DATA7_REG},         // range address of EFUSE_BLK3  USR_DATA
+    {EFUSE_RD_KEY0_DATA0_REG,   EFUSE_RD_KEY0_DATA7_REG},        // range address of EFUSE_BLK4  KEY0
+    {EFUSE_RD_KEY1_DATA0_REG,   EFUSE_RD_KEY1_DATA7_REG},        // range address of EFUSE_BLK5  KEY1
+    {EFUSE_RD_KEY2_DATA0_REG,   EFUSE_RD_KEY2_DATA7_REG},        // range address of EFUSE_BLK6  KEY2
+    {EFUSE_RD_KEY3_DATA0_REG,   EFUSE_RD_KEY3_DATA7_REG},        // range address of EFUSE_BLK7  KEY3
+    {EFUSE_RD_KEY4_DATA0_REG,   EFUSE_RD_KEY4_DATA7_REG},        // range address of EFUSE_BLK8  KEY4
+    {EFUSE_RD_KEY5_DATA0_REG,   EFUSE_RD_KEY5_DATA7_REG},        // range address of EFUSE_BLK9  KEY5
+    {EFUSE_RD_SYS_PART2_DATA0_REG,   EFUSE_RD_SYS_PART2_DATA7_REG}         // range address of EFUSE_BLK10 KEY6
+};
+
+static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
+
+/*Range addresses to write blocks (it is not real regs, it is buffer) */
+const esp_efuse_range_addr_t range_write_addr_blocks[] = {
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
+};
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+// Update Efuse timing configuration
+static esp_err_t esp_efuse_set_timing(void)
+{
+    // efuse clock is fixed.
+    // An argument (0) is for compatibility and will be ignored.
+    efuse_hal_set_timing(0);
+    return ESP_OK;
+}
+#endif // ifndef CONFIG_EFUSE_VIRTUAL
+
+// Efuse read operation: copies data from physical efuses to efuse read registers.
+void esp_efuse_utility_clear_program_registers(void)
+{
+    efuse_hal_read();
+    efuse_hal_clear_program_registers();
+}
+
+esp_err_t esp_efuse_utility_check_errors(void)
+{
+    return ESP_OK;
+}
+
+// Burn values written to the efuse write registers
+esp_err_t esp_efuse_utility_burn_chip(void)
+{
+    esp_err_t error = ESP_OK;
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
+    for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+        int subblock = 0;
+        for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+            virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
+        }
+    }
+#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_utility_write_efuses_to_flash();
+#endif
+#else // CONFIG_EFUSE_VIRTUAL
+    if (esp_efuse_set_timing() != ESP_OK) {
+        ESP_LOGE(TAG, "Efuse fields are not burnt");
+    } else {
+        // Permanently update values written to the efuse write registers
+        // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
+        for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+            bool need_burn_block = false;
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block) != 0) {
+                    need_burn_block = true;
+                    break;
+                }
+            }
+            if (!need_burn_block) {
+                continue;
+            }
+            if (error) {
+                // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
+                // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
+                ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
+                continue;
+            }
+            efuse_hal_clear_program_registers();
+            if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+                uint8_t block_rs[12];
+                efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
+                hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
+            }
+            unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
+            unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
+            memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
+
+            uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
+            hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
+            int repeat_burn_op = 1;
+            bool correct_written_data;
+            bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
+            if (coding_error_before) {
+                ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
+            }
+            bool coding_error_occurred;
+
+            do {
+                ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
+                efuse_hal_program(num_block); // BURN a block
+
+                bool coding_error_after;
+                for (unsigned i = 0; i < 5; i++) {
+                    efuse_hal_read();
+                    coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
+                    if (coding_error_after == true) {
+                        break;
+                    }
+                }
+                coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
+                if (coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
+                }
+
+                correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
+                if (!correct_written_data || coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
+                    hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
+                }
+
+            } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
+
+            if (coding_error_occurred) {
+                ESP_LOGW(TAG, "Coding error was not fixed");
+                if (num_block == 0) {
+                    ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
+                    error = ESP_FAIL;
+                }
+            }
+            if (!correct_written_data) {
+                ESP_LOGE(TAG, "Written data are incorrect");
+                error = ESP_FAIL;
+            }
+        }
+    }
+#endif // CONFIG_EFUSE_VIRTUAL
+    esp_efuse_utility_reset();
+    return error;
+}
+
+// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
+// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
+// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
+// They will be filled during the burn operation.
+esp_err_t esp_efuse_utility_apply_new_coding_scheme()
+{
+    // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
+    for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
+        if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block)) {
+                    int num_reg = 0;
+                    for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
+                        if (esp_efuse_utility_read_reg(num_block, num_reg)) {
+                            ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
+                            return ESP_ERR_CODING;
+                        }
+                    }
+                    break;
+                }
+            }
+        }
+    }
+    return ESP_OK;
+}

components/efuse/esp32p4/include/esp_efuse_chip.h

@@ -0,0 +1,81 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of eFuse blocks ESP32P4
+ */
+typedef enum {
+    EFUSE_BLK0                 = 0,   /**< Number of eFuse BLOCK0. REPEAT_DATA */
+
+    EFUSE_BLK1                 = 1,   /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
+
+    EFUSE_BLK2                 = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+    EFUSE_BLK_SYS_DATA_PART1   = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+
+    EFUSE_BLK3                 = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+    EFUSE_BLK_USER_DATA        = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+
+    EFUSE_BLK4                 = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+    EFUSE_BLK_KEY0             = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+
+    EFUSE_BLK5                 = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+    EFUSE_BLK_KEY1             = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+
+    EFUSE_BLK6                 = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+    EFUSE_BLK_KEY2             = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+
+    EFUSE_BLK7                 = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+    EFUSE_BLK_KEY3             = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+
+    EFUSE_BLK8                 = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+    EFUSE_BLK_KEY4             = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+
+    EFUSE_BLK9                 = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY5             = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY_MAX          = 10,
+
+    EFUSE_BLK10                = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+    EFUSE_BLK_SYS_DATA_PART2   = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+
+    EFUSE_BLK_MAX
+} esp_efuse_block_t;
+
+/**
+ * @brief Type of coding scheme
+ */
+typedef enum {
+    EFUSE_CODING_SCHEME_NONE    = 0,    /**< None */
+    EFUSE_CODING_SCHEME_RS      = 3,    /**< Reed-Solomon coding */
+} esp_efuse_coding_scheme_t;
+
+/**
+ * @brief Type of key purpose
+ */
+typedef enum {
+    ESP_EFUSE_KEY_PURPOSE_USER = 0,                         /**< User purposes (software-only use) */
+    ESP_EFUSE_KEY_PURPOSE_RESERVED = 1,                     /**< Reserved */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2,            /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3,            /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,              /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,                /**< HMAC Downstream mode */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,               /**< JTAG soft enable key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,  /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8,                      /**< HMAC Upstream mode */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,          /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,         /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,         /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_MAX,                              /**< MAX PURPOSE */
+} esp_efuse_purpose_t;
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32p4/include/esp_efuse_rtc_calib.h

@@ -0,0 +1,59 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_types.h>
+#include <esp_err.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//This is the ADC calibration value version burnt in efuse
+#define ESP_EFUSE_ADC_CALIB_VER     1
+
+/**
+ * @brief Get the RTC calibration efuse version
+ *
+ * @return Version of the stored efuse
+ */
+int esp_efuse_rtc_calib_get_ver(void);
+
+/**
+ * @brief Get the init code in the efuse, for the corresponding attenuation.
+ *
+ * @param version   Version of the stored efuse
+ * @param adc_unit  ADC unit. Not used, for compatibility. On esp32P4, for calibration v1, both ADC units use the same init code (calibrated by ADC1)
+ * @param atten     Attenuation of the init code
+ * @return The init code stored in efuse
+ */
+uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten);
+
+/**
+ * @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
+ *
+ * @param version Version of the stored efuse
+ * @param atten         Attenuation to use
+ * @param out_digi      Output buffer of the digits
+ * @param out_vol_mv    Output of the voltage, in mV
+ * @return
+ *      - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
+ *      - ESP_OK: if success
+ */
+esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
+
+/**
+ * @brief Get the temperature sensor calibration number delta_T stored in the efuse.
+ *
+ * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
+ *
+ * @return ESP_OK if get the calibration value successfully.
+ *         ESP_ERR_INVALID_ARG if can't get the calibration value.
+ */
+esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32p4/include/esp_efuse_table.h

@@ -0,0 +1,170 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_efuse.h"
+
+// md5_digest_table 78dff63df528392f0f37f4880b83c6db
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART1 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[];
+#define ESP_EFUSE_SYS_DATA_PART1 ESP_EFUSE_BLOCK_SYS_DATA1
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
+#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32p4/private_include/esp_efuse_utility.h

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COUNT_EFUSE_REG_PER_BLOCK 8      /* The number of registers per block. */
+
+#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
+
+#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32p4/sources.cmake

@@ -0,0 +1,4 @@
+set(EFUSE_SOC_SRCS  "esp_efuse_table.c"
+                    "esp_efuse_fields.c"
+                    "esp_efuse_rtc_calib.c"
+                    "esp_efuse_utility.c")

components/esp_gdbstub/esp32p4/gdbstub_esp32p4.c

@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include "soc/uart_periph.h"
+#include "soc/gpio_periph.h"
+#include "soc/soc.h"
+#include "soc/usb_serial_jtag_struct.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "esp_gdbstub_common.h"
+#include "sdkconfig.h"
+
+#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
+
+#define GDBSTUB_MEM_REGION_COUNT 10
+
+#define UART_REG_FIELD_LEN 0x84
+
+typedef struct {
+    intptr_t lower;
+    intptr_t upper;
+} mem_bound_t;
+
+static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] =
+{
+    {SOC_DROM_LOW, SOC_DROM_HIGH},
+    {SOC_IROM_LOW, SOC_IROM_HIGH},
+    {SOC_IRAM_LOW, SOC_IRAM_HIGH},
+    {SOC_DRAM_LOW, SOC_DRAM_HIGH},
+    {SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH},
+    {SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH},
+    {SOC_TCM_LOW, SOC_TCM_HIGH},
+    {SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH},
+    // RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them
+    // We shouldn't read the uart registers since it will disturb the debugging via UART,
+    // so skip UART part of the peripheral registers.
+    {DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH},
+    {SOC_DEBUG_LOW, SOC_DEBUG_HIGH},
+};
+
+static inline bool check_inside_valid_region(intptr_t addr)
+{
+    for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) {
+        if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+void esp_gdbstub_target_init()
+{
+}
+
+#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
+
+int esp_gdbstub_getchar()
+{
+    uint8_t c;
+    //retry the read until we succeed
+    while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ;
+    return c;
+}
+
+void esp_gdbstub_putchar(int c)
+{
+    uint8_t cc=c;
+    //retry the write until we succeed
+    while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ;
+}
+
+void esp_gdbstub_flush()
+{
+    usb_serial_jtag_ll_txfifo_flush();
+}
+
+
+#else
+
+//assume UART gdbstub channel
+
+int esp_gdbstub_getchar()
+{
+    while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) {
+        ;
+    }
+    return REG_READ(UART_FIFO_AHB_REG(UART_NUM));
+}
+
+void esp_gdbstub_putchar(int c)
+{
+    while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) {
+        ;
+    }
+    REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
+}
+
+void esp_gdbstub_flush()
+{
+    //not needed for uart
+}
+
+#endif
+
+int esp_gdbstub_readmem(intptr_t addr)
+{
+    if (!check_inside_valid_region(addr)) {
+        /* see esp_cpu_configure_region_protection */
+        return -1;
+    }
+    uint32_t val_aligned = *(uint32_t *)(addr & (~3));
+    uint32_t shift = (addr & 3) * 8;
+    return (val_aligned >> shift) & 0xff;
+}
+
+int esp_gdbstub_writemem(unsigned int addr, unsigned char data)
+{
+    if (!check_inside_valid_region(addr)) {
+        /* see esp_cpu_configure_region_protection */
+        return -1;
+    }
+
+    int *i = (int *)(addr & (~3));
+    if ((addr & 3) == 0) {
+        *i = (*i & 0xffffff00) | (data << 0);
+    }
+    if ((addr & 3) == 1) {
+        *i = (*i & 0xffff00ff) | (data << 8);
+    }
+    if ((addr & 3) == 2) {
+        *i = (*i & 0xff00ffff) | (data << 16);
+    }
+    if ((addr & 3) == 3) {
+        *i = (*i & 0x00ffffff) | (data << 24);
+    }
+    return 0;
+}

components/esp_gdbstub/esp32p4/gdbstub_target_config.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once

components/esp_hw_support/CMakeLists.txt

@@ -124,6 +124,16 @@ if(NOT BOOTLOADER_BUILD)
     if(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED)
         list(APPEND srcs "sleep_wake_stub.c")
     endif()
+
+    if(CONFIG_IDF_TARGET_ESP32P4)
+        list(REMOVE_ITEM srcs
+                "sleep_cpu.c"         # TODO: IDF-7528, IDF-7529
+                "sleep_modes.c"       # TODO: IDF-7528, IDF-7529
+                "sleep_wake_stub.c"   # TODO: IDF-7529
+                "sleep_gpio.c"        # TODO: IDF-7528, IDF-7529
+                "port/esp_clk_tree_common.c"    # TODO: IDF-7526
+            )
+    endif()
 else()
     # Requires "_esp_error_check_failed()" function
     list(APPEND priv_requires "esp_system")

components/esp_hw_support/include/esp_memory_utils.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -164,6 +164,20 @@ inline static void * esp_ptr_diram_iram_to_dram(const void *p) {
 #endif
 }
 
+#if SOC_MEM_TCM_SUPPORTED
+/**
+ * @brief Check if the pointer is in TCM
+ *
+ * @param p pointer
+ *
+ * @return true: is in TCM; false: not in TCM
+ */
+__attribute__((always_inline))
+inline static bool esp_ptr_in_tcm(const void *p) {
+    return ((intptr_t)p >= SOC_TCM_LOW && (intptr_t)p < SOC_TCM_HIGH);
+}
+#endif  //#if SOC_MEM_TCM_SUPPORTED
+
 /** End of common functions to be kept in sync with bootloader_memory_utils.h **/
 /** Add app-specific functions below **/
 

components/esp_hw_support/include/soc/esp32p4/esp_crypto_lock.h

@@ -0,0 +1,68 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Acquire lock for HMAC cryptography peripheral
+ *
+ * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral
+ */
+void esp_crypto_hmac_lock_acquire(void);
+
+/**
+ * @brief Release lock for HMAC cryptography peripheral
+ *
+ * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral
+ */
+void esp_crypto_hmac_lock_release(void);
+
+/**
+ * @brief Acquire lock for DS cryptography peripheral
+ *
+ * Internally also locks the HMAC (which locks SHA), AES and MPI  peripheral, as the DS depends on these peripherals
+ */
+void esp_crypto_ds_lock_acquire(void);
+
+/**
+ * @brief Release lock for DS cryptography peripheral
+ *
+ * Internally also releases the HMAC (which locks SHA), AES and MPI  peripheral, as the DS depends on these peripherals
+ */
+void esp_crypto_ds_lock_release(void);
+
+/**
+ * @brief Acquire lock for the SHA and AES cryptography peripheral.
+ *
+ */
+void esp_crypto_sha_aes_lock_acquire(void);
+
+/**
+ * @brief Release lock for the SHA and AES cryptography peripheral.
+ *
+ */
+void esp_crypto_sha_aes_lock_release(void);
+
+
+/**
+ * @brief Acquire lock for the mpi cryptography peripheral.
+ *
+ */
+void esp_crypto_mpi_lock_acquire(void);
+
+/**
+ * @brief Release lock for the mpi/rsa cryptography peripheral.
+ *
+ */
+void esp_crypto_mpi_lock_release(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/soc/esp32p4/rtc.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file esp32c6/rtc.h
+ *
+ * This file contains declarations of rtc related functions.
+ */
+
+/**
+ * @brief Get current value of RTC counter in microseconds
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter in microseconds
+ */
+uint64_t esp_rtc_get_time_us(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/soc/esp32p4/soc_memprot_types.h

@@ -0,0 +1,175 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//////////////////////////////////////////////////////////
+// ESP32-P4 PMS memory protection types
+//
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Memory types recognized by PMS
+ */
+typedef enum {
+    MEMPROT_TYPE_NONE                           = 0x00000000,
+    MEMPROT_TYPE_IRAM0_SRAM                     = 0x00000001,
+    MEMPROT_TYPE_DRAM0_SRAM                     = 0x00000002,
+    MEMPROT_TYPE_IRAM0_RTCFAST                  = 0x00000004,
+    MEMPROT_TYPE_ALL                            = 0x7FFFFFFF,
+    MEMPROT_TYPE_INVALID                        = 0x80000000,
+    MEMPROT_TYPE_IRAM0_ANY                      = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_IRAM0_RTCFAST
+} esp_mprot_mem_t;
+
+/**
+ * @brief Splitting address (line) type
+ */
+typedef enum {
+    MEMPROT_SPLIT_ADDR_NONE                     = 0x00000000,
+    MEMPROT_SPLIT_ADDR_IRAM0_DRAM0              = 0x00000001,
+    MEMPROT_SPLIT_ADDR_IRAM0_LINE_0             = 0x00000002,
+    MEMPROT_SPLIT_ADDR_IRAM0_LINE_1             = 0x00000004,
+    MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0         = 0x00000008,
+    MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1         = 0x00000010,
+    MEMPROT_SPLIT_ADDR_ALL                      = 0x7FFFFFFF,
+    MEMPROT_SPLIT_ADDR_INVALID                  = 0x80000000,
+    MEMPROT_SPLIT_ADDR_MAIN                     = MEMPROT_SPLIT_ADDR_IRAM0_DRAM0
+} esp_mprot_split_addr_t;
+
+/**
+ * @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address)
+ */
+typedef enum {
+    MEMPROT_PMS_AREA_NONE                       = 0x00000000,
+    MEMPROT_PMS_AREA_IRAM0_0                    = 0x00000001,
+    MEMPROT_PMS_AREA_IRAM0_1                    = 0x00000002,
+    MEMPROT_PMS_AREA_IRAM0_2                    = 0x00000004,
+    MEMPROT_PMS_AREA_IRAM0_3                    = 0x00000008,
+    MEMPROT_PMS_AREA_DRAM0_0                    = 0x00000010,
+    MEMPROT_PMS_AREA_DRAM0_1                    = 0x00000020,
+    MEMPROT_PMS_AREA_DRAM0_2                    = 0x00000040,
+    MEMPROT_PMS_AREA_DRAM0_3                    = 0x00000080,
+    MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO           = 0x00000100,
+    MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI           = 0x00000200,
+    MEMPROT_PMS_AREA_ALL                        = 0x7FFFFFFF,
+    MEMPROT_PMS_AREA_INVALID                    = 0x80000000
+} esp_mprot_pms_area_t;
+
+/**
+* @brief Memory protection configuration
+*/
+typedef struct {
+    bool invoke_panic_handler;  /*!< Register PMS violation interrupt for panic-handling */
+    bool lock_feature;          /*!< Lock all PMS settings */
+    void *split_addr;           /*!< Main I/D splitting address */
+    uint32_t mem_type_mask;     /*!< Memory types required to protect. See esp_mprot_mem_t enum */
+} esp_memp_config_t;
+
+#define ESP_MEMPROT_DEFAULT_CONFIG() { \
+    .invoke_panic_handler = true, \
+    .lock_feature = true, \
+    .split_addr = NULL, \
+    .mem_type_mask = MEMPROT_TYPE_ALL \
+}
+
+/**
+ * @brief Converts Memory protection type to string
+ *
+ * @param mem_type Memory protection type
+ */
+static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type)
+{
+    switch (mem_type) {
+    case MEMPROT_TYPE_NONE:
+        return "NONE";
+    case MEMPROT_TYPE_IRAM0_SRAM:
+        return "IRAM0_SRAM";
+    case MEMPROT_TYPE_DRAM0_SRAM:
+        return "DRAM0_SRAM";
+    case MEMPROT_TYPE_IRAM0_RTCFAST:
+        return "IRAM0_RTCFAST";
+    case MEMPROT_TYPE_IRAM0_ANY:
+        return "IRAM0_ANY";
+    case MEMPROT_TYPE_ALL:
+        return "ALL";
+    default:
+        return "INVALID";
+    }
+}
+
+/**
+ * @brief Converts Splitting address type to string
+ *
+ * @param line_type Split line type
+ */
+static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type)
+{
+    switch (line_type) {
+    case MEMPROT_SPLIT_ADDR_NONE:
+        return "SPLIT_ADDR_NONE";
+    case MEMPROT_SPLIT_ADDR_IRAM0_DRAM0:
+        return "SPLIT_ADDR_IRAM0_DRAM0";
+    case MEMPROT_SPLIT_ADDR_IRAM0_LINE_0:
+        return "SPLIT_ADDR_IRAM0_LINE_0";
+    case MEMPROT_SPLIT_ADDR_IRAM0_LINE_1:
+        return "SPLIT_ADDR_IRAM0_LINE_1";
+    case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0:
+        return "SPLIT_ADDR_DRAM0_DMA_LINE_0";
+    case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1:
+        return "SPLIT_ADDR_DRAM0_DMA_LINE_1";
+    case MEMPROT_SPLIT_ADDR_ALL:
+        return "SPLIT_ADDR_ALL";
+    default:
+        return "SPLIT_ADDR_INVALID";
+    }
+}
+
+/**
+ * @brief Converts PMS Area type to string
+ *
+ * @param area_type PMS Area type
+ */
+static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type)
+{
+    switch (area_type) {
+    case MEMPROT_PMS_AREA_NONE:
+        return "PMS_AREA_NONE";
+    case MEMPROT_PMS_AREA_IRAM0_0:
+        return "PMS_AREA_IRAM0_0";
+    case MEMPROT_PMS_AREA_IRAM0_1:
+        return "PMS_AREA_IRAM0_1";
+    case MEMPROT_PMS_AREA_IRAM0_2:
+        return "PMS_AREA_IRAM0_2";
+    case MEMPROT_PMS_AREA_IRAM0_3:
+        return "PMS_AREA_IRAM0_3";
+    case MEMPROT_PMS_AREA_DRAM0_0:
+        return "PMS_AREA_DRAM0_0";
+    case MEMPROT_PMS_AREA_DRAM0_1:
+        return "PMS_AREA_DRAM0_1";
+    case MEMPROT_PMS_AREA_DRAM0_2:
+        return "PMS_AREA_DRAM0_2";
+    case MEMPROT_PMS_AREA_DRAM0_3:
+        return "PMS_AREA_DRAM0_3";
+    case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO:
+        return "PMS_AREA_IRAM0_RTCFAST_LO";
+    case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI:
+        return "PMS_AREA_IRAM0_RTCFAST_HI";
+    case MEMPROT_PMS_AREA_ALL:
+        return "PMS_AREA_ALL";
+    default:
+        return "PMS_AREA_INVALID";
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/linker.lf

@@ -18,7 +18,7 @@ entries:
     if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y:
         rtc_init:rtc_vddsdio_get_config (noflash)
         rtc_init:rtc_vddsdio_set_config (noflash)
-    if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645
+    if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n && IDF_TARGET_ESP32P4 = n: # TODO: IDF-5645
         rtc_sleep (noflash_text)
     rtc_time (noflash_text)
     if SOC_PMU_SUPPORTED = y:
@@ -37,11 +37,11 @@ entries:
         mspi_timing_config (noflash)
         if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY = y:
             mspi_timing_by_mspi_delay (noflash)
-
-    if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
-        sar_periph_ctrl (noflash)
-    else:
-        sar_periph_ctrl: sar_periph_ctrl_power_enable (noflash)
+    if SOC_ADC_SHARED_POWER = y:
+        if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
+            sar_periph_ctrl (noflash)
+        else:
+            sar_periph_ctrl: sar_periph_ctrl_power_enable (noflash)
 
 [mapping:soc_pm]
 archive: libsoc.a

components/esp_hw_support/periph_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,6 +48,7 @@ void periph_module_reset(periph_module_t periph)
 }
 
 #if !SOC_IEEE802154_BLE_ONLY
+#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED
 IRAM_ATTR void wifi_bt_common_module_enable(void)
 {
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT
@@ -75,7 +76,8 @@ IRAM_ATTR void wifi_bt_common_module_disable(void)
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
 #endif
 }
-#endif
+#endif  //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED
+#endif  //#if !SOC_IEEE802154_BLE_ONLY
 
 #if CONFIG_ESP_WIFI_ENABLED
 void wifi_module_enable(void)

components/esp_hw_support/port/esp32p4/CMakeLists.txt

@@ -0,0 +1,29 @@
+set(srcs "rtc_clk_init.c"
+         "rtc_clk.c"
+         "pmu_param.c"
+         "pmu_init.c"
+         "pmu_sleep.c"
+         "rtc_time.c"
+         "chip_info.c"
+         )
+
+if(NOT BOOTLOADER_BUILD)
+    list(APPEND srcs "esp_crypto_lock.c")
+
+    if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
+        list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
+    endif()
+
+endif()
+
+list(REMOVE_ITEM srcs
+        "pmu_param.c" # TODO: IDF-7531
+        "pmu_sleep.c" # TODO: IDF-7531
+        "pmu_init.c"  # TODO: IDF-7531
+    )
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
+target_include_directories(${COMPONENT_LIB} PRIVATE ../hal)

components/esp_hw_support/port/esp32p4/Kconfig.hw_support

@@ -0,0 +1,41 @@
+choice ESP32P4_REV_MIN
+    prompt "Minimum Supported ESP32-P4 Revision"
+    default ESP32P4_REV_MIN_0
+    help
+        Required minimum chip revision. ESP-IDF will check for it and
+        reject to boot if the chip revision fails the check.
+        This ensures the chip used will have some modifications (features, or bugfixes).
+
+        The complied binary will only support chips above this revision,
+        this will also help to reduce binary size.
+
+    config ESP32P4_REV_MIN_0
+        bool "Rev v0.0"
+endchoice
+
+config ESP32P4_REV_MIN_FULL
+    int
+    default 0 if ESP32P4_REV_MIN_0
+
+config ESP_REV_MIN_FULL
+    int
+    default ESP32P4_REV_MIN_FULL
+
+    #
+    # MAX Revision
+    #
+
+    comment "Maximum Supported ESP32-P4 Revision (Rev v0.99)"
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32P4_REV_MIN_FULL to ESP32P4_REV_MAX_FULL
+
+config ESP32P4_REV_MAX_FULL
+    int
+    default 99
+    # keep in sync the "Maximum Supported Revision" description with this value
+
+config ESP_REV_MAX_FULL
+    int
+    default ESP32P4_REV_MAX_FULL

components/esp_hw_support/port/esp32p4/Kconfig.rtc

@@ -0,0 +1,41 @@
+# TODO: IDF-7526
+
+choice RTC_CLK_SRC
+    prompt "RTC clock source"
+    default RTC_CLK_SRC_INT_RC
+    help
+        Choose which clock is used as RTC clock source.
+
+    config RTC_CLK_SRC_INT_RC
+        bool "Internal 136kHz RC oscillator"
+    config RTC_CLK_SRC_EXT_CRYS
+        bool "External 32kHz crystal"
+        select ESP_SYSTEM_RTC_EXT_XTAL
+    config RTC_CLK_SRC_EXT_OSC
+        bool "External 32kHz oscillator at 32K_XP pin"
+        select ESP_SYSTEM_RTC_EXT_OSC
+    config RTC_CLK_SRC_INT_RC32K
+        bool "Internal 32kHz RC oscillator"
+endchoice
+
+config RTC_CLK_CAL_CYCLES
+    int "Number of cycles for RTC_SLOW_CLK calibration"
+    default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+    default 1024 if RTC_CLK_SRC_INT_RC
+    range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+    range 0 32766 if RTC_CLK_SRC_INT_RC
+    help
+        When the startup code initializes RTC_SLOW_CLK, it can perform
+        calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
+        frequency. This option sets the number of RTC_SLOW_CLK cycles measured
+        by the calibration routine. Higher numbers increase calibration
+        precision, which may be important for applications which spend a lot of
+        time in deep sleep. Lower numbers reduce startup time.
+
+        When this option is set to 0, clock calibration will not be performed at
+        startup, and approximate clock frequencies will be assumed:
+
+        - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
+        - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
+            In case more value will help improve the definition of the launch of the crystal.
+            If the crystal could not start, it will be switched to internal RC.

components/esp_hw_support/port/esp32p4/chip_info.c

@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "esp_chip_info.h"
+#include "hal/efuse_hal.h"
+
+void esp_chip_info(esp_chip_info_t *out_info)
+{
+    memset(out_info, 0, sizeof(*out_info));
+    out_info->model = CHIP_ESP32P4;
+    out_info->revision = efuse_hal_chip_revision();
+    out_info->cores = 2;
+    out_info->features = 0;
+}

components/esp_hw_support/port/esp32p4/cpu_region_protect.c

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "esp_cpu.h"
+#include "esp_fault.h"
+
+#ifdef BOOTLOADER_BUILD
+// Without L bit set
+#define CONDITIONAL_NONE        0x0
+#define CONDITIONAL_RX          PMP_R | PMP_X
+#define CONDITIONAL_RW          PMP_R | PMP_W
+#define CONDITIONAL_RWX         PMP_R | PMP_W | PMP_X
+#else
+// With L bit set
+#define CONDITIONAL_NONE        NONE
+#define CONDITIONAL_RX          RX
+#define CONDITIONAL_RW          RW
+#define CONDITIONAL_RWX         RWX
+#endif
+
+void esp_cpu_configure_region_protection(void)
+{
+    //IDF-7542
+}

components/esp_hw_support/port/esp32p4/esp_crypto_lock.c

@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/lock.h>
+
+#include "esp_crypto_lock.h"
+
+/* Lock overview:
+SHA: peripheral independent, but DMA is shared with AES
+AES: peripheral independent, but DMA is shared with SHA
+MPI/RSA: independent
+HMAC: needs SHA
+DS: needs HMAC (which needs SHA), AES and MPI
+*/
+
+/* Lock for DS peripheral */
+static _lock_t s_crypto_ds_lock;
+
+/* Lock for HMAC peripheral */
+static _lock_t s_crypto_hmac_lock;
+
+/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */
+static _lock_t s_crypto_mpi_lock;
+
+/* Single lock for SHA and AES, sharing a reserved GDMA channel */
+static _lock_t s_crypto_sha_aes_lock;
+
+void esp_crypto_hmac_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_hmac_lock);
+    esp_crypto_sha_aes_lock_acquire();
+}
+
+void esp_crypto_hmac_lock_release(void)
+{
+    esp_crypto_sha_aes_lock_release();
+    _lock_release(&s_crypto_hmac_lock);
+}
+
+void esp_crypto_ds_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_ds_lock);
+    esp_crypto_hmac_lock_acquire();
+    esp_crypto_mpi_lock_acquire();
+}
+
+void esp_crypto_ds_lock_release(void)
+{
+    esp_crypto_mpi_lock_release();
+    esp_crypto_hmac_lock_release();
+    _lock_release(&s_crypto_ds_lock);
+}
+
+void esp_crypto_sha_aes_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_sha_aes_lock);
+}
+
+void esp_crypto_sha_aes_lock_release(void)
+{
+    _lock_release(&s_crypto_sha_aes_lock);
+}
+
+void esp_crypto_mpi_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_mpi_lock);
+}
+
+void esp_crypto_mpi_lock_release(void)
+{
+    _lock_release(&s_crypto_mpi_lock);
+}

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -0,0 +1,391 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <stdlib.h>
+#include "sdkconfig.h"
+#include "esp32p4/rom/ets_sys.h"
+#include "esp32p4/rom/rtc.h"
+#include "soc/rtc.h"
+#include "esp_private/rtc_clk.h"
+#include "esp_hw_log.h"
+#include "esp_rom_sys.h"
+#include "hal/clk_tree_ll.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "soc/io_mux_reg.h"
+#include "soc/lp_clkrst_reg.h"
+
+static const char *TAG = "rtc_clk";
+
+// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
+static int s_cur_pll_freq;
+
+static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
+
+void rtc_clk_bbpll_add_consumer(void)
+{
+    s_bbpll_digi_consumers_ref_count += 1;
+}
+
+void rtc_clk_bbpll_remove_consumer(void)
+{
+    s_bbpll_digi_consumers_ref_count -= 1;
+}
+
+void rtc_clk_32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
+    } else {
+        clk_ll_xtal32k_disable();
+    }
+}
+
+void rtc_clk_32k_enable_external(void)
+{
+}
+
+void rtc_clk_32k_bootstrap(uint32_t cycle)
+{
+    /* No special bootstrapping needed for ESP32-P4, 'cycle' argument is to keep the signature
+     * same as for the ESP32. Just enable the XTAL here.
+     */
+    (void)cycle;
+    rtc_clk_32k_enable(true);
+}
+
+bool rtc_clk_32k_enabled(void)
+{
+    return clk_ll_xtal32k_is_enabled();
+}
+
+void rtc_clk_rc32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_rc32k_enable();
+        esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE);
+    } else {
+        clk_ll_rc32k_disable();
+    }
+}
+
+void rtc_clk_8m_enable(bool clk_8m_en)
+{
+    if (clk_8m_en) {
+        clk_ll_rc_fast_enable();
+        esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE);
+    } else {
+        clk_ll_rc_fast_disable();
+    }
+}
+
+bool rtc_clk_8m_enabled(void)
+{
+    return clk_ll_rc_fast_is_enabled();
+}
+
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
+{
+    clk_ll_rtc_slow_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
+}
+
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
+{
+    return clk_ll_rtc_slow_get_src();
+}
+
+uint32_t rtc_clk_slow_freq_get_hz(void)
+{
+    switch (rtc_clk_slow_src_get()) {
+    case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
+    case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
+    default: return 0;
+    }
+}
+
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
+{
+    clk_ll_rtc_fast_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
+}
+
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
+{
+    return clk_ll_rtc_fast_get_src();
+}
+
+static void rtc_clk_bbpll_disable(void)
+{
+    clk_ll_bbpll_disable();
+    s_cur_pll_freq = 0;
+}
+
+static void rtc_clk_bbpll_enable(void)
+{
+    clk_ll_bbpll_enable();
+}
+
+static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
+{
+    /* Digital part */
+    clk_ll_bbpll_set_freq_mhz(pll_freq);
+    /* Analog part */
+    /* BBPLL CALIBRATION START */
+    regi2c_ctrl_ll_bbpll_calibration_start();
+    clk_ll_bbpll_set_config(pll_freq, xtal_freq);
+    /* WAIT CALIBRATION DONE */
+    while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    /* BBPLL CALIBRATION STOP */
+    regi2c_ctrl_ll_bbpll_calibration_stop();
+
+    s_cur_pll_freq = pll_freq;
+}
+
+/**
+ * Switch to use XTAL as the CPU clock source.
+ * Must satisfy: cpu_freq = XTAL_FREQ / div.
+ * Does not disable the PLL.
+ */
+static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
+{
+    clk_ll_ahb_set_ls_divider(div);
+    clk_ll_cpu_set_ls_divider(div);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
+    ets_update_cpu_frequency(cpu_freq);
+}
+
+static void rtc_clk_cpu_freq_to_8m(void)
+{
+    clk_ll_ahb_set_ls_divider(1);
+    clk_ll_cpu_set_ls_divider(1);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
+    ets_update_cpu_frequency(20);
+}
+
+/**
+ * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
+ * PLL must already be enabled.
+ * @param cpu_freq new CPU frequency
+ */
+static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+    clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
+    ets_update_cpu_frequency(cpu_freq_mhz);
+}
+
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
+{
+    uint32_t source_freq_mhz;
+    soc_cpu_clk_src_t source;
+    uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t real_freq_mhz;
+
+    uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 80) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 6;
+    } else if (freq_mhz == 120) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 4;
+    } else if (freq_mhz == 160) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        divider = 3;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .div = divider,
+        .source_freq_mhz = source_freq_mhz,
+        .freq_mhz = real_freq_mhz
+    };
+    return true;
+}
+
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
+{
+    soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
+            // We don't turn off the bbpll if some consumers depend on bbpll
+            rtc_clk_bbpll_disable();
+        }
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL) {
+        if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) {
+            rtc_clk_bbpll_enable();
+            rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
+        }
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
+            // We don't turn off the bbpll if some consumers depend on bbpll
+            rtc_clk_bbpll_disable();
+        }
+    }
+}
+
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t source_freq_mhz;
+    uint32_t div; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t freq_mhz;
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL: {
+        div = clk_ll_cpu_get_ls_divider();
+        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_PLL: {
+        div = clk_ll_cpu_get_hs_divider();
+        source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        div = clk_ll_cpu_get_ls_divider();
+        source_freq_mhz = 20;
+        freq_mhz = source_freq_mhz / div;
+        break;
+    default:
+        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
+        abort();
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .source_freq_mhz = source_freq_mhz,
+        .div = div,
+        .freq_mhz = freq_mhz
+    };
+}
+
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
+{
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL &&
+               s_cur_pll_freq == config->source_freq_mhz) {
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+    } else {
+        /* fallback */
+        rtc_clk_cpu_freq_set_config(config);
+    }
+}
+
+void rtc_clk_cpu_freq_set_xtal(void)
+{
+    rtc_clk_cpu_set_to_default_config();
+    // We don't turn off the bbpll if some consumers depend on bbpll
+    if (!s_bbpll_digi_consumers_ref_count) {
+        rtc_clk_bbpll_disable();
+    }
+}
+
+void rtc_clk_cpu_set_to_default_config(void)
+{
+    int freq_mhz = (int)rtc_clk_xtal_freq_get();
+
+    rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+}
+
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
+{
+    uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
+    if (xtal_freq_mhz == 0) {
+        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
+        return RTC_XTAL_FREQ_40M;
+    }
+    return (rtc_xtal_freq_t)xtal_freq_mhz;
+}
+
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
+{
+    clk_ll_xtal_store_freq_mhz(xtal_freq);
+}
+
+static uint32_t rtc_clk_ahb_freq_get(void)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t soc_root_freq_mhz;
+    uint32_t divider;
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        soc_root_freq_mhz = rtc_clk_xtal_freq_get();
+        divider = clk_ll_ahb_get_ls_divider();
+        break;
+    case SOC_CPU_CLK_SRC_PLL:
+        soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        divider = clk_ll_ahb_get_hs_divider();
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        soc_root_freq_mhz = 20;
+        divider = clk_ll_ahb_get_ls_divider();
+        break;
+    default:
+        // Unknown SOC_ROOT clock source
+        soc_root_freq_mhz = 0;
+        divider = 1;
+        ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK");
+        break;
+    }
+    return soc_root_freq_mhz / divider;
+}
+
+uint32_t rtc_clk_apb_freq_get(void)
+{
+    return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ;
+}
+
+void rtc_dig_clk8m_enable(void)
+{
+    clk_ll_rc_fast_digi_enable();
+    esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
+}
+
+void rtc_dig_clk8m_disable(void)
+{
+    clk_ll_rc_fast_digi_disable();
+    esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
+}
+
+bool rtc_dig_8m_enabled(void)
+{
+    return clk_ll_rc_fast_digi_is_enabled();
+}
+
+/* Name used in libphy.a:phy_chip_v7.o
+ * TODO: update the library to use rtc_clk_xtal_freq_get
+ */
+rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));

components/esp_hw_support/port/esp32p4/rtc_clk_init.c

@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include "esp32p4/rom/ets_sys.h"
+#include "esp32p4/rom/rtc.h"
+#include "esp32p4/rom/uart.h"
+#include "soc/rtc.h"
+#include "esp_cpu.h"
+#include "regi2c_ctrl.h"
+#include "soc/lp_clkrst_reg.h"
+#include "soc/regi2c_dig_reg.h"
+#include "esp_hw_log.h"
+#include "sdkconfig.h"
+#include "esp_rom_uart.h"
+#include "esp_private/esp_pmu.h"
+#include "hal/clk_tree_ll.h"
+
+static const char *TAG = "rtc_clk_init";
+
+#if SOC_PMU_SUPPORTED
+/**
+ * Initialize the ICG map of some modem clock domains in the PMU_ACTIVE state
+ *
+ * A pre-initialization interface is used to initialize the ICG map of the
+ * MODEM_APB, I2C_MST and LP_APB clock domains in the PMU_ACTIVE state, and
+ * disable the clock gating of these clock domains in the PMU_ACTIVE state,
+ * because the system clock source (PLL) in the system boot up process needs
+ * to use the i2c master peripheral.
+ *
+ * ICG map of all modem clock domains under different power states (PMU_ACTIVE,
+ * PMU_MODEM and PMU_SLEEP) will be initialized in esp_perip_clk_init().
+ */
+static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
+{
+    /* Configure modem ICG code in PMU_ACTIVE state */
+    pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
+
+    /* Disable clock gating for MODEM_APB, I2C_MST and LP_APB clock domains in PMU_ACTIVE state */
+    modem_syscon_ll_set_modem_apb_icg_bitmap(&MODEM_SYSCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+    modem_lpcon_ll_set_i2c_master_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+    modem_lpcon_ll_set_lp_apb_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
+
+    /* Software trigger force update modem ICG code and ICG switch */
+    pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
+    pmu_ll_imm_update_dig_icg_switch(&PMU, true);
+}
+#endif  //#if SOC_PMU_SUPPORTED
+
+void rtc_clk_init(rtc_clk_config_t cfg)
+{
+    rtc_cpu_freq_config_t old_config, new_config;
+
+#if SOC_PMU_SUPPORTED
+    rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
+#endif  //#if SOC_PMU_SUPPORTED
+
+    /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
+     * Note: this doesn't attempt to set the clocks to precise frequencies.
+     * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
+     * - SCK_DCAP value controls tuning of RC_SLOW clock.
+     *   The higher the value of DCAP is, the lower is the frequency.
+     * - CK8M_DFREQ value controls tuning of RC_FAST clock.
+     *   CLK_8M_DFREQ constant gives the best temperature characteristics.
+     * - RC32K_DFREQ value controls tuning of RC32K clock.
+     */
+    REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap);
+    REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
+
+    rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
+    esp_rom_uart_tx_wait_idle(0);
+    rtc_clk_xtal_freq_update(xtal_freq);
+
+    /* Set CPU frequency */
+    rtc_clk_cpu_freq_get_config(&old_config);
+    uint32_t freq_before = old_config.freq_mhz;
+    bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
+    if (!res) {
+        ESP_HW_LOGE(TAG, "invalid CPU frequency value");
+        abort();
+    }
+    rtc_clk_cpu_freq_set_config(&new_config);
+
+    /* Re-calculate the ccount to make time calculation correct. */
+    esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
+
+    /* Slow & fast clocks setup */
+    // We will not power off RC_FAST in bootloader stage even if it is not being used as any
+    // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
+    bool need_rc_fast_en = true;
+    if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
+        rtc_clk_32k_enable(true);
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+        rtc_clk_32k_enable_external();
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
+       rtc_clk_rc32k_enable(true);
+    }
+    rtc_clk_8m_enable(need_rc_fast_en);
+    rtc_clk_fast_src_set(cfg.fast_clk_src);
+    rtc_clk_slow_src_set(cfg.slow_clk_src);
+}

components/esp_hw_support/port/esp32p4/rtc_time.c

@@ -0,0 +1,227 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp32p4/rom/ets_sys.h"
+#include "soc/rtc.h"
+#include "soc/lp_timer_reg.h"
+#include "hal/lp_timer_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/timer_group_reg.h"
+#include "esp_rom_sys.h"
+#include "assert.h"
+
+static const char *TAG = "rtc_time";
+
+/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ */
+
+/* On ESP32P4, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
+ * 0 or 3: calibrate RC_SLOW clock
+ * 1: calibrate RC_FAST clock
+ * 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by lp_pad_gpio0
+ */
+#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
+#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
+#define TIMG_RTC_CALI_CLK_SEL_32K     2
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
+
+    uint32_t cali_clk_sel = 0;
+    soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
+    soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target();
+    if (cal_clk == RTC_CAL_RTC_MUX) {
+        cal_clk = (rtc_cal_sel_t)slow_clk_src;
+    }
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
+    } else if (cal_clk == RTC_CAL_RC_SLOW) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
+    } else {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
+        clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
+    }
+
+
+    /* Enable requested clock (150k clock is always on) */
+    // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
+    // Only enable if orignally was disabled, and set back to the disable state after calibration is done
+    // If the clock is already on, then do nothing
+    bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+            clk_ll_xtal32k_digi_enable();
+    }
+
+    bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
+    bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(true);
+        }
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_enable();
+        }
+    }
+
+    bool rc32k_enabled = clk_ll_rc32k_is_enabled();
+    bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(true);
+        }
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_enable();
+        }
+    }
+
+    /* There may be another calibration process already running during we call this function,
+     * so we should wait the last process is done.
+     */
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        /**
+         * Set a small timeout threshold to accelerate the generation of timeout.
+         * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
+         */
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
+    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
+    /* Figure out how long to wait for calibration to finish */
+
+    /* Set timeout reg and expect time delay*/
+    uint32_t expected_freq;
+    if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
+    } else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
+    } else {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
+    }
+    uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
+    /* Start calibration */
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+    SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* Wait for calibration to finish up to another us_time_estimate */
+    esp_rom_delay_us(us_time_estimate);
+    uint32_t cal_val;
+    while (true) {
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
+            cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
+            break;
+        }
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
+            cal_val = 0;
+            break;
+        }
+    }
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+        clk_ll_xtal32k_digi_disable();
+    }
+
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_disable();
+        }
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(false);
+        }
+    }
+
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_disable();
+        }
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(false);
+        }
+    }
+
+    // Always set back the calibration 32kHz clock selection
+    if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
+        clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
+    }
+
+    return cal_val;
+}
+
+static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
+{
+    uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
+    uint64_t delta = expected_xtal_cycles / 2000;                                    // 5/10000 = 0.05% error range
+    return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
+}
+
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
+
+    if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
+        return 0;
+    }
+
+    uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
+    uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
+    uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
+    return period;
+}
+
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
+{
+    /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
+     * TODO: fix overflow.
+     */
+    return (time_in_us << RTC_CLK_CAL_FRACT) / period;
+}
+
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
+{
+    return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
+}
+
+uint64_t rtc_time_get(void)
+{
+    // return lp_timer_hal_get_cycle_count(0);
+    ESP_EARLY_LOGE(TAG, "rtc_time_get has not been implemented yet");
+    return 0;
+}
+
+void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
+{
+    // TODO: IDF-5781
+    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
+}
+
+uint32_t rtc_clk_freq_cal(uint32_t cal_val)
+{
+    if (cal_val == 0) {
+        return 0;   // cal_val will be denominator, return 0 as the symbol of failure.
+    }
+    return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
+}

components/esp_hw_support/port/esp32p4/systimer.c

@@ -7,6 +7,7 @@
 #include "esp_private/systimer.h"
 
 /**
+ * //TODO: IDF-7487
  * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
  *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
  */

components/esp_hw_support/rtc_module.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,11 +26,11 @@
 #endif
 #include "sys/queue.h"
 
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4// TODO: IDF-8008
 static const char *TAG = "rtc_module";
 #endif
 
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
 
 #define NOT_REGISTERED      (-1)
 
@@ -95,11 +95,11 @@ out:
     portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
     return err;
 }
-#endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-5645
+#endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-8008
 
 esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
 {
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
     ESP_EARLY_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
     return ESP_OK;
 #else
@@ -130,7 +130,7 @@ esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t r
 
 esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
 {
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
     ESP_EARLY_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
     return ESP_OK;
 #else
@@ -159,7 +159,7 @@ esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
 #endif
 }
 
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
 /**
  * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
  *        There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
@@ -182,7 +182,7 @@ static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)
 
 IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
 {
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
     if (rtc_isr_cpu == cpu) {
         rtc_intr_enabled |= RTCCNTL.int_ena.val;
         RTCCNTL.int_ena.val &= rtc_intr_cache;
@@ -192,7 +192,7 @@ IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
 
 IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
 {
-#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5645
+#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
     if (rtc_isr_cpu == cpu) {
         RTCCNTL.int_ena.val = rtc_intr_enabled;
         rtc_intr_enabled = 0;

components/esp_mm/esp_mmu_map.c

@@ -391,7 +391,10 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v
     mmu_hal_map_region(0, target, vaddr_start, paddr_start, size, &actual_mapped_len);
 #if (SOC_MMU_PERIPH_NUM == 2)
 #if !CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_IDF_TARGET_ESP32P4 // for spi flash mmap, we always use flash mmu
+    //TODO: IDF-7509
     mmu_hal_map_region(1, target, vaddr_start, paddr_start, size, &actual_mapped_len);
+#endif
 #endif //  #if !CONFIG_FREERTOS_UNICORE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)
 
@@ -529,6 +532,11 @@ esp_err_t esp_mmu_map(esp_paddr_t paddr_start, size_t size, mmu_target_t target,
     new_block->laddr_end = new_block->laddr_start + aligned_size;
     new_block->size = aligned_size;
     new_block->caps = caps;
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7509
+    new_block->vaddr_start = mmu_ll_laddr_to_vaddr(new_block->laddr_start, MMU_VADDR_FLASH);
+    new_block->vaddr_end = mmu_ll_laddr_to_vaddr(new_block->laddr_end, MMU_VADDR_FLASH);
+#else
     if (caps & MMU_MEM_CAP_EXEC) {
         new_block->vaddr_start = mmu_ll_laddr_to_vaddr(new_block->laddr_start, MMU_VADDR_INSTRUCTION);
         new_block->vaddr_end = mmu_ll_laddr_to_vaddr(new_block->laddr_end, MMU_VADDR_INSTRUCTION);
@@ -536,6 +544,7 @@ esp_err_t esp_mmu_map(esp_paddr_t paddr_start, size_t size, mmu_target_t target,
         new_block->vaddr_start = mmu_ll_laddr_to_vaddr(new_block->laddr_start, MMU_VADDR_DATA);
         new_block->vaddr_end = mmu_ll_laddr_to_vaddr(new_block->laddr_end, MMU_VADDR_DATA);
     }
+#endif
     new_block->paddr_start = paddr_start;
     new_block->paddr_end = paddr_start + aligned_size;
     new_block->target = target;
@@ -570,7 +579,10 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_unmapping(uint32_t vaddr_start, uint32_
     mmu_hal_unmap_region(0, vaddr_start, size);
 #if (SOC_MMU_PERIPH_NUM == 2)
 #if !CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_IDF_TARGET_ESP32P4 // for flash mmap, we always use flash mmu
+    //TODO: IDF-7509
     mmu_hal_unmap_region(1, vaddr_start, size);
+#endif
 #endif //  #if !CONFIG_FREERTOS_UNICORE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)
 

components/esp_mm/port/esp32p4/ext_mem_layout.c

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/ext_mem_defs.h"
+#include "../ext_mem_layout.h"
+#include "hal/mmu_types.h"
+
+/**
+ * The start addresses in this list should always be sorted from low to high, as MMU driver will need to
+ * coalesce adjacent regions
+ */
+const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
+    [0] = {
+        .start = SOC_MMU_FLASH_LINEAR_ADDRESS_LOW,
+        .end = SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH,
+        .size = SOC_MMU_FLASH_LINEAR_ADDRESS_SIZE,
+        .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
+        .targets = MMU_TARGET_FLASH0,
+        .caps = MMU_MEM_CAP_FLASH | MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
+    },
+    [1] = {
+        .start = SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW,
+        .end = SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH,
+        .size = SOC_MMU_PSRAM_LINEAR_ADDRESS_SIZE,
+        .bus_id = CACHE_BUS_IBUS1 | CACHE_BUS_DBUS1,
+        .targets = MMU_TARGET_PSRAM0,
+        .caps = MMU_MEM_CAP_PSRAM | MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
+    },
+};

components/esp_pm/pm_impl.c

@@ -83,6 +83,8 @@
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define REF_CLK_DIV_MIN 2
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define REF_CLK_DIV_MIN 2
 #endif
 
 #ifdef CONFIG_PM_PROFILING

components/esp_psram/esp_psram.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -196,19 +196,34 @@ esp_err_t esp_psram_init(void)
     size_t total_mapped_size = 0;
     size_t size_to_map = 0;
     size_t byte_aligned_size = 0;
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7495
+    ret = esp_mmu_map_get_max_consecutive_free_block_size(MMU_MEM_CAP_PSRAM, MMU_TARGET_PSRAM0, &byte_aligned_size);
+#else
     ret = esp_mmu_map_get_max_consecutive_free_block_size(MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &byte_aligned_size);
+#endif
     assert(ret == ESP_OK);
     size_to_map = MIN(byte_aligned_size, psram_available_size);
 
     const void *v_start_8bit_aligned = NULL;
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7495
+    ret = esp_mmu_map_reserve_block_with_caps(size_to_map, MMU_MEM_CAP_PSRAM, MMU_TARGET_PSRAM0, &v_start_8bit_aligned);
+#else
     ret = esp_mmu_map_reserve_block_with_caps(size_to_map, MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_8BIT | MMU_MEM_CAP_32BIT, MMU_TARGET_PSRAM0, &v_start_8bit_aligned);
+#endif
     assert(ret == ESP_OK);
 
 #if CONFIG_IDF_TARGET_ESP32
     s_mapping((int)v_start_8bit_aligned, size_to_map);
 #else
     uint32_t actual_mapped_len = 0;
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7495
+    mmu_hal_map_region(1, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
+#else
     mmu_hal_map_region(0, MMU_TARGET_PSRAM0, (intptr_t)v_start_8bit_aligned, MMU_PAGE_TO_BYTES(start_page), size_to_map, &actual_mapped_len);
+#endif
     start_page += BYTES_TO_MMU_PAGE(actual_mapped_len);
     ESP_EARLY_LOGV(TAG, "8bit-aligned-region: actual_mapped_len is 0x%x bytes", actual_mapped_len);
 

components/esp_rom/include/esp32p4/rom/cache.h

@@ -1425,7 +1425,7 @@ uint32_t Cache_Get_L2_Cache_Line_Size(void);
   *
   * @return uint32_t: 16, 32, 64 Byte
   */
-uint32_t Cache_Get_DCache_Line_Size();
+uint32_t Cache_Get_DCache_Line_Size(void);
 
 /**
   * @brief Freeze L1 core0 icache

components/esp_system/ld/esp32p4/memory.ld.in

@@ -23,7 +23,7 @@
 #define SRAM_DRAM_START     0x4ff00000
 
 #define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
-#define SRAM_DRAM_END       0x4ff30bd0 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
+#define SRAM_DRAM_END       0x4FF2DBD0 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
 
 #define SRAM_IRAM_ORG       (SRAM_IRAM_START)
 #define SRAM_DRAM_ORG       (SRAM_DRAM_START)

components/esp_system/port/cpu_start.c

@@ -485,8 +485,8 @@ void IRAM_ATTR call_start_cpu0(void)
 
 #if CONFIG_IDF_TARGET_ESP32P4
     //TODO: IDF-7516, add cache init API
-    extern void esp_config_llc_mode(void);
-    esp_config_llc_mode();
+    extern void esp_config_l2_cache_mode(void);
+    esp_config_l2_cache_mode();
 #endif
     if (esp_efuse_check_errors() != ESP_OK) {
         esp_restart();

components/hal/esp32p4/include/hal/clk_tree_ll.h

@@ -359,7 +359,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(void)
 {
-    return 0;
+    return 1;
 }
 
 /**
@@ -379,7 +379,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
 {
-    return 0;
+    return 1;
 }
 
 /**

components/hal/esp32p4/include/hal/uart_ll.h

@@ -11,6 +11,7 @@
 #pragma once
 
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "hal/uart_types.h"
 #include "soc/uart_periph.h"
 #include "soc/uart_reg.h"
@@ -82,7 +83,7 @@ static inline void uart_ll_update(uart_dev_t *hw)
 static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
 {
     // hw->clk_conf.rst_core = core_rst_en;
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -97,7 +98,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
     // hw->clk_conf.sclk_en = 1;
     // hw->clk_conf.rx_sclk_en = 1;
     // hw->clk_conf.tx_sclk_en = 1;
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -112,7 +113,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
     // hw->clk_conf.sclk_en = 0;
     // hw->clk_conf.rx_sclk_en = 0;
     // hw->clk_conf.tx_sclk_en = 0;
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -184,7 +185,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
 {
     // typeof(hw->clkdiv_sync) div_reg = hw->clkdiv_sync;
     // return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -576,7 +577,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
     // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
     // uart_ll_update(hw);
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -774,7 +775,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
 {
     // *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
     // *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -937,7 +938,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
 static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
 {
     // return UART_RX_TOUT_THRHD_V;
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -1014,7 +1015,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
     // REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
     // REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
     // uart_ll_update(UART_LL_GET_HW(uart_num));
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -1030,7 +1031,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
     // REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
     // REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
     // uart_ll_update(UART_LL_GET_HW(uart_num));
-    abort();
+    HAL_ASSERT(false);
 }
 
 /**
@@ -1043,7 +1044,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
 static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
 {
     // return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
-    abort();
+    HAL_ASSERT(false);
 }
 
 #ifdef __cplusplus

components/heap/include/esp_heap_caps.h

@@ -42,6 +42,7 @@ extern "C" {
 #define MALLOC_CAP_IRAM_8BIT        (1<<13) ///< Memory must be in IRAM and allow unaligned access
 #define MALLOC_CAP_RETENTION        (1<<14) ///< Memory must be able to accessed by retention DMA
 #define MALLOC_CAP_RTCRAM           (1<<15) ///< Memory must be in RTC fast memory
+#define MALLOC_CAP_TCM              (1<<16) ///< Memory must be in TCM memory
 
 #define MALLOC_CAP_INVALID          (1<<31) ///< Memory can't be used / list end marker
 

components/heap/port/esp32p4/memory_layout.c

@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "esp_attr.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "heap_memory_layout.h"
+#include "esp_heap_caps.h"
+
+/**
+ * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
+ * Each type of memory map consists of one or more regions in the address space.
+ * Each type contains an array of prioritized capabilities.
+ * Types with later entries are only taken if earlier ones can't fulfill the memory request.
+ *
+ * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
+ * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
+ * - Most other malloc caps only fit in one region anyway.
+ *
+ */
+
+/* Index of memory in `soc_memory_types[]` */
+enum {
+    SOC_MEMORY_TYPE_DRAM        = 0,
+    SOC_MEMORY_TYPE_STACK_DRAM  = 1,
+    SOC_MEMORY_TYPE_DIRAM       = 2,
+    SOC_MEMORY_TYPE_STACK_DIRAM = 3,
+    SOC_MEMORY_TYPE_RTCRAM      = 4,
+    SOC_MEMORY_TYPE_TCM         = 5,
+    SOC_MEMORY_TYPE_NUM,
+};
+
+const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
+    // Type 0: DRAM
+    [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
+    // Type 1: DRAM used for startup stacks
+    [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
+    // Type 2: DRAM which has an alias on the I-port
+    [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
+    // Type 3: DIRAM used for startup stacks
+    [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
+    // Type 4: RTCRAM   // TODO: IDF-5667 Better to rename to LPRAM
+    [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
+    // Type 5: TCM
+    [SOC_MEMORY_TYPE_TCM] = {"TCM", {MALLOC_CAP_TCM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT}, false, false},
+};
+
+#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
+#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
+#else
+#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
+#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
+#endif
+
+const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
+
+/**
+ * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
+ *
+ * @note Because of requirements in the coalescing code which merges adjacent regions,
+ *       this list should always be sorted from low to high by start address.
+ *
+ */
+
+/**
+ * Register the shared buffer area of the last memory block into the heap during heap initialization
+ */
+#define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
+
+const soc_memory_region_t soc_memory_regions[] = {
+#ifdef CONFIG_SPIRAM
+    { SOC_EXTRAM_LOW,  SOC_EXTRAM_HIGH,                                SOC_MEMORY_TYPE_SPIRAM,     0}, //PSRAM, if available
+#endif
+    // base 192k is always avaible, even if we config l2 cache size to 512k
+    { 0x4ff00000,           0x30000,                                   SOC_MEMORY_TYPE_DEFAULT,     0x4ff00000},
+    // 64k for rom startup stack
+    { 0x4ff30000,           0x10000,                                   SOC_MEMORY_TYPE_STACK_DRAM,     0x4ff30000},
+#if CONFIG_ESP32P4_L2_CACHE_256KB // 768-256 = 512k avaible for l2 memory, add extra 256k
+    { 0x4ff40000,           0x40000,                                   SOC_MEMORY_TYPE_DEFAULT,     0x4ff40000},
+#endif
+#if CONFIG_ESP32P4_L2_CACHE_128KB // 768 - 128 = 640k avaible for l2 memory, add extra 384k
+    { 0x4ff40000,           0x60000,                                   SOC_MEMORY_TYPE_DEFAULT,     0x4ff40000},
+#endif
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+    { 0x50108000,           0x8000,                                    SOC_MEMORY_TYPE_RTCRAM,      0},          //LPRAM
+#endif
+    { 0x30100000,           0x2000,                                    SOC_MEMORY_TYPE_TCM,     0},
+};
+
+const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
+
+
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+extern int _tcm_text_start, _tcm_data_end;
+
+/**
+ * Reserved memory regions.
+ * These are removed from the soc_memory_regions array when heaps are created.
+ *
+ */
+
+// Static data region. DRAM used by data+bss and possibly rodata
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
+
+// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
+
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_tcm_text_start, (intptr_t)&_tcm_data_end, tcm_code_data);
+
+#ifdef CONFIG_SPIRAM
+SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region);
+#endif
+
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+// TODO: IDF-6019 check reserved lp mem region
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
+#endif

components/heap/port/memory_layout_utils.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,8 @@
 #include "esp32c6/rom/rom_layout.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rom_layout.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rom_layout.h"
 #endif
 #endif // ESP_ROM_HAS_LAYOUT_TABLE
 
@@ -69,7 +71,12 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
     /* Get the ROM layout to find which part of DRAM is reserved */
     const ets_rom_layout_t *layout = ets_rom_layout_p;
     reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7921
+    reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH;
+#else
     reserved[0].end = SOC_DIRAM_DRAM_HIGH;
+#endif
 
     memcpy(reserved + 1, &soc_reserved_memory_region_start, (count - 1) * sizeof(soc_reserved_region_t));
 #else

components/idf_test/include/esp32p4/idf_performance_target.h

@@ -0,0 +1,5 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

components/newlib/newlib_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,8 @@
 #include "esp32c6/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/libc_stubs.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/libc_stubs.h"
 #endif
 
 static struct _reent s_reent;
@@ -112,7 +114,7 @@ static struct syscall_stub_table s_stub_table = {
     ._scanf_float = NULL,
 #endif
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \
-    || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+    || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
     /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM
        assertion failures (as function names & source file names will be similar)
     */
@@ -135,8 +137,7 @@ void esp_newlib_init(void)
     syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table;
 #elif CONFIG_IDF_TARGET_ESP32S2
     syscall_table_ptr_pro = &s_stub_table;
-#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \
-    || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#else
     syscall_table_ptr = &s_stub_table;
 #endif
 

components/newlib/port/esp_time_impl.c

@@ -42,6 +42,9 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rtc.h"
+#include "esp32p4/rtc.h"
 #endif
 
 

components/newlib/test_apps/newlib/main/test_time.c

@@ -41,6 +41,8 @@
 #include "esp32c6/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rtc.h"
 #endif
 
 #if portNUM_PROCESSORS == 2

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -235,6 +235,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
     int
     default 12
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y

components/soc/esp32/include/soc/soc_caps.h

@@ -134,6 +134,9 @@
 #define SOC_ADC_RTC_MIN_BITWIDTH                (9)
 #define SOC_ADC_RTC_MAX_BITWIDTH                (12)
 
+/*!< ADC power control is shared by PWDET */
+#define SOC_ADC_SHARED_POWER                    1
+
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #if SOC_CAPS_ECO_VER >= 100
 #define SOC_BROWNOUT_RESET_SUPPORTED 1

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -179,6 +179,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_BROWNOUT_RESET_SUPPORTED
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -84,6 +84,9 @@
 #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
 #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
 
+/*!< ADC power control is shared by PWDET, TempSensor */
+#define SOC_ADC_SHARED_POWER                    1
+
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -259,6 +259,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -112,6 +112,9 @@
 #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
 #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
 
+/*!< ADC power control is shared by PWDET, TempSensor */
+#define SOC_ADC_SHARED_POWER                    1
+
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (1)
 

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -315,6 +315,10 @@ config SOC_ADC_TEMPERATURE_SHARE_INTR
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default n

components/soc/esp32c6/include/soc/soc_caps.h

@@ -125,6 +125,9 @@
 /*!< Interrupt */
 #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
 
+/*!< ADC power control is shared by PWDET */
+#define SOC_ADC_SHARED_POWER                    1
+
 // ESP32C6-TODO: Copy from esp32c6, need check
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (0)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -295,6 +295,10 @@ config SOC_ADC_TEMPERATURE_SHARE_INTR
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default n

components/soc/esp32h2/include/soc/soc_caps.h

@@ -121,6 +121,9 @@
 /*!< Interrupt */
 #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
 
+/*!< ADC power control is shared by PWDET */
+#define SOC_ADC_SHARED_POWER                    1
+
 // ESP32H2-TODO: Copy from esp32c6, need check
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (0)

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -994,3 +994,7 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
 config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
     bool
     default y
+
+config SOC_MEM_TCM_SUPPORTED
+    bool
+    default y

components/soc/esp32p4/include/soc/efuse_defs.h

@@ -0,0 +1,17 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_READ_OP_CODE 0x5aa5
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/efuse_reg.h

@@ -7,13 +7,11 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
+#include "efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define EFUSE_READ_OP_CODE 0x5aa5
-#define EFUSE_WRITE_OP_CODE 0x5a5a
-
 /** EFUSE_PGM_DATA0_REG register
  *  Register 0 that stores data to be programmed.
  */
@@ -200,6 +198,13 @@ extern "C" {
 #define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
 #define EFUSE_POWERGLITCH_EN_V  0x00000001U
 #define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
  *  Represents whether the function that forces chip into download mode is disabled or
  *  enabled. 1: disabled. 0: enabled.
@@ -256,6 +261,20 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
+ *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  23
 /** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
  *  TBD
  */
@@ -322,6 +341,13 @@ extern "C" {
 #define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
 #define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
 #define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
  *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
  *  selected. 0: not selected.
@@ -446,6 +472,13 @@ extern "C" {
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    (BIT(22))
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_118_S  22
 /** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
  *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
  */
@@ -585,34 +618,34 @@ extern "C" {
  *  BLOCK0 data register 5.
  */
 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
  *  TBD
  */
-#define EFUSE_0PXA_TIEH_SEL_0    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_M  (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S)
-#define EFUSE_0PXA_TIEH_SEL_0_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_S  0
-/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
+#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_S  0
+/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_1    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_M  (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S)
-#define EFUSE_0PXA_TIEH_SEL_1_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_S  2
-/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
+#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_S  2
+/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_2    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_M  (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S)
-#define EFUSE_0PXA_TIEH_SEL_2_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_S  4
-/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
+#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_S  4
+/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_3    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_M  (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S)
-#define EFUSE_0PXA_TIEH_SEL_3_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_S  6
+#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
+#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_S  6
 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
  *  TBD.
  */
@@ -620,6 +653,29 @@ extern "C" {
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step
+ *  of 80 mV.
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
+ *  Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step
+ *  of 80 mV.
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  14
+/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_176    0x00000003U
+#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
+#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_176_S  16
 /** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
  *  HP system power source select. 0:LDO. 1: DCDC.
  */
@@ -648,6 +704,13 @@ extern "C" {
 #define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
 #define EFUSE_DIS_SWD_V  0x00000001U
 #define EFUSE_DIS_SWD_S  21
+/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_182    0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
+#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_S  22
 
 /** EFUSE_RD_MAC_SYS_0_REG register
  *  BLOCK1 data register $n.
@@ -1645,6 +1708,13 @@ extern "C" {
 #define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
 #define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
 #define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
  *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
  */
@@ -1694,6 +1764,20 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFH.
+ */
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFH.
+ */
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
 /** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
  *  Indicates a programming error of USB_PHY_SEL.
  */
@@ -2001,34 +2085,34 @@ extern "C" {
  *  Programming error record register 4 of BLOCK0.
  */
 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_0.
  */
-#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_S  0
-/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
+/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_1.
  */
-#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
-/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
+/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_2.
  */
-#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
-/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
+/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_3.
  */
-#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
+#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
 /** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
  *  TBD.
  */
@@ -2302,6 +2386,48 @@ extern "C" {
 #define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
 #define EFUSE_STATE_V  0x0000000FU
 #define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
  *  Indicates the number of block valid bit.
  */

components/soc/esp32p4/include/soc/efuse_struct.h

@@ -197,7 +197,10 @@ typedef union {
          *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
          */
         uint32_t powerglitch_en:1;
-        uint32_t reserved_11:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
         /** dis_force_download : RO; bitpos: [12]; default: 0;
          *  Represents whether the function that forces chip into download mode is disabled or
          *  enabled. 1: disabled. 0: enabled.
@@ -233,7 +236,14 @@ typedef union {
          *  mode). 1: disabled. 0: enabled.
          */
         uint32_t dis_download_manual_encrypt:1;
-        uint32_t reserved_21:4;
+        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
+         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
+         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_otg11_drefh:2;
         /** usb_phy_sel : RO; bitpos: [25]; default: 0;
          *  TBD
          */
@@ -280,7 +290,10 @@ typedef union {
          *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
          */
         uint32_t xts_key_length_256:1;
-        uint32_t reserved_15:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
         /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
          *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
          *  selected. 0: not selected.
@@ -361,7 +374,10 @@ typedef union {
          *  enabled. 0: disabled.
          */
         uint32_t secure_boot_aggressive_revoke:1;
-        uint32_t reserved_22:1;
+        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:1;
         /** flash_type : RO; bitpos: [23]; default: 0;
          *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
          */
@@ -458,27 +474,40 @@ typedef union {
  */
 typedef union {
     struct {
-        /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
          *  TBD
          */
-        uint32_t rd_0pxa_tieh_sel_0:2;
-        /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_1:2;
-        /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+        uint32_t pxa0_tieh_sel_1:2;
+        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_2:2;
-        /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+        uint32_t pxa0_tieh_sel_2:2;
+        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_3:2;
+        uint32_t pxa0_tieh_sel_3:2;
         /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
          *  TBD.
          */
         uint32_t km_disable_deploy_mode:4;
-        uint32_t reserved_12:6;
+        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
+         *  Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
+         *  Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_176:2;
         /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
          *  HP system power source select. 0:LDO. 1: DCDC.
          */
@@ -495,7 +524,10 @@ typedef union {
          *  Set this bit to disable super-watchdog.
          */
         uint32_t dis_swd:1;
-        uint32_t reserved_22:10;
+        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_182:10;
     };
     uint32_t val;
 } efuse_rd_repeat_data4_reg_t;
@@ -1551,7 +1583,10 @@ typedef union {
          *  Indicates a programming error of POWERGLITCH_EN.
          */
         uint32_t powerglitch_en_err:1;
-        uint32_t reserved_11:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
         /** dis_force_download_err : RO; bitpos: [12]; default: 0;
          *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
          */
@@ -1580,7 +1615,14 @@ typedef union {
          *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
          */
         uint32_t dis_download_manual_encrypt_err:1;
-        uint32_t reserved_21:4;
+        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFH.
+         */
+        uint32_t usb_device_drefh_err:2;
+        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFH.
+         */
+        uint32_t usb_otg11_drefh_err:2;
         /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
          *  Indicates a programming error of USB_PHY_SEL.
          */
@@ -1783,22 +1825,22 @@ typedef union {
  */
 typedef union {
     struct {
-        /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_0.
          */
-        uint32_t rd_0pxa_tieh_sel_0_err:2;
-        /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_1.
          */
-        uint32_t rd_0pxa_tieh_sel_1_err:2;
-        /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+        uint32_t pxa0_tieh_sel_1_err:2;
+        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_2.
          */
-        uint32_t rd_0pxa_tieh_sel_2_err:2;
-        /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+        uint32_t pxa0_tieh_sel_2_err:2;
+        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_3.
          */
-        uint32_t rd_0pxa_tieh_sel_3_err:2;
+        uint32_t pxa0_tieh_sel_3_err:2;
         /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
          *  TBD.
          */
@@ -1996,7 +2038,30 @@ typedef union {
          *  Indicates the state of the eFuse state machine.
          */
         uint32_t state:4;
-        uint32_t reserved_4:6;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
         /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
          *  Indicates the number of block valid bit.
          */

components/soc/esp32p4/include/soc/ext_mem_defs.h

@@ -25,7 +25,9 @@ extern "C" {
 
 #define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
 #define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
-#define DRAM0_CACHE_OPERATION_HIGH               0x44000000
+
+#define DRAM_FLASH_ADDRESS_LOW                   DRAM0_CACHE_ADDRESS_LOW
+#define DRAM_FLASH_ADDRESS_HIGH                  0x44000000
 
 #define SINGLE_BANK_CACHE_ADDRESS_LOW                0x40000000
 #define SINGLE_BANK_CACHE_ADDRESS_HIGH               0x44000000

components/soc/esp32p4/include/soc/gpio_sig_map.h

@@ -485,3 +485,4 @@
 #define SIG_IN_FUNC254_IDX                                 254
 #define SIG_IN_FUNC255_IDX                                 255
 #define SIG_IN_FUNC255_IDX                                 255
+#define SIG_GPIO_OUT_IDX                                   256

components/soc/esp32p4/include/soc/lp_wdt_reg.h

@@ -11,6 +11,10 @@
 extern "C" {
 #endif
 
+/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
+//TODO: IDF-7539
+#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
+
 /** LP_WDT_CONFIG0_REG register
  *  need_des
  */

components/soc/esp32p4/include/soc/mcpwm_struct.h

@@ -1881,7 +1881,7 @@ typedef struct {
     volatile mcpwm_op_tstmp_reg_t timestamp[2];
 } mcpwm_operator_tstmp_reg_t;
 
-typedef struct {
+typedef struct mcpwm_dev_t {
     volatile mcpwm_clk_cfg_reg_t clk_cfg;
     volatile mcpwm_timer_regs_t timer[3];
     volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;

components/soc/esp32p4/include/soc/soc.h

@@ -160,8 +160,8 @@
 
 #define SOC_SINGLE_BANK_LOW  0x40000000
 #define SOC_SINGLE_BANK_HIGH 0x44000000
-#define SOC_DUAL_BANK_LOW    0x48000000
-#define SOC_DUAL_BANK_HIGH   0x4c000000
+#define SOC_EXTRAM_LOW    0x48000000
+#define SOC_EXTRAM_HIGH   0x4c000000
 #define SOC_EXT_DBRAM_DATA_LOW 0x4a000000
 #define SOC_EXT_DBRAM_DATA_HIGH 0x4c000000
 
@@ -210,7 +210,7 @@
 #define SOC_MEM_INTERNAL_LOW1       0x4ff00000
 #define SOC_MEM_INTERNAL_HIGH1      0x4ffc0000
 
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_DUAL_BANK_HIGH - SOC_DUAL_BANK_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_HIGH - SOC_EXTRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
 
 #define CPU_PERIPH_LOW     0x3ff00000
 #define CPU_PERIPH_HIGH    0x3ff20000

components/soc/esp32p4/include/soc/soc_caps.h

@@ -485,3 +485,6 @@
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)
+
+/*-------------------------- Memory CAPS --------------------------*/
+#define SOC_MEM_TCM_SUPPORTED    (1)

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -275,6 +275,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_BROWNOUT_RESET_SUPPORTED
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -122,6 +122,9 @@
 #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
 #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
 
+/*!< ADC power control is shared by PWDET, TempSensor */
+#define SOC_ADC_SHARED_POWER                    1
+
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -315,6 +315,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -115,6 +115,9 @@
 #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
 #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
 
+/*!< ADC power control is shared by PWDET, TempSensor */
+#define SOC_ADC_SHARED_POWER                    1
+
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (1)
 

components/spi_flash/cache_utils.c

@@ -487,7 +487,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
     int i;
     bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
     uint32_t drom0_in_icache = 1;//always 1 in esp32s2
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
     drom0_in_icache = 0;
 #endif
 
@@ -919,7 +919,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
 
 #if CONFIG_IDF_TARGET_ESP32P4
 //TODO: IDF-5670
-TCM_IRAM_ATTR void esp_config_llc_mode(void)
+void esp_config_l2_cache_mode(void)
 {
     cache_size_t cache_size;
     cache_line_size_t cache_line_size;

components/spi_flash/esp32p4/Kconfig.soc_caps.in

@@ -0,0 +1,8 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config SPI_FLASH_VENDOR_XMC_SUPPORTED
+    bool
+    default y

components/spi_flash/esp32p4/flash_vendor_caps.h

@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#define SPI_FLASH_VENDOR_XMC_SUPPORTED       (1)

components/spi_flash/flash_mmap.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +27,9 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp_private/esp_cache_esp32_private.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+//TODO: IDF-7509
+#include "esp32p4/rom/cache.h"
 #endif
 
 #include "esp_private/cache_utils.h"
@@ -79,7 +82,12 @@ esp_err_t spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_memory_t m
     } else {
         caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_8BIT;
     }
+#if CONFIG_IDF_TARGET_ESP32P4
+    //TODO: IDF-7509
+    ret = esp_mmu_map(src_addr, size, MMU_TARGET_FLASH0, MMU_MEM_CAP_FLASH | caps, ESP_MMU_MMAP_FLAG_PADDR_SHARED, &ptr);
+#else
     ret = esp_mmu_map(src_addr, size, MMU_TARGET_FLASH0, caps, ESP_MMU_MMAP_FLAG_PADDR_SHARED, &ptr);
+#endif
     if (ret == ESP_OK) {
         vaddr_list[0] = (uint32_t)ptr;
         block->list_num = 1;
@@ -371,7 +379,12 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
             return true;
 #else // CONFIG_IDF_TARGET_ESP32
             if (vaddr != NULL) {
+#if CONFIG_IDF_TARGET_ESP32P4
+                //TODO: IDF-7509
+                Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE, (uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE);
+#else
                 cache_hal_invalidate_addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE);
+#endif
                 ret = true;
             }
 #endif // CONFIG_IDF_TARGET_ESP32

components/spi_flash/spi_flash_os_func_noos.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,9 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/ets_sys.h"
 #include "esp32h2/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/ets_sys.h"
+#include "esp32p4/rom/cache.h"
 #endif
 
 #include "esp_attr.h"
@@ -40,7 +43,7 @@ typedef struct {
 } spi_noos_arg_t;
 
 static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
 typedef struct {
     uint32_t icache_autoload;
 } spi_noos_arg_t;
@@ -60,6 +63,9 @@ static IRAM_ATTR esp_err_t start(void *arg)
 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
     spi_noos_arg_t *spi_arg = arg;
     spi_arg->icache_autoload = Cache_Suspend_ICache();
+#elif CONFIG_IDF_TARGET_ESP32P4
+    spi_noos_arg_t *spi_arg = arg;
+    spi_arg->icache_autoload = Cache_Suspend_L2_Cache();
 #endif
     return ESP_OK;
 }
@@ -78,6 +84,10 @@ static IRAM_ATTR esp_err_t end(void *arg)
     spi_noos_arg_t *spi_arg = arg;
     Cache_Invalidate_ICache_All();
     Cache_Resume_ICache(spi_arg->icache_autoload);
+#elif CONFIG_IDF_TARGET_ESP32P4
+    spi_noos_arg_t *spi_arg = arg;
+    Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
+    Cache_Resume_L2_Cache(spi_arg->icache_autoload);
 #endif
     return ESP_OK;
 }

components/spi_flash/test_apps/mspi_test/main/test_cache_disabled.c

@@ -91,7 +91,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
 
 #if CONFIG_IDF_TARGET_ESP32
 #define CACHE_ERROR_REASON "Cache disabled,SW_RESET"
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32P4
 #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST"