gdma: support esp32h2

components/esp_hw_support/CMakeLists.txt

@@ -47,7 +47,7 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "dma/async_memcpy_impl_cp_dma.c")
     endif()
 
-    if(CONFIG_SOC_GDMA_SUPPORTED OR CONFIG_SOC_CP_DMA_SUPPORTED)
+    if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED)
         list(APPEND srcs "dma/esp_async_memcpy.c")
     endif()
 

components/esp_hw_support/dma/async_memcpy_impl_gdma.c

@@ -15,6 +15,9 @@
 #include "esp_attr.h"
 #include "esp_err.h"
 #include "esp_async_memcpy_impl.h"
+#if SOC_APM_SUPPORTED
+#include "hal/apm_ll.h"
+#endif
 
 IRAM_ATTR static bool async_memcpy_impl_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {
@@ -71,6 +74,14 @@ esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl)
     gdma_apply_strategy(impl->tx_channel, &strategy_config);
     gdma_apply_strategy(impl->rx_channel, &strategy_config);
 
+#if SOC_APM_SUPPORTED
+    // APM GDMA master for M2M should have the same offset of its GDMA trigger
+    ESP_STATIC_ASSERT((APM_LL_MASTER_GDMA_M2M - 16) == SOC_GDMA_TRIG_PERIPH_M2M0);
+    // APM strategy: trusted mode
+    // TODO: IDF-5354 GDMA for M2M usage only need read and write permissions, we should disable the execute permission by the APM controller
+    apm_ll_set_master_secure_mode(APM_LL_MASTER_GDMA_M2M, APM_LL_SECURE_MODE_TEE);
+#endif // SOC_APM_SUPPORTED
+
     gdma_rx_event_callbacks_t cbs = {
         .on_recv_eof = async_memcpy_impl_rx_eof_callback
     };

components/hal/esp32c6/include/hal/gdma_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/gdma_struct.h"
 #include "soc/gdma_reg.h"
 #include "soc/soc_etm_source.h"
+#include "soc/gdma_channel.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -89,8 +90,8 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo
     dev->channel[channel].in.in_conf0.mem_trans_en = enable;
     if (enable) {
         // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a dummy value
-        dev->channel[channel].in.in_peri_sel.peri_in_sel = 1;
-        dev->channel[channel].out.out_peri_sel.peri_out_sel = 1;
+        dev->channel[channel].in.in_peri_sel.peri_in_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
+        dev->channel[channel].out.out_peri_sel.peri_out_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
     }
 }
 

components/hal/esp32h2/include/hal/gdma_ll.h

@@ -0,0 +1,535 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h> /* Required for NULL constant */
+#include <stdint.h>
+#include <stdbool.h>
+#include "hal/gdma_types.h"
+#include "soc/gdma_struct.h"
+#include "soc/gdma_reg.h"
+#include "soc/soc_etm_source.h"
+#include "soc/gdma_channel.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
+
+#define GDMA_LL_RX_EVENT_MASK       (0x7F)
+#define GDMA_LL_TX_EVENT_MASK       (0x3F)
+
+#define GDMA_LL_EVENT_TX_FIFO_UDF   (1<<5)
+#define GDMA_LL_EVENT_TX_FIFO_OVF   (1<<4)
+#define GDMA_LL_EVENT_RX_FIFO_UDF   (1<<6)
+#define GDMA_LL_EVENT_RX_FIFO_OVF   (1<<5)
+#define GDMA_LL_EVENT_TX_TOTAL_EOF  (1<<3)
+#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
+#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
+#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
+#define GDMA_LL_EVENT_TX_EOF        (1<<1)
+#define GDMA_LL_EVENT_TX_DONE       (1<<0)
+#define GDMA_LL_EVENT_RX_ERR_EOF    (1<<2)
+#define GDMA_LL_EVENT_RX_SUC_EOF    (1<<1)
+#define GDMA_LL_EVENT_RX_DONE       (1<<0)
+
+#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                                     \
+    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \
+                                          },                                               \
+                                          {                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \
+                                          },                                               \
+                                          {                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \
+                                          }}}[group][chan][event]
+
+#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event)                                        \
+    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \
+                                          },                                                  \
+                                          {                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \
+                                          },                                                  \
+                                          {                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \
+                                          }}}[group][chan][event]
+
+#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task)                                          \
+    (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \
+                                         },                                                   \
+                                         {                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \
+                                         },                                                   \
+                                         {                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \
+                                         }}}[group][chan][task]
+
+#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task)                                         \
+    (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \
+                                         },                                                  \
+                                         {                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \
+                                         },                                                  \
+                                         {                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \
+                                         }}}[group][chan][task]
+
+///////////////////////////////////// Common /////////////////////////////////////////
+/**
+ * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default
+ */
+static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.mem_trans_en = enable;
+    if (enable) {
+        // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a dummy value
+        dev->channel[channel].in.in_peri_sel.peri_in_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
+        dev->channel[channel].out.out_peri_sel.peri_out_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
+    }
+}
+
+/**
+ * @brief Enable DMA clock gating
+ */
+static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
+{
+    dev->misc_conf.clk_en = enable;
+}
+
+///////////////////////////////////// RX /////////////////////////////////////////
+/**
+ * @brief Get DMA RX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->in_intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
+}
+
+/**
+ * @brief Enable DMA RX channel interrupt
+ */
+static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->in_intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
+    } else {
+        dev->in_intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);
+    }
+}
+
+/**
+ * @brief Clear DMA RX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->in_intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);
+}
+
+/**
+ * @brief Get DMA RX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->in_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf1.in_check_owner = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading data, disabled by default
+ */
+static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_data_burst_en = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.indscr_burst_en = enable;
+}
+
+/**
+ * @brief Reset DMA RX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_conf0.in_rst = 1;
+    dev->channel[channel].in.in_conf0.in_rst = 0;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in RX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.infifo_cnt;
+}
+
+/**
+ * @brief Pop data from DMA RX FIFO
+ */
+static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_pop.infifo_pop = 1;
+    return dev->channel[channel].in.in_pop.infifo_rdata;
+}
+
+/**
+ * @brief Set the descriptor link base address for RX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].in.in_link.inlink_addr = addr;
+}
+
+/**
+ * @brief Start dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_start = 1;
+}
+
+/**
+ * @brief Stop dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_stop = 1;
+}
+
+/**
+ * @brief Restart a new inlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_restart = 1;
+}
+
+/**
+ * @brief Enable DMA RX to return the address of current descriptor when receives error
+ */
+static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_link.inlink_auto_ret = enable;
+}
+
+/**
+ * @brief Check if DMA RX FSM is in IDLE state
+ */
+static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_link.inlink_park;
+}
+
+/**
+ * @brief Get RX success EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_suc_eof_des_addr.val;
+}
+
+/**
+ * @brief Get RX error EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_err_eof_des_addr.val;
+}
+
+/**
+ * @brief Get current RX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA RX channel
+ */
+static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].in.in_pri.rx_pri = prio;
+}
+
+/**
+ * @brief Connect DMA RX channel to a given peripheral
+ */
+static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel = periph_id;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for RX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_etm_en = enable;
+}
+
+///////////////////////////////////// TX /////////////////////////////////////////
+/**
+ * @brief Get DMA TX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->out_intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
+}
+
+/**
+ * @brief Enable DMA TX channel interrupt
+ */
+static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->out_intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);
+    } else {
+        dev->out_intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);
+    }
+}
+
+/**
+ * @brief Clear DMA TX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->out_intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);
+}
+
+/**
+ * @brief Get DMA TX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->out_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf1.out_check_owner = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst sending data, disabled by default
+ */
+static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_data_burst_en = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.outdscr_burst_en = enable;
+}
+
+/**
+ * @brief Set TX channel EOF mode
+ */
+static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
+{
+    dev->channel[channel].out.out_conf0.out_eof_mode = mode;
+}
+
+/**
+ * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
+ */
+static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_auto_wrback = enable;
+}
+
+/**
+ * @brief Reset DMA TX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_conf0.out_rst = 1;
+    dev->channel[channel].out.out_conf0.out_rst = 0;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in TX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.outfifo_cnt;
+}
+
+/**
+ * @brief Push data into DMA TX FIFO
+ */
+static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
+{
+    dev->channel[channel].out.out_push.outfifo_wdata = data;
+    dev->channel[channel].out.out_push.outfifo_push = 1;
+}
+
+/**
+ * @brief Set the descriptor link base address for TX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].out.out_link.outlink_addr = addr;
+}
+
+/**
+ * @brief Start dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_start = 1;
+}
+
+/**
+ * @brief Stop dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_stop = 1;
+}
+
+/**
+ * @brief Restart a new outlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_restart = 1;
+}
+
+/**
+ * @brief Check if DMA TX FSM is in IDLE state
+ */
+static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_link.outlink_park;
+}
+
+/**
+ * @brief Get TX EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_eof_des_addr.val;
+}
+
+/**
+ * @brief Get current TX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA TX channel
+ */
+static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].out.out_pri.tx_pri = prio;
+}
+
+/**
+ * @brief Connect DMA TX channel to a given peripheral
+ */
+static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
+{
+    dev->channel[channel].out.out_peri_sel.peri_out_sel = periph_id;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for TX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_etm_en = enable;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c6/include/soc/gdma_channel.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,9 +7,9 @@
 #pragma once
 
 // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
-#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
 #define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
-#define SOC_GDMA_TRIG_PERIPH_UART0   (2)
+#define SOC_GDMA_TRIG_PERIPH_M2M0    (1)
+#define SOC_GDMA_TRIG_PERIPH_UHCI0   (2)
 #define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
 #define SOC_GDMA_TRIG_PERIPH_AES0    (6)
 #define SOC_GDMA_TRIG_PERIPH_SHA0    (7)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -3,6 +3,14 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_ASYNC_MEMCPY_SUPPORTED
+    bool
+    default y
+
 config SOC_IEEE802154_BLE_ONLY
     bool
     default y
@@ -187,6 +195,10 @@ config SOC_GDMA_PAIRS_PER_GROUP
     int
     default 3
 
+config SOC_GDMA_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1

components/soc/esp32h2/include/soc/gdma_channel.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,10 +7,11 @@
 #pragma once
 
 // The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
-#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
 #define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
-#define SOC_GDMA_TRIG_PERIPH_UART0   (2)
+#define SOC_GDMA_TRIG_PERIPH_M2M0    (1)
+#define SOC_GDMA_TRIG_PERIPH_UHCI0   (2)
 #define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
 #define SOC_GDMA_TRIG_PERIPH_AES0    (6)
 #define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
 #define SOC_GDMA_TRIG_PERIPH_ADC0    (8)
+#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)

components/soc/esp32h2/include/soc/soc_caps.h

@@ -27,14 +27,14 @@
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1 // TODO: IDF-6214
 // #define SOC_DEDICATED_GPIO_SUPPORTED    1 // TODO: IDF-6241
-// #define SOC_GDMA_SUPPORTED              1 // TODO: IDF-6222
+#define SOC_GDMA_SUPPORTED              1
+#define SOC_ASYNC_MEMCPY_SUPPORTED      1
 // #define SOC_PCNT_SUPPORTED              1 // TODO: IDF-6221
 // #define SOC_MCPWM_SUPPORTED             1 // TODO: IDF-6237
 // #define SOC_TWAI_SUPPORTED              1 // TODO: IDF-6217
 // #define SOC_BT_SUPPORTED                1 // TODO: IDF-6416
 // #define SOC_IEEE802154_SUPPORTED        1 // TODO: IDF-6577
 #define SOC_IEEE802154_BLE_ONLY            1
-// #define SOC_ASYNC_MEMCPY_SUPPORTED      1 // TODO: IDF-6238
 // #define SOC_USB_SERIAL_JTAG_SUPPORTED   1 // TODO: IDF-6239
 // #define SOC_TEMP_SENSOR_SUPPORTED       1 // TODO: IDF-6229
 // #define SOC_SUPPORTS_SECURE_DL_MODE     1 // TODO: IDF-6281
@@ -137,10 +137,10 @@
     See TRM DS chapter for more details */
 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
 
-// TODO: IDF-6222 (Copy from esp32c6, need check)
 /*-------------------------- GDMA CAPS -------------------------------------*/
 #define SOC_GDMA_GROUPS                 (1U) // Number of GDMA groups
 #define SOC_GDMA_PAIRS_PER_GROUP        (3)  // Number of GDMA pairs in each group
+#define SOC_GDMA_SUPPORT_ETM            (1)  // Support ETM submodule
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C6 has 1 GPIO peripheral