ESP8684: add soc, riscv, newlib support

components/newlib/locks.c

@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include <sys/lock.h>
 #include <stdlib.h>
@@ -252,7 +244,7 @@ static StaticSemaphore_t s_common_mutex;
 static StaticSemaphore_t s_common_recursive_mutex;
 
 
-#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
+#if ESP_ROM_HAS_RETARGETABLE_LOCKING
 /* C3 and S3 ROMs are built without Newlib static lock symbols exported, and
  * with an extra level of _LOCK_T indirection in mind.
  * The following is a workaround for this:
@@ -267,7 +259,7 @@ static StaticSemaphore_t s_common_recursive_mutex;
  */
 
 #define ROM_NEEDS_MUTEX_OVERRIDE
-#endif // defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
+#endif // ESP_ROM_HAS_RETARGETABLE_LOCKING
 
 #ifdef ROM_NEEDS_MUTEX_OVERRIDE
 #define ROM_MUTEX_MAGIC  0xbb10c433
@@ -393,7 +385,7 @@ void esp_newlib_locks_init(void)
     __sinit_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
     extern _lock_t __sfp_recursive_mutex;
     __sfp_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
-#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
+#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP8684)
     /* Newlib 3.3.0 is used in ROM, built with _RETARGETABLE_LOCKING.
      * No access to lock variables for the purpose of ECO forward compatibility,
      * however we have an API to initialize lock variables used in the ROM.

components/newlib/newlib_init.c

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "sdkconfig.h"
 #include <string.h>
@@ -39,6 +31,8 @@
 #include "esp32c3/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/libc_stubs.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/libc_stubs.h"
 #endif
 
 static struct _reent s_reent;
@@ -115,7 +109,7 @@ static struct syscall_stub_table s_stub_table = {
     ._printf_float = NULL,
     ._scanf_float = NULL,
 #endif
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
     /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM
        assertion failures (as function names & source file names will be similar)
     */
@@ -138,7 +132,7 @@ void esp_newlib_init(void)
     syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table;
 #elif CONFIG_IDF_TARGET_ESP32S2
     syscall_table_ptr_pro = &s_stub_table;
-#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
     syscall_table_ptr = &s_stub_table;
 #endif
 

components/newlib/port/esp_time_impl.c

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #include <stdint.h>
 #include <time.h>
 #include <sys/time.h>
@@ -48,6 +40,10 @@
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/clk.h"
 #include "esp32h2/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/rtc.h"
+#include "esp_private/esp_clk.h"
+#include "esp8684/rtc.h"
 #endif
 
 

components/newlib/test/test_newlib.c

@@ -141,7 +141,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]")
 #if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM)
     TEST_ASSERT(fn_in_rom(atoi));
     TEST_ASSERT(fn_in_rom(strtol));
-#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
+#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP8684)
     /* S3 and C3 always use these from ROM */
     TEST_ASSERT(fn_in_rom(atoi));
     TEST_ASSERT(fn_in_rom(strtol));

components/newlib/test/test_time.c

@@ -42,6 +42,9 @@
 #include "esp32h2/clk.h"
 #include "esp32h2/rtc.h"
 #define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp_private/esp_clk.h"
+#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP8684_DEFAULT_CPU_FREQ_MHZ
 #endif
 
 #if portNUM_PROCESSORS == 2

components/riscv/CMakeLists.txt

@@ -1,7 +1,7 @@
 idf_build_get_property(target IDF_TARGET)
 
 # should test arch here not target: IDF-1754
-if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2")
+if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2" AND NOT "${target}" STREQUAL "esp8684")
     return()
 endif()
 

components/riscv/include/riscv/csr.h

@@ -81,6 +81,11 @@ extern "C" {
     RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
     } while(0)
 
+/*Only set PMPCFG entries*/
+#define PMP_ENTRY_CFG_SET(ENTRY, CFG) do {\
+    RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
+    } while(0)
+
 /********************************************************
    Trigger Module register fields (Debug specification)
  ********************************************************/

components/soc/esp32/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -63,9 +63,11 @@
 #define SOC_EMAC_SUPPORTED          1
 #define SOC_CPU_CORES_NUM           2
 #define SOC_ULP_SUPPORTED           1
-#define SOC_RTC_SLOW_MEM_SUPPORTED  1
 #define SOC_CCOMP_TIMER_SUPPORTED   1
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
+#define SOC_RTC_FAST_MEM_SUPPORTED        1
+#define SOC_RTC_SLOW_MEM_SUPPORTED        1
+
 
 /*-------------------------- ADC CAPS ----------------------------------------*/
 /**

components/soc/esp32c3/include/soc/cache_memory.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _CACHE_MEMORY_H_
 #define _CACHE_MEMORY_H_
 

components/soc/esp32c3/include/soc/soc_caps.h

@@ -22,6 +22,9 @@
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
 #define SOC_ICACHE_ACCESS_RODATA_SUPPORTED  1
+#define SOC_RTC_FAST_MEM_SUPPORTED        1
+#define SOC_RTC_SLOW_MEM_SUPPORTED        0
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY               1
 
 /*-------------------------- AES CAPS -----------------------------------------*/
 #define SOC_AES_SUPPORT_DMA     (1)

components/soc/esp32h2/include/soc/cache_memory.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _CACHE_MEMORY_H_
 #define _CACHE_MEMORY_H_
 

components/soc/esp32h2/include/soc/soc_caps.h

@@ -19,6 +19,9 @@
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
 #define SOC_ICACHE_ACCESS_RODATA_SUPPORTED  1
 #define SOC_TEMP_SENSOR_SUPPORTED           1
+#define SOC_RTC_FAST_MEM_SUPPORTED          1
+#define SOC_RTC_SLOW_MEM_SUPPORTED          0
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY                 1
 
 
 /*-------------------------- AES CAPS -----------------------------------------*/

components/soc/esp32s2/include/soc/cache_memory.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _CACHE_MEMORY_H_
 #define _CACHE_MEMORY_H_
 

components/soc/esp32s2/include/soc/soc_caps.h

@@ -39,7 +39,6 @@
 #define SOC_USB_OTG_SUPPORTED           1
 #define SOC_PCNT_SUPPORTED              1
 #define SOC_ULP_SUPPORTED               1
-#define SOC_RTC_SLOW_MEM_SUPPORTED      1
 #define SOC_CCOMP_TIMER_SUPPORTED       1
 #define SOC_DIG_SIGN_SUPPORTED          1
 #define SOC_HMAC_SUPPORTED              1
@@ -51,8 +50,12 @@
 #define SOC_CACHE_SUPPORT_WRAP              1
 #define SOC_FLASH_ENCRYPTION_XTS_AES        1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_256    1
+#define SOC_RTC_FAST_MEM_SUPPORTED      1
+#define SOC_RTC_SLOW_MEM_SUPPORTED      1
 #define SOC_PSRAM_DMA_CAPABLE               1
 #define SOC_XT_WDT_SUPPORTED                1
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY             1
+
 
 /*-------------------------- ADC CAPS ----------------------------------------*/
 /*!< SAR ADC Module*/

components/soc/esp32s3/include/soc/cache_memory.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 #ifdef __cplusplus

components/soc/esp32s3/include/soc/soc_caps.h

@@ -24,7 +24,6 @@
 #define SOC_BT_SUPPORTED                1
 #define SOC_USB_OTG_SUPPORTED           1
 #define SOC_USB_SERIAL_JTAG_SUPPORTED   1
-#define SOC_RTC_SLOW_MEM_SUPPORTED      1
 #define SOC_CCOMP_TIMER_SUPPORTED       1
 #define SOC_DIG_SIGN_SUPPORTED          1
 #define SOC_HMAC_SUPPORTED              1
@@ -34,7 +33,10 @@
 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
 #define SOC_SDMMC_HOST_SUPPORTED          1
 #define SOC_FLASH_ENCRYPTION_XTS_AES      1
+#define SOC_RTC_FAST_MEM_SUPPORTED        1
+#define SOC_RTC_SLOW_MEM_SUPPORTED        1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_256  1
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY             1
 #define SOC_PSRAM_DMA_CAPABLE             1
 #define SOC_XT_WDT_SUPPORTED              1
 

components/soc/esp8684/CMakeLists.txt

@@ -0,0 +1,15 @@
+set(srcs
+    "adc_periph.c"
+    "gdma_periph.c"
+    "gpio_periph.c"
+    "interrupts.c"
+    "spi_periph.c"
+    "ledc_periph.c"
+    "i2c_periph.c"
+    "uart_periph.c"
+    "timer_periph.c")
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . include)

components/soc/esp8684/adc_periph.c

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
+    },
+    /* ADC2 */
+    {
+        ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
+    }
+};

components/soc/esp8684/gdma_periph.c

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gdma_periph.h"
+
+const gdma_signal_conn_t gdma_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_GDMA_MODULE,
+            .pairs = {
+                [0]  = {
+                    .rx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
+                    .tx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
+                },
+            }
+        }
+    }
+};

components/soc/esp8684/gpio_periph.c

@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_periph.h"
+
+const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
+    IO_MUX_GPIO0_REG,
+    IO_MUX_GPIO1_REG,
+    IO_MUX_GPIO2_REG,
+    IO_MUX_GPIO3_REG,
+    IO_MUX_GPIO4_REG,
+    IO_MUX_GPIO5_REG,
+    IO_MUX_GPIO6_REG,
+    IO_MUX_GPIO7_REG,
+    IO_MUX_GPIO8_REG,
+    IO_MUX_GPIO9_REG,
+    IO_MUX_GPIO10_REG,
+    IO_MUX_GPIO11_REG,
+    IO_MUX_GPIO12_REG,
+    IO_MUX_GPIO13_REG,
+    IO_MUX_GPIO14_REG,
+    IO_MUX_GPIO15_REG,
+    IO_MUX_GPIO16_REG,
+    IO_MUX_GPIO17_REG,
+    IO_MUX_GPIO18_REG,
+    IO_MUX_GPIO19_REG,
+    IO_MUX_GPIO20_REG,
+};
+
+const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
+    BIT(0),     //GPIO0
+    BIT(1),     //GPIO1
+    BIT(2),     //GPIO2
+    BIT(3),     //GPIO3
+    BIT(4),     //GPIO4
+    BIT(5),     //GPIO5
+    BIT(5),     //GPIO6
+    BIT(6),     //GPIO7
+    BIT(3),     //GPIO8
+    BIT(4),     //GPIO9
+    BIT(0),     //GPIO10
+    BIT(15),    //GPIO11
+    BIT(10),    //GPIO12
+    BIT(12),    //GPIO13
+    BIT(8),     //GPIO14
+    BIT(7),     //GPIO15
+    BIT(9),     //GPIO16
+    BIT(11),    //GPIO17
+    BIT(1),     //GPIO18
+    BIT(2),     //GPIO19
+    BIT(13),    //GPIO20
+};

components/soc/esp8684/i2c_bbpll.h

@@ -0,0 +1,175 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file i2c_apll.h
+ * @brief Register definitions for digital PLL (BBPLL)
+ *
+ * This file lists register fields of BBPLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * rtc_clk_cpu_freq_set function in rtc_clk.c.
+ */
+
+#define I2C_BBPLL           0x66
+#define I2C_BBPLL_HOSTID    1
+
+#define I2C_BBPLL_IR_CAL_DELAY        0
+#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
+#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_BBPLL_IR_CAL_CK_DIV        0
+#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
+#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
+
+#define I2C_BBPLL_IR_CAL_EXT_CAP        1
+#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
+#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_BBPLL_IR_CAL_ENX_CAP        1
+#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
+#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
+
+#define I2C_BBPLL_IR_CAL_RSTB        1
+#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
+#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
+
+#define I2C_BBPLL_IR_CAL_START        1
+#define I2C_BBPLL_IR_CAL_START_MSB    6
+#define I2C_BBPLL_IR_CAL_START_LSB    6
+
+#define I2C_BBPLL_IR_CAL_UNSTOP        1
+#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
+#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
+
+#define I2C_BBPLL_OC_REF_DIV        2
+#define I2C_BBPLL_OC_REF_DIV_MSB    3
+#define I2C_BBPLL_OC_REF_DIV_LSB    0
+
+#define I2C_BBPLL_OC_DCHGP        2
+#define I2C_BBPLL_OC_DCHGP_MSB    6
+#define I2C_BBPLL_OC_DCHGP_LSB    4
+
+#define I2C_BBPLL_OC_ENB_FCAL        2
+#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
+#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_BBPLL_OC_DIV_7_0        3
+#define I2C_BBPLL_OC_DIV_7_0_MSB    7
+#define I2C_BBPLL_OC_DIV_7_0_LSB    0
+
+#define I2C_BBPLL_RSTB_DIV_ADC        4
+#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
+#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
+
+#define I2C_BBPLL_MODE_HF        4
+#define I2C_BBPLL_MODE_HF_MSB    1
+#define I2C_BBPLL_MODE_HF_LSB    1
+
+#define I2C_BBPLL_DIV_ADC        4
+#define I2C_BBPLL_DIV_ADC_MSB    3
+#define I2C_BBPLL_DIV_ADC_LSB    2
+
+#define I2C_BBPLL_DIV_DAC        4
+#define I2C_BBPLL_DIV_DAC_MSB    4
+#define I2C_BBPLL_DIV_DAC_LSB    4
+
+#define I2C_BBPLL_DIV_CPU        4
+#define I2C_BBPLL_DIV_CPU_MSB    5
+#define I2C_BBPLL_DIV_CPU_LSB    5
+
+#define I2C_BBPLL_OC_ENB_VCON        4
+#define I2C_BBPLL_OC_ENB_VCON_MSB    6
+#define I2C_BBPLL_OC_ENB_VCON_LSB    6
+
+#define I2C_BBPLL_OC_TSCHGP        4
+#define I2C_BBPLL_OC_TSCHGP_MSB    7
+#define I2C_BBPLL_OC_TSCHGP_LSB    7
+
+#define I2C_BBPLL_OC_DR1        5
+#define I2C_BBPLL_OC_DR1_MSB    2
+#define I2C_BBPLL_OC_DR1_LSB    0
+
+#define I2C_BBPLL_OC_DR3        5
+#define I2C_BBPLL_OC_DR3_MSB    6
+#define I2C_BBPLL_OC_DR3_LSB    4
+
+#define I2C_BBPLL_EN_USB        5
+#define I2C_BBPLL_EN_USB_MSB    7
+#define I2C_BBPLL_EN_USB_LSB    7
+
+#define I2C_BBPLL_OC_DCUR        6
+#define I2C_BBPLL_OC_DCUR_MSB    2
+#define I2C_BBPLL_OC_DCUR_LSB    0
+
+#define I2C_BBPLL_INC_CUR        6
+#define I2C_BBPLL_INC_CUR_MSB    3
+#define I2C_BBPLL_INC_CUR_LSB    3
+
+#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
+#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
+
+#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
+#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
+
+#define I2C_BBPLL_OR_CAL_CAP        8
+#define I2C_BBPLL_OR_CAL_CAP_MSB    3
+#define I2C_BBPLL_OR_CAL_CAP_LSB    0
+
+#define I2C_BBPLL_OR_CAL_UDF        8
+#define I2C_BBPLL_OR_CAL_UDF_MSB    4
+#define I2C_BBPLL_OR_CAL_UDF_LSB    4
+
+#define I2C_BBPLL_OR_CAL_OVF        8
+#define I2C_BBPLL_OR_CAL_OVF_MSB    5
+#define I2C_BBPLL_OR_CAL_OVF_LSB    5
+
+#define I2C_BBPLL_OR_CAL_END        8
+#define I2C_BBPLL_OR_CAL_END_MSB    6
+#define I2C_BBPLL_OR_CAL_END_LSB    6
+
+#define I2C_BBPLL_OR_LOCK        8
+#define I2C_BBPLL_OR_LOCK_MSB    7
+#define I2C_BBPLL_OR_LOCK_LSB    7
+
+#define I2C_BBPLL_BBADC_DELAY1        9
+#define I2C_BBPLL_BBADC_DELAY1_MSB    1
+#define I2C_BBPLL_BBADC_DELAY1_LSB    0
+
+#define I2C_BBPLL_BBADC_DELAY2        9
+#define I2C_BBPLL_BBADC_DELAY2_MSB    3
+#define I2C_BBPLL_BBADC_DELAY2_LSB    2
+
+#define I2C_BBPLL_BBADC_DVDD        9
+#define I2C_BBPLL_BBADC_DVDD_MSB    5
+#define I2C_BBPLL_BBADC_DVDD_LSB    4
+
+#define I2C_BBPLL_BBADC_DREF        9
+#define I2C_BBPLL_BBADC_DREF_MSB    7
+#define I2C_BBPLL_BBADC_DREF_LSB    6
+
+#define I2C_BBPLL_BBADC_DCUR        10
+#define I2C_BBPLL_BBADC_DCUR_MSB    1
+#define I2C_BBPLL_BBADC_DCUR_LSB    0
+
+#define I2C_BBPLL_BBADC_INPUT_SHORT        10
+#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
+#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
+
+#define I2C_BBPLL_ENT_PLL        10
+#define I2C_BBPLL_ENT_PLL_MSB    3
+#define I2C_BBPLL_ENT_PLL_LSB    3
+
+#define I2C_BBPLL_DTEST        10
+#define I2C_BBPLL_DTEST_MSB    5
+#define I2C_BBPLL_DTEST_LSB    4
+
+#define I2C_BBPLL_ENT_ADC        10
+#define I2C_BBPLL_ENT_ADC_MSB    7
+#define I2C_BBPLL_ENT_ADC_LSB    6

components/soc/esp8684/i2c_periph.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2c_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
+    {
+        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
+        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
+        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
+        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
+        .irq = ETS_I2C_EXT0_INTR_SOURCE,
+        .module = PERIPH_I2C0_MODULE,
+    },
+};

components/soc/esp8684/include/soc/adc_channel.h

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_ADC_CHANNEL_H
+#define _SOC_ADC_CHANNEL_H
+
+#define ADC1_GPIO1_CHANNEL     ADC1_CHANNEL_0
+#define ADC1_CHANNEL_0_GPIO_NUM 0
+
+#define ADC1_GPIO2_CHANNEL     ADC1_CHANNEL_1
+#define ADC1_CHANNEL_1_GPIO_NUM 1
+
+#define ADC1_GPIO3_CHANNEL     ADC1_CHANNEL_2
+#define ADC1_CHANNEL_2_GPIO_NUM 2
+
+#define ADC1_GPIO4_CHANNEL     ADC1_CHANNEL_3
+#define ADC1_CHANNEL_3_GPIO_NUM 3
+
+#define ADC1_GPIO5_CHANNEL     ADC1_CHANNEL_4
+#define ADC1_CHANNEL_4_GPIO_NUM 4
+
+#define ADC2_GPIO5_CHANNEL      ADC2_CHANNEL_0
+#define ADC2_CHANNEL_0_GPIO_NUM 5
+
+#endif

components/soc/esp8684/include/soc/apb_ctrl_reg.h

@@ -0,0 +1,584 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: reg_rst_tick_cnt.*/
+#define APB_CTRL_RST_TICK_CNT    (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: reg_clk_en.*/
+#define APB_CTRL_CLK_EN    (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: reg_clk_320m_en.*/
+#define APB_CTRL_CLK_320M_EN    (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: reg_pre_div_cnt.*/
+#define APB_CTRL_PRE_DIV_CNT    0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
+/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: reg_tick_enable.*/
+#define APB_CTRL_TICK_ENABLE    (BIT(16))
+#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_V  0x1
+#define APB_CTRL_TICK_ENABLE_S  16
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: reg_ck8m_tick_num.*/
+#define APB_CTRL_CK8M_TICK_NUM    0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  8
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: reg_xtal_tick_num.*/
+#define APB_CTRL_XTAL_TICK_NUM    0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
+/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: reg_clk_xtal_oen.*/
+#define APB_CTRL_CLK_XTAL_OEN    (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_V  0x1
+#define APB_CTRL_CLK_XTAL_OEN_S  10
+/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: reg_clk40x_bb_oen.*/
+#define APB_CTRL_CLK40X_BB_OEN    (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_V  0x1
+#define APB_CTRL_CLK40X_BB_OEN_S  9
+/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: reg_clk_dac_cpu_oen.*/
+#define APB_CTRL_CLK_DAC_CPU_OEN    (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
+#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
+/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: reg_clk_adc_inf_oen.*/
+#define APB_CTRL_CLK_ADC_INF_OEN    (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
+#define APB_CTRL_CLK_ADC_INF_OEN_S  7
+/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_clk_320m_oen.*/
+#define APB_CTRL_CLK_320M_OEN    (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_V  0x1
+#define APB_CTRL_CLK_320M_OEN_S  6
+/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: reg_clk160_oen.*/
+#define APB_CTRL_CLK160_OEN    (BIT(5))
+#define APB_CTRL_CLK160_OEN_M  (BIT(5))
+#define APB_CTRL_CLK160_OEN_V  0x1
+#define APB_CTRL_CLK160_OEN_S  5
+/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_clk80_oen.*/
+#define APB_CTRL_CLK80_OEN    (BIT(4))
+#define APB_CTRL_CLK80_OEN_M  (BIT(4))
+#define APB_CTRL_CLK80_OEN_V  0x1
+#define APB_CTRL_CLK80_OEN_S  4
+/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: reg_clk_bb_oen.*/
+#define APB_CTRL_CLK_BB_OEN    (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_V  0x1
+#define APB_CTRL_CLK_BB_OEN_S  3
+/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_clk44_oen.*/
+#define APB_CTRL_CLK44_OEN    (BIT(2))
+#define APB_CTRL_CLK44_OEN_M  (BIT(2))
+#define APB_CTRL_CLK44_OEN_V  0x1
+#define APB_CTRL_CLK44_OEN_S  2
+/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: reg_clk22_oen.*/
+#define APB_CTRL_CLK22_OEN    (BIT(1))
+#define APB_CTRL_CLK22_OEN_M  (BIT(1))
+#define APB_CTRL_CLK22_OEN_V  0x1
+#define APB_CTRL_CLK22_OEN_S  1
+/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_clk20_oen.*/
+#define APB_CTRL_CLK20_OEN    (BIT(0))
+#define APB_CTRL_CLK20_OEN_M  (BIT(0))
+#define APB_CTRL_CLK20_OEN_V  0x1
+#define APB_CTRL_CLK20_OEN_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
+/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg.*/
+#define APB_CTRL_WIFI_BB_CFG    0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
+#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
+/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg_2.*/
+#define APB_CTRL_WIFI_BB_CFG_2    0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
+#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_S  0
+
+#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
+/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: reg_wifi_clk_en.*/
+#define APB_CTRL_WIFI_CLK_EN    0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
+#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_S  0
+
+#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
+/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_rst.*/
+#define APB_CTRL_WIFI_RST    0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
+#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_S  0
+
+#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
+/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: reg_peri_io_swap.*/
+#define APB_CTRL_PERI_IO_SWAP    0x000000FF
+#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
+#define APB_CTRL_PERI_IO_SWAP_V  0xFF
+#define APB_CTRL_PERI_IO_SWAP_S  0
+
+#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
+/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_ext_mem_pms_lock.*/
+#define APB_CTRL_EXT_MEM_PMS_LOCK    (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
+#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
+
+#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
+/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace0_attr.*/
+#define APB_CTRL_FLASH_ACE0_ATTR    0x00000003
+#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
+#define APB_CTRL_FLASH_ACE0_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE0_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
+/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace1_attr.*/
+#define APB_CTRL_FLASH_ACE1_ATTR    0x00000003
+#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
+#define APB_CTRL_FLASH_ACE1_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE1_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
+/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace2_attr.*/
+#define APB_CTRL_FLASH_ACE2_ATTR    0x00000003
+#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
+#define APB_CTRL_FLASH_ACE2_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE2_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
+/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace3_attr.*/
+#define APB_CTRL_FLASH_ACE3_ATTR    0x00000003
+#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
+#define APB_CTRL_FLASH_ACE3_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE3_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
+/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_flash_ace0_addr_s.*/
+#define APB_CTRL_FLASH_ACE0_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
+/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: reg_flash_ace1_addr_s.*/
+#define APB_CTRL_FLASH_ACE1_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
+/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: reg_flash_ace2_addr_s.*/
+#define APB_CTRL_FLASH_ACE2_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
+/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
+/*description: reg_flash_ace3_addr_s.*/
+#define APB_CTRL_FLASH_ACE3_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
+/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace0_size.*/
+#define APB_CTRL_FLASH_ACE0_SIZE    0x00001FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
+#define APB_CTRL_FLASH_ACE0_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
+/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace1_size.*/
+#define APB_CTRL_FLASH_ACE1_SIZE    0x00001FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
+#define APB_CTRL_FLASH_ACE1_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
+/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace2_size.*/
+#define APB_CTRL_FLASH_ACE2_SIZE    0x00001FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
+#define APB_CTRL_FLASH_ACE2_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
+/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace3_size.*/
+#define APB_CTRL_FLASH_ACE3_SIZE    0x00001FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
+#define APB_CTRL_FLASH_ACE3_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_S  0
+
+#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
+/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: reg_spi_mem_reject_cde.*/
+#define APB_CTRL_SPI_MEM_REJECT_CDE    0x0000001F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
+#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
+/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_clr.*/
+#define APB_CTRL_SPI_MEM_REJECT_CLR    (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
+/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_int.*/
+#define APB_CTRL_SPI_MEM_REJECT_INT    (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
+
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
+/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_spi_mem_reject_addr.*/
+#define APB_CTRL_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
+
+#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
+/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: reg_sdio_win_access_en.*/
+#define APB_CTRL_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
+
+#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
+/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_andor.*/
+#define APB_CTRL_REDCY_ANDOR    (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_V  0x1
+#define APB_CTRL_REDCY_ANDOR_S  31
+/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig0.*/
+#define APB_CTRL_REDCY_SIG0    0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
+#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_S  0
+
+#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
+/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_nandor.*/
+#define APB_CTRL_REDCY_NANDOR    (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_V  0x1
+#define APB_CTRL_REDCY_NANDOR_S  31
+/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig1.*/
+#define APB_CTRL_REDCY_SIG1    0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
+#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_S  0
+
+#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
+/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_freq_mem_force_pd.*/
+#define APB_CTRL_FREQ_MEM_FORCE_PD    (BIT(7))
+#define APB_CTRL_FREQ_MEM_FORCE_PD_M  (BIT(7))
+#define APB_CTRL_FREQ_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_FREQ_MEM_FORCE_PD_S  7
+/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_freq_mem_force_pu.*/
+#define APB_CTRL_FREQ_MEM_FORCE_PU    (BIT(6))
+#define APB_CTRL_FREQ_MEM_FORCE_PU_M  (BIT(6))
+#define APB_CTRL_FREQ_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_FREQ_MEM_FORCE_PU_S  6
+/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: reg_dc_mem_force_pd.*/
+#define APB_CTRL_DC_MEM_FORCE_PD    (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PD_S  5
+/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_dc_mem_force_pu.*/
+#define APB_CTRL_DC_MEM_FORCE_PU    (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PU_S  4
+/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: reg_pbus_mem_force_pd.*/
+#define APB_CTRL_PBUS_MEM_FORCE_PD    (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
+/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_pbus_mem_force_pu.*/
+#define APB_CTRL_PBUS_MEM_FORCE_PU    (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
+/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_agc_mem_force_pd.*/
+#define APB_CTRL_AGC_MEM_FORCE_PD    (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
+/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_agc_mem_force_pu.*/
+#define APB_CTRL_AGC_MEM_FORCE_PU    (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
+
+#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
+/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reg_nobypass_cpu_iso_rst.*/
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
+/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: reg_retention_link_addr.*/
+#define APB_CTRL_RETENTION_LINK_ADDR    0x07FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_M  ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
+#define APB_CTRL_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_S  0
+
+#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA4)
+/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
+hen only when have access the sram have clock.*/
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON    0x0000000F
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  3
+/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
+en only when have access the rom have clock.*/
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON    0x00000007
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x7
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
+
+#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xA8)
+/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power down.*/
+#define APB_CTRL_SRAM_POWER_DOWN    0x0000000F
+#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
+#define APB_CTRL_SRAM_POWER_DOWN_V  0xF
+#define APB_CTRL_SRAM_POWER_DOWN_S  3
+/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power down.*/
+#define APB_CTRL_ROM_POWER_DOWN    0x00000007
+#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
+#define APB_CTRL_ROM_POWER_DOWN_V  0x7
+#define APB_CTRL_ROM_POWER_DOWN_S  0
+
+#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xAC)
+/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power up.*/
+#define APB_CTRL_SRAM_POWER_UP    0x0000000F
+#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
+#define APB_CTRL_SRAM_POWER_UP_V  0xF
+#define APB_CTRL_SRAM_POWER_UP_S  3
+/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power up.*/
+#define APB_CTRL_ROM_POWER_UP    0x00000007
+#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
+#define APB_CTRL_ROM_POWER_UP_V  0x7
+#define APB_CTRL_ROM_POWER_UP_S  0
+
+#define APB_CTRL_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0xB0)
+/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: reg_rnd_data.*/
+#define APB_CTRL_RND_DATA    0xFFFFFFFF
+#define APB_CTRL_RND_DATA_M  ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
+#define APB_CTRL_RND_DATA_V  0xFFFFFFFF
+#define APB_CTRL_RND_DATA_S  0
+
+#define APB_CTRL_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0xB4)
+/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: reg_peri_backup_ena.*/
+#define APB_CTRL_PERI_BACKUP_ENA    (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_M  (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ENA_S  31
+/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reg_peri_backup_to_mem.*/
+#define APB_CTRL_PERI_BACKUP_TO_MEM    (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_V  0x1
+#define APB_CTRL_PERI_BACKUP_TO_MEM_S  30
+/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: reg_peri_backup_start.*/
+#define APB_CTRL_PERI_BACKUP_START    (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_M  (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_V  0x1
+#define APB_CTRL_PERI_BACKUP_START_S  29
+/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: reg_peri_backup_size.*/
+#define APB_CTRL_PERI_BACKUP_SIZE    0x000003FF
+#define APB_CTRL_PERI_BACKUP_SIZE_M  ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
+#define APB_CTRL_PERI_BACKUP_SIZE_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_SIZE_S  19
+/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: reg_peri_backup_tout_thres.*/
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES    0x000003FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M  ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S  9
+/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: reg_peri_backup_burst_limit.*/
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT    0x0000001F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M  ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S  4
+/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: reg_peri_backup_flow_err.*/
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR    0x00000003
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M  ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V  0x3
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S  1
+
+#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0xB8)
+/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_apb_start_addr.*/
+#define APB_CTRL_BACKUP_APB_START_ADDR    0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_M  ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
+#define APB_CTRL_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0xBC)
+/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_mem_start_addr.*/
+#define APB_CTRL_BACKUP_MEM_START_ADDR    0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_M  ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
+#define APB_CTRL_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0xC0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_raw.*/
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW    (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_raw.*/
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW    (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0xC4)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_st.*/
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST    (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_st.*/
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST    (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0xC8)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_ena.*/
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA    (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_ena.*/
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA    (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0xD0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_clr.*/
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR    (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_clr.*/
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR    (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
+/*description: reg_dateVersion control.*/
+#define APB_CTRL_DATE    0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */

components/soc/esp8684/include/soc/apb_ctrl_struct.h

@@ -0,0 +1,481 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_CTRL_STRUCT_H_
+#define _SOC_APB_CTRL_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct apb_ctrl_dev_s{
+    union {
+        struct {
+            uint32_t pre_div                       :    10;  /*reg_pre_div_cnt*/
+            uint32_t clk_320m_en                   :    1;  /*reg_clk_320m_en*/
+            uint32_t clk_en                        :    1;  /*reg_clk_en*/
+            uint32_t rst_tick                      :    1;  /*reg_rst_tick_cnt*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t xtal_tick                     :    8;  /*reg_xtal_tick_num*/
+            uint32_t ck8m_tick                     :    8;  /*reg_ck8m_tick_num*/
+            uint32_t tick_enable                   :    1;  /*reg_tick_enable*/
+            uint32_t reserved17                    :    15;  /*Reserved.*/
+        };
+        uint32_t val;
+    } tick_conf;
+    union {
+        struct {
+            uint32_t clk20_oen                     :    1;  /*reg_clk20_oen*/
+            uint32_t clk22_oen                     :    1;  /*reg_clk22_oen*/
+            uint32_t clk44_oen                     :    1;  /*reg_clk44_oen*/
+            uint32_t clk_bb_oen                    :    1;  /*reg_clk_bb_oen*/
+            uint32_t clk80_oen                     :    1;  /*reg_clk80_oen*/
+            uint32_t clk160_oen                    :    1;  /*reg_clk160_oen*/
+            uint32_t clk_320m_oen                  :    1;  /*reg_clk_320m_oen*/
+            uint32_t clk_adc_inf_oen               :    1;  /*reg_clk_adc_inf_oen*/
+            uint32_t clk_dac_cpu_oen               :    1;  /*reg_clk_dac_cpu_oen*/
+            uint32_t clk40x_bb_oen                 :    1;  /*reg_clk40x_bb_oen*/
+            uint32_t clk_xtal_oen                  :    1;  /*reg_clk_xtal_oen*/
+            uint32_t reserved11                    :    21;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk_out_en;
+    uint32_t wifi_bb_cfg;
+    uint32_t wifi_bb_cfg_2;
+    uint32_t wifi_clk_en;
+    uint32_t wifi_rst_en;
+    union {
+        struct {
+            uint32_t peri_io_swap                  :    8;  /*reg_peri_io_swap*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } host_inf_sel;
+    union {
+        struct {
+            uint32_t ext_mem_pms_lock              :    1;  /*reg_ext_mem_pms_lock*/
+            uint32_t reserved1                     :    31;  /*Reserved.*/
+        };
+        uint32_t val;
+    } ext_mem_pms_lock;
+    uint32_t reserved_24;
+    union {
+        struct {
+            uint32_t flash_ace0_attr               :    2;  /*reg_flash_ace0_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace0_attr;
+    union {
+        struct {
+            uint32_t flash_ace1_attr               :    2;  /*reg_flash_ace1_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace1_attr;
+    union {
+        struct {
+            uint32_t flash_ace2_attr               :    2;  /*reg_flash_ace2_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace2_attr;
+    union {
+        struct {
+            uint32_t flash_ace3_attr               :    2;  /*reg_flash_ace3_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace3_attr;
+    uint32_t flash_ace0_addr;
+    uint32_t flash_ace1_addr;
+    uint32_t flash_ace2_addr;
+    uint32_t flash_ace3_addr;
+    union {
+        struct {
+            uint32_t flash_ace0_size               :    13;  /*reg_flash_ace0_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace0_size;
+    union {
+        struct {
+            uint32_t flash_ace1_size               :    13;  /*reg_flash_ace1_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace1_size;
+    union {
+        struct {
+            uint32_t flash_ace2_size               :    13;  /*reg_flash_ace2_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace2_size;
+    union {
+        struct {
+            uint32_t flash_ace3_size               :    13;  /*reg_flash_ace3_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace3_size;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    union {
+        struct {
+            uint32_t spi_mem_reject_int            :    1;  /*reg_spi_mem_reject_int*/
+            uint32_t spi_mem_reject_clr            :    1;  /*reg_spi_mem_reject_clr*/
+            uint32_t spi_mem_reject_cde            :    5;  /*reg_spi_mem_reject_cde*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } spi_mem_pms_ctrl;
+    uint32_t spi_mem_reject_addr;
+    union {
+        struct {
+            uint32_t sdio_win_access_en            :    1;  /*reg_sdio_win_access_en*/
+            uint32_t reserved1                     :    31;  /*Reserved.*/
+        };
+        uint32_t val;
+    } sdio_ctrl;
+    union {
+        struct {
+            uint32_t redcy_sig0                    :    31;  /*reg_redcy_sig0*/
+            uint32_t redcy_andor                   :    1;  /*reg_redcy_andor*/
+        };
+        uint32_t val;
+    } redcy_sig0;
+    union {
+        struct {
+            uint32_t redcy_sig1                    :    31;  /*reg_redcy_sig1*/
+            uint32_t redcy_nandor                  :    1;  /*reg_redcy_nandor*/
+        };
+        uint32_t val;
+    } redcy_sig1;
+    union {
+        struct {
+            uint32_t agc_mem_force_pu              :    1;  /*reg_agc_mem_force_pu*/
+            uint32_t agc_mem_force_pd              :    1;  /*reg_agc_mem_force_pd*/
+            uint32_t pbus_mem_force_pu             :    1;  /*reg_pbus_mem_force_pu*/
+            uint32_t pbus_mem_force_pd             :    1;  /*reg_pbus_mem_force_pd*/
+            uint32_t dc_mem_force_pu               :    1;  /*reg_dc_mem_force_pu*/
+            uint32_t dc_mem_force_pd               :    1;  /*reg_dc_mem_force_pd*/
+            uint32_t freq_mem_force_pu             :    1;  /*reg_freq_mem_force_pu*/
+            uint32_t freq_mem_force_pd             :    1;  /*reg_freq_mem_force_pd*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } front_end_mem_pd;
+    union {
+        struct {
+            uint32_t retention_link_addr           :    27;  /*reg_retention_link_addr*/
+            uint32_t nobypass_cpu_iso_rst          :    1;  /*reg_nobypass_cpu_iso_rst*/
+            uint32_t reserved28                    :    4;  /*Reserved.*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rom_clkgate_force_on          :    3;  /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/
+            uint32_t sram_clkgate_force_on         :    4;  /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clkgate_force_on;
+    union {
+        struct {
+            uint32_t rom_power_down                :    3;  /*Set 1 to let rom power down*/
+            uint32_t sram_power_down               :    4;  /*Set 1 to let sram power down*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } mem_power_down;
+    union {
+        struct {
+            uint32_t rom_power_up                  :    3;  /*Set 1 to let rom power up*/
+            uint32_t sram_power_up                 :    4;  /*Set 1 to let sram power up*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } mem_power_up;
+    uint32_t rnd_data;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved.*/
+            uint32_t peri_backup_flow_err          :    2;  /*reg_peri_backup_flow_err*/
+            uint32_t reserved3                     :    1;  /*Reserved.*/
+            uint32_t peri_backup_burst_limit       :    5;  /*reg_peri_backup_burst_limit*/
+            uint32_t peri_backup_tout_thres        :    10;  /*reg_peri_backup_tout_thres*/
+            uint32_t peri_backup_size              :    10;  /*reg_peri_backup_size*/
+            uint32_t peri_backup_start             :    1;  /*reg_peri_backup_start*/
+            uint32_t peri_backup_to_mem            :    1;  /*reg_peri_backup_to_mem*/
+            uint32_t peri_backup_ena               :    1;  /*reg_peri_backup_ena*/
+        };
+        uint32_t val;
+    } peri_backup_config;
+    uint32_t peri_backup_addr;
+    uint32_t peri_backup_mem_addr;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_raw*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_raw*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_raw;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_st*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_st*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_st;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_ena*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_ena*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_ena;
+    uint32_t reserved_cc;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_clr*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_clr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_clr;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t date;
+} apb_ctrl_dev_t;
+extern apb_ctrl_dev_t APB_CTRL;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_STRUCT_H_ */

components/soc/esp8684/include/soc/apb_saradc_reg.h

@@ -0,0 +1,638 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_SARADC_REG_H_
+#define _SOC_APB_SARADC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x0)
+/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
+/*description: wait arbit signal stable after sar_done.*/
+#define APB_SARADC_WAIT_ARB_CYCLE    0x00000003
+#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
+#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
+#define APB_SARADC_WAIT_ARB_CYCLE_S  30
+/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks.*/
+#define APB_SARADC_XPD_SAR_FORCE    0x00000003
+#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
+#define APB_SARADC_XPD_SAR_FORCE_V  0x3
+#define APB_SARADC_XPD_SAR_FORCE_S  27
+/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
+#define APB_SARADC_SAR_PATT_P_CLEAR    (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_M  (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_V  0x1
+#define APB_SARADC_SAR_PATT_P_CLEAR_S  23
+/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
+/*description:  0 ~ 15 means length 1 ~ 16.*/
+#define APB_SARADC_SAR_PATT_LEN    0x00000007
+#define APB_SARADC_SAR_PATT_LEN_M  ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
+#define APB_SARADC_SAR_PATT_LEN_V  0x7
+#define APB_SARADC_SAR_PATT_LEN_S  15
+/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider.*/
+#define APB_SARADC_SAR_CLK_DIV    0x000000FF
+#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
+#define APB_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_SARADC_SAR_CLK_DIV_S  7
+/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define APB_SARADC_SAR_CLK_GATED    (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_SARADC_SAR_CLK_GATED_S  6
+/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_START    (BIT(1))
+#define APB_SARADC_START_M  (BIT(1))
+#define APB_SARADC_START_V  0x1
+#define APB_SARADC_START_S  1
+/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_START_FORCE    (BIT(0))
+#define APB_SARADC_START_FORCE_M  (BIT(0))
+#define APB_SARADC_START_FORCE_V  0x1
+#define APB_SARADC_START_FORCE_S  0
+
+#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x4)
+/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger.*/
+#define APB_SARADC_TIMER_EN    (BIT(24))
+#define APB_SARADC_TIMER_EN_M  (BIT(24))
+#define APB_SARADC_TIMER_EN_V  0x1
+#define APB_SARADC_TIMER_EN_S  24
+/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
+/*description: to set saradc timer target.*/
+#define APB_SARADC_TIMER_TARGET    0x00000FFF
+#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
+#define APB_SARADC_TIMER_TARGET_V  0xFFF
+#define APB_SARADC_TIMER_TARGET_S  12
+/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
+#define APB_SARADC_SAR2_INV    (BIT(10))
+#define APB_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_SARADC_SAR2_INV_V  0x1
+#define APB_SARADC_SAR2_INV_S  10
+/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
+#define APB_SARADC_SAR1_INV    (BIT(9))
+#define APB_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_SARADC_SAR1_INV_V  0x1
+#define APB_SARADC_SAR1_INV_S  9
+/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number.*/
+#define APB_SARADC_MAX_MEAS_NUM    0x000000FF
+#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
+#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_SARADC_MAX_MEAS_NUM_S  1
+/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_MEAS_NUM_LIMIT    (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x8)
+/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_FILTER_FACTOR0    0x00000007
+#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
+#define APB_SARADC_FILTER_FACTOR0_V  0x7
+#define APB_SARADC_FILTER_FACTOR0_S  29
+/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_FILTER_FACTOR1    0x00000007
+#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
+#define APB_SARADC_FILTER_FACTOR1_V  0x7
+#define APB_SARADC_FILTER_FACTOR1_S  26
+
+#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0xC)
+/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: Need add description.*/
+#define APB_SARADC_STANDBY_WAIT    0x000000FF
+#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
+#define APB_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_SARADC_STANDBY_WAIT_S  16
+/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: Need add description.*/
+#define APB_SARADC_RSTB_WAIT    0x000000FF
+#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
+#define APB_SARADC_RSTB_WAIT_V  0xFF
+#define APB_SARADC_RSTB_WAIT_S  8
+/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: Need add description.*/
+#define APB_SARADC_XPD_WAIT    0x000000FF
+#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
+#define APB_SARADC_XPD_WAIT_V  0xFF
+#define APB_SARADC_XPD_WAIT_S  0
+
+#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x10)
+/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_SAR1_STATUS    0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
+#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_S  0
+
+#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x14)
+/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_SAR2_STATUS    0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
+#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_S  0
+
+#define APB_SARADC_SAR_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x18)
+/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR_PATT_TAB1    0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_M  ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
+#define APB_SARADC_SAR_PATT_TAB1_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_S  0
+
+#define APB_SARADC_SAR_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x1C)
+/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR_PATT_TAB2    0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_M  ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
+#define APB_SARADC_SAR_PATT_TAB2_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_S  0
+
+#define APB_SARADC_ONETIME_SAMPLE_REG          (DR_REG_APB_SARADC_BASE + 0x20)
+/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC1_ONETIME_SAMPLE    (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_M  (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC1_ONETIME_SAMPLE_S  31
+/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC2_ONETIME_SAMPLE    (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_M  (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC2_ONETIME_SAMPLE_S  30
+/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ONETIME_START    (BIT(29))
+#define APB_SARADC_ONETIME_START_M  (BIT(29))
+#define APB_SARADC_ONETIME_START_V  0x1
+#define APB_SARADC_ONETIME_START_S  29
+/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ONETIME_CHANNEL    0x0000000F
+#define APB_SARADC_ONETIME_CHANNEL_M  ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
+#define APB_SARADC_ONETIME_CHANNEL_V  0xF
+#define APB_SARADC_ONETIME_CHANNEL_S  25
+/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ONETIME_ATTEN    0x00000003
+#define APB_SARADC_ONETIME_ATTEN_M  ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
+#define APB_SARADC_ONETIME_ATTEN_V  0x3
+#define APB_SARADC_ONETIME_ATTEN_S  23
+
+#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x24)
+/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority.*/
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
+/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority.*/
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
+/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority.*/
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
+/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiterapb priority.*/
+#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
+/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant.*/
+#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
+/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller.*/
+#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
+/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller.*/
+#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
+/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enableapb controller.*/
+#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
+
+#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x28)
+/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable apb_adc1_filter.*/
+#define APB_SARADC_FILTER_RESET    (BIT(31))
+#define APB_SARADC_FILTER_RESET_M  (BIT(31))
+#define APB_SARADC_FILTER_RESET_V  0x1
+#define APB_SARADC_FILTER_RESET_S  31
+/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
+/*description: apb_adc1_filter_factor.*/
+#define APB_SARADC_FILTER_CHANNEL0    0x0000000F
+#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
+#define APB_SARADC_FILTER_CHANNEL0_V  0xF
+#define APB_SARADC_FILTER_CHANNEL0_S  22
+/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
+/*description: Need add description.*/
+#define APB_SARADC_FILTER_CHANNEL1    0x0000000F
+#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
+#define APB_SARADC_FILTER_CHANNEL1_V  0xF
+#define APB_SARADC_FILTER_CHANNEL1_S  18
+
+#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x2C)
+/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC1_DATA    0x0001FFFF
+#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
+#define APB_SARADC_ADC1_DATA_V  0x1FFFF
+#define APB_SARADC_ADC1_DATA_S  0
+
+#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x30)
+/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC2_DATA    0x0001FFFF
+#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
+#define APB_SARADC_ADC2_DATA_V  0x1FFFF
+#define APB_SARADC_ADC2_DATA_S  0
+
+#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x34)
+/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES0_LOW    0x00001FFF
+#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
+#define APB_SARADC_THRES0_LOW_V  0x1FFF
+#define APB_SARADC_THRES0_LOW_S  18
+/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES0_HIGH    0x00001FFF
+#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
+#define APB_SARADC_THRES0_HIGH_V  0x1FFF
+#define APB_SARADC_THRES0_HIGH_S  5
+/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_CHANNEL    0x0000000F
+#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
+#define APB_SARADC_THRES0_CHANNEL_V  0xF
+#define APB_SARADC_THRES0_CHANNEL_S  0
+
+#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x38)
+/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES1_LOW    0x00001FFF
+#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
+#define APB_SARADC_THRES1_LOW_V  0x1FFF
+#define APB_SARADC_THRES1_LOW_S  18
+/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES1_HIGH    0x00001FFF
+#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
+#define APB_SARADC_THRES1_HIGH_V  0x1FFF
+#define APB_SARADC_THRES1_HIGH_S  5
+/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_CHANNEL    0x0000000F
+#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
+#define APB_SARADC_THRES1_CHANNEL_V  0xF
+#define APB_SARADC_THRES1_CHANNEL_S  0
+
+#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x3C)
+/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_EN    (BIT(31))
+#define APB_SARADC_THRES0_EN_M  (BIT(31))
+#define APB_SARADC_THRES0_EN_V  0x1
+#define APB_SARADC_THRES0_EN_S  31
+/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_EN    (BIT(30))
+#define APB_SARADC_THRES1_EN_M  (BIT(30))
+#define APB_SARADC_THRES1_EN_V  0x1
+#define APB_SARADC_THRES1_EN_S  30
+/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES2_EN    (BIT(29))
+#define APB_SARADC_THRES2_EN_M  (BIT(29))
+#define APB_SARADC_THRES2_EN_V  0x1
+#define APB_SARADC_THRES2_EN_S  29
+/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES3_EN    (BIT(28))
+#define APB_SARADC_THRES3_EN_M  (BIT(28))
+#define APB_SARADC_THRES3_EN_V  0x1
+#define APB_SARADC_THRES3_EN_S  28
+/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES_ALL_EN    (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_V  0x1
+#define APB_SARADC_THRES_ALL_EN_S  27
+
+#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x40)
+/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC1_DONE_INT_ENA    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
+/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC2_DONE_INT_ENA    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
+/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
+/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
+
+#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x44)
+/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC1_DONE_INT_RAW    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
+/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC2_DONE_INT_RAW    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
+/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
+/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
+/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
+/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
+
+#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x48)
+/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC1_DONE_INT_ST    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ST_S  31
+/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC2_DONE_INT_ST    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ST_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
+/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ST_S  27
+/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ST_S  26
+
+#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x4C)
+/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC1_DONE_INT_CLR    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
+/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_ADC2_DONE_INT_CLR    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
+/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
+/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
+/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
+/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
+
+#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x50)
+/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: enable apb_adc use spi_dma.*/
+#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_V  0x1
+#define APB_SARADC_APB_ADC_TRANS_S  31
+/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reset_apb_adc_state.*/
+#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
+#define APB_SARADC_APB_ADC_RESET_FSM_S  30
+/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
+/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
+#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
+#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_S  0
+
+#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x54)
+/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
+/*description: Set this bit to enable clk_apll.*/
+#define APB_SARADC_CLK_SEL    0x00000003
+#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
+#define APB_SARADC_CLK_SEL_V  0x3
+#define APB_SARADC_CLK_SEL_S  21
+/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_CLK_EN    (BIT(20))
+#define APB_SARADC_CLK_EN_M  (BIT(20))
+#define APB_SARADC_CLK_EN_V  0x1
+#define APB_SARADC_CLK_EN_S  20
+/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value.*/
+#define APB_SARADC_CLKM_DIV_A    0x0000003F
+#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
+#define APB_SARADC_CLKM_DIV_A_V  0x3F
+#define APB_SARADC_CLKM_DIV_A_S  14
+/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value.*/
+#define APB_SARADC_CLKM_DIV_B    0x0000003F
+#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
+#define APB_SARADC_CLKM_DIV_B_V  0x3F
+#define APB_SARADC_CLKM_DIV_B_S  8
+/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: Integral I2S clock divider value.*/
+#define APB_SARADC_CLKM_DIV_NUM    0x000000FF
+#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
+#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
+#define APB_SARADC_CLKM_DIV_NUM_S  0
+
+#define APB_SARADC_APB_TSENS_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x58)
+/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_PU    (BIT(22))
+#define APB_SARADC_TSENS_PU_M  (BIT(22))
+#define APB_SARADC_TSENS_PU_V  0x1
+#define APB_SARADC_TSENS_PU_S  22
+/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_CLK_DIV    0x000000FF
+#define APB_SARADC_TSENS_CLK_DIV_M  ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
+#define APB_SARADC_TSENS_CLK_DIV_V  0xFF
+#define APB_SARADC_TSENS_CLK_DIV_S  14
+/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_IN_INV    (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_M  (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_V  0x1
+#define APB_SARADC_TSENS_IN_INV_S  13
+/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_OUT    0x000000FF
+#define APB_SARADC_TSENS_OUT_M  ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
+#define APB_SARADC_TSENS_OUT_V  0xFF
+#define APB_SARADC_TSENS_OUT_S  0
+
+#define APB_SARADC_ APB_TSENS_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x5C)
+/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_CLK_SEL    (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_M  (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_V  0x1
+#define APB_SARADC_TSENS_CLK_SEL_S  15
+/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_CLK_INV    (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_M  (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_V  0x1
+#define APB_SARADC_TSENS_CLK_INV_S  14
+/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_XPD_FORCE    0x00000003
+#define APB_SARADC_TSENS_XPD_FORCE_M  ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
+#define APB_SARADC_TSENS_XPD_FORCE_V  0x3
+#define APB_SARADC_TSENS_XPD_FORCE_S  12
+/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: Need add description.*/
+#define APB_SARADC_TSENS_XPD_WAIT    0x00000FFF
+#define APB_SARADC_TSENS_XPD_WAIT_M  ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
+#define APB_SARADC_TSENS_XPD_WAIT_V  0xFFF
+#define APB_SARADC_TSENS_XPD_WAIT_S  0
+
+#define APB_SARADC_CALI_REG          (DR_REG_APB_SARADC_BASE + 0x60)
+/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
+/*description: Need add description.*/
+#define APB_SARADC_CALI_CFG    0x0001FFFF
+#define APB_SARADC_CALI_CFG_M  ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
+#define APB_SARADC_CALI_CFG_V  0x1FFFF
+#define APB_SARADC_CALI_CFG_S  0
+
+#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3FC)
+/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02107210 ; */
+/*description: Need add description.*/
+#define APB_SARADC_DATE    0xFFFFFFFF
+#define APB_SARADC_DATE_M  ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
+#define APB_SARADC_DATE_V  0xFFFFFFFF
+#define APB_SARADC_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_SARADC_REG_H_ */

components/soc/esp8684/include/soc/apb_saradc_struct.h

@@ -0,0 +1,487 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_SARADC_STRUCT_H_
+#define _SOC_APB_SARADC_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct apb_saradc_dev_s {
+    union {
+        struct {
+            uint32_t start_force                   :    1;  /*Need add description*/
+            uint32_t start                         :    1;  /*Need add description*/
+            uint32_t reserved2                     :    4;  /*Reserved 0: single mode, 1: double mode, 2: alternate mode*/
+            uint32_t sar_clk_gated                 :    1;  /*Need add description*/
+            uint32_t sar_clk_div                   :    8;  /*SAR clock divider*/
+            uint32_t sar_patt_len                  :    3;  /* 0 ~ 15 means length 1 ~ 16*/
+            uint32_t reserved18                    :    5;  /*Reserved*/
+            uint32_t sar_patt_p_clear              :    1;  /*clear the pointer of pattern table for DIG ADC1 CTRL*/
+            uint32_t reserved24                    :    3;  /*Reserved*/
+            uint32_t xpd_sar_force                 :    2;  /*force option to xpd sar blocks*/
+            uint32_t reserved29                    :    1;  /*Reserved*/
+            uint32_t wait_arb_cycle                :    2;  /*wait arbit signal stable after sar_done*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t meas_num_limit                :    1;  /*Need add description*/
+            uint32_t max_meas_num                  :    8;  /*max conversion number*/
+            uint32_t sar1_inv                      :    1;  /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/
+            uint32_t sar2_inv                      :    1;  /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/
+            uint32_t reserved11                    :    1;  /*Reserved1: select saradc timer 0: i2s_ws trigger*/
+            uint32_t timer_target                  :    12;  /*to set saradc timer target*/
+            uint32_t timer_en                      :    1;  /*to enable saradc timer trigger*/
+            uint32_t reserved25                    :    7;  /*Reserved*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t filter_factor1                :    3;  /*Need add description*/
+            uint32_t filter_factor0                :    3;  /*Need add description*/
+        };
+        uint32_t val;
+    } filter_ctrl1;
+    union {
+        struct {
+            uint32_t xpd_wait                      :    8;  /*Need add description*/
+            uint32_t rstb_wait                     :    8;  /*Need add description*/
+            uint32_t standby_wait                  :    8;  /*Need add description*/
+            uint32_t reserved24                    :    8;  /*Reserved*/
+        };
+        uint32_t val;
+    } fsm_wait;
+    uint32_t sar1_status;
+    uint32_t sar2_status;
+    union {
+        struct {
+            uint32_t sar_patt_tab1                 :    24;  /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
+            uint32_t reserved24                    :    8;  /*Reserved*/
+        };
+        uint32_t val;
+    } sar_patt_tab[2];
+    union {
+        struct {
+            uint32_t reserved0                     :    23;  /*Reserved*/
+            uint32_t onetime_atten                 :    2;  /*Need add description*/
+            uint32_t onetime_channel               :    4;  /*Need add description*/
+            uint32_t onetime_start                 :    1;  /*Need add description*/
+            uint32_t adc2_onetime_sample           :    1;  /*Need add description*/
+            uint32_t adc1_onetime_sample           :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } onetime_sample;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;  /*Reserved*/
+            uint32_t adc_arb_apb_force             :    1;  /*adc2 arbiter force to enableapb controller*/
+            uint32_t adc_arb_rtc_force             :    1;  /*adc2 arbiter force to enable rtc controller*/
+            uint32_t adc_arb_wifi_force            :    1;  /*adc2 arbiter force to enable wifi controller*/
+            uint32_t adc_arb_grant_force           :    1;  /*adc2 arbiter force grant*/
+            uint32_t adc_arb_apb_priority          :    2;  /*Set adc2 arbiterapb priority*/
+            uint32_t adc_arb_rtc_priority          :    2;  /*Set adc2 arbiter rtc priority*/
+            uint32_t adc_arb_wifi_priority         :    2;  /*Set adc2 arbiter wifi priority*/
+            uint32_t adc_arb_fix_priority          :    1;  /*adc2 arbiter uses fixed priority*/
+            uint32_t reserved13                    :    19;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_adc_arb_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t filter_channel1               :    4;  /*Need add description*/
+            uint32_t filter_channel0               :    4;  /*apb_adc1_filter_factor*/
+            uint32_t reserved26                    :    5;  /*Reserved*/
+            uint32_t filter_reset                  :    1;  /*enable apb_adc1_filter*/
+        };
+        uint32_t val;
+    } filter_ctrl0;
+    union {
+        struct {
+            uint32_t adc1_data                     :    17;  /*Need add description*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_saradc1_data_status;
+    union {
+        struct {
+            uint32_t adc2_data                     :    17;  /*Need add description*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_saradc2_data_status;
+    union {
+        struct {
+            uint32_t thres0_channel                :    4;  /*Need add description*/
+            uint32_t reserved4                     :    1;  /*Reserved*/
+            uint32_t thres0_high                   :    13;  /*saradc1's thres0 monitor thres*/
+            uint32_t thres0_low                    :    13;  /*saradc1's thres0 monitor thres*/
+            uint32_t reserved31                    :    1;  /*Reserved*/
+        };
+        uint32_t val;
+    } thres0_ctrl;
+    union {
+        struct {
+            uint32_t thres1_channel                :    4;  /*Need add description*/
+            uint32_t reserved4                     :    1;  /*Reserved*/
+            uint32_t thres1_high                   :    13;  /*saradc1's thres0 monitor thres*/
+            uint32_t thres1_low                    :    13;  /*saradc1's thres0 monitor thres*/
+            uint32_t reserved31                    :    1;  /*Reserved*/
+        };
+        uint32_t val;
+    } thres1_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t thres_all_en                  :    1;  /*Need add description*/
+            uint32_t thres3_en                     :    1;  /*Need add description*/
+            uint32_t thres2_en                     :    1;  /*Need add description*/
+            uint32_t thres1_en                     :    1;  /*Need add description*/
+            uint32_t thres0_en                     :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } thres_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t thres1_low                    :    1;  /*Need add description*/
+            uint32_t thres0_low                    :    1;  /*Need add description*/
+            uint32_t thres1_high                   :    1;  /*Need add description*/
+            uint32_t thres0_high                   :    1;  /*Need add description*/
+            uint32_t adc2_done                     :    1;  /*Need add description*/
+            uint32_t adc1_done                     :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t thres1_low                    :    1;  /*Need add description*/
+            uint32_t thres0_low                    :    1;  /*Need add description*/
+            uint32_t thres1_high                   :    1;  /*Need add description*/
+            uint32_t thres0_high                   :    1;  /*Need add description*/
+            uint32_t adc2_done                     :    1;  /*Need add description*/
+            uint32_t adc1_done                     :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t thres1_low                    :    1;  /*Need add description*/
+            uint32_t thres0_low                    :    1;  /*Need add description*/
+            uint32_t thres1_high                   :    1;  /*Need add description*/
+            uint32_t thres0_high                   :    1;  /*Need add description*/
+            uint32_t adc2_done                     :    1;  /*Need add description*/
+            uint32_t adc1_done                     :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t thres1_low                    :    1;  /*Need add description*/
+            uint32_t thres0_low                    :    1;  /*Need add description*/
+            uint32_t thres1_high                   :    1;  /*Need add description*/
+            uint32_t thres0_high                   :    1;  /*Need add description*/
+            uint32_t adc2_done                     :    1;  /*Need add description*/
+            uint32_t adc1_done                     :    1;  /*Need add description*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t apb_adc_eof_num               :    16;  /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
+            uint32_t reserved16                    :    14;  /*Reserved*/
+            uint32_t apb_adc_reset_fsm             :    1;  /*reset_apb_adc_state*/
+            uint32_t apb_adc_trans                 :    1;  /*enable apb_adc use spi_dma*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t clkm_div_num                  :    8;  /*Integral I2S clock divider value*/
+            uint32_t clkm_div_b                    :    6;  /*Fractional clock divider numerator value*/
+            uint32_t clkm_div_a                    :    6;  /*Fractional clock divider denominator value*/
+            uint32_t clk_en                        :    1;  /*Need add description*/
+            uint32_t clk_sel                       :    2;  /*Set this bit to enable clk_apll*/
+            uint32_t reserved23                    :    9;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_adc_clkm_conf;
+    union {
+        struct {
+            uint32_t tsens_out                     :    8;  /*Need add description*/
+            uint32_t reserved8                     :    5;  /*Reserved*/
+            uint32_t tsens_in_inv                  :    1;  /*Need add description*/
+            uint32_t tsens_clk_div                 :    8;  /*Need add description*/
+            uint32_t tsens_pu                      :    1;  /*Need add description*/
+            uint32_t reserved23                    :    9;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_tsens_ctrl;
+    union {
+        struct {
+            uint32_t tsens_xpd_wait                :    12;  /*Need add description*/
+            uint32_t tsens_xpd_force               :    2;  /*Need add description*/
+            uint32_t tsens_clk_inv                 :    1;  /*Need add description*/
+            uint32_t tsens_clk_sel                 :    1;  /*Need add description*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    }  apb_tsens_ctrl2;
+    union {
+        struct {
+            uint32_t cali_cfg                      :    17;  /*Need add description*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } cali;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t apb_ctrl_date;
+} apb_saradc_dev_t;
+extern apb_saradc_dev_t APB_SARADC;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_SARADC_STRUCT_H_ */

components/soc/esp8684/include/soc/assist_debug_reg.h

@@ -0,0 +1,226 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  enbale sp underlow monitor
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  enbale sp overflow monitor
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  sp underlow monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  sp overflow monitor interupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  enbale sp underlow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  enbale sp overflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  clr sp underlow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  clr sp overflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration regsiter
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This regsiter stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status regsiter
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status regsiter
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock gate register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  clock gate register
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
+/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34627616;
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/bb_reg.h

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/* Some of the baseband control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
+#define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_M (BIT(3))
+#define BB_FFT_FORCE_PU_V 1
+#define BB_FFT_FORCE_PU_S 3
+#define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_M (BIT(2))
+#define BB_FFT_FORCE_PD_V 1
+#define BB_FFT_FORCE_PD_S 2
+#define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_M (BIT(1))
+#define BB_DC_EST_FORCE_PU_V 1
+#define BB_DC_EST_FORCE_PU_S 1
+#define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_M (BIT(0))
+#define BB_DC_EST_FORCE_PD_V 1
+#define BB_DC_EST_FORCE_PD_S 0

components/soc/esp8684/include/soc/boot_mode.h

@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXX(v)                              (((v)&0x08)==0x08)
+
+/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
+#define IS_01XX(v)                              (((v)&0x0c)==0x04)
+
+/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
+#define IS_0100(v)                              (((v)&0x0f)==0x04)
+
+/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
+#define IS_0101(v)                              (((v)&0x0f)==0x05)
+
+/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
+#define IS_0110(v)                              (((v)&0x0f)==0x06)
+
+/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
+#define IS_0111(v)                              (((v)&0x0f)==0x07)
+
+/*Diagnostic Mode1+USB download Mode*/
+#define IS_0000(v)                              (((v)&0x0f)==0x00)
+
+/*SPI(or SDIO_V1) download Mode*/
+#define IS_0001(v)                              (((v)&0x0f)==0x01)
+
+/*Diagnostic Mode0+UART0 download Mode*/
+#define IS_0010(v)                              (((v)&0x0f)==0x02)
+
+/*ATE/ANALOG Mode*/
+#define IS_0011(v)                              (((v)&0x0f)==0x03)
+
+/*print control*/
+#define IS_X1XX(v)                              (((v)&0x04)==0x04)
+
+#define BOOT_MODE_GET()                         (GPIO_REG_READ(GPIO_STRAP_REG))
+
+#define ETS_PRINT_CONTROL_HIGH_LEVEL()          IS_X1XX(BOOT_MODE_GET())
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()                      IS_0010(BOOT_MODE_GET())
+
+#define ETS_IS_USB_BOOT()                       IS_0000(BOOT_MODE_GET())
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_FLASH_BOOT()                     IS_1XXX(BOOT_MODE_GET())
+
+/*all faster spi boot including spi*/
+#define ETS_IS_FAST_FLASH_BOOT()                IS_1XXX(BOOT_MODE_GET())
+
+#if SUPPORT_SDIO_DOWNLOAD
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()           IS_0100(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()           IS_0101(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()           IS_0110(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()           IS_0111(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()           IS_0001(BOOT_MODE_GET())
+
+/*do not include joint download mode*/
+#define ETS_IS_SDIO_BOOT()                      IS_0001(BOOT_MODE_GET())
+#else
+
+/*do not include joint download mode*/
+#define ETS_IS_SPI_DOWNLOAD_BOOT()              IS_0001(BOOT_MODE_GET())
+
+#endif
+
+/*joint download boot*/
+#define ETS_IS_JOINT_DOWNLOAD_BOOT()            IS_01XX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()                       IS_0011(BOOT_MODE_GET())
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                             0
+#define SEL_SDIO_BOOT                           BIT0
+#define SEL_UART_BOOT                           BIT1
+#define SEL_SPI_SLAVE_BOOT                      BIT2
+#define SEL_USB_BOOT                            BIT3
+
+#endif /* _SOC_BOOT_MODE_H_ */

components/soc/esp8684/include/soc/cache_memory.h

@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _CACHE_MEMORY_H_
+#define _CACHE_MEMORY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp8684/rom/cache.h"
+
+/*IRAM0 is connected with Cache IBUS0*/
+#define MMU_PAGE_MODE			MMU_Get_Page_Mode()
+
+#define IRAM0_ADDRESS_LOW               0x40000000
+#define IRAM0_ADDRESS_HIGH              IRAM0_CACHE_ADDRESS_HIGH
+#define IRAM0_CACHE_ADDRESS_LOW         0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH        (IRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
+
+/*DRAM0 is connected with Cache DBUS0*/
+#define DRAM0_ADDRESS_LOW               0x3C000000
+#define DRAM0_ADDRESS_HIGH              0x40000000
+#define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
+#define DRAM0_CACHE_ADDRESS_HIGH        (DRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
+#define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH
+#define ESP_CACHE_TEMP_ADDR             0x3C000000
+
+#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+//IDF-3821
+// #define MMU_SIZE                        0x100
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x100
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x100
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x100
+
+#define ICACHE_MMU_SIZE                 0x100
+#define DCACHE_MMU_SIZE                 0x100
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x100
+
+#define MMU_INVALID                     BIT(6)
+#define MMU_TYPE                        0
+#define MMU_ACCESS_FLASH                0
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
+#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
+
+#define MMU_TABLE_INVALID_VAL 		MMU_INVALID
+#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
+#define MMU_ADDRESS_MASK 		(MMU_TABLE_INVALID_VAL - 1)
+#define MMU_PAGE_SIZE                   (0x4000 << (MMU_PAGE_MODE))
+#define INVALID_PHY_PAGE                (MMU_PAGE_SIZE - 1)
+
+#define BUS_ADDR_SIZE 			(0x100000 << (MMU_PAGE_MODE))
+#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+#define BUS_PMS_MASK  0xffffff
+
+#define CACHE_ICACHE_LOW_SHIFT         0
+#define CACHE_ICACHE_HIGH_SHIFT        2
+#define CACHE_DCACHE_LOW_SHIFT         4
+#define CACHE_DCACHE_HIGH_SHIFT        6
+
+#define CACHE_MEMORY_IBANK0_ADDR        0x4037C000
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CACHE_MEMORY_H_ */

components/soc/esp8684/include/soc/clkout_channel.h

@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_CLKOUT_CHANNEL_H
+#define _SOC_CLKOUT_CHANNEL_H
+
+//CLKOUT channels
+#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
+#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
+#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
+#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
+#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
+#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
+
+#endif

components/soc/esp8684/include/soc/dport_access.h

@@ -0,0 +1,103 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp_attr.h"
+#include "esp8684/dport_access.h"
+#include "soc.h"
+#include "uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
+
+// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+// Write value to DPORT register (does not require protecting)
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
+
+#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
+#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
+#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
+#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
+#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
+
+#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DPORT_ACCESS_H_ */

components/soc/esp8684/include/soc/efuse_reg.h

@@ -0,0 +1,813 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EFUSE_REG_H_
+#define _SOC_EFUSE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0)
+/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 0th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_0    0xFFFFFFFF
+#define EFUSE_PGM_DATA_0_M  ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S))
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_0_S  0
+
+#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x4)
+/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 1st 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_1    0xFFFFFFFF
+#define EFUSE_PGM_DATA_1_M  ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S))
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_1_S  0
+
+#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x8)
+/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 2nd 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_2    0xFFFFFFFF
+#define EFUSE_PGM_DATA_2_M  ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S))
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_2_S  0
+
+#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0xC)
+/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 3rd 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_3    0xFFFFFFFF
+#define EFUSE_PGM_DATA_3_M  ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S))
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_3_S  0
+
+#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10)
+/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 4th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_4    0xFFFFFFFF
+#define EFUSE_PGM_DATA_4_M  ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S))
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_4_S  0
+
+#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x14)
+/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 5th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_5    0xFFFFFFFF
+#define EFUSE_PGM_DATA_5_M  ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S))
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_5_S  0
+
+#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x18)
+/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 6th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_6    0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_M  ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_S  0
+
+#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x1C)
+/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 7th 32-bit data to be programmed..*/
+#define EFUSE_PGM_DATA_7    0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_M  ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_S  0
+
+#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x20)
+/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 0th 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_M  ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x24)
+/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 1st 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_M  ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x28)
+/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 2nd 32-bit RS code to be programmed..*/
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_M  ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x2C)
+/* EFUSE_WR_DIS : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Disable programming of individual eFuses..*/
+#define EFUSE_WR_DIS    0x000000FF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x30)
+/* EFUSE_RPT4_RESERVED : RO ;bitpos:[31:22] ;default: 10'h0 ; */
+/*description: Reserved (used for four backups method)..*/
+#define EFUSE_RPT4_RESERVED    0x000003FF
+#define EFUSE_RPT4_RESERVED_M  ((EFUSE_RPT4_RESERVED_V)<<(EFUSE_RPT4_RESERVED_S))
+#define EFUSE_RPT4_RESERVED_V  0x3FF
+#define EFUSE_RPT4_RESERVED_S  22
+/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit be set to enable secure boot..*/
+#define EFUSE_SECURE_BOOT_EN    (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  21
+/* EFUSE_FLASH_TPUW : RO ;bitpos:[20:17] ;default: 4'h0 ; */
+/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les
+s than 15, the waiting time is the configurable value.  Otherwise, the waiting t
+ime is twice the configurable value..*/
+#define EFUSE_FLASH_TPUW    0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  17
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable secure UART download mode..*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  16
+/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This bit set means disable direct_boot mode..*/
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_M  (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_V  0x1
+#define EFUSE_DIS_DIRECT_BOOT_S  15
+/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7)..*/
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  14
+/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: Set this bit to disable usb printing..*/
+#define EFUSE_UART_PRINT_CONTROL    0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  11
+/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwi
+se, XTS_AES use 128-bit eFuse data in BLOCK3..*/
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x1
+#define EFUSE_XTS_KEY_LENGTH_256_S  10
+/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. e
+ven number of 1: disable..*/
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT    0x00000007
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M  ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S  7
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit be set to disable manual encryption..*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  6
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit be set to disable icache in download mode..*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  5
+/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to disable pad jtag..*/
+#define EFUSE_DIS_PAD_JTAG    (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_M  (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_V  0x1
+#define EFUSE_DIS_PAD_JTAG_S  4
+/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1
+: 80000. 2: 160000. 3:320000..*/
+#define EFUSE_WDT_DELAY_SEL    0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  2
+/* EFUSE_KEY0_RD_DIS : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: The bit be set to disable software read high/low 128-bit of BLK3..*/
+#define EFUSE_KEY0_RD_DIS    0x00000003
+#define EFUSE_KEY0_RD_DIS_M  ((EFUSE_KEY0_RD_DIS_V)<<(EFUSE_KEY0_RD_DIS_S))
+#define EFUSE_KEY0_RD_DIS_V  0x3
+#define EFUSE_KEY0_RD_DIS_S  0
+
+#define EFUSE_RD_BLK1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x34)
+/* EFUSE_SYSTEM_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the bits [0:31] of system data..*/
+#define EFUSE_SYSTEM_DATA0    0xFFFFFFFF
+#define EFUSE_SYSTEM_DATA0_M  ((EFUSE_SYSTEM_DATA0_V)<<(EFUSE_SYSTEM_DATA0_S))
+#define EFUSE_SYSTEM_DATA0_V  0xFFFFFFFF
+#define EFUSE_SYSTEM_DATA0_S  0
+
+#define EFUSE_RD_BLK1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x38)
+/* EFUSE_SYSTEM_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the bits [32:63] of system data..*/
+#define EFUSE_SYSTEM_DATA1    0xFFFFFFFF
+#define EFUSE_SYSTEM_DATA1_M  ((EFUSE_SYSTEM_DATA1_V)<<(EFUSE_SYSTEM_DATA1_S))
+#define EFUSE_SYSTEM_DATA1_V  0xFFFFFFFF
+#define EFUSE_SYSTEM_DATA1_S  0
+
+#define EFUSE_RD_BLK1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x3C)
+/* EFUSE_SYSTEM_DATA2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Stores the bits [64:87] of system data..*/
+#define EFUSE_SYSTEM_DATA2    0x00FFFFFF
+#define EFUSE_SYSTEM_DATA2_M  ((EFUSE_SYSTEM_DATA2_V)<<(EFUSE_SYSTEM_DATA2_S))
+#define EFUSE_SYSTEM_DATA2_V  0xFFFFFF
+#define EFUSE_SYSTEM_DATA2_S  0
+
+#define EFUSE_RD_BLK2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x40)
+/* EFUSE_MAC_ID_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the bit [0:31] of MAC..*/
+#define EFUSE_MAC_ID_LOW    0xFFFFFFFF
+#define EFUSE_MAC_ID_LOW_M  ((EFUSE_MAC_ID_LOW_V)<<(EFUSE_MAC_ID_LOW_S))
+#define EFUSE_MAC_ID_LOW_V  0xFFFFFFFF
+#define EFUSE_MAC_ID_LOW_S  0
+
+#define EFUSE_RD_BLK2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x44)
+/* EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO ;bitpos:[31:29] ;default: 3'h0 ; */
+/*description: Store the bit [0:2] of ido configuration parameters..*/
+#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW    0x00000007
+#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M  ((EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S))
+#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V  0x7
+#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S  29
+/* EFUSE_RF_REF_I_BIAS_CONFIG : RO ;bitpos:[28:25] ;default: 4'h0 ; */
+/*description: Store rf configuration parameters..*/
+#define EFUSE_RF_REF_I_BIAS_CONFIG    0x0000000F
+#define EFUSE_RF_REF_I_BIAS_CONFIG_M  ((EFUSE_RF_REF_I_BIAS_CONFIG_V)<<(EFUSE_RF_REF_I_BIAS_CONFIG_S))
+#define EFUSE_RF_REF_I_BIAS_CONFIG_V  0xF
+#define EFUSE_RF_REF_I_BIAS_CONFIG_S  25
+/* EFUSE_BLK2_EFUSE_VERSION : RO ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: Store efuse version..*/
+#define EFUSE_BLK2_EFUSE_VERSION    0x00000007
+#define EFUSE_BLK2_EFUSE_VERSION_M  ((EFUSE_BLK2_EFUSE_VERSION_V)<<(EFUSE_BLK2_EFUSE_VERSION_S))
+#define EFUSE_BLK2_EFUSE_VERSION_V  0x7
+#define EFUSE_BLK2_EFUSE_VERSION_S  22
+/* EFUSE_PKG_VERSION : RO ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: Store package version..*/
+#define EFUSE_PKG_VERSION    0x00000007
+#define EFUSE_PKG_VERSION_M  ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
+#define EFUSE_PKG_VERSION_V  0x7
+#define EFUSE_PKG_VERSION_S  19
+/* EFUSE_WAFER_VERSION : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: Store wafer version..*/
+#define EFUSE_WAFER_VERSION    0x00000007
+#define EFUSE_WAFER_VERSION_M  ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
+#define EFUSE_WAFER_VERSION_V  0x7
+#define EFUSE_WAFER_VERSION_S  16
+/* EFUSE_MAC_ID_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Store the bit [31:47] of MAC..*/
+#define EFUSE_MAC_ID_HIGH    0x0000FFFF
+#define EFUSE_MAC_ID_HIGH_M  ((EFUSE_MAC_ID_HIGH_V)<<(EFUSE_MAC_ID_HIGH_S))
+#define EFUSE_MAC_ID_HIGH_V  0xFFFF
+#define EFUSE_MAC_ID_HIGH_S  0
+
+#define EFUSE_RD_BLK2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x48)
+/* EFUSE_PVT_LOW : RO ;bitpos:[31:27] ;default: 5'h0 ; */
+/*description: Store the bit [0:4] of pvt..*/
+#define EFUSE_PVT_LOW    0x0000001F
+#define EFUSE_PVT_LOW_M  ((EFUSE_PVT_LOW_V)<<(EFUSE_PVT_LOW_S))
+#define EFUSE_PVT_LOW_V  0x1F
+#define EFUSE_PVT_LOW_S  27
+/* EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: Store the bit [3:29] of ido configuration parameters..*/
+#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH    0x07FFFFFF
+#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M  ((EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S))
+#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V  0x7FFFFFF
+#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S  0
+
+#define EFUSE_RD_BLK2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x4C)
+/* EFUSE_ADC_CALIBRATION_0 : RO ;bitpos:[31:10] ;default: 22'h0 ; */
+/*description: Store the bit [0:21] of ADC calibration data..*/
+#define EFUSE_ADC_CALIBRATION_0    0x003FFFFF
+#define EFUSE_ADC_CALIBRATION_0_M  ((EFUSE_ADC_CALIBRATION_0_V)<<(EFUSE_ADC_CALIBRATION_0_S))
+#define EFUSE_ADC_CALIBRATION_0_V  0x3FFFFF
+#define EFUSE_ADC_CALIBRATION_0_S  10
+/* EFUSE_PVT_HIGH : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: Store the bit [5:14] of pvt..*/
+#define EFUSE_PVT_HIGH    0x000003FF
+#define EFUSE_PVT_HIGH_M  ((EFUSE_PVT_HIGH_V)<<(EFUSE_PVT_HIGH_S))
+#define EFUSE_PVT_HIGH_V  0x3FF
+#define EFUSE_PVT_HIGH_S  0
+
+#define EFUSE_RD_BLK2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x50)
+/* EFUSE_ADC_CALIBRATION_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the bit [22:53] of ADC calibration data..*/
+#define EFUSE_ADC_CALIBRATION_1    0xFFFFFFFF
+#define EFUSE_ADC_CALIBRATION_1_M  ((EFUSE_ADC_CALIBRATION_1_V)<<(EFUSE_ADC_CALIBRATION_1_S))
+#define EFUSE_ADC_CALIBRATION_1_V  0xFFFFFFFF
+#define EFUSE_ADC_CALIBRATION_1_S  0
+
+#define EFUSE_RD_BLK2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x54)
+/* EFUSE_ADC_CALIBRATION_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the bit [54:85] of ADC calibration data..*/
+#define EFUSE_ADC_CALIBRATION_2    0xFFFFFFFF
+#define EFUSE_ADC_CALIBRATION_2_M  ((EFUSE_ADC_CALIBRATION_2_V)<<(EFUSE_ADC_CALIBRATION_2_S))
+#define EFUSE_ADC_CALIBRATION_2_V  0xFFFFFFFF
+#define EFUSE_ADC_CALIBRATION_2_S  0
+
+#define EFUSE_RD_BLK2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x58)
+/* EFUSE_BLK2_RESERVED_DATA_0 : RO ;bitpos:[31:11] ;default: 21'h0 ; */
+/*description: Store the bit [0:20] of block2 reserved data..*/
+#define EFUSE_BLK2_RESERVED_DATA_0    0x001FFFFF
+#define EFUSE_BLK2_RESERVED_DATA_0_M  ((EFUSE_BLK2_RESERVED_DATA_0_V)<<(EFUSE_BLK2_RESERVED_DATA_0_S))
+#define EFUSE_BLK2_RESERVED_DATA_0_V  0x1FFFFF
+#define EFUSE_BLK2_RESERVED_DATA_0_S  11
+/* EFUSE_ADC_CALIBRATION_3 : RO ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: Store the bit [86:96] of ADC calibration data..*/
+#define EFUSE_ADC_CALIBRATION_3    0x000007FF
+#define EFUSE_ADC_CALIBRATION_3_M  ((EFUSE_ADC_CALIBRATION_3_V)<<(EFUSE_ADC_CALIBRATION_3_S))
+#define EFUSE_ADC_CALIBRATION_3_V  0x7FF
+#define EFUSE_ADC_CALIBRATION_3_S  0
+
+#define EFUSE_RD_BLK2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x5C)
+/* EFUSE_BLK2_RESERVED_DATA_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the bit [21:52] of block2 reserved data..*/
+#define EFUSE_BLK2_RESERVED_DATA_1    0xFFFFFFFF
+#define EFUSE_BLK2_RESERVED_DATA_1_M  ((EFUSE_BLK2_RESERVED_DATA_1_V)<<(EFUSE_BLK2_RESERVED_DATA_1_S))
+#define EFUSE_BLK2_RESERVED_DATA_1_V  0xFFFFFFFF
+#define EFUSE_BLK2_RESERVED_DATA_1_S  0
+
+#define EFUSE_RD_BLK3_DATA0_REG          (DR_REG_EFUSE_BASE + 0x60)
+/* EFUSE_BLK3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the first 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA0    0xFFFFFFFF
+#define EFUSE_BLK3_DATA0_M  ((EFUSE_BLK3_DATA0_V)<<(EFUSE_BLK3_DATA0_S))
+#define EFUSE_BLK3_DATA0_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA0_S  0
+
+#define EFUSE_RD_BLK3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x64)
+/* EFUSE_BLK3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the second 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA1    0xFFFFFFFF
+#define EFUSE_BLK3_DATA1_M  ((EFUSE_BLK3_DATA1_V)<<(EFUSE_BLK3_DATA1_S))
+#define EFUSE_BLK3_DATA1_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA1_S  0
+
+#define EFUSE_RD_BLK3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x68)
+/* EFUSE_BLK3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the third 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA2    0xFFFFFFFF
+#define EFUSE_BLK3_DATA2_M  ((EFUSE_BLK3_DATA2_V)<<(EFUSE_BLK3_DATA2_S))
+#define EFUSE_BLK3_DATA2_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA2_S  0
+
+#define EFUSE_RD_BLK3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x6C)
+/* EFUSE_BLK3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the fourth 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA3    0xFFFFFFFF
+#define EFUSE_BLK3_DATA3_M  ((EFUSE_BLK3_DATA3_V)<<(EFUSE_BLK3_DATA3_S))
+#define EFUSE_BLK3_DATA3_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA3_S  0
+
+#define EFUSE_RD_BLK3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x70)
+/* EFUSE_BLK3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the fifth 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA4    0xFFFFFFFF
+#define EFUSE_BLK3_DATA4_M  ((EFUSE_BLK3_DATA4_V)<<(EFUSE_BLK3_DATA4_S))
+#define EFUSE_BLK3_DATA4_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA4_S  0
+
+#define EFUSE_RD_BLK3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x74)
+/* EFUSE_BLK3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the sixth 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA5    0xFFFFFFFF
+#define EFUSE_BLK3_DATA5_M  ((EFUSE_BLK3_DATA5_V)<<(EFUSE_BLK3_DATA5_S))
+#define EFUSE_BLK3_DATA5_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA5_S  0
+
+#define EFUSE_RD_BLK3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x78)
+/* EFUSE_BLK3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the seventh 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA6    0xFFFFFFFF
+#define EFUSE_BLK3_DATA6_M  ((EFUSE_BLK3_DATA6_V)<<(EFUSE_BLK3_DATA6_S))
+#define EFUSE_BLK3_DATA6_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA6_S  0
+
+#define EFUSE_RD_BLK3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x7C)
+/* EFUSE_BLK3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Store the eighth 32-bit of Block3..*/
+#define EFUSE_BLK3_DATA7    0xFFFFFFFF
+#define EFUSE_BLK3_DATA7_M  ((EFUSE_BLK3_DATA7_V)<<(EFUSE_BLK3_DATA7_S))
+#define EFUSE_BLK3_DATA7_V  0xFFFFFFFF
+#define EFUSE_BLK3_DATA7_S  0
+
+#define EFUSE_RD_REPEAT_ERR_REG          (DR_REG_EFUSE_BASE + 0x80)
+/* EFUSE_RPT4_RESERVED_ERR : RO ;bitpos:[31:22] ;default: 12'h0 ; */
+/*description: Reserved..*/
+#define EFUSE_RPT4_RESERVED_ERR    0x000003FF
+#define EFUSE_RPT4_RESERVED_ERR_M  ((EFUSE_RPT4_RESERVED_ERR_V)<<(EFUSE_RPT4_RESERVED_ERR_S))
+#define EFUSE_RPT4_RESERVED_ERR_V  0x3FF
+#define EFUSE_RPT4_RESERVED_ERR_S  22
+/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_EN_ERR_S  21
+/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[20:17] ;default: 4'h0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_FLASH_TPUW_ERR    0x0000000F
+#define EFUSE_FLASH_TPUW_ERR_M  ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
+#define EFUSE_FLASH_TPUW_ERR_V  0xF
+#define EFUSE_FLASH_TPUW_ERR_S  17
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  16
+/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x1
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  15
+/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  14
+/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error..*/
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error..*/
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  11
+/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error..*/
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x1
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  10
+/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
+ error..*/
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR    0x00000007
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M  ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S))
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V  0x7
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S  7
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
+error..*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  6
+/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: If any bit in this filed is 1, then it indicates a programming error..*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  5
+/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error..*/
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x1
+#define EFUSE_DIS_PAD_JTAG_ERR_S  4
+/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error..*/
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_M  ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x3
+#define EFUSE_WDT_DELAY_SEL_ERR_S  2
+/* EFUSE_KEY0_RD_DIS_ERR : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: If any bit in RD_DIS is 1, then it indicates a programming error..*/
+#define EFUSE_KEY0_RD_DIS_ERR    0x00000003
+#define EFUSE_KEY0_RD_DIS_ERR_M  ((EFUSE_KEY0_RD_DIS_ERR_V)<<(EFUSE_KEY0_RD_DIS_ERR_S))
+#define EFUSE_KEY0_RD_DIS_ERR_V  0x3
+#define EFUSE_KEY0_RD_DIS_ERR_S  0
+
+#define EFUSE_RD_RS_ERR_REG          (DR_REG_EFUSE_BASE + 0x84)
+/* EFUSE_BLK3_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the block3 data is reliable 1: Means that programmi
+ng user data failed and the number of error bytes is over 6..*/
+#define EFUSE_BLK3_FAIL    (BIT(11))
+#define EFUSE_BLK3_FAIL_M  (BIT(11))
+#define EFUSE_BLK3_FAIL_V  0x1
+#define EFUSE_BLK3_FAIL_S  11
+/* EFUSE_BLK3_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes in block3..*/
+#define EFUSE_BLK3_ERR_NUM    0x00000007
+#define EFUSE_BLK3_ERR_NUM_M  ((EFUSE_BLK3_ERR_NUM_V)<<(EFUSE_BLK3_ERR_NUM_S))
+#define EFUSE_BLK3_ERR_NUM_V  0x7
+#define EFUSE_BLK3_ERR_NUM_S  8
+/* EFUSE_BLK2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of block2 is reliable 1: Means that progra
+mming user data failed and the number of error bytes is over 6..*/
+#define EFUSE_BLK2_FAIL    (BIT(7))
+#define EFUSE_BLK2_FAIL_M  (BIT(7))
+#define EFUSE_BLK2_FAIL_V  0x1
+#define EFUSE_BLK2_FAIL_S  7
+/* EFUSE_BLK2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes in block2..*/
+#define EFUSE_BLK2_ERR_NUM    0x00000007
+#define EFUSE_BLK2_ERR_NUM_M  ((EFUSE_BLK2_ERR_NUM_V)<<(EFUSE_BLK2_ERR_NUM_S))
+#define EFUSE_BLK2_ERR_NUM_V  0x7
+#define EFUSE_BLK2_ERR_NUM_S  4
+/* EFUSE_BLK1_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of block1 is reliable 1: Means that progra
+mming user data failed and the number of error bytes is over 6..*/
+#define EFUSE_BLK1_FAIL    (BIT(3))
+#define EFUSE_BLK1_FAIL_M  (BIT(3))
+#define EFUSE_BLK1_FAIL_V  0x1
+#define EFUSE_BLK1_FAIL_S  3
+/* EFUSE_BLK1_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes in block1..*/
+#define EFUSE_BLK1_ERR_NUM    0x00000007
+#define EFUSE_BLK1_ERR_NUM_M  ((EFUSE_BLK1_ERR_NUM_V)<<(EFUSE_BLK1_ERR_NUM_S))
+#define EFUSE_BLK1_ERR_NUM_V  0x7
+#define EFUSE_BLK1_ERR_NUM_S  0
+
+#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x88)
+/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit and force to enable clock signal of eFuse memory..*/
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (BIT(16))
+#define EFUSE_CLK_EN_V  0x1
+#define EFUSE_CLK_EN_S  16
+/* EFUSE_EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into working mode..*/
+#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_M  (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x1
+#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
+/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x1
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/* EFUSE_EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into power-saving mode..*/
+#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_M  (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x1
+#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
+
+#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x8C)
+/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/
+#define EFUSE_OP_CODE    0x0000FFFF
+#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V  0xFFFF
+#define EFUSE_OP_CODE_S  0
+
+#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x90)
+/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[15:10] ;default: 8'h0 ; */
+/*description: Record the number of bit '1' in BLOCK0..*/
+#define EFUSE_BLK0_VALID_BIT_CNT    0x0000003F
+#define EFUSE_BLK0_VALID_BIT_CNT_M  ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S))
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x3F
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_IS_SW..*/
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of OTP_PGENB_SW..*/
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_V  0x1
+#define EFUSE_OTP_PGENB_SW_S  8
+/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of OTP_CSB_SW..*/
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (BIT(7))
+#define EFUSE_OTP_CSB_SW_V  0x1
+#define EFUSE_OTP_CSB_SW_S  7
+/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The value of OTP_STROBE_SW..*/
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_V  0x1
+#define EFUSE_OTP_STROBE_SW_S  6
+/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_C_SYNC2..*/
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of OTP_LOAD_SW..*/
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_V  0x1
+#define EFUSE_OTP_LOAD_SW_S  4
+/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Indicates the state of the eFuse state machine..*/
+#define EFUSE_STATE    0x0000000F
+#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
+#define EFUSE_STATE_V  0xF
+#define EFUSE_STATE_S  0
+
+#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x94)
+/* EFUSE_BLK_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: The serial number of the block to be programmed. Value 0-3 corresponds to block
+number 0-3, respectively..*/
+#define EFUSE_BLK_NUM    0x00000003
+#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
+#define EFUSE_BLK_NUM_V  0x3
+#define EFUSE_BLK_NUM_S  2
+/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to send programming command..*/
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (BIT(1))
+#define EFUSE_PGM_CMD_V  0x1
+#define EFUSE_PGM_CMD_S  1
+/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to send read command..*/
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (BIT(0))
+#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_S  0
+
+#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x98)
+/* EFUSE_PGM_DONE_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V  0x1
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+/* EFUSE_READ_DONE_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_S  0
+
+#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x9C)
+/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V  0x1
+#define EFUSE_PGM_DONE_INT_ST_S  1
+/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_S  0
+
+#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V  0x1
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_S  0
+
+#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear signal for pgm_done interrupt..*/
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V  0x1
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear signal for read_done interrupt..*/
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_S  0
+
+#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Reduces the power supply of the programming voltage..*/
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (BIT(17))
+#define EFUSE_OE_CLR_V  0x1
+#define EFUSE_OE_CLR_S  17
+/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
+/*description: Controls the rising period of the programming voltage..*/
+#define EFUSE_DAC_NUM    0x000000FF
+#define EFUSE_DAC_NUM_M  ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
+#define EFUSE_DAC_NUM_V  0xFF
+#define EFUSE_DAC_NUM_S  9
+/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Don't care..*/
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */
+/*description: Controls the division factor of the rising clock of the programming voltage..*/
+#define EFUSE_DAC_CLK_DIV    0x000000FF
+#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V  0xFF
+#define EFUSE_DAC_CLK_DIV_S  0
+
+#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x10C)
+/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
+/*description: Configures the initial read time of eFuse..*/
+#define EFUSE_READ_INIT_NUM    0x000000FF
+#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
+#define EFUSE_READ_INIT_NUM_V  0xFF
+#define EFUSE_READ_INIT_NUM_S  24
+/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
+/*description: Configures setup time for efuse read..*/
+#define EFUSE_TSUR_A    0x000000FF
+#define EFUSE_TSUR_A_M  ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
+#define EFUSE_TSUR_A_V  0xFF
+#define EFUSE_TSUR_A_S  16
+/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: Configures pulse time for efuse read..*/
+#define EFUSE_TRD    0x000000FF
+#define EFUSE_TRD_M  ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
+#define EFUSE_TRD_V  0xFF
+#define EFUSE_TRD_S  8
+/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: Configures hold time for efuse read..*/
+#define EFUSE_THR_A    0x000000FF
+#define EFUSE_THR_A_M  ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
+#define EFUSE_THR_A_V  0xFF
+#define EFUSE_THR_A_S  0
+
+#define EFUSE_WR_TIM_CONF0_REG          (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */
+/*description: Configures pulse time for burning '1' bit..*/
+#define EFUSE_TPGM    0x0000FFFF
+#define EFUSE_TPGM_M  ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
+#define EFUSE_TPGM_V  0xFFFF
+#define EFUSE_TPGM_S  16
+/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: Configures pulse time for burning '0' bit..*/
+#define EFUSE_TPGM_INACTIVE    0x000000FF
+#define EFUSE_TPGM_INACTIVE_M  ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
+#define EFUSE_TPGM_INACTIVE_V  0xFF
+#define EFUSE_TPGM_INACTIVE_S  8
+/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: Configures hold time for efuse program..*/
+#define EFUSE_THP_A    0x000000FF
+#define EFUSE_THP_A_M  ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
+#define EFUSE_THP_A_V  0xFF
+#define EFUSE_THP_A_S  0
+
+#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h3000 ; */
+/*description: Configures the power up time for VDDQ..*/
+#define EFUSE_PWR_ON_NUM    0x0000FFFF
+#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
+#define EFUSE_PWR_ON_NUM_V  0xFFFF
+#define EFUSE_PWR_ON_NUM_S  8
+/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: Configures setup time for efuse program..*/
+#define EFUSE_TSUP_A    0x000000FF
+#define EFUSE_TSUP_A_M  ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
+#define EFUSE_TSUP_A_V  0xFF
+#define EFUSE_TSUP_A_S  0
+
+#define EFUSE_WR_TIM_CONF2_REG          (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */
+/*description: Configures the power outage time for VDDQ..*/
+#define EFUSE_PWR_OFF_NUM    0x0000FFFF
+#define EFUSE_PWR_OFF_NUM_M  ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
+#define EFUSE_PWR_OFF_NUM_V  0xFFFF
+#define EFUSE_PWR_OFF_NUM_S  0
+
+#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
+/*description: Stores eFuse version..*/
+#define EFUSE_DATE    0x0FFFFFFF
+#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V  0xFFFFFFF
+#define EFUSE_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EFUSE_REG_H_ */

components/soc/esp8684/include/soc/efuse_struct.h

@@ -0,0 +1,348 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EFUSE_STRUCT_H_
+#define _SOC_EFUSE_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct efuse_dev_s {
+    uint32_t pgm_data0;
+    uint32_t pgm_data1;
+    uint32_t pgm_data2;
+    uint32_t pgm_data3;
+    uint32_t pgm_data4;
+    uint32_t pgm_data5;
+    uint32_t pgm_data6;
+    uint32_t pgm_data7;
+    uint32_t pgm_check_value0;
+    uint32_t pgm_check_value1;
+    uint32_t pgm_check_value2;
+    union {
+        struct {
+            uint32_t reg_wr_dis                    :    8;  /*Disable programming of individual eFuses.*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_wr_dis;
+    union {
+        struct {
+            uint32_t reg_rd_dis                    :    2;  /*The bit be set to disable software read high/low 128-bit of BLK3.*/
+            uint32_t reg_wdt_delay_sel             :    2;  /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
+            uint32_t reg_dis_pad_jtag              :    1;  /*Set this bit to disable pad jtag.*/
+            uint32_t reg_dis_download_icache       :    1;  /*The bit be set to disable icache in download mode.*/
+            uint32_t reg_dis_download_manual_encrypt:    1;  /*The bit be set to disable manual encryption.*/
+            uint32_t reg_spi_boot_encrypt_decrypt_cnt:    3;  /*These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
+            uint32_t reg_xts_key_length_256        :    1;  /*The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3.*/
+            uint32_t reg_uart_print_control        :    2;  /*Set this bit to disable usb printing.*/
+            uint32_t reg_force_send_resume         :    1;  /*Set this bit to force ROM code to send a resume command during SPI boot.*/
+            uint32_t reg_dis_download_mode         :    1;  /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).*/
+            uint32_t reg_dis_direct_boot           :    1;  /*This bit set means disable direct_boot mode.*/
+            uint32_t reg_enable_security_download  :    1;  /*Set this bit to enable secure UART download mode.*/
+            uint32_t reg_flash_tpuw                :    4;  /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value.  Otherwise, the waiting time is twice the configurable value.*/
+            uint32_t reg_secure_boot_en            :    1;  /*The bit be set to enable secure boot.*/
+            uint32_t reg_rpt4_reserved             :    10;  /*Reserved (used for four backups method).*/
+        };
+        uint32_t val;
+    } rd_repeat_data0;
+    uint32_t rd_blk1_data0;
+    uint32_t rd_blk1_data1;
+    union {
+        struct {
+            uint32_t reg_system_data2              :    24;  /*Stores the bits [64:87] of system data.*/
+            uint32_t reserved24                    :    8;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_blk1_data2;
+    uint32_t rd_blk2_data0;
+    union {
+        struct {
+            uint32_t reg_mac_id_high               :    16;  /*Store the bit [31:47] of MAC.*/
+            uint32_t reg_wafer_version             :    3;  /*Store wafer version.*/
+            uint32_t reg_pkg_version               :    3;  /*Store package version.*/
+            uint32_t reg_blk2_efuse_version        :    3;  /*Store efuse version.*/
+            uint32_t reg_rf_ref_i_bias_config      :    4;  /*Store rf configuration parameters.*/
+            uint32_t reg_ldo_vol_bias_config_low   :    3;  /*Store the bit [0:2] of ido configuration parameters.*/
+        };
+        uint32_t val;
+    } rd_blk2_data1;
+    union {
+        struct {
+            uint32_t reg_ldo_vol_bias_config_high  :    27;  /*Store the bit [3:29] of ido configuration parameters.*/
+            uint32_t reg_pvt_low                   :    5;  /*Store the bit [0:4] of pvt.*/
+        };
+        uint32_t val;
+    } rd_blk2_data2;
+    union {
+        struct {
+            uint32_t reg_pvt_high                  :    10;  /*Store the bit [5:14] of pvt.*/
+            uint32_t reg_adc_calibration_0         :    22;  /*Store the bit [0:21] of ADC calibration data.*/
+        };
+        uint32_t val;
+    } rd_blk2_data3;
+    uint32_t rd_blk2_data4;
+    uint32_t rd_blk2_data5;
+    union {
+        struct {
+            uint32_t reg_adc_calibration_3         :    11;  /*Store the bit [86:96] of ADC calibration data.*/
+            uint32_t reg_blk2_reserved_data_0      :    21;  /*Store the bit [0:20] of block2 reserved data.*/
+        };
+        uint32_t val;
+    } rd_blk2_data6;
+    uint32_t rd_blk2_data7;
+    uint32_t rd_blk3_data0;
+    uint32_t rd_blk3_data1;
+    uint32_t rd_blk3_data2;
+    uint32_t rd_blk3_data3;
+    uint32_t rd_blk3_data4;
+    uint32_t rd_blk3_data5;
+    uint32_t rd_blk3_data6;
+    uint32_t rd_blk3_data7;
+    union {
+        struct {
+            uint32_t reg_rd_dis_err                :    2;  /*If any bit in RD_DIS is 1, then it indicates a programming error.*/
+            uint32_t reg_wdt_delay_sel_err         :    2;  /*If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.*/
+            uint32_t reg_dis_pad_jtag_err          :    1;  /*If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.*/
+            uint32_t reg_dis_download_icache       :    1;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_dis_download_manual_encrypt_err:    1;  /*If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.*/
+            uint32_t reg_spi_boot_encrypt_decrypt_cnt_err:    3;  /*If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error.*/
+            uint32_t reg_xts_key_length_256_err    :    1;  /*If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.*/
+            uint32_t reg_uart_print_control_err    :    2;  /*If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.*/
+            uint32_t reg_force_send_resume_err     :    1;  /*If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.*/
+            uint32_t reg_dis_download_mode_err     :    1;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_dis_direct_boot_err       :    1;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_enable_security_download_err:    1;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_flash_tpuw_err            :    4;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_secure_boot_en_err        :    1;  /*If any bit in this filed is 1, then it indicates a programming error.*/
+            uint32_t reg_rpt4_reserved_err         :    10;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_err;
+    union {
+        struct {
+            uint32_t blk1_err_num                  :    3;  /*The value of this signal means the number of error bytes in block1.*/
+            uint32_t blk1_fail                     :    1;  /*0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t blk2_err_num                  :    3;  /*The value of this signal means the number of error bytes in block2.*/
+            uint32_t blk2_fail                     :    1;  /*0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t blk3_err_num                  :    3;  /*The value of this signal means the number of error bytes in block3.*/
+            uint32_t blk3_fail                     :    1;  /*0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t reserved12                    :    20;  /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_rs_err;
+    union {
+        struct {
+            uint32_t reg_efuse_mem_force_pd        :    1;  /*Set this bit to force eFuse SRAM into power-saving mode.*/
+            uint32_t reg_mem_clk_force_on          :    1;  /*Set this bit and force to activate clock signal of eFuse SRAM.*/
+            uint32_t reg_efuse_mem_force_pu        :    1;  /*Set this bit to force eFuse SRAM into working mode.*/
+            uint32_t reserved3                     :    13;  /*Reserved.*/
+            uint32_t reg_clk_en                    :    1;  /*Set this bit and force to enable clock signal of eFuse memory.*/
+            uint32_t reserved17                    :    15;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk;
+    union {
+        struct {
+            uint32_t reg_op_code                   :    16;  /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
+            uint32_t reserved16                    :    16;  /*Reserved.*/
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t reg_state                     :    4;  /*Indicates the state of the eFuse state machine.*/
+            uint32_t reg_otp_load_sw               :    1;  /*The value of OTP_LOAD_SW.*/
+            uint32_t reg_otp_vddq_c_sync2          :    1;  /*The value of OTP_VDDQ_C_SYNC2.*/
+            uint32_t reg_otp_strobe_sw             :    1;  /*The value of OTP_STROBE_SW.*/
+            uint32_t reg_otp_csb_sw                :    1;  /*The value of OTP_CSB_SW.*/
+            uint32_t reg_otp_pgenb_sw              :    1;  /*The value of OTP_PGENB_SW.*/
+            uint32_t reg_otp_vddq_is_sw            :    1;  /*The value of OTP_VDDQ_IS_SW.*/
+            uint32_t reg_blk0_valid_bit_cnt        :    6;  /*Record the number of bit '1' in BLOCK0.*/
+            uint32_t reserved16                    :    16;  /*Reserved.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t reg_read_cmd                  :    1;  /*Set this bit to send read command.*/
+            uint32_t reg_pgm_cmd                   :    1;  /*Set this bit to send programming command.*/
+            uint32_t reg_blk_num                   :    2;  /*The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively.*/
+            uint32_t reserved4                     :    28;  /*Reserved.*/
+        };
+        uint32_t val;
+    } cmd;
+    union {
+        struct {
+            uint32_t reg_read_done_int_raw         :    1;  /*The raw bit signal for read_done interrupt.*/
+            uint32_t reg_pgm_done_int_raw          :    1;  /*The raw bit signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t reg_read_done_int_st          :    1;  /*The status signal for read_done interrupt.*/
+            uint32_t reg_pgm_done_int_st           :    1;  /*The status signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    union {
+        struct {
+            uint32_t reg_read_done_int_ena         :    1;  /*The enable signal for read_done interrupt.*/
+            uint32_t reg_pgm_done_int_ena          :    1;  /*The enable signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t reg_read_done_int_clr         :    1;  /*The clear signal for read_done interrupt.*/
+            uint32_t reg_pgm_done_int_clr          :    1;  /*The clear signal for pgm_done interrupt.*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t reg_dac_clk_div               :    8;  /*Controls the division factor of the rising clock of the programming voltage.*/
+            uint32_t reg_dac_clk_pad_sel           :    1;  /*Don't care.*/
+            uint32_t reg_dac_num                   :    8;  /*Controls the rising period of the programming voltage.*/
+            uint32_t reg_oe_clr                    :    1;  /*Reduces the power supply of the programming voltage.*/
+            uint32_t reserved18                    :    14;  /*Reserved.*/
+        };
+        uint32_t val;
+    } dac_conf;
+    union {
+        struct {
+            uint32_t reg_thr_a                     :    8;  /*Configures hold time for efuse read.*/
+            uint32_t reg_trd                       :    8;  /*Configures pulse time for efuse read.*/
+            uint32_t reg_tsur_a                    :    8;  /*Configures setup time for efuse read.*/
+            uint32_t reg_read_init_num             :    8;  /*Configures the initial read time of eFuse.*/
+        };
+        uint32_t val;
+    } rd_tim_conf;
+    union {
+        struct {
+            uint32_t reg_thp_a                     :    8;  /*Configures hold time for efuse program.*/
+            uint32_t reg_tpgm_inactive             :    8;  /*Configures pulse time for burning '0' bit.*/
+            uint32_t reg_tpgm                      :    16;  /*Configures pulse time for burning '1' bit.*/
+        };
+        uint32_t val;
+    } wr_tim_conf0;
+    union {
+        struct {
+            uint32_t reg_tsup_a                    :    8;  /*Configures setup time for efuse program.*/
+            uint32_t reg_pwr_on_num                :    16;  /*Configures the power up time for VDDQ.*/
+            uint32_t reserved24                    :    8;  /*Reserved.*/
+        };
+        uint32_t val;
+    } wr_tim_conf1;
+    union {
+        struct {
+            uint32_t reg_pwr_off_num               :    16;  /*Configures the power outage time for VDDQ.*/
+            uint32_t reserved16                    :    16;  /*Reserved.*/
+        };
+        uint32_t val;
+    } wr_tim_conf2;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t reg_efuse_date                :    28;  /*Stores eFuse version.*/
+            uint32_t reserved28                    :    4;  /*Reserved.*/
+        };
+        uint32_t val;
+    } date;
+} efuse_dev_t;
+extern efuse_dev_t EFUSE;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EFUSE_STRUCT_H_ */

components/soc/esp8684/include/soc/extmem_reg.h

@@ -0,0 +1,661 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0)
+/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
+#define EXTMEM_ICACHE_ENABLE    (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_V  0x1
+#define EXTMEM_ICACHE_ENABLE_S  0
+
+#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x4)
+/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/
+#define EXTMEM_ICACHE_SHUT_DBUS    (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_M  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_DBUS_S  1
+/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/
+#define EXTMEM_ICACHE_SHUT_IBUS    (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_M  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_IBUS_S  0
+
+#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x8)
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU    (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power d
+own.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD    (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of  icache tag memory. 1: close gating, 0:
+ open clock gating..*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON    (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
+
+#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
+/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate invalidate operation is finished..*/
+#define EXTMEM_ICACHE_SYNC_DONE    (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
+#define EXTMEM_ICACHE_SYNC_DONE_S  1
+/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W/SS ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+fter invalidate operation done..*/
+#define EXTMEM_ICACHE_INVALIDATE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x2C)
+/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for clean operations. I
+t should be combined with ICACHE_SYNC_SIZE_REG..*/
+#define EXTMEM_ICACHE_SYNC_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
+#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x30)
+/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
+/*description: The bits are used to configure the length for sync operations. The bits are the
+counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/
+#define EXTMEM_ICACHE_SYNC_SIZE    0x007FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
+#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x54)
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
+/*description: The bits are used to configure the start virtual address of ibus to access flash
+. The register is used to give constraints to ibus access counter..*/
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x58)
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h423fffff ; */
+/*description: The bits are used to configure the end virtual address of ibus to access flash.
+The register is used to give constraints to ibus access counter..*/
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x5C)
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c000000 ; */
+/*description: The bits are used to configure the start virtual address of dbus to access flash
+. The register is used to give constraints to dbus access counter..*/
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x60)
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c3fffff ; */
+/*description: The bits are used to configure the end virtual address of dbus to access flash.
+The register is used to give constraints to dbus access counter..*/
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x64)
+/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus counter..*/
+#define EXTMEM_DBUS_ACS_CNT_CLR    (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_M  (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_CLR_S  1
+/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear ibus counter..*/
+#define EXTMEM_IBUS_ACS_CNT_CLR    (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_M  (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_CLR_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x78)
+/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus counter overflow..*/
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA    (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus counter overflow..*/
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA    (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
+
+#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x7C)
+/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus counter overflow..*/
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR    (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus counter overflow..*/
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR    (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x80)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow
+..*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST    (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
+/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl
+ow..*/
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST    (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
+/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o
+verflow..*/
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST    (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
+/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl
+ow..*/
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST    (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_ST    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x84)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus trying to write icache.*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA    (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
+ dbus is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
+ ibus is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x88)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus trying to write icache.*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR    (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
+dbus is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
+ibus is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x8C)
+/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus trying to write icache.*/
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST    (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_ST    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access icache while the core0_dbus
+is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_ST    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
+/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access  icache while the core0_ibus
+ is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x90)
+/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE0_DBUS_WORLD    (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_DBUS_WORLD_S  3
+/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE0_DBUS_ATTR    0x00000007
+#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
+#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_DBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x94)
+/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
+tication fail..*/
+#define EXTMEM_CORE0_DBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
+#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x98)
+/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE0_IBUS_WORLD    (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_IBUS_WORLD_S  3
+/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
+#define EXTMEM_CORE0_IBUS_ATTR    0x00000007
+#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
+#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_IBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x9C)
+/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
+ntication fail..*/
+#define EXTMEM_CORE0_IBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
+#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0xA0)
+/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
+/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault
+occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
+evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
+ 7: external dma rx. The most significant bit is used to indicate this operation
+ occurs in which one icache..*/
+#define EXTMEM_CACHE_MMU_FAULT_CODE    0x0000000F
+#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
+#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
+#define EXTMEM_CACHE_MMU_FAULT_CODE_S  10
+/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT    0x000000FF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0xFF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xA4)
+/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to indicate the virtual address which cause mmu fault...*/
+#define EXTMEM_CACHE_MMU_FAULT_VADDR    0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
+
+#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xA8)
+/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable wrap around mode when read data from flash..*/
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND    (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
+
+#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xAC)
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU    (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD    (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
+/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable clock gating to save power when access mmu memory, 0:
+enable, 1: disable.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON    (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
+
+#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0xB0)
+/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
+/*description: The bit is used to indicate whether  icache main fsm is in idle state or not. 1:
+ in idle state,  0: not in idle state.*/
+#define EXTMEM_ICACHE_STATE    0x00000FFF
+#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
+#define EXTMEM_ICACHE_STATE_V  0xFFF
+#define EXTMEM_ICACHE_STATE_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0xB4)
+/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT    (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
+/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT    (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0xB8)
+/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo
+ck. 1: close gating, 0: open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_CRYPT    (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
+/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating,
+ 0: open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT    (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
+/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
+ open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT    (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
+
+#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xBC)
+/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR    (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
+/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
+/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ST    (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
+
+#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xC0)
+/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_CLR    (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
+/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_ST    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
+
+#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0xC4)
+/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus.*/
+#define EXTMEM_CACHE_MMU_OWNER    0x0000000F
+#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
+#define EXTMEM_CACHE_MMU_OWNER_V  0xF
+#define EXTMEM_CACHE_MMU_OWNER_S  0
+
+#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0xC8)
+/* EXTMEM_CACHE_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB.*/
+#define EXTMEM_CACHE_MMU_PAGE_SIZE    0x00000003
+#define EXTMEM_CACHE_MMU_PAGE_SIZE_M  ((EXTMEM_CACHE_MMU_PAGE_SIZE_V)<<(EXTMEM_CACHE_MMU_PAGE_SIZE_S))
+#define EXTMEM_CACHE_MMU_PAGE_SIZE_V  0x3
+#define EXTMEM_CACHE_MMU_PAGE_SIZE_S  3
+/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to enable cache trace function..*/
+#define EXTMEM_CACHE_TRACE_ENA    (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_V  0x1
+#define EXTMEM_CACHE_TRACE_ENA_S  2
+/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by sync operation..*/
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT    (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
+/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by preload operation..*/
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT    (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
+
+#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0xCC)
+/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate icache freeze success.*/
+#define EXTMEM_ICACHE_FREEZE_DONE    (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_DONE_S  2
+/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert
+hit if CPU miss.*/
+#define EXTMEM_ICACHE_FREEZE_MODE    (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_MODE_S  1
+/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable icache freeze mode.*/
+#define EXTMEM_ICACHE_FREEZE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
+#define EXTMEM_ICACHE_FREEZE_ENA_S  0
+
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0xD0)
+/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to activate icache atomic operation protection. In this case, sy
+nc/lock operation can not interrupt miss-work. This feature does not work during
+ invalidateAll operation..*/
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
+
+#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0xD4)
+/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to disable request recording which could cause performance issue.*/
+#define EXTMEM_CACHE_REQUEST_BYPASS    (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
+#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
+
+#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x100)
+/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: clock gate enable..*/
+#define EXTMEM_CLK_EN    (BIT(0))
+#define EXTMEM_CLK_EN_M  (BIT(0))
+#define EXTMEM_CLK_EN_V  0x1
+#define EXTMEM_CLK_EN_S  0
+
+#define EXTMEM_REG_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107050 ; */
+/*description: version information.*/
+#define EXTMEM_DATE    0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */

components/soc/esp8684/include/soc/fe_reg.h

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the RF frontend control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
+#define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_M (BIT(5))
+#define FE_IQ_EST_FORCE_PU_V 1
+#define FE_IQ_EST_FORCE_PU_S 5
+#define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_M (BIT(4))
+#define FE_IQ_EST_FORCE_PD_V 1
+#define FE_IQ_EST_FORCE_PD_S 4
+
+#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
+#define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_M (BIT(10))
+#define FE2_TX_INF_FORCE_PU_V 1
+#define FE2_TX_INF_FORCE_PU_S 10
+#define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_M (BIT(9))
+#define FE2_TX_INF_FORCE_PD_V 1
+#define FE2_TX_INF_FORCE_PD_S 9

components/soc/esp8684/include/soc/gdma_channel.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
+#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
+#define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
+#define SOC_GDMA_TRIG_PERIPH_UART0   (2)
+#define SOC_GDMA_TRIG_PERIPH_AES0    (6)
+#define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
+#define SOC_GDMA_TRIG_PERIPH_ADC0    (8)

components/soc/esp8684/include/soc/gdma_reg.h

@@ -0,0 +1,1064 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GDMA_INT_RAW_CH0_REG register
+ *  GDMA_INT_RAW_CH0_REG.
+ */
+#define GDMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0)
+/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define GDMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define GDMA_IN_DONE_CH0_INT_RAW_M  (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S)
+#define GDMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define GDMA_IN_DONE_CH0_INT_RAW_S  0
+/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define GDMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M  (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw
+ *  interrupt is reserved.
+ */
+#define GDMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M  (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define GDMA_OUT_DONE_CH0_INT_RAW    (BIT(3))
+#define GDMA_OUT_DONE_CH0_INT_RAW_M  (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S)
+#define GDMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUT_DONE_CH0_INT_RAW_S  3
+/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define GDMA_OUT_EOF_CH0_INT_RAW    (BIT(4))
+#define GDMA_OUT_EOF_CH0_INT_RAW_M  (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S)
+#define GDMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUT_EOF_CH0_INT_RAW_S  4
+/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define GDMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(5))
+#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M  (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S  5
+/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(6))
+#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S  6
+/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed, but there is no more inlink for Rx channel 0.
+ */
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(7))
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  7
+/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(8))
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  8
+/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define GDMA_INFIFO_OVF_CH0_INT_RAW    (BIT(9))
+#define GDMA_INFIFO_OVF_CH0_INT_RAW_M  (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S)
+#define GDMA_INFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_INFIFO_OVF_CH0_INT_RAW_S  9
+/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define GDMA_INFIFO_UDF_CH0_INT_RAW    (BIT(10))
+#define GDMA_INFIFO_UDF_CH0_INT_RAW_M  (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S)
+#define GDMA_INFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_INFIFO_UDF_CH0_INT_RAW_S  10
+/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+ *  overflow.
+ */
+#define GDMA_OUTFIFO_OVF_CH0_INT_RAW    (BIT(11))
+#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M  (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S)
+#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S  11
+/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+ *  underflow.
+ */
+#define GDMA_OUTFIFO_UDF_CH0_INT_RAW    (BIT(12))
+#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M  (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S)
+#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S  12
+
+/** GDMA_INT_ST_CH0_REG register
+ *  GDMA_INT_ST_CH0_REG.
+ */
+#define GDMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4)
+/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define GDMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define GDMA_IN_DONE_CH0_INT_ST_M  (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S)
+#define GDMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define GDMA_IN_DONE_CH0_INT_ST_S  0
+/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define GDMA_IN_SUC_EOF_CH0_INT_ST_M  (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define GDMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define GDMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define GDMA_IN_ERR_EOF_CH0_INT_ST_M  (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define GDMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define GDMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define GDMA_OUT_DONE_CH0_INT_ST    (BIT(3))
+#define GDMA_OUT_DONE_CH0_INT_ST_M  (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S)
+#define GDMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUT_DONE_CH0_INT_ST_S  3
+/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_EOF_CH0_INT_ST    (BIT(4))
+#define GDMA_OUT_EOF_CH0_INT_ST_M  (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S)
+#define GDMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUT_EOF_CH0_INT_ST_S  4
+/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(5))
+#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M  (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S  5
+/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(6))
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M  (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S  6
+/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(7))
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S  7
+/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(8))
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S  8
+/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_OVF_CH0_INT_ST    (BIT(9))
+#define GDMA_INFIFO_OVF_CH0_INT_ST_M  (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S)
+#define GDMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define GDMA_INFIFO_OVF_CH0_INT_ST_S  9
+/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_UDF_CH0_INT_ST    (BIT(10))
+#define GDMA_INFIFO_UDF_CH0_INT_ST_M  (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S)
+#define GDMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define GDMA_INFIFO_UDF_CH0_INT_ST_S  10
+/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(11))
+#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M  (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S  11
+/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(12))
+#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M  (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S  12
+
+/** GDMA_INT_ENA_CH0_REG register
+ *  GDMA_INT_ENA_CH0_REG.
+ */
+#define GDMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8)
+/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define GDMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define GDMA_IN_DONE_CH0_INT_ENA_M  (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S)
+#define GDMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define GDMA_IN_DONE_CH0_INT_ENA_S  0
+/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M  (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M  (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define GDMA_OUT_DONE_CH0_INT_ENA    (BIT(3))
+#define GDMA_OUT_DONE_CH0_INT_ENA_M  (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S)
+#define GDMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUT_DONE_CH0_INT_ENA_S  3
+/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_EOF_CH0_INT_ENA    (BIT(4))
+#define GDMA_OUT_EOF_CH0_INT_ENA_M  (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S)
+#define GDMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUT_EOF_CH0_INT_ENA_S  4
+/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(5))
+#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M  (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S  5
+/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(6))
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S  6
+/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(7))
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  7
+/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(8))
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  8
+/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_OVF_CH0_INT_ENA    (BIT(9))
+#define GDMA_INFIFO_OVF_CH0_INT_ENA_M  (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S)
+#define GDMA_INFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_INFIFO_OVF_CH0_INT_ENA_S  9
+/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_UDF_CH0_INT_ENA    (BIT(10))
+#define GDMA_INFIFO_UDF_CH0_INT_ENA_M  (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S)
+#define GDMA_INFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_INFIFO_UDF_CH0_INT_ENA_S  10
+/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_OVF_CH0_INT_ENA    (BIT(11))
+#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M  (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S)
+#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S  11
+/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_UDF_CH0_INT_ENA    (BIT(12))
+#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M  (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S)
+#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S  12
+
+/** GDMA_INT_CLR_CH0_REG register
+ *  GDMA_INT_CLR_CH0_REG.
+ */
+#define GDMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc)
+/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define GDMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define GDMA_IN_DONE_CH0_INT_CLR_M  (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S)
+#define GDMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define GDMA_IN_DONE_CH0_INT_CLR_S  0
+/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M  (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define GDMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M  (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define GDMA_OUT_DONE_CH0_INT_CLR    (BIT(3))
+#define GDMA_OUT_DONE_CH0_INT_CLR_M  (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S)
+#define GDMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUT_DONE_CH0_INT_CLR_S  3
+/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_EOF_CH0_INT_CLR    (BIT(4))
+#define GDMA_OUT_EOF_CH0_INT_CLR_M  (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S)
+#define GDMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUT_EOF_CH0_INT_CLR_S  4
+/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(5))
+#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M  (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S  5
+/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(6))
+#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S  6
+/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(7))
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  7
+/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(8))
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  8
+/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_OVF_CH0_INT_CLR    (BIT(9))
+#define GDMA_INFIFO_OVF_CH0_INT_CLR_M  (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S)
+#define GDMA_INFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_INFIFO_OVF_CH0_INT_CLR_S  9
+/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_INFIFO_UDF_CH0_INT_CLR    (BIT(10))
+#define GDMA_INFIFO_UDF_CH0_INT_CLR_M  (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S)
+#define GDMA_INFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_INFIFO_UDF_CH0_INT_CLR_S  10
+/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_OVF_CH0_INT_CLR    (BIT(11))
+#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M  (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S)
+#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S  11
+/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define GDMA_OUTFIFO_UDF_CH0_INT_CLR    (BIT(12))
+#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M  (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S)
+#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S  12
+
+/** GDMA_AHB_TEST_REG register
+ *  GDMA_AHB_TEST_REG.
+ */
+#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40)
+/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define GDMA_AHB_TESTMODE    0x00000007U
+#define GDMA_AHB_TESTMODE_M  (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S)
+#define GDMA_AHB_TESTMODE_V  0x00000007U
+#define GDMA_AHB_TESTMODE_S  0
+/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ *  reserved
+ */
+#define GDMA_AHB_TESTADDR    0x00000003U
+#define GDMA_AHB_TESTADDR_M  (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S)
+#define GDMA_AHB_TESTADDR_V  0x00000003U
+#define GDMA_AHB_TESTADDR_S  4
+
+/** GDMA_MISC_CONF_REG register
+ *  GDMA_MISC_CONF_REG.
+ */
+#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44)
+/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
+ *  Set this bit, then clear this bit to reset the internal ahb FSM.
+ */
+#define GDMA_AHBM_RST_INTER    (BIT(0))
+#define GDMA_AHBM_RST_INTER_M  (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S)
+#define GDMA_AHBM_RST_INTER_V  0x00000001U
+#define GDMA_AHBM_RST_INTER_S  0
+/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable priority arbitration function.
+ */
+#define GDMA_ARB_PRI_DIS    (BIT(2))
+#define GDMA_ARB_PRI_DIS_M  (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S)
+#define GDMA_ARB_PRI_DIS_V  0x00000001U
+#define GDMA_ARB_PRI_DIS_S  2
+/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  reg_clk_en
+ */
+#define GDMA_CLK_EN    (BIT(3))
+#define GDMA_CLK_EN_M  (GDMA_CLK_EN_V << GDMA_CLK_EN_S)
+#define GDMA_CLK_EN_V  0x00000001U
+#define GDMA_CLK_EN_S  3
+
+/** GDMA_DATE_REG register
+ *  GDMA_DATE_REG.
+ */
+#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x48)
+/** GDMA_DATE : R/W; bitpos: [31:0]; default: 34624128;
+ *  register version.
+ */
+#define GDMA_DATE    0xFFFFFFFFU
+#define GDMA_DATE_M  (GDMA_DATE_V << GDMA_DATE_S)
+#define GDMA_DATE_V  0xFFFFFFFFU
+#define GDMA_DATE_S  0
+
+/** GDMA_IN_CONF0_CH0_REG register
+ *  GDMA_IN_CONF0_CH0_REG.
+ */
+#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70)
+/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset GDMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define GDMA_IN_RST_CH0    (BIT(0))
+#define GDMA_IN_RST_CH0_M  (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S)
+#define GDMA_IN_RST_CH0_V  0x00000001U
+#define GDMA_IN_RST_CH0_S  0
+/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define GDMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define GDMA_IN_LOOP_TEST_CH0_M  (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S)
+#define GDMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define GDMA_IN_LOOP_TEST_CH0_S  1
+/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define GDMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define GDMA_INDSCR_BURST_EN_CH0_M  (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S)
+#define GDMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define GDMA_INDSCR_BURST_EN_CH0_S  2
+/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
+ *  when accessing internal SRAM.
+ */
+#define GDMA_IN_DATA_BURST_EN_CH0    (BIT(3))
+#define GDMA_IN_DATA_BURST_EN_CH0_M  (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S)
+#define GDMA_IN_DATA_BURST_EN_CH0_V  0x00000001U
+#define GDMA_IN_DATA_BURST_EN_CH0_S  3
+/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA.
+ */
+#define GDMA_MEM_TRANS_EN_CH0    (BIT(4))
+#define GDMA_MEM_TRANS_EN_CH0_M  (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S)
+#define GDMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define GDMA_MEM_TRANS_EN_CH0_S  4
+
+/** GDMA_IN_CONF1_CH0_REG register
+ *  GDMA_IN_CONF1_CH0_REG.
+ */
+#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74)
+/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define GDMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define GDMA_IN_CHECK_OWNER_CH0_M  (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S)
+#define GDMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define GDMA_IN_CHECK_OWNER_CH0_S  12
+
+/** GDMA_INFIFO_STATUS_CH0_REG register
+ *  GDMA_INFIFO_STATUS_CH0_REG.
+ */
+#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78)
+/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define GDMA_INFIFO_FULL_CH0    (BIT(0))
+#define GDMA_INFIFO_FULL_CH0_M  (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S)
+#define GDMA_INFIFO_FULL_CH0_V  0x00000001U
+#define GDMA_INFIFO_FULL_CH0_S  0
+/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define GDMA_INFIFO_EMPTY_CH0    (BIT(1))
+#define GDMA_INFIFO_EMPTY_CH0_M  (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S)
+#define GDMA_INFIFO_EMPTY_CH0_V  0x00000001U
+#define GDMA_INFIFO_EMPTY_CH0_S  1
+/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define GDMA_INFIFO_CNT_CH0    0x0000003FU
+#define GDMA_INFIFO_CNT_CH0_M  (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S)
+#define GDMA_INFIFO_CNT_CH0_V  0x0000003FU
+#define GDMA_INFIFO_CNT_CH0_S  2
+/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define GDMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define GDMA_IN_REMAIN_UNDER_1B_CH0_M  (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define GDMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define GDMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define GDMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define GDMA_IN_REMAIN_UNDER_2B_CH0_M  (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define GDMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define GDMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define GDMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define GDMA_IN_REMAIN_UNDER_3B_CH0_M  (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define GDMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define GDMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define GDMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define GDMA_IN_REMAIN_UNDER_4B_CH0_M  (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define GDMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define GDMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define GDMA_IN_BUF_HUNGRY_CH0    (BIT(27))
+#define GDMA_IN_BUF_HUNGRY_CH0_M  (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S)
+#define GDMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define GDMA_IN_BUF_HUNGRY_CH0_S  27
+
+/** GDMA_IN_POP_CH0_REG register
+ *  GDMA_IN_POP_CH0_REG.
+ */
+#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c)
+/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from GDMA FIFO.
+ */
+#define GDMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define GDMA_INFIFO_RDATA_CH0_M  (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S)
+#define GDMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define GDMA_INFIFO_RDATA_CH0_S  0
+/** GDMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from GDMA FIFO.
+ */
+#define GDMA_INFIFO_POP_CH0    (BIT(12))
+#define GDMA_INFIFO_POP_CH0_M  (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S)
+#define GDMA_INFIFO_POP_CH0_V  0x00000001U
+#define GDMA_INFIFO_POP_CH0_S  12
+
+/** GDMA_IN_LINK_CH0_REG register
+ *  GDMA_IN_LINK_CH0_REG.
+ */
+#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80)
+/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define GDMA_INLINK_ADDR_CH0    0x000FFFFFU
+#define GDMA_INLINK_ADDR_CH0_M  (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S)
+#define GDMA_INLINK_ADDR_CH0_V  0x000FFFFFU
+#define GDMA_INLINK_ADDR_CH0_S  0
+/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define GDMA_INLINK_AUTO_RET_CH0    (BIT(20))
+#define GDMA_INLINK_AUTO_RET_CH0_M  (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S)
+#define GDMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define GDMA_INLINK_AUTO_RET_CH0_S  20
+/** GDMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define GDMA_INLINK_STOP_CH0    (BIT(21))
+#define GDMA_INLINK_STOP_CH0_M  (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S)
+#define GDMA_INLINK_STOP_CH0_V  0x00000001U
+#define GDMA_INLINK_STOP_CH0_S  21
+/** GDMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define GDMA_INLINK_START_CH0    (BIT(22))
+#define GDMA_INLINK_START_CH0_M  (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S)
+#define GDMA_INLINK_START_CH0_V  0x00000001U
+#define GDMA_INLINK_START_CH0_S  22
+/** GDMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define GDMA_INLINK_RESTART_CH0    (BIT(23))
+#define GDMA_INLINK_RESTART_CH0_M  (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S)
+#define GDMA_INLINK_RESTART_CH0_V  0x00000001U
+#define GDMA_INLINK_RESTART_CH0_S  23
+/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define GDMA_INLINK_PARK_CH0    (BIT(24))
+#define GDMA_INLINK_PARK_CH0_M  (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S)
+#define GDMA_INLINK_PARK_CH0_V  0x00000001U
+#define GDMA_INLINK_PARK_CH0_S  24
+
+/** GDMA_IN_STATE_CH0_REG register
+ *  GDMA_IN_STATE_CH0_REG.
+ */
+#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84)
+/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define GDMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define GDMA_INLINK_DSCR_ADDR_CH0_M  (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S)
+#define GDMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define GDMA_INLINK_DSCR_ADDR_CH0_S  0
+/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define GDMA_IN_DSCR_STATE_CH0    0x00000003U
+#define GDMA_IN_DSCR_STATE_CH0_M  (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S)
+#define GDMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define GDMA_IN_DSCR_STATE_CH0_S  18
+/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define GDMA_IN_STATE_CH0    0x00000007U
+#define GDMA_IN_STATE_CH0_M  (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S)
+#define GDMA_IN_STATE_CH0_V  0x00000007U
+#define GDMA_IN_STATE_CH0_S  20
+
+/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+ */
+#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88)
+/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define GDMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M  (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+ */
+#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c)
+/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define GDMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M  (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** GDMA_IN_DSCR_CH0_REG register
+ *  GDMA_IN_DSCR_CH0_REG.
+ */
+#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90)
+/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define GDMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_CH0_M  (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S)
+#define GDMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_CH0_S  0
+
+/** GDMA_IN_DSCR_BF0_CH0_REG register
+ *  GDMA_IN_DSCR_BF0_CH0_REG.
+ */
+#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94)
+/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define GDMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_BF0_CH0_M  (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S)
+#define GDMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** GDMA_IN_DSCR_BF1_CH0_REG register
+ *  GDMA_IN_DSCR_BF1_CH0_REG.
+ */
+#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98)
+/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define GDMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_BF1_CH0_M  (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S)
+#define GDMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define GDMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** GDMA_IN_PRI_CH0_REG register
+ *  GDMA_IN_PRI_CH0_REG.
+ */
+#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c)
+/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value, the higher of the priority.
+ */
+#define GDMA_RX_PRI_CH0    0x0000000FU
+#define GDMA_RX_PRI_CH0_M  (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S)
+#define GDMA_RX_PRI_CH0_V  0x0000000FU
+#define GDMA_RX_PRI_CH0_S  0
+
+/** GDMA_IN_PERI_SEL_CH0_REG register
+ *  GDMA_IN_PERI_SEL_CH0_REG.
+ */
+#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0)
+/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved.
+ *  2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+ */
+#define GDMA_PERI_IN_SEL_CH0    0x0000003FU
+#define GDMA_PERI_IN_SEL_CH0_M  (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S)
+#define GDMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define GDMA_PERI_IN_SEL_CH0_S  0
+
+/** GDMA_OUT_CONF0_CH0_REG register
+ *  GDMA_OUT_CONF0_CH0_REG.
+ */
+#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0)
+/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer.
+ */
+#define GDMA_OUT_RST_CH0    (BIT(0))
+#define GDMA_OUT_RST_CH0_M  (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S)
+#define GDMA_OUT_RST_CH0_V  0x00000001U
+#define GDMA_OUT_RST_CH0_S  0
+/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define GDMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define GDMA_OUT_LOOP_TEST_CH0_M  (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S)
+#define GDMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define GDMA_OUT_LOOP_TEST_CH0_S  1
+/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define GDMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define GDMA_OUT_AUTO_WRBACK_CH0_M  (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S)
+#define GDMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define GDMA_OUT_AUTO_WRBACK_CH0_S  2
+/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to transmit has been popped from FIFO in GDMA
+ */
+#define GDMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define GDMA_OUT_EOF_MODE_CH0_M  (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S)
+#define GDMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define GDMA_OUT_EOF_MODE_CH0_S  3
+/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define GDMA_OUTDSCR_BURST_EN_CH0    (BIT(4))
+#define GDMA_OUTDSCR_BURST_EN_CH0_M  (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S)
+#define GDMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define GDMA_OUTDSCR_BURST_EN_CH0_S  4
+/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define GDMA_OUT_DATA_BURST_EN_CH0    (BIT(5))
+#define GDMA_OUT_DATA_BURST_EN_CH0_M  (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S)
+#define GDMA_OUT_DATA_BURST_EN_CH0_V  0x00000001U
+#define GDMA_OUT_DATA_BURST_EN_CH0_S  5
+
+/** GDMA_OUT_CONF1_CH0_REG register
+ *  GDMA_OUT_CONF1_CH0_REG.
+ */
+#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4)
+/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define GDMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define GDMA_OUT_CHECK_OWNER_CH0_M  (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S)
+#define GDMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define GDMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** GDMA_OUTFIFO_STATUS_CH0_REG register
+ *  GDMA_OUTFIFO_STATUS_CH0_REG.
+ */
+#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8)
+/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel 0.
+ */
+#define GDMA_OUTFIFO_FULL_CH0    (BIT(0))
+#define GDMA_OUTFIFO_FULL_CH0_M  (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S)
+#define GDMA_OUTFIFO_FULL_CH0_V  0x00000001U
+#define GDMA_OUTFIFO_FULL_CH0_S  0
+/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel 0.
+ */
+#define GDMA_OUTFIFO_EMPTY_CH0    (BIT(1))
+#define GDMA_OUTFIFO_EMPTY_CH0_M  (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S)
+#define GDMA_OUTFIFO_EMPTY_CH0_V  0x00000001U
+#define GDMA_OUTFIFO_EMPTY_CH0_S  1
+/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define GDMA_OUTFIFO_CNT_CH0    0x0000003FU
+#define GDMA_OUTFIFO_CNT_CH0_M  (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S)
+#define GDMA_OUTFIFO_CNT_CH0_V  0x0000003FU
+#define GDMA_OUTFIFO_CNT_CH0_S  2
+/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define GDMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M  (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define GDMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M  (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define GDMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M  (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define GDMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M  (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+
+/** GDMA_OUT_PUSH_CH0_REG register
+ *  GDMA_OUT_PUSH_CH0_REG.
+ */
+#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc)
+/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into GDMA FIFO.
+ */
+#define GDMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define GDMA_OUTFIFO_WDATA_CH0_M  (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S)
+#define GDMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define GDMA_OUTFIFO_WDATA_CH0_S  0
+/** GDMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0;
+ *  Set this bit to push data into GDMA FIFO.
+ */
+#define GDMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define GDMA_OUTFIFO_PUSH_CH0_M  (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S)
+#define GDMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define GDMA_OUTFIFO_PUSH_CH0_S  9
+
+/** GDMA_OUT_LINK_CH0_REG register
+ *  GDMA_OUT_LINK_CH0_REG.
+ */
+#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0)
+/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define GDMA_OUTLINK_ADDR_CH0    0x000FFFFFU
+#define GDMA_OUTLINK_ADDR_CH0_M  (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S)
+#define GDMA_OUTLINK_ADDR_CH0_V  0x000FFFFFU
+#define GDMA_OUTLINK_ADDR_CH0_S  0
+/** GDMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define GDMA_OUTLINK_STOP_CH0    (BIT(20))
+#define GDMA_OUTLINK_STOP_CH0_M  (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S)
+#define GDMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define GDMA_OUTLINK_STOP_CH0_S  20
+/** GDMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define GDMA_OUTLINK_START_CH0    (BIT(21))
+#define GDMA_OUTLINK_START_CH0_M  (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S)
+#define GDMA_OUTLINK_START_CH0_V  0x00000001U
+#define GDMA_OUTLINK_START_CH0_S  21
+/** GDMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define GDMA_OUTLINK_RESTART_CH0    (BIT(22))
+#define GDMA_OUTLINK_RESTART_CH0_M  (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S)
+#define GDMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define GDMA_OUTLINK_RESTART_CH0_S  22
+/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define GDMA_OUTLINK_PARK_CH0    (BIT(23))
+#define GDMA_OUTLINK_PARK_CH0_M  (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S)
+#define GDMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define GDMA_OUTLINK_PARK_CH0_S  23
+
+/** GDMA_OUT_STATE_CH0_REG register
+ *  GDMA_OUT_STATE_CH0_REG.
+ */
+#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4)
+/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define GDMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define GDMA_OUTLINK_DSCR_ADDR_CH0_M  (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define GDMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define GDMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define GDMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define GDMA_OUT_DSCR_STATE_CH0_M  (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S)
+#define GDMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define GDMA_OUT_DSCR_STATE_CH0_S  18
+/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define GDMA_OUT_STATE_CH0    0x00000007U
+#define GDMA_OUT_STATE_CH0_M  (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S)
+#define GDMA_OUT_STATE_CH0_V  0x00000007U
+#define GDMA_OUT_STATE_CH0_S  20
+
+/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  GDMA_OUT_EOF_DES_ADDR_CH0_REG.
+ */
+#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8)
+/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define GDMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define GDMA_OUT_EOF_DES_ADDR_CH0_M  (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S)
+#define GDMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define GDMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+ */
+#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec)
+/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** GDMA_OUT_DSCR_CH0_REG register
+ *  GDMA_OUT_DSCR_CH0_REG.
+ */
+#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0)
+/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define GDMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_CH0_M  (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S)
+#define GDMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_CH0_S  0
+
+/** GDMA_OUT_DSCR_BF0_CH0_REG register
+ *  GDMA_OUT_DSCR_BF0_CH0_REG.
+ */
+#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4)
+/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define GDMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_BF0_CH0_M  (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S)
+#define GDMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** GDMA_OUT_DSCR_BF1_CH0_REG register
+ *  GDMA_OUT_DSCR_BF1_CH0_REG.
+ */
+#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8)
+/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define GDMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_BF1_CH0_M  (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S)
+#define GDMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define GDMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** GDMA_OUT_PRI_CH0_REG register
+ *  GDMA_OUT_PRI_CH0_REG.
+ */
+#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc)
+/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel 0. The larger of the value, the higher of the priority.
+ */
+#define GDMA_TX_PRI_CH0    0x0000000FU
+#define GDMA_TX_PRI_CH0_M  (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S)
+#define GDMA_TX_PRI_CH0_V  0x0000000FU
+#define GDMA_TX_PRI_CH0_S  0
+
+/** GDMA_OUT_PERI_SEL_CH0_REG register
+ *  GDMA_OUT_PERI_SEL_CH0_REG.
+ */
+#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100)
+/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved.
+ *  2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+ */
+#define GDMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define GDMA_PERI_OUT_SEL_CH0_M  (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S)
+#define GDMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define GDMA_PERI_OUT_SEL_CH0_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/gdma_struct.h

@@ -0,0 +1,323 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GDMA_STRUCT_H_
+#define _SOC_GDMA_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct gdma_dev_s {
+    struct {
+        union {
+            struct {
+                uint32_t in_done                       :    1;  /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
+                uint32_t in_suc_eof                    :    1;  /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
+                uint32_t in_err_eof                    :    1;  /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
+                uint32_t out_done                      :    1;  /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
+                uint32_t out_eof                       :    1;  /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
+                uint32_t in_dscr_err                   :    1;  /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
+                uint32_t out_dscr_err                  :    1;  /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
+                uint32_t in_dscr_empty                 :    1;  /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
+                uint32_t out_total_eof                 :    1;  /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
+                uint32_t infifo_ovf                    :    1;  /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
+                uint32_t infifo_udf                    :    1;  /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
+                uint32_t outfifo_ovf                   :    1;  /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
+                uint32_t outfifo_udf                   :    1;  /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
+                uint32_t reserved13                    :    19;  /*reserved*/
+            };
+            uint32_t val;
+        } raw;
+        union {
+            struct {
+                uint32_t in_done                       :    1;  /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof                    :    1;  /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof                    :    1;  /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done                      :    1;  /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof                       :    1;  /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err                   :    1;  /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err                  :    1;  /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty                 :    1;  /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof                 :    1;  /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf                    :    1;  /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf                    :    1;  /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf                   :    1;  /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf                   :    1;  /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13                    :    19;  /*reserved*/
+            };
+            uint32_t val;
+        } st;
+        union {
+            struct {
+                uint32_t in_done                       :    1;  /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof                    :    1;  /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof                    :    1;  /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done                      :    1;  /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof                       :    1;  /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err                   :    1;  /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err                  :    1;  /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty                 :    1;  /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof                 :    1;  /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf                    :    1;  /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf                    :    1;  /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf                   :    1;  /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf                   :    1;  /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13                    :    19;  /*reserved*/
+            };
+            uint32_t val;
+        } ena;
+        union {
+            struct {
+                uint32_t in_done                       :    1;  /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof                    :    1;  /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof                    :    1;  /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done                      :    1;  /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof                       :    1;  /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err                   :    1;  /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err                  :    1;  /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty                 :    1;  /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof                 :    1;  /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf                    :    1;  /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf                    :    1;  /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf                   :    1;  /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf                   :    1;  /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13                    :    19;  /*reserved*/
+            };
+            uint32_t val;
+        } clr;
+    } intr[1];
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    uint32_t reserved_1c;
+    uint32_t reserved_20;
+    uint32_t reserved_24;
+    uint32_t reserved_28;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    union {
+        struct {
+            uint32_t ahb_testmode                  :    3;  /*reserved*/
+            uint32_t reserved3                     :    1;  /*reserved*/
+            uint32_t ahb_testaddr                  :    2;  /*reserved*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } ahb_test;
+    union {
+        struct {
+            uint32_t ahbm_rst_inter                :    1;  /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
+            uint32_t reserved1                     :    1;
+            uint32_t arb_pri_dis                   :    1;  /*Set this bit to disable priority arbitration function.*/
+            uint32_t clk_en                        :    1;  /*reg_clk_en*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } misc_conf;
+    uint32_t date;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t in_rst                        :    1;  /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
+                    uint32_t in_loop_test                  :    1;  /*reserved*/
+                    uint32_t indscr_burst_en               :    1;  /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
+                    uint32_t in_data_burst_en              :    1;  /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
+                    uint32_t mem_trans_en                  :    1;  /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
+                    uint32_t reserved5                     :    27;  /*reserved*/
+                };
+                uint32_t val;
+            } in_conf0;
+            union {
+                struct {
+                    uint32_t reserved0                     :    12;
+                    uint32_t in_check_owner                :    1;  /*Set this bit to enable checking the owner attribute of the link descriptor.*/
+                    uint32_t reserved13                    :    19;  /*reserved*/
+                };
+                uint32_t val;
+            } in_conf1;
+            union {
+                struct {
+                    uint32_t infifo_full                   :    1;  /*L1 Rx FIFO full signal for Rx channel 0.*/
+                    uint32_t infifo_empty                  :    1;  /*L1 Rx FIFO empty signal for Rx channel 0.*/
+                    uint32_t infifo_cnt                    :    6;  /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
+                    uint32_t reserved8                     :    15;  /*reserved*/
+                    uint32_t in_remain_under_1b            :    1;  /*reserved*/
+                    uint32_t in_remain_under_2b            :    1;  /*reserved*/
+                    uint32_t in_remain_under_3b            :    1;  /*reserved*/
+                    uint32_t in_remain_under_4b            :    1;  /*reserved*/
+                    uint32_t in_buf_hungry                 :    1;  /*reserved*/
+                    uint32_t reserved28                    :    4;  /*reserved*/
+                };
+                uint32_t val;
+            } infifo_status;
+            union {
+                struct {
+                    uint32_t infifo_rdata                  :    12;  /*This register stores the data popping from DMA FIFO.*/
+                    uint32_t infifo_pop                    :    1;  /*Set this bit to pop data from DMA FIFO.*/
+                    uint32_t reserved13                    :    19;  /*reserved*/
+                };
+                uint32_t val;
+            } in_pop;
+            union {
+                struct {
+                    uint32_t addr                          :    20;  /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
+                    uint32_t auto_ret                      :    1;  /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
+                    uint32_t stop                          :    1;  /*Set this bit to stop dealing with the inlink descriptors.*/
+                    uint32_t start                         :    1;  /*Set this bit to start dealing with the inlink descriptors.*/
+                    uint32_t restart                       :    1;  /*Set this bit to mount a new inlink descriptor.*/
+                    uint32_t park                          :    1;  /*1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.*/
+                    uint32_t reserved25                    :    7;
+                };
+                uint32_t val;
+            } in_link;
+            union {
+                struct {
+                    uint32_t dscr_addr                     :    18;  /*This register stores the current inlink descriptor's address.*/
+                    uint32_t in_dscr_state                 :    2;  /*reserved*/
+                    uint32_t in_state                      :    3;  /*reserved*/
+                    uint32_t reserved23                    :    9;  /*reserved*/
+                };
+                uint32_t val;
+            } in_state;
+            uint32_t in_suc_eof_des_addr;
+            uint32_t in_err_eof_des_addr;
+            uint32_t in_dscr;
+            uint32_t in_dscr_bf0;
+            uint32_t in_dscr_bf1;
+            union {
+                struct {
+                    uint32_t rx_pri                        :    4;  /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
+                    uint32_t reserved4                     :    28;
+                };
+                uint32_t val;
+            } in_pri;
+            union {
+                struct {
+                    uint32_t sel                           :    6;  /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+                    uint32_t reserved6                     :    26;
+                };
+                uint32_t val;
+            } in_peri_sel;
+            uint32_t reserved_a4;
+            uint32_t reserved_a8;
+            uint32_t reserved_ac;
+            uint32_t reserved_b0;
+            uint32_t reserved_b4;
+            uint32_t reserved_b8;
+            uint32_t reserved_bc;
+            uint32_t reserved_c0;
+            uint32_t reserved_c4;
+            uint32_t reserved_c8;
+            uint32_t reserved_cc;
+        } in;
+        struct {
+            union {
+                struct {
+                    uint32_t out_rst                       :    1;  /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
+                    uint32_t out_loop_test                 :    1;  /*reserved*/
+                    uint32_t out_auto_wrback               :    1;  /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
+                    uint32_t out_eof_mode                  :    1;  /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
+                    uint32_t outdscr_burst_en              :    1;  /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
+                    uint32_t out_data_burst_en             :    1;  /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
+                    uint32_t reserved6                     :    26;
+                };
+                uint32_t val;
+            } out_conf0;
+            union {
+                struct {
+                    uint32_t reserved0                     :    12;
+                    uint32_t out_check_owner               :    1;  /*Set this bit to enable checking the owner attribute of the link descriptor.*/
+                    uint32_t reserved13                    :    19;  /*reserved*/
+                };
+                uint32_t val;
+            } out_conf1;
+            union {
+                struct {
+                    uint32_t outfifo_full                  :    1;  /*L1 Tx FIFO full signal for Tx channel 0.*/
+                    uint32_t outfifo_empty                 :    1;  /*L1 Tx FIFO empty signal for Tx channel 0.*/
+                    uint32_t outfifo_cnt                   :    6;  /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
+                    uint32_t reserved8                     :    15;  /*reserved*/
+                    uint32_t out_remain_under_1b           :    1;  /*reserved*/
+                    uint32_t out_remain_under_2b           :    1;  /*reserved*/
+                    uint32_t out_remain_under_3b           :    1;  /*reserved*/
+                    uint32_t out_remain_under_4b           :    1;  /*reserved*/
+                    uint32_t reserved27                    :    5;  /*reserved*/
+                };
+                uint32_t val;
+            } outfifo_status;
+            union {
+                struct {
+                    uint32_t outfifo_wdata                 :    9;  /*This register stores the data that need to be pushed into DMA FIFO.*/
+                    uint32_t outfifo_push                  :    1;  /*Set this bit to push data into DMA FIFO.*/
+                    uint32_t reserved10                    :    22;  /*reserved*/
+                };
+                uint32_t val;
+            } out_push;
+            union {
+                struct {
+                    uint32_t addr                          :    20;  /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
+                    uint32_t stop                          :    1;  /*Set this bit to stop dealing with the outlink descriptors.*/
+                    uint32_t start                         :    1;  /*Set this bit to start dealing with the outlink descriptors.*/
+                    uint32_t restart                       :    1;  /*Set this bit to restart a new outlink from the last address. */
+                    uint32_t park                          :    1;  /*1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.*/
+                    uint32_t reserved24                    :    8;
+                };
+                uint32_t val;
+            } out_link;
+            union {
+                struct {
+                    uint32_t dscr_addr                     :    18;  /*This register stores the current outlink descriptor's address.*/
+                    uint32_t out_dscr_state                :    2;  /*reserved*/
+                    uint32_t out_state                     :    3;  /*reserved*/
+                    uint32_t reserved23                    :    9;  /*reserved*/
+                };
+                uint32_t val;
+            } out_state;
+            uint32_t out_eof_des_addr;
+            uint32_t out_eof_bfr_des_addr;
+            uint32_t out_dscr;
+            uint32_t out_dscr_bf0;
+            uint32_t out_dscr_bf1;
+            union {
+                struct {
+                    uint32_t tx_pri                        :    4;  /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
+                    uint32_t reserved4                     :    28;
+                };
+                uint32_t val;
+            } out_pri;
+            union {
+                struct {
+                    uint32_t sel                           :    6;  /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+                    uint32_t reserved6                     :    26;
+                };
+                uint32_t val;
+            } out_peri_sel;
+        } out;
+    } channel[1];
+} gdma_dev_t;
+extern gdma_dev_t GDMA;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_DMA_STRUCT_H_ */

components/soc/esp8684/include/soc/gpio_pins.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/gpio_reg.h

@@ -0,0 +1,6075 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_BT_SELECT_REG register
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SEL    0xFFFFFFFFU
+#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
+#define GPIO_BT_SEL_V  0xFFFFFFFFU
+#define GPIO_BT_SEL_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SS; bitpos: [24:0]; default: 0;
+ *  GPIO output register for GPIO0-24
+ */
+#define GPIO_OUT_DATA_ORIG    0x01FFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0x01FFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output set register for GPIO0-24
+ */
+#define GPIO_OUT_W1TS    0x01FFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0x01FFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output clear register for GPIO0-24
+ */
+#define GPIO_OUT_W1TC    0x01FFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0x01FFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_SDIO_SELECT_REG register
+ *  GPIO sdio select register
+ */
+#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c)
+/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  GPIO sdio select register
+ */
+#define GPIO_SDIO_SEL    0x000000FFU
+#define GPIO_SDIO_SEL_M  (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S)
+#define GPIO_SDIO_SEL_V  0x000000FFU
+#define GPIO_SDIO_SEL_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
+/** GPIO_ENABLE_DATA : R/W/SS; bitpos: [24:0]; default: 0;
+ *  GPIO output enable register for GPIO0-24
+ */
+#define GPIO_ENABLE_DATA    0x01FFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0x01FFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable set register for GPIO0-24
+ */
+#define GPIO_ENABLE_W1TS    0x01FFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0x01FFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable clear register for GPIO0-24
+ */
+#define GPIO_ENABLE_W1TC    0x01FFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0x01FFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_STRAP_REG register
+ *  pad strapping register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  pad strapping register
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO input register for GPIO0-24
+ */
+#define GPIO_IN_DATA_NEXT    0x01FFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0x01FFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
+/** GPIO_STATUS_INTERRUPT : R/W/SS; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status register for GPIO0-24
+ */
+#define GPIO_STATUS_INTERRUPT    0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
+/** GPIO_STATUS_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO0-24
+ */
+#define GPIO_STATUS_W1TS    0x01FFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0x01FFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO0-24
+ */
+#define GPIO_STATUS_W1TC    0x01FFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0x01FFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_PCPU_INT_REG register
+ *  GPIO PRO_CPU interrupt status register
+ */
+#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c)
+/** GPIO_PROCPU_INT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO PRO_CPU interrupt status register for GPIO0-24
+ */
+#define GPIO_PROCPU_INT    0x01FFFFFFU
+#define GPIO_PROCPU_INT_M  (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S)
+#define GPIO_PROCPU_INT_V  0x01FFFFFFU
+#define GPIO_PROCPU_INT_S  0
+
+/** GPIO_PCPU_NMI_INT_REG register
+ *  GPIO PRO_CPU(not shielded) interrupt status register
+ */
+#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60)
+/** GPIO_PROCPU_NMI_INT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24
+ */
+#define GPIO_PROCPU_NMI_INT    0x01FFFFFFU
+#define GPIO_PROCPU_NMI_INT_M  (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S)
+#define GPIO_PROCPU_NMI_INT_V  0x01FFFFFFU
+#define GPIO_PROCPU_NMI_INT_S  0
+
+/** GPIO_CPUSDIO_INT_REG register
+ *  GPIO CPUSDIO interrupt status register
+ */
+#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_SDIO_INT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO CPUSDIO interrupt status register for GPIO0-24
+ */
+#define GPIO_SDIO_INT    0x01FFFFFFU
+#define GPIO_SDIO_INT_M  (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S)
+#define GPIO_SDIO_INT_V  0x01FFFFFFU
+#define GPIO_SDIO_INT_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN0_CONFIG    0x00000003U
+#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
+#define GPIO_PIN0_CONFIG_V  0x00000003U
+#define GPIO_PIN0_CONFIG_S  11
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN1_CONFIG    0x00000003U
+#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
+#define GPIO_PIN1_CONFIG_V  0x00000003U
+#define GPIO_PIN1_CONFIG_S  11
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN2_CONFIG    0x00000003U
+#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
+#define GPIO_PIN2_CONFIG_V  0x00000003U
+#define GPIO_PIN2_CONFIG_S  11
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN3_CONFIG    0x00000003U
+#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
+#define GPIO_PIN3_CONFIG_V  0x00000003U
+#define GPIO_PIN3_CONFIG_S  11
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN4_CONFIG    0x00000003U
+#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
+#define GPIO_PIN4_CONFIG_V  0x00000003U
+#define GPIO_PIN4_CONFIG_S  11
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN5_CONFIG    0x00000003U
+#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
+#define GPIO_PIN5_CONFIG_V  0x00000003U
+#define GPIO_PIN5_CONFIG_S  11
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN6_CONFIG    0x00000003U
+#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
+#define GPIO_PIN6_CONFIG_V  0x00000003U
+#define GPIO_PIN6_CONFIG_S  11
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN7_CONFIG    0x00000003U
+#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
+#define GPIO_PIN7_CONFIG_V  0x00000003U
+#define GPIO_PIN7_CONFIG_S  11
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN8_CONFIG    0x00000003U
+#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
+#define GPIO_PIN8_CONFIG_V  0x00000003U
+#define GPIO_PIN8_CONFIG_S  11
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN9_CONFIG    0x00000003U
+#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
+#define GPIO_PIN9_CONFIG_V  0x00000003U
+#define GPIO_PIN9_CONFIG_S  11
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN10_CONFIG    0x00000003U
+#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
+#define GPIO_PIN10_CONFIG_V  0x00000003U
+#define GPIO_PIN10_CONFIG_S  11
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN11_CONFIG    0x00000003U
+#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
+#define GPIO_PIN11_CONFIG_V  0x00000003U
+#define GPIO_PIN11_CONFIG_S  11
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN12_CONFIG    0x00000003U
+#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
+#define GPIO_PIN12_CONFIG_V  0x00000003U
+#define GPIO_PIN12_CONFIG_S  11
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN13_CONFIG    0x00000003U
+#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
+#define GPIO_PIN13_CONFIG_V  0x00000003U
+#define GPIO_PIN13_CONFIG_S  11
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN14_CONFIG    0x00000003U
+#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
+#define GPIO_PIN14_CONFIG_V  0x00000003U
+#define GPIO_PIN14_CONFIG_S  11
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN15_CONFIG    0x00000003U
+#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
+#define GPIO_PIN15_CONFIG_V  0x00000003U
+#define GPIO_PIN15_CONFIG_S  11
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN16_CONFIG    0x00000003U
+#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
+#define GPIO_PIN16_CONFIG_V  0x00000003U
+#define GPIO_PIN16_CONFIG_S  11
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN17_CONFIG    0x00000003U
+#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
+#define GPIO_PIN17_CONFIG_V  0x00000003U
+#define GPIO_PIN17_CONFIG_S  11
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN18_CONFIG    0x00000003U
+#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
+#define GPIO_PIN18_CONFIG_V  0x00000003U
+#define GPIO_PIN18_CONFIG_S  11
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN19_CONFIG    0x00000003U
+#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
+#define GPIO_PIN19_CONFIG_V  0x00000003U
+#define GPIO_PIN19_CONFIG_S  11
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN20_CONFIG    0x00000003U
+#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
+#define GPIO_PIN20_CONFIG_V  0x00000003U
+#define GPIO_PIN20_CONFIG_S  11
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN21_CONFIG    0x00000003U
+#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
+#define GPIO_PIN21_CONFIG_V  0x00000003U
+#define GPIO_PIN21_CONFIG_S  11
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN22_CONFIG    0x00000003U
+#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
+#define GPIO_PIN22_CONFIG_V  0x00000003U
+#define GPIO_PIN22_CONFIG_S  11
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN23_CONFIG    0x00000003U
+#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
+#define GPIO_PIN23_CONFIG_V  0x00000003U
+#define GPIO_PIN23_CONFIG_S  11
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN24_CONFIG    0x00000003U
+#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
+#define GPIO_PIN24_CONFIG_V  0x00000003U
+#define GPIO_PIN24_CONFIG_S  11
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [25:0]; default: 0;
+ *  GPIO interrupt source register for GPIO0-24
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0x03FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0x03FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_FUNC0_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154)
+/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC0_IN_SEL    0x0000001FU
+#define GPIO_FUNC0_IN_SEL_M  (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
+#define GPIO_FUNC0_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC0_IN_SEL_S  0
+/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC0_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_M  (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
+#define GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_IN_INV_SEL_S  5
+/** GPIO_SIG0_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG0_IN_SEL    (BIT(6))
+#define GPIO_SIG0_IN_SEL_M  (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
+#define GPIO_SIG0_IN_SEL_V  0x00000001U
+#define GPIO_SIG0_IN_SEL_S  6
+
+/** GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158)
+/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC1_IN_SEL    0x0000001FU
+#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
+#define GPIO_FUNC1_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC1_IN_SEL_S  0
+/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
+#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_IN_INV_SEL_S  5
+/** GPIO_SIG1_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG1_IN_SEL    (BIT(6))
+#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
+#define GPIO_SIG1_IN_SEL_V  0x00000001U
+#define GPIO_SIG1_IN_SEL_S  6
+
+/** GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC2_IN_SEL    0x0000001FU
+#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
+#define GPIO_FUNC2_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC2_IN_SEL_S  0
+/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
+#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_IN_INV_SEL_S  5
+/** GPIO_SIG2_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG2_IN_SEL    (BIT(6))
+#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
+#define GPIO_SIG2_IN_SEL_V  0x00000001U
+#define GPIO_SIG2_IN_SEL_S  6
+
+/** GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC3_IN_SEL    0x0000001FU
+#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
+#define GPIO_FUNC3_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC3_IN_SEL_S  0
+/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
+#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_IN_INV_SEL_S  5
+/** GPIO_SIG3_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG3_IN_SEL    (BIT(6))
+#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
+#define GPIO_SIG3_IN_SEL_V  0x00000001U
+#define GPIO_SIG3_IN_SEL_S  6
+
+/** GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC4_IN_SEL    0x0000001FU
+#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
+#define GPIO_FUNC4_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC4_IN_SEL_S  0
+/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
+#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_IN_INV_SEL_S  5
+/** GPIO_SIG4_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG4_IN_SEL    (BIT(6))
+#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
+#define GPIO_SIG4_IN_SEL_V  0x00000001U
+#define GPIO_SIG4_IN_SEL_S  6
+
+/** GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC5_IN_SEL    0x0000001FU
+#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
+#define GPIO_FUNC5_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC5_IN_SEL_S  0
+/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
+#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_IN_INV_SEL_S  5
+/** GPIO_SIG5_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG5_IN_SEL    (BIT(6))
+#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
+#define GPIO_SIG5_IN_SEL_V  0x00000001U
+#define GPIO_SIG5_IN_SEL_S  6
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC6_IN_SEL    0x0000001FU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  5
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(6))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  6
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC7_IN_SEL    0x0000001FU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  5
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(6))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  6
+
+/** GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC8_IN_SEL    0x0000001FU
+#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
+#define GPIO_FUNC8_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC8_IN_SEL_S  0
+/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
+#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_IN_INV_SEL_S  5
+/** GPIO_SIG8_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG8_IN_SEL    (BIT(6))
+#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
+#define GPIO_SIG8_IN_SEL_V  0x00000001U
+#define GPIO_SIG8_IN_SEL_S  6
+
+/** GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
+/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC9_IN_SEL    0x0000001FU
+#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
+#define GPIO_FUNC9_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC9_IN_SEL_S  0
+/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
+#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_IN_INV_SEL_S  5
+/** GPIO_SIG9_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG9_IN_SEL    (BIT(6))
+#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
+#define GPIO_SIG9_IN_SEL_V  0x00000001U
+#define GPIO_SIG9_IN_SEL_S  6
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC10_IN_SEL    0x0000001FU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  5
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(6))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  6
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC11_IN_SEL    0x0000001FU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  5
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(6))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  6
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC12_IN_SEL    0x0000001FU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  5
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(6))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  6
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC13_IN_SEL    0x0000001FU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  5
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(6))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  6
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC14_IN_SEL    0x0000001FU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  5
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(6))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  6
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC15_IN_SEL    0x0000001FU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  5
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(6))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  6
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC16_IN_SEL    0x0000001FU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  5
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(6))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  6
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC17_IN_SEL    0x0000001FU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  5
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(6))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  6
+
+/** GPIO_FUNC18_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
+/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC18_IN_SEL    0x0000001FU
+#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
+#define GPIO_FUNC18_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC18_IN_SEL_S  0
+/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
+#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_IN_INV_SEL_S  5
+/** GPIO_SIG18_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG18_IN_SEL    (BIT(6))
+#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
+#define GPIO_SIG18_IN_SEL_V  0x00000001U
+#define GPIO_SIG18_IN_SEL_S  6
+
+/** GPIO_FUNC19_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
+/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC19_IN_SEL    0x0000001FU
+#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
+#define GPIO_FUNC19_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC19_IN_SEL_S  0
+/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
+#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_IN_INV_SEL_S  5
+/** GPIO_SIG19_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG19_IN_SEL    (BIT(6))
+#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
+#define GPIO_SIG19_IN_SEL_V  0x00000001U
+#define GPIO_SIG19_IN_SEL_S  6
+
+/** GPIO_FUNC20_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
+/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC20_IN_SEL    0x0000001FU
+#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
+#define GPIO_FUNC20_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC20_IN_SEL_S  0
+/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
+#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_IN_INV_SEL_S  5
+/** GPIO_SIG20_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG20_IN_SEL    (BIT(6))
+#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
+#define GPIO_SIG20_IN_SEL_V  0x00000001U
+#define GPIO_SIG20_IN_SEL_S  6
+
+/** GPIO_FUNC21_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
+/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC21_IN_SEL    0x0000001FU
+#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
+#define GPIO_FUNC21_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC21_IN_SEL_S  0
+/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
+#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_IN_INV_SEL_S  5
+/** GPIO_SIG21_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG21_IN_SEL    (BIT(6))
+#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
+#define GPIO_SIG21_IN_SEL_V  0x00000001U
+#define GPIO_SIG21_IN_SEL_S  6
+
+/** GPIO_FUNC22_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
+/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC22_IN_SEL    0x0000001FU
+#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
+#define GPIO_FUNC22_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC22_IN_SEL_S  0
+/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
+#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_IN_INV_SEL_S  5
+/** GPIO_SIG22_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG22_IN_SEL    (BIT(6))
+#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
+#define GPIO_SIG22_IN_SEL_V  0x00000001U
+#define GPIO_SIG22_IN_SEL_S  6
+
+/** GPIO_FUNC23_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
+/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC23_IN_SEL    0x0000001FU
+#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
+#define GPIO_FUNC23_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC23_IN_SEL_S  0
+/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
+#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_IN_INV_SEL_S  5
+/** GPIO_SIG23_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG23_IN_SEL    (BIT(6))
+#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
+#define GPIO_SIG23_IN_SEL_V  0x00000001U
+#define GPIO_SIG23_IN_SEL_S  6
+
+/** GPIO_FUNC24_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
+/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC24_IN_SEL    0x0000001FU
+#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
+#define GPIO_FUNC24_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC24_IN_SEL_S  0
+/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
+#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_IN_INV_SEL_S  5
+/** GPIO_SIG24_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG24_IN_SEL    (BIT(6))
+#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
+#define GPIO_SIG24_IN_SEL_V  0x00000001U
+#define GPIO_SIG24_IN_SEL_S  6
+
+/** GPIO_FUNC25_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
+/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC25_IN_SEL    0x0000001FU
+#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
+#define GPIO_FUNC25_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC25_IN_SEL_S  0
+/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
+#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_IN_INV_SEL_S  5
+/** GPIO_SIG25_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG25_IN_SEL    (BIT(6))
+#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
+#define GPIO_SIG25_IN_SEL_V  0x00000001U
+#define GPIO_SIG25_IN_SEL_S  6
+
+/** GPIO_FUNC26_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
+/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC26_IN_SEL    0x0000001FU
+#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
+#define GPIO_FUNC26_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC26_IN_SEL_S  0
+/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
+#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_IN_INV_SEL_S  5
+/** GPIO_SIG26_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG26_IN_SEL    (BIT(6))
+#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
+#define GPIO_SIG26_IN_SEL_V  0x00000001U
+#define GPIO_SIG26_IN_SEL_S  6
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC27_IN_SEL    0x0000001FU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  5
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(6))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  6
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC28_IN_SEL    0x0000001FU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  5
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(6))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  6
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC29_IN_SEL    0x0000001FU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  5
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(6))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  6
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC30_IN_SEL    0x0000001FU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  5
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(6))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  6
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC31_IN_SEL    0x0000001FU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  5
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(6))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  6
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC32_IN_SEL    0x0000001FU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  5
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(6))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  6
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC33_IN_SEL    0x0000001FU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  5
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(6))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  6
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC34_IN_SEL    0x0000001FU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  5
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(6))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  6
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC35_IN_SEL    0x0000001FU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  5
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(6))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  6
+
+/** GPIO_FUNC36_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
+/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC36_IN_SEL    0x0000001FU
+#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
+#define GPIO_FUNC36_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC36_IN_SEL_S  0
+/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
+#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_IN_INV_SEL_S  5
+/** GPIO_SIG36_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG36_IN_SEL    (BIT(6))
+#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
+#define GPIO_SIG36_IN_SEL_V  0x00000001U
+#define GPIO_SIG36_IN_SEL_S  6
+
+/** GPIO_FUNC37_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
+/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC37_IN_SEL    0x0000001FU
+#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
+#define GPIO_FUNC37_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC37_IN_SEL_S  0
+/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
+#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_IN_INV_SEL_S  5
+/** GPIO_SIG37_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG37_IN_SEL    (BIT(6))
+#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
+#define GPIO_SIG37_IN_SEL_V  0x00000001U
+#define GPIO_SIG37_IN_SEL_S  6
+
+/** GPIO_FUNC38_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
+/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC38_IN_SEL    0x0000001FU
+#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
+#define GPIO_FUNC38_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC38_IN_SEL_S  0
+/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
+#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_IN_INV_SEL_S  5
+/** GPIO_SIG38_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG38_IN_SEL    (BIT(6))
+#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
+#define GPIO_SIG38_IN_SEL_V  0x00000001U
+#define GPIO_SIG38_IN_SEL_S  6
+
+/** GPIO_FUNC39_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
+/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC39_IN_SEL    0x0000001FU
+#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
+#define GPIO_FUNC39_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC39_IN_SEL_S  0
+/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
+#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_IN_INV_SEL_S  5
+/** GPIO_SIG39_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG39_IN_SEL    (BIT(6))
+#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
+#define GPIO_SIG39_IN_SEL_V  0x00000001U
+#define GPIO_SIG39_IN_SEL_S  6
+
+/** GPIO_FUNC40_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
+/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC40_IN_SEL    0x0000001FU
+#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
+#define GPIO_FUNC40_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC40_IN_SEL_S  0
+/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
+#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_IN_INV_SEL_S  5
+/** GPIO_SIG40_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG40_IN_SEL    (BIT(6))
+#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
+#define GPIO_SIG40_IN_SEL_V  0x00000001U
+#define GPIO_SIG40_IN_SEL_S  6
+
+/** GPIO_FUNC41_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
+/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC41_IN_SEL    0x0000001FU
+#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
+#define GPIO_FUNC41_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC41_IN_SEL_S  0
+/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
+#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_IN_INV_SEL_S  5
+/** GPIO_SIG41_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG41_IN_SEL    (BIT(6))
+#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
+#define GPIO_SIG41_IN_SEL_V  0x00000001U
+#define GPIO_SIG41_IN_SEL_S  6
+
+/** GPIO_FUNC42_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
+/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC42_IN_SEL    0x0000001FU
+#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
+#define GPIO_FUNC42_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC42_IN_SEL_S  0
+/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
+#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_IN_INV_SEL_S  5
+/** GPIO_SIG42_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG42_IN_SEL    (BIT(6))
+#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
+#define GPIO_SIG42_IN_SEL_V  0x00000001U
+#define GPIO_SIG42_IN_SEL_S  6
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC43_IN_SEL    0x0000001FU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  5
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(6))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  6
+
+/** GPIO_FUNC44_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
+/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC44_IN_SEL    0x0000001FU
+#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
+#define GPIO_FUNC44_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC44_IN_SEL_S  0
+/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
+#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_IN_INV_SEL_S  5
+/** GPIO_SIG44_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG44_IN_SEL    (BIT(6))
+#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
+#define GPIO_SIG44_IN_SEL_V  0x00000001U
+#define GPIO_SIG44_IN_SEL_S  6
+
+/** GPIO_FUNC45_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
+/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC45_IN_SEL    0x0000001FU
+#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
+#define GPIO_FUNC45_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC45_IN_SEL_S  0
+/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
+#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_IN_INV_SEL_S  5
+/** GPIO_SIG45_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG45_IN_SEL    (BIT(6))
+#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
+#define GPIO_SIG45_IN_SEL_V  0x00000001U
+#define GPIO_SIG45_IN_SEL_S  6
+
+/** GPIO_FUNC46_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
+/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC46_IN_SEL    0x0000001FU
+#define GPIO_FUNC46_IN_SEL_M  (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S)
+#define GPIO_FUNC46_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC46_IN_SEL_S  0
+/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC46_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_M  (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S)
+#define GPIO_FUNC46_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_IN_INV_SEL_S  5
+/** GPIO_SIG46_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG46_IN_SEL    (BIT(6))
+#define GPIO_SIG46_IN_SEL_M  (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S)
+#define GPIO_SIG46_IN_SEL_V  0x00000001U
+#define GPIO_SIG46_IN_SEL_S  6
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC47_IN_SEL    0x0000001FU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  5
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(6))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  6
+
+/** GPIO_FUNC48_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
+/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC48_IN_SEL    0x0000001FU
+#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
+#define GPIO_FUNC48_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC48_IN_SEL_S  0
+/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
+#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_IN_INV_SEL_S  5
+/** GPIO_SIG48_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG48_IN_SEL    (BIT(6))
+#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
+#define GPIO_SIG48_IN_SEL_V  0x00000001U
+#define GPIO_SIG48_IN_SEL_S  6
+
+/** GPIO_FUNC49_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
+/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC49_IN_SEL    0x0000001FU
+#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
+#define GPIO_FUNC49_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC49_IN_SEL_S  0
+/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
+#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_IN_INV_SEL_S  5
+/** GPIO_SIG49_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG49_IN_SEL    (BIT(6))
+#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
+#define GPIO_SIG49_IN_SEL_V  0x00000001U
+#define GPIO_SIG49_IN_SEL_S  6
+
+/** GPIO_FUNC50_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
+/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC50_IN_SEL    0x0000001FU
+#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
+#define GPIO_FUNC50_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC50_IN_SEL_S  0
+/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
+#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_IN_INV_SEL_S  5
+/** GPIO_SIG50_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG50_IN_SEL    (BIT(6))
+#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
+#define GPIO_SIG50_IN_SEL_V  0x00000001U
+#define GPIO_SIG50_IN_SEL_S  6
+
+/** GPIO_FUNC51_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
+/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC51_IN_SEL    0x0000001FU
+#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
+#define GPIO_FUNC51_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC51_IN_SEL_S  0
+/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
+#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_IN_INV_SEL_S  5
+/** GPIO_SIG51_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG51_IN_SEL    (BIT(6))
+#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
+#define GPIO_SIG51_IN_SEL_V  0x00000001U
+#define GPIO_SIG51_IN_SEL_S  6
+
+/** GPIO_FUNC52_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
+/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC52_IN_SEL    0x0000001FU
+#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
+#define GPIO_FUNC52_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC52_IN_SEL_S  0
+/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
+#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_IN_INV_SEL_S  5
+/** GPIO_SIG52_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG52_IN_SEL    (BIT(6))
+#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
+#define GPIO_SIG52_IN_SEL_V  0x00000001U
+#define GPIO_SIG52_IN_SEL_S  6
+
+/** GPIO_FUNC53_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
+/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC53_IN_SEL    0x0000001FU
+#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
+#define GPIO_FUNC53_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC53_IN_SEL_S  0
+/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
+#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_IN_INV_SEL_S  5
+/** GPIO_SIG53_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG53_IN_SEL    (BIT(6))
+#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
+#define GPIO_SIG53_IN_SEL_V  0x00000001U
+#define GPIO_SIG53_IN_SEL_S  6
+
+/** GPIO_FUNC54_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
+/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC54_IN_SEL    0x0000001FU
+#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
+#define GPIO_FUNC54_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC54_IN_SEL_S  0
+/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
+#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_IN_INV_SEL_S  5
+/** GPIO_SIG54_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG54_IN_SEL    (BIT(6))
+#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
+#define GPIO_SIG54_IN_SEL_V  0x00000001U
+#define GPIO_SIG54_IN_SEL_S  6
+
+/** GPIO_FUNC55_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
+/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC55_IN_SEL    0x0000001FU
+#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
+#define GPIO_FUNC55_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC55_IN_SEL_S  0
+/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
+#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_IN_INV_SEL_S  5
+/** GPIO_SIG55_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG55_IN_SEL    (BIT(6))
+#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
+#define GPIO_SIG55_IN_SEL_V  0x00000001U
+#define GPIO_SIG55_IN_SEL_S  6
+
+/** GPIO_FUNC56_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
+/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC56_IN_SEL    0x0000001FU
+#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
+#define GPIO_FUNC56_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC56_IN_SEL_S  0
+/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
+#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_IN_INV_SEL_S  5
+/** GPIO_SIG56_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG56_IN_SEL    (BIT(6))
+#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
+#define GPIO_SIG56_IN_SEL_V  0x00000001U
+#define GPIO_SIG56_IN_SEL_S  6
+
+/** GPIO_FUNC57_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
+/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC57_IN_SEL    0x0000001FU
+#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
+#define GPIO_FUNC57_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC57_IN_SEL_S  0
+/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
+#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_IN_INV_SEL_S  5
+/** GPIO_SIG57_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG57_IN_SEL    (BIT(6))
+#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
+#define GPIO_SIG57_IN_SEL_V  0x00000001U
+#define GPIO_SIG57_IN_SEL_S  6
+
+/** GPIO_FUNC58_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
+/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC58_IN_SEL    0x0000001FU
+#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
+#define GPIO_FUNC58_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC58_IN_SEL_S  0
+/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
+#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_IN_INV_SEL_S  5
+/** GPIO_SIG58_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG58_IN_SEL    (BIT(6))
+#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
+#define GPIO_SIG58_IN_SEL_V  0x00000001U
+#define GPIO_SIG58_IN_SEL_S  6
+
+/** GPIO_FUNC59_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
+/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC59_IN_SEL    0x0000001FU
+#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
+#define GPIO_FUNC59_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC59_IN_SEL_S  0
+/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
+#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_IN_INV_SEL_S  5
+/** GPIO_SIG59_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG59_IN_SEL    (BIT(6))
+#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
+#define GPIO_SIG59_IN_SEL_V  0x00000001U
+#define GPIO_SIG59_IN_SEL_S  6
+
+/** GPIO_FUNC60_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
+/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC60_IN_SEL    0x0000001FU
+#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
+#define GPIO_FUNC60_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC60_IN_SEL_S  0
+/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
+#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_IN_INV_SEL_S  5
+/** GPIO_SIG60_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG60_IN_SEL    (BIT(6))
+#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
+#define GPIO_SIG60_IN_SEL_V  0x00000001U
+#define GPIO_SIG60_IN_SEL_S  6
+
+/** GPIO_FUNC61_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
+/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC61_IN_SEL    0x0000001FU
+#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
+#define GPIO_FUNC61_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC61_IN_SEL_S  0
+/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
+#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_IN_INV_SEL_S  5
+/** GPIO_SIG61_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG61_IN_SEL    (BIT(6))
+#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
+#define GPIO_SIG61_IN_SEL_V  0x00000001U
+#define GPIO_SIG61_IN_SEL_S  6
+
+/** GPIO_FUNC62_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
+/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC62_IN_SEL    0x0000001FU
+#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
+#define GPIO_FUNC62_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC62_IN_SEL_S  0
+/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
+#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_IN_INV_SEL_S  5
+/** GPIO_SIG62_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG62_IN_SEL    (BIT(6))
+#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
+#define GPIO_SIG62_IN_SEL_V  0x00000001U
+#define GPIO_SIG62_IN_SEL_S  6
+
+/** GPIO_FUNC63_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
+/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC63_IN_SEL    0x0000001FU
+#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
+#define GPIO_FUNC63_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC63_IN_SEL_S  0
+/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
+#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC63_IN_INV_SEL_S  5
+/** GPIO_SIG63_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG63_IN_SEL    (BIT(6))
+#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
+#define GPIO_SIG63_IN_SEL_V  0x00000001U
+#define GPIO_SIG63_IN_SEL_S  6
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC64_IN_SEL    0x0000001FU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  5
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(6))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  6
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC65_IN_SEL    0x0000001FU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  5
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(6))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  6
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC66_IN_SEL    0x0000001FU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  5
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(6))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  6
+
+/** GPIO_FUNC67_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
+/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC67_IN_SEL    0x0000001FU
+#define GPIO_FUNC67_IN_SEL_M  (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S)
+#define GPIO_FUNC67_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC67_IN_SEL_S  0
+/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC67_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_M  (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S)
+#define GPIO_FUNC67_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC67_IN_INV_SEL_S  5
+/** GPIO_SIG67_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG67_IN_SEL    (BIT(6))
+#define GPIO_SIG67_IN_SEL_M  (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S)
+#define GPIO_SIG67_IN_SEL_V  0x00000001U
+#define GPIO_SIG67_IN_SEL_S  6
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC68_IN_SEL    0x0000001FU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  5
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(6))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  6
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC69_IN_SEL    0x0000001FU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  5
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(6))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  6
+
+/** GPIO_FUNC70_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
+/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC70_IN_SEL    0x0000001FU
+#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
+#define GPIO_FUNC70_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC70_IN_SEL_S  0
+/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
+#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC70_IN_INV_SEL_S  5
+/** GPIO_SIG70_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG70_IN_SEL    (BIT(6))
+#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
+#define GPIO_SIG70_IN_SEL_V  0x00000001U
+#define GPIO_SIG70_IN_SEL_S  6
+
+/** GPIO_FUNC71_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
+/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC71_IN_SEL    0x0000001FU
+#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
+#define GPIO_FUNC71_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC71_IN_SEL_S  0
+/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
+#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC71_IN_INV_SEL_S  5
+/** GPIO_SIG71_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG71_IN_SEL    (BIT(6))
+#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
+#define GPIO_SIG71_IN_SEL_V  0x00000001U
+#define GPIO_SIG71_IN_SEL_S  6
+
+/** GPIO_FUNC72_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
+/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC72_IN_SEL    0x0000001FU
+#define GPIO_FUNC72_IN_SEL_M  (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S)
+#define GPIO_FUNC72_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC72_IN_SEL_S  0
+/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC72_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_M  (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S)
+#define GPIO_FUNC72_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC72_IN_INV_SEL_S  5
+/** GPIO_SIG72_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG72_IN_SEL    (BIT(6))
+#define GPIO_SIG72_IN_SEL_M  (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S)
+#define GPIO_SIG72_IN_SEL_V  0x00000001U
+#define GPIO_SIG72_IN_SEL_S  6
+
+/** GPIO_FUNC73_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278)
+/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC73_IN_SEL    0x0000001FU
+#define GPIO_FUNC73_IN_SEL_M  (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S)
+#define GPIO_FUNC73_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC73_IN_SEL_S  0
+/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC73_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_M  (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S)
+#define GPIO_FUNC73_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC73_IN_INV_SEL_S  5
+/** GPIO_SIG73_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG73_IN_SEL    (BIT(6))
+#define GPIO_SIG73_IN_SEL_M  (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S)
+#define GPIO_SIG73_IN_SEL_V  0x00000001U
+#define GPIO_SIG73_IN_SEL_S  6
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC74_IN_SEL    0x0000001FU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  5
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(6))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  6
+
+/** GPIO_FUNC75_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
+/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC75_IN_SEL    0x0000001FU
+#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
+#define GPIO_FUNC75_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC75_IN_SEL_S  0
+/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
+#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC75_IN_INV_SEL_S  5
+/** GPIO_SIG75_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG75_IN_SEL    (BIT(6))
+#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
+#define GPIO_SIG75_IN_SEL_V  0x00000001U
+#define GPIO_SIG75_IN_SEL_S  6
+
+/** GPIO_FUNC76_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
+/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC76_IN_SEL    0x0000001FU
+#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
+#define GPIO_FUNC76_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC76_IN_SEL_S  0
+/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
+#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC76_IN_INV_SEL_S  5
+/** GPIO_SIG76_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG76_IN_SEL    (BIT(6))
+#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
+#define GPIO_SIG76_IN_SEL_V  0x00000001U
+#define GPIO_SIG76_IN_SEL_S  6
+
+/** GPIO_FUNC77_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
+/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC77_IN_SEL    0x0000001FU
+#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
+#define GPIO_FUNC77_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC77_IN_SEL_S  0
+/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
+#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC77_IN_INV_SEL_S  5
+/** GPIO_SIG77_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG77_IN_SEL    (BIT(6))
+#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
+#define GPIO_SIG77_IN_SEL_V  0x00000001U
+#define GPIO_SIG77_IN_SEL_S  6
+
+/** GPIO_FUNC78_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
+/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC78_IN_SEL    0x0000001FU
+#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
+#define GPIO_FUNC78_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC78_IN_SEL_S  0
+/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
+#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC78_IN_INV_SEL_S  5
+/** GPIO_SIG78_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG78_IN_SEL    (BIT(6))
+#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
+#define GPIO_SIG78_IN_SEL_V  0x00000001U
+#define GPIO_SIG78_IN_SEL_S  6
+
+/** GPIO_FUNC79_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
+/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC79_IN_SEL    0x0000001FU
+#define GPIO_FUNC79_IN_SEL_M  (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S)
+#define GPIO_FUNC79_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC79_IN_SEL_S  0
+/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC79_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_M  (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S)
+#define GPIO_FUNC79_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC79_IN_INV_SEL_S  5
+/** GPIO_SIG79_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG79_IN_SEL    (BIT(6))
+#define GPIO_SIG79_IN_SEL_M  (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S)
+#define GPIO_SIG79_IN_SEL_V  0x00000001U
+#define GPIO_SIG79_IN_SEL_S  6
+
+/** GPIO_FUNC80_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294)
+/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC80_IN_SEL    0x0000001FU
+#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
+#define GPIO_FUNC80_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC80_IN_SEL_S  0
+/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
+#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC80_IN_INV_SEL_S  5
+/** GPIO_SIG80_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG80_IN_SEL    (BIT(6))
+#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
+#define GPIO_SIG80_IN_SEL_V  0x00000001U
+#define GPIO_SIG80_IN_SEL_S  6
+
+/** GPIO_FUNC81_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
+/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC81_IN_SEL    0x0000001FU
+#define GPIO_FUNC81_IN_SEL_M  (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S)
+#define GPIO_FUNC81_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC81_IN_SEL_S  0
+/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC81_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_M  (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S)
+#define GPIO_FUNC81_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC81_IN_INV_SEL_S  5
+/** GPIO_SIG81_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG81_IN_SEL    (BIT(6))
+#define GPIO_SIG81_IN_SEL_M  (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S)
+#define GPIO_SIG81_IN_SEL_V  0x00000001U
+#define GPIO_SIG81_IN_SEL_S  6
+
+/** GPIO_FUNC82_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c)
+/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC82_IN_SEL    0x0000001FU
+#define GPIO_FUNC82_IN_SEL_M  (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S)
+#define GPIO_FUNC82_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC82_IN_SEL_S  0
+/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC82_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_M  (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S)
+#define GPIO_FUNC82_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC82_IN_INV_SEL_S  5
+/** GPIO_SIG82_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG82_IN_SEL    (BIT(6))
+#define GPIO_SIG82_IN_SEL_M  (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S)
+#define GPIO_SIG82_IN_SEL_V  0x00000001U
+#define GPIO_SIG82_IN_SEL_S  6
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC83_IN_SEL    0x0000001FU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  5
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(6))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  6
+
+/** GPIO_FUNC84_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
+/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC84_IN_SEL    0x0000001FU
+#define GPIO_FUNC84_IN_SEL_M  (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S)
+#define GPIO_FUNC84_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC84_IN_SEL_S  0
+/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC84_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_M  (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S)
+#define GPIO_FUNC84_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC84_IN_INV_SEL_S  5
+/** GPIO_SIG84_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG84_IN_SEL    (BIT(6))
+#define GPIO_SIG84_IN_SEL_M  (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S)
+#define GPIO_SIG84_IN_SEL_V  0x00000001U
+#define GPIO_SIG84_IN_SEL_S  6
+
+/** GPIO_FUNC85_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8)
+/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC85_IN_SEL    0x0000001FU
+#define GPIO_FUNC85_IN_SEL_M  (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S)
+#define GPIO_FUNC85_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC85_IN_SEL_S  0
+/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC85_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_M  (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S)
+#define GPIO_FUNC85_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC85_IN_INV_SEL_S  5
+/** GPIO_SIG85_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG85_IN_SEL    (BIT(6))
+#define GPIO_SIG85_IN_SEL_M  (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S)
+#define GPIO_SIG85_IN_SEL_V  0x00000001U
+#define GPIO_SIG85_IN_SEL_S  6
+
+/** GPIO_FUNC86_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac)
+/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC86_IN_SEL    0x0000001FU
+#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
+#define GPIO_FUNC86_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC86_IN_SEL_S  0
+/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
+#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC86_IN_INV_SEL_S  5
+/** GPIO_SIG86_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG86_IN_SEL    (BIT(6))
+#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
+#define GPIO_SIG86_IN_SEL_V  0x00000001U
+#define GPIO_SIG86_IN_SEL_S  6
+
+/** GPIO_FUNC87_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
+/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC87_IN_SEL    0x0000001FU
+#define GPIO_FUNC87_IN_SEL_M  (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S)
+#define GPIO_FUNC87_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC87_IN_SEL_S  0
+/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC87_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_M  (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S)
+#define GPIO_FUNC87_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC87_IN_INV_SEL_S  5
+/** GPIO_SIG87_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG87_IN_SEL    (BIT(6))
+#define GPIO_SIG87_IN_SEL_M  (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S)
+#define GPIO_SIG87_IN_SEL_V  0x00000001U
+#define GPIO_SIG87_IN_SEL_S  6
+
+/** GPIO_FUNC88_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4)
+/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC88_IN_SEL    0x0000001FU
+#define GPIO_FUNC88_IN_SEL_M  (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S)
+#define GPIO_FUNC88_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC88_IN_SEL_S  0
+/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC88_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_M  (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S)
+#define GPIO_FUNC88_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC88_IN_INV_SEL_S  5
+/** GPIO_SIG88_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG88_IN_SEL    (BIT(6))
+#define GPIO_SIG88_IN_SEL_M  (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S)
+#define GPIO_SIG88_IN_SEL_V  0x00000001U
+#define GPIO_SIG88_IN_SEL_S  6
+
+/** GPIO_FUNC89_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8)
+/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC89_IN_SEL    0x0000001FU
+#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
+#define GPIO_FUNC89_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC89_IN_SEL_S  0
+/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
+#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC89_IN_INV_SEL_S  5
+/** GPIO_SIG89_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG89_IN_SEL    (BIT(6))
+#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
+#define GPIO_SIG89_IN_SEL_V  0x00000001U
+#define GPIO_SIG89_IN_SEL_S  6
+
+/** GPIO_FUNC90_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
+/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC90_IN_SEL    0x0000001FU
+#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
+#define GPIO_FUNC90_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC90_IN_SEL_S  0
+/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
+#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC90_IN_INV_SEL_S  5
+/** GPIO_SIG90_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG90_IN_SEL    (BIT(6))
+#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
+#define GPIO_SIG90_IN_SEL_V  0x00000001U
+#define GPIO_SIG90_IN_SEL_S  6
+
+/** GPIO_FUNC91_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
+/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC91_IN_SEL    0x0000001FU
+#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
+#define GPIO_FUNC91_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC91_IN_SEL_S  0
+/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
+#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC91_IN_INV_SEL_S  5
+/** GPIO_SIG91_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG91_IN_SEL    (BIT(6))
+#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
+#define GPIO_SIG91_IN_SEL_V  0x00000001U
+#define GPIO_SIG91_IN_SEL_S  6
+
+/** GPIO_FUNC92_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC92_IN_SEL    0x0000001FU
+#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
+#define GPIO_FUNC92_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC92_IN_SEL_S  0
+/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
+#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC92_IN_INV_SEL_S  5
+/** GPIO_SIG92_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG92_IN_SEL    (BIT(6))
+#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
+#define GPIO_SIG92_IN_SEL_V  0x00000001U
+#define GPIO_SIG92_IN_SEL_S  6
+
+/** GPIO_FUNC93_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
+/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC93_IN_SEL    0x0000001FU
+#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
+#define GPIO_FUNC93_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC93_IN_SEL_S  0
+/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
+#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC93_IN_INV_SEL_S  5
+/** GPIO_SIG93_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG93_IN_SEL    (BIT(6))
+#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
+#define GPIO_SIG93_IN_SEL_V  0x00000001U
+#define GPIO_SIG93_IN_SEL_S  6
+
+/** GPIO_FUNC94_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
+/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC94_IN_SEL    0x0000001FU
+#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
+#define GPIO_FUNC94_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC94_IN_SEL_S  0
+/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
+#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC94_IN_INV_SEL_S  5
+/** GPIO_SIG94_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG94_IN_SEL    (BIT(6))
+#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
+#define GPIO_SIG94_IN_SEL_V  0x00000001U
+#define GPIO_SIG94_IN_SEL_S  6
+
+/** GPIO_FUNC95_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
+/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC95_IN_SEL    0x0000001FU
+#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
+#define GPIO_FUNC95_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC95_IN_SEL_S  0
+/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
+#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC95_IN_INV_SEL_S  5
+/** GPIO_SIG95_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG95_IN_SEL    (BIT(6))
+#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
+#define GPIO_SIG95_IN_SEL_V  0x00000001U
+#define GPIO_SIG95_IN_SEL_S  6
+
+/** GPIO_FUNC96_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
+/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC96_IN_SEL    0x0000001FU
+#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
+#define GPIO_FUNC96_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC96_IN_SEL_S  0
+/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
+#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC96_IN_INV_SEL_S  5
+/** GPIO_SIG96_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG96_IN_SEL    (BIT(6))
+#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
+#define GPIO_SIG96_IN_SEL_V  0x00000001U
+#define GPIO_SIG96_IN_SEL_S  6
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC97_IN_SEL    0x0000001FU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  5
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(6))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  6
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC98_IN_SEL    0x0000001FU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  5
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(6))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  6
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC99_IN_SEL    0x0000001FU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  5
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(6))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  6
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC100_IN_SEL    0x0000001FU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  5
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(6))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  6
+
+/** GPIO_FUNC101_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC101_IN_SEL    0x0000001FU
+#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
+#define GPIO_FUNC101_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC101_IN_SEL_S  0
+/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
+#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC101_IN_INV_SEL_S  5
+/** GPIO_SIG101_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG101_IN_SEL    (BIT(6))
+#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
+#define GPIO_SIG101_IN_SEL_V  0x00000001U
+#define GPIO_SIG101_IN_SEL_S  6
+
+/** GPIO_FUNC102_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC102_IN_SEL    0x0000001FU
+#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
+#define GPIO_FUNC102_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC102_IN_SEL_S  0
+/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
+#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC102_IN_INV_SEL_S  5
+/** GPIO_SIG102_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG102_IN_SEL    (BIT(6))
+#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
+#define GPIO_SIG102_IN_SEL_V  0x00000001U
+#define GPIO_SIG102_IN_SEL_S  6
+
+/** GPIO_FUNC103_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC103_IN_SEL    0x0000001FU
+#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
+#define GPIO_FUNC103_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC103_IN_SEL_S  0
+/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
+#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC103_IN_INV_SEL_S  5
+/** GPIO_SIG103_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG103_IN_SEL    (BIT(6))
+#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
+#define GPIO_SIG103_IN_SEL_V  0x00000001U
+#define GPIO_SIG103_IN_SEL_S  6
+
+/** GPIO_FUNC104_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC104_IN_SEL    0x0000001FU
+#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
+#define GPIO_FUNC104_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC104_IN_SEL_S  0
+/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
+#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC104_IN_INV_SEL_S  5
+/** GPIO_SIG104_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG104_IN_SEL    (BIT(6))
+#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
+#define GPIO_SIG104_IN_SEL_V  0x00000001U
+#define GPIO_SIG104_IN_SEL_S  6
+
+/** GPIO_FUNC105_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC105_IN_SEL    0x0000001FU
+#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
+#define GPIO_FUNC105_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC105_IN_SEL_S  0
+/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
+#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC105_IN_INV_SEL_S  5
+/** GPIO_SIG105_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG105_IN_SEL    (BIT(6))
+#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
+#define GPIO_SIG105_IN_SEL_V  0x00000001U
+#define GPIO_SIG105_IN_SEL_S  6
+
+/** GPIO_FUNC106_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC106_IN_SEL    0x0000001FU
+#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
+#define GPIO_FUNC106_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC106_IN_SEL_S  0
+/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
+#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC106_IN_INV_SEL_S  5
+/** GPIO_SIG106_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG106_IN_SEL    (BIT(6))
+#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
+#define GPIO_SIG106_IN_SEL_V  0x00000001U
+#define GPIO_SIG106_IN_SEL_S  6
+
+/** GPIO_FUNC107_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC107_IN_SEL    0x0000001FU
+#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
+#define GPIO_FUNC107_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC107_IN_SEL_S  0
+/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
+#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC107_IN_INV_SEL_S  5
+/** GPIO_SIG107_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG107_IN_SEL    (BIT(6))
+#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
+#define GPIO_SIG107_IN_SEL_V  0x00000001U
+#define GPIO_SIG107_IN_SEL_S  6
+
+/** GPIO_FUNC108_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC108_IN_SEL    0x0000001FU
+#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
+#define GPIO_FUNC108_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC108_IN_SEL_S  0
+/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
+#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC108_IN_INV_SEL_S  5
+/** GPIO_SIG108_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG108_IN_SEL    (BIT(6))
+#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
+#define GPIO_SIG108_IN_SEL_V  0x00000001U
+#define GPIO_SIG108_IN_SEL_S  6
+
+/** GPIO_FUNC109_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC109_IN_SEL    0x0000001FU
+#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
+#define GPIO_FUNC109_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC109_IN_SEL_S  0
+/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
+#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC109_IN_INV_SEL_S  5
+/** GPIO_SIG109_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG109_IN_SEL    (BIT(6))
+#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
+#define GPIO_SIG109_IN_SEL_V  0x00000001U
+#define GPIO_SIG109_IN_SEL_S  6
+
+/** GPIO_FUNC110_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC110_IN_SEL    0x0000001FU
+#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
+#define GPIO_FUNC110_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC110_IN_SEL_S  0
+/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
+#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC110_IN_INV_SEL_S  5
+/** GPIO_SIG110_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG110_IN_SEL    (BIT(6))
+#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
+#define GPIO_SIG110_IN_SEL_V  0x00000001U
+#define GPIO_SIG110_IN_SEL_S  6
+
+/** GPIO_FUNC111_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC111_IN_SEL    0x0000001FU
+#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
+#define GPIO_FUNC111_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC111_IN_SEL_S  0
+/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
+#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC111_IN_INV_SEL_S  5
+/** GPIO_SIG111_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG111_IN_SEL    (BIT(6))
+#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
+#define GPIO_SIG111_IN_SEL_V  0x00000001U
+#define GPIO_SIG111_IN_SEL_S  6
+
+/** GPIO_FUNC112_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
+/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC112_IN_SEL    0x0000001FU
+#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
+#define GPIO_FUNC112_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC112_IN_SEL_S  0
+/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
+#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC112_IN_INV_SEL_S  5
+/** GPIO_SIG112_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG112_IN_SEL    (BIT(6))
+#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
+#define GPIO_SIG112_IN_SEL_V  0x00000001U
+#define GPIO_SIG112_IN_SEL_S  6
+
+/** GPIO_FUNC113_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
+/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC113_IN_SEL    0x0000001FU
+#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
+#define GPIO_FUNC113_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC113_IN_SEL_S  0
+/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
+#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC113_IN_INV_SEL_S  5
+/** GPIO_SIG113_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG113_IN_SEL    (BIT(6))
+#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
+#define GPIO_SIG113_IN_SEL_V  0x00000001U
+#define GPIO_SIG113_IN_SEL_S  6
+
+/** GPIO_FUNC114_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC114_IN_SEL    0x0000001FU
+#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
+#define GPIO_FUNC114_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC114_IN_SEL_S  0
+/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
+#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC114_IN_INV_SEL_S  5
+/** GPIO_SIG114_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG114_IN_SEL    (BIT(6))
+#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
+#define GPIO_SIG114_IN_SEL_V  0x00000001U
+#define GPIO_SIG114_IN_SEL_S  6
+
+/** GPIO_FUNC115_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC115_IN_SEL    0x0000001FU
+#define GPIO_FUNC115_IN_SEL_M  (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S)
+#define GPIO_FUNC115_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC115_IN_SEL_S  0
+/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC115_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_M  (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S)
+#define GPIO_FUNC115_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC115_IN_INV_SEL_S  5
+/** GPIO_SIG115_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG115_IN_SEL    (BIT(6))
+#define GPIO_SIG115_IN_SEL_M  (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S)
+#define GPIO_SIG115_IN_SEL_V  0x00000001U
+#define GPIO_SIG115_IN_SEL_S  6
+
+/** GPIO_FUNC116_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324)
+/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC116_IN_SEL    0x0000001FU
+#define GPIO_FUNC116_IN_SEL_M  (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S)
+#define GPIO_FUNC116_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC116_IN_SEL_S  0
+/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC116_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_M  (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S)
+#define GPIO_FUNC116_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC116_IN_INV_SEL_S  5
+/** GPIO_SIG116_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG116_IN_SEL    (BIT(6))
+#define GPIO_SIG116_IN_SEL_M  (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S)
+#define GPIO_SIG116_IN_SEL_V  0x00000001U
+#define GPIO_SIG116_IN_SEL_S  6
+
+/** GPIO_FUNC117_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328)
+/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC117_IN_SEL    0x0000001FU
+#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
+#define GPIO_FUNC117_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC117_IN_SEL_S  0
+/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC117_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
+#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC117_IN_INV_SEL_S  5
+/** GPIO_SIG117_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG117_IN_SEL    (BIT(6))
+#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
+#define GPIO_SIG117_IN_SEL_V  0x00000001U
+#define GPIO_SIG117_IN_SEL_S  6
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC118_IN_SEL    0x0000001FU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  5
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(6))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  6
+
+/** GPIO_FUNC119_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC119_IN_SEL    0x0000001FU
+#define GPIO_FUNC119_IN_SEL_M  (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S)
+#define GPIO_FUNC119_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC119_IN_SEL_S  0
+/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC119_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_M  (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S)
+#define GPIO_FUNC119_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC119_IN_INV_SEL_S  5
+/** GPIO_SIG119_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG119_IN_SEL    (BIT(6))
+#define GPIO_SIG119_IN_SEL_M  (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S)
+#define GPIO_SIG119_IN_SEL_V  0x00000001U
+#define GPIO_SIG119_IN_SEL_S  6
+
+/** GPIO_FUNC120_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
+/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC120_IN_SEL    0x0000001FU
+#define GPIO_FUNC120_IN_SEL_M  (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S)
+#define GPIO_FUNC120_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC120_IN_SEL_S  0
+/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC120_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_M  (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S)
+#define GPIO_FUNC120_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC120_IN_INV_SEL_S  5
+/** GPIO_SIG120_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG120_IN_SEL    (BIT(6))
+#define GPIO_SIG120_IN_SEL_M  (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S)
+#define GPIO_SIG120_IN_SEL_V  0x00000001U
+#define GPIO_SIG120_IN_SEL_S  6
+
+/** GPIO_FUNC121_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
+/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC121_IN_SEL    0x0000001FU
+#define GPIO_FUNC121_IN_SEL_M  (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S)
+#define GPIO_FUNC121_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC121_IN_SEL_S  0
+/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC121_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_M  (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S)
+#define GPIO_FUNC121_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC121_IN_INV_SEL_S  5
+/** GPIO_SIG121_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG121_IN_SEL    (BIT(6))
+#define GPIO_SIG121_IN_SEL_M  (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S)
+#define GPIO_SIG121_IN_SEL_V  0x00000001U
+#define GPIO_SIG121_IN_SEL_S  6
+
+/** GPIO_FUNC122_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
+/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC122_IN_SEL    0x0000001FU
+#define GPIO_FUNC122_IN_SEL_M  (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S)
+#define GPIO_FUNC122_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC122_IN_SEL_S  0
+/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC122_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_M  (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S)
+#define GPIO_FUNC122_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC122_IN_INV_SEL_S  5
+/** GPIO_SIG122_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG122_IN_SEL    (BIT(6))
+#define GPIO_SIG122_IN_SEL_M  (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S)
+#define GPIO_SIG122_IN_SEL_V  0x00000001U
+#define GPIO_SIG122_IN_SEL_S  6
+
+/** GPIO_FUNC123_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
+/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC123_IN_SEL    0x0000001FU
+#define GPIO_FUNC123_IN_SEL_M  (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S)
+#define GPIO_FUNC123_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC123_IN_SEL_S  0
+/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC123_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_M  (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S)
+#define GPIO_FUNC123_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC123_IN_INV_SEL_S  5
+/** GPIO_SIG123_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG123_IN_SEL    (BIT(6))
+#define GPIO_SIG123_IN_SEL_M  (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S)
+#define GPIO_SIG123_IN_SEL_V  0x00000001U
+#define GPIO_SIG123_IN_SEL_S  6
+
+/** GPIO_FUNC124_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
+/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC124_IN_SEL    0x0000001FU
+#define GPIO_FUNC124_IN_SEL_M  (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S)
+#define GPIO_FUNC124_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC124_IN_SEL_S  0
+/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC124_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_M  (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S)
+#define GPIO_FUNC124_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC124_IN_INV_SEL_S  5
+/** GPIO_SIG124_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG124_IN_SEL    (BIT(6))
+#define GPIO_SIG124_IN_SEL_M  (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S)
+#define GPIO_SIG124_IN_SEL_V  0x00000001U
+#define GPIO_SIG124_IN_SEL_S  6
+
+/** GPIO_FUNC125_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348)
+/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC125_IN_SEL    0x0000001FU
+#define GPIO_FUNC125_IN_SEL_M  (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S)
+#define GPIO_FUNC125_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC125_IN_SEL_S  0
+/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC125_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_M  (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S)
+#define GPIO_FUNC125_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC125_IN_INV_SEL_S  5
+/** GPIO_SIG125_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG125_IN_SEL    (BIT(6))
+#define GPIO_SIG125_IN_SEL_M  (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S)
+#define GPIO_SIG125_IN_SEL_V  0x00000001U
+#define GPIO_SIG125_IN_SEL_S  6
+
+/** GPIO_FUNC126_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c)
+/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC126_IN_SEL    0x0000001FU
+#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
+#define GPIO_FUNC126_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC126_IN_SEL_S  0
+/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
+#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC126_IN_INV_SEL_S  5
+/** GPIO_SIG126_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG126_IN_SEL    (BIT(6))
+#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
+#define GPIO_SIG126_IN_SEL_V  0x00000001U
+#define GPIO_SIG126_IN_SEL_S  6
+
+/** GPIO_FUNC127_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+ *  high level. s=0x3C: set this port always low level.
+ */
+#define GPIO_FUNC127_IN_SEL    0x0000001FU
+#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
+#define GPIO_FUNC127_IN_SEL_V  0x0000001FU
+#define GPIO_FUNC127_IN_SEL_S  0
+/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [5]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
+#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC127_IN_INV_SEL_S  5
+/** GPIO_SIG127_IN_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG127_IN_SEL    (BIT(6))
+#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
+#define GPIO_SIG127_IN_SEL_V  0x00000001U
+#define GPIO_SIG127_IN_SEL_S  6
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+/** GPIO_FUNC0_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000000FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  8
+/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC0_OEN_SEL    (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
+#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_SEL_S  9
+/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+/** GPIO_FUNC1_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000000FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  8
+/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC1_OEN_SEL    (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
+#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_SEL_S  9
+/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+/** GPIO_FUNC2_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000000FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  8
+/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC2_OEN_SEL    (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
+#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_SEL_S  9
+/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+/** GPIO_FUNC3_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000000FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  8
+/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC3_OEN_SEL    (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
+#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_SEL_S  9
+/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+/** GPIO_FUNC4_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000000FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  8
+/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC4_OEN_SEL    (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
+#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_SEL_S  9
+/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
+/** GPIO_FUNC5_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000000FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  8
+/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC5_OEN_SEL    (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
+#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_SEL_S  9
+/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+/** GPIO_FUNC6_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000000FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  8
+/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC6_OEN_SEL    (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
+#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_SEL_S  9
+/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+/** GPIO_FUNC7_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000000FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  8
+/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC7_OEN_SEL    (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
+#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_SEL_S  9
+/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+/** GPIO_FUNC8_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000000FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  8
+/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC8_OEN_SEL    (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
+#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_SEL_S  9
+/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+/** GPIO_FUNC9_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000000FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  8
+/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC9_OEN_SEL    (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
+#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_SEL_S  9
+/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+/** GPIO_FUNC10_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000000FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  8
+/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC10_OEN_SEL    (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
+#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_SEL_S  9
+/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+/** GPIO_FUNC11_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000000FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  8
+/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC11_OEN_SEL    (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
+#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_SEL_S  9
+/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+/** GPIO_FUNC12_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000000FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  8
+/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC12_OEN_SEL    (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
+#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_SEL_S  9
+/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+/** GPIO_FUNC13_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000000FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  8
+/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC13_OEN_SEL    (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
+#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_SEL_S  9
+/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+/** GPIO_FUNC14_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000000FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  8
+/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC14_OEN_SEL    (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
+#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_SEL_S  9
+/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+/** GPIO_FUNC15_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000000FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  8
+/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC15_OEN_SEL    (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
+#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_SEL_S  9
+/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+/** GPIO_FUNC16_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000000FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  8
+/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC16_OEN_SEL    (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
+#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_SEL_S  9
+/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+/** GPIO_FUNC17_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000000FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  8
+/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC17_OEN_SEL    (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
+#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_SEL_S  9
+/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+/** GPIO_FUNC18_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000000FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  8
+/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC18_OEN_SEL    (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
+#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_SEL_S  9
+/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+/** GPIO_FUNC19_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000000FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  8
+/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC19_OEN_SEL    (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
+#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_SEL_S  9
+/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+/** GPIO_FUNC20_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000000FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  8
+/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC20_OEN_SEL    (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
+#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_SEL_S  9
+/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+/** GPIO_FUNC21_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000000FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  8
+/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC21_OEN_SEL    (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
+#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_SEL_S  9
+/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+/** GPIO_FUNC22_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000000FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  8
+/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC22_OEN_SEL    (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
+#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_SEL_S  9
+/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+/** GPIO_FUNC23_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000000FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  8
+/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC23_OEN_SEL    (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
+#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_SEL_S  9
+/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_INV_SEL_S  10
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+/** GPIO_FUNC24_OUT_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000000FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000000FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  8
+/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC24_OEN_SEL    (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
+#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_SEL_S  9
+/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OEN_INV_SEL    (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_INV_SEL_S  10
+
+/** GPIO_CLOCK_GATE_REG_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG_REG (DR_REG_GPIO_BASE + 0x62c)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  set this bit to enable GPIO clock gate
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_REG_DATE_REG_REG register
+ *  GPIO version register
+ */
+#define GPIO_REG_DATE_REG_REG (DR_REG_GPIO_BASE + 0x6fc)
+/** GPIO_REG_DATE : R/W; bitpos: [27:0]; default: 34627984;
+ *  version register
+ */
+#define GPIO_REG_DATE    0x0FFFFFFFU
+#define GPIO_REG_DATE_M  (GPIO_REG_DATE_V << GPIO_REG_DATE_S)
+#define GPIO_REG_DATE_V  0x0FFFFFFFU
+#define GPIO_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/gpio_sig_map.h

@@ -0,0 +1,152 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GPIO_SIG_MAP_H_
+#define _SOC_GPIO_SIG_MAP_H_
+
+#define SPICLK_OUT_MUX_IDX            SPICLK_OUT_IDX
+#define SPIQ_IN_IDX                   0
+#define SPIQ_OUT_IDX                  0
+#define SPID_IN_IDX                   1
+#define SPID_OUT_IDX                  1
+#define SPIHD_IN_IDX                  2
+#define SPIHD_OUT_IDX                 2
+#define SPIWP_IN_IDX                  3
+#define SPIWP_OUT_IDX                 3
+#define SPICLK_OUT_IDX                4
+#define SPICS0_OUT_IDX                5
+#define U0RXD_IN_IDX                  6
+#define U0TXD_OUT_IDX                 6
+#define U0CTS_IN_IDX                  7
+#define U0RTS_OUT_IDX                 7
+#define U0DSR_IN_IDX                  8
+#define U0DTR_OUT_IDX                 8
+#define U1RXD_IN_IDX                  9
+#define U1TXD_OUT_IDX                 9
+#define U1CTS_IN_IDX                  10
+#define U1RTS_OUT_IDX                 10
+#define U1DSR_IN_IDX                  11
+#define U1DTR_OUT_IDX                 11
+#define SPIQ_MONITOR_IDX              15
+#define SPID_MONITOR_IDX              16
+#define SPIHD_MONITOR_IDX             17
+#define SPIWP_MONITOR_IDX             18
+#define SPICS1_OUT_IDX                19
+#define CPU_TESTBUS0_IDX              20
+#define CPU_TESTBUS1_IDX              21
+#define CPU_TESTBUS2_IDX              22
+#define CPU_TESTBUS3_IDX              23
+#define CPU_TESTBUS4_IDX              24
+#define CPU_TESTBUS5_IDX              25
+#define CPU_TESTBUS6_IDX              26
+#define CPU_TESTBUS7_IDX              27
+#define CPU_GPIO_IN0_IDX              28
+#define CPU_GPIO_OUT0_IDX             28
+#define CPU_GPIO_IN1_IDX              29
+#define CPU_GPIO_OUT1_IDX             29
+#define CPU_GPIO_IN2_IDX              30
+#define CPU_GPIO_OUT2_IDX             30
+#define CPU_GPIO_IN3_IDX              31
+#define CPU_GPIO_OUT3_IDX             31
+#define CPU_GPIO_IN4_IDX              32
+#define CPU_GPIO_OUT4_IDX             32
+#define CPU_GPIO_IN5_IDX              33
+#define CPU_GPIO_OUT5_IDX             33
+#define CPU_GPIO_IN6_IDX              34
+#define CPU_GPIO_OUT6_IDX             34
+#define CPU_GPIO_IN7_IDX              35
+#define CPU_GPIO_OUT7_IDX             35
+#define EXT_ADC_START_IDX             45
+#define LEDC_LS_SIG_OUT0_IDX          45
+#define LEDC_LS_SIG_OUT1_IDX          46
+#define LEDC_LS_SIG_OUT2_IDX          47
+#define LEDC_LS_SIG_OUT3_IDX          48
+#define LEDC_LS_SIG_OUT4_IDX          49
+#define LEDC_LS_SIG_OUT5_IDX          50
+#define RMT_SIG_IN0_IDX               51
+#define RMT_SIG_OUT0_IDX              51
+#define RMT_SIG_IN1_IDX               52
+#define RMT_SIG_OUT1_IDX              52
+#define I2CEXT0_SCL_IN_IDX            53
+#define I2CEXT0_SCL_OUT_IDX           53
+#define I2CEXT0_SDA_IN_IDX            54
+#define I2CEXT0_SDA_OUT_IDX           54
+#define FSPICLK_IN_IDX                63
+#define FSPICLK_OUT_IDX               63
+#define FSPIQ_IN_IDX                  64
+#define FSPIQ_OUT_IDX                 64
+#define FSPID_IN_IDX                  65
+#define FSPID_OUT_IDX                 65
+#define FSPIHD_IN_IDX                 66
+#define FSPIHD_OUT_IDX                66
+#define FSPIWP_IN_IDX                 67
+#define FSPIWP_OUT_IDX                67
+#define FSPICS0_IN_IDX                68
+#define FSPICS0_OUT_IDX               68
+#define FSPICS1_OUT_IDX               69
+#define FSPICS2_OUT_IDX               70
+#define FSPICS3_OUT_IDX               71
+#define FSPICS4_OUT_IDX               72
+#define FSPICS5_OUT_IDX               73
+#define EXTERN_PRIORITY_I_IDX         77
+#define EXTERN_PRIORITY_O_IDX         77
+#define EXTERN_ACTIVE_I_IDX           78
+#define EXTERN_ACTIVE_O_IDX           78
+#define GPIO_EVENT_MATRIX_IN0_IDX     79
+#define GPIO_TASK_MATRIX_OUT0_IDX     79
+#define GPIO_EVENT_MATRIX_IN1_IDX     80
+#define GPIO_TASK_MATRIX_OUT1_IDX     80
+#define GPIO_EVENT_MATRIX_IN2_IDX     81
+#define GPIO_TASK_MATRIX_OUT2_IDX     81
+#define GPIO_EVENT_MATRIX_IN3_IDX     82
+#define GPIO_TASK_MATRIX_OUT3_IDX     82
+#define BB_DIAG8_OUT_IDX              83
+#define BB_DIAG9_OUT_IDX              84
+#define BB_DIAG10_OUT_IDX             85
+#define BB_DIAG11_OUT_IDX             86
+#define BB_DIAG12_OUT_IDX             87
+#define BB_DIAG13_OUT_IDX             88
+#define ANT_SEL0_IDX                  89
+#define ANT_SEL1_IDX                  90
+#define ANT_SEL2_IDX                  91
+#define ANT_SEL3_IDX                  92
+#define ANT_SEL4_IDX                  93
+#define ANT_SEL5_IDX                  94
+#define ANT_SEL6_IDX                  95
+#define ANT_SEL7_IDX                  96
+#define SIG_IN_FUNC_97_IDX            97
+#define SIG_IN_FUNC97_IDX             97
+#define SIG_IN_FUNC_98_IDX            98
+#define SIG_IN_FUNC98_IDX             98
+#define SIG_IN_FUNC_99_IDX            99
+#define SIG_IN_FUNC99_IDX             99
+#define SIG_IN_FUNC_100_IDX           100
+#define SIG_IN_FUNC100_IDX            100
+#define BLE_DBG_SYNCERR_IDX           101
+#define BLE_DBG_SYNC_FOUND_IDX        102
+#define BLE_DBG_CH_IDX_IDX            103
+#define BLE_DBG_SYNC_WINDOW_IDX       104
+#define BLE_DBG_DATA_EN_IDX           105
+#define BLE_DBG_DATA_IDX              106
+#define BLE_DBG_PKT_TX_ON_IDX         107
+#define BLE_DBG_PKT_RX_ON_IDX         108
+#define BLE_DBG_TXRU_ON_IDX           109
+#define BLE_DBG_RXRU_ON_IDX           110
+#define BLE_DBG_LELC_ST0_IDX          111
+#define BLE_DBG_LELC_ST1_IDX          112
+#define BLE_DBG_LELC_ST2_IDX          113
+#define BLE_DBG_LELC_ST3_IDX          114
+#define BLE_DBG_CRCOK_IDX             115
+#define BLE_DBG_CLK_GPIO_IDX          116
+#define BLE_DBG_RADIO_START_IDX       117
+#define BLE_DBG_SEQUENCE_ON_IDX       118
+#define BLE_DBG_COEX_BT_ON_IDX        119
+#define BLE_DBG_COEX_WIFI_ON_IDX      120
+#define CLK_OUT_OUT1_IDX              123
+#define CLK_OUT_OUT2_IDX              124
+#define CLK_OUT_OUT3_IDX              125
+#define SIG_GPIO_OUT_IDX              128
+#define GPIO_MAP_DATE_IDX             0x2106190
+#endif  /* _SOC_GPIO_SIG_MAP_H_ */

components/soc/esp8684/include/soc/gpio_struct.h

@@ -0,0 +1,419 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SS; bitpos: [24:0]; default: 0;
+         *  GPIO output register for GPIO0-24
+         */
+        uint32_t out_data_orig:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output set register for GPIO0-24
+         */
+        uint32_t out_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output clear register for GPIO0-24
+         */
+        uint32_t out_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of sdio_select register
+ *  GPIO sdio select register
+ */
+typedef union {
+    struct {
+        /** sdio_sel : R/W; bitpos: [7:0]; default: 0;
+         *  GPIO sdio select register
+         */
+        uint32_t sdio_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_sdio_select_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/SS; bitpos: [24:0]; default: 0;
+         *  GPIO output enable register for GPIO0-24
+         */
+        uint32_t enable_data:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-24
+         */
+        uint32_t enable_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-24
+         */
+        uint32_t enable_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [24:0]; default: 0;
+         *  GPIO input register for GPIO0-24
+         */
+        uint32_t in_data_next:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/SS; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-24
+         */
+        uint32_t status_interrupt:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-24
+         */
+        uint32_t status_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-24
+         */
+        uint32_t status_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of pcpu_int register
+ *  GPIO PRO_CPU interrupt status register
+ */
+typedef union {
+    struct {
+        /** procpu_int : RO; bitpos: [24:0]; default: 0;
+         *  GPIO PRO_CPU interrupt status register for GPIO0-24
+         */
+        uint32_t procpu_int:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_pcpu_int_reg_t;
+
+/** Type of pcpu_nmi_int register
+ *  GPIO PRO_CPU(not shielded) interrupt status register
+ */
+typedef union {
+    struct {
+        /** procpu_nmi_int : RO; bitpos: [24:0]; default: 0;
+         *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24
+         */
+        uint32_t procpu_nmi_int:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_pcpu_nmi_int_reg_t;
+
+/** Type of cpusdio_int register
+ *  GPIO CPUSDIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** sdio_int : RO; bitpos: [24:0]; default: 0;
+         *  GPIO CPUSDIO interrupt status register for GPIO0-24
+         */
+        uint32_t sdio_int:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_cpusdio_int_reg_t;
+
+/** Type of pin0 register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync2_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pad_driver:1;
+        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t wakeup_enable:1;
+        /** config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t config:2;
+        /** int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [25:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-24
+         */
+        uint32_t status_interrupt_next:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** in_sel : R/W; bitpos: [4:0]; default: 0;
+         *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
+         *  high level. s=0x3C: set this port always low level.
+         */
+        uint32_t func_sel:5;
+        /** in_inv_sel : R/W; bitpos: [5]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t sig_in_inv:1;
+        /** in_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** out_sel : R/W; bitpos: [7:0]; default: 128;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t func_sel:8;
+        /** out_inv_sel : R/W; bitpos: [8]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t inv_sel:1;
+        /** oen_sel : R/W; bitpos: [9]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t oen_sel:1;
+        /** oen_inv_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t oen_inv_sel:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of clock_gate_reg register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_reg_t;
+
+/** Type of reg_date_reg register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 34627984;
+         *  version register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_reg_date_reg_reg_t;
+
+
+typedef struct {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    uint32_t reserved_010[3];
+    volatile gpio_sdio_select_reg_t sdio_select;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    uint32_t reserved_02c[3];
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    uint32_t reserved_040;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    uint32_t reserved_050[3];
+    volatile gpio_pcpu_int_reg_t pcpu_int;
+    volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
+    volatile gpio_cpusdio_int_reg_t cpusdio_int;
+    uint32_t reserved_068[3];
+    volatile gpio_pin_reg_t pin[25];
+    uint32_t reserved_0d8[29];
+    volatile gpio_status_next_reg_t status_next;
+    uint32_t reserved_150;
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];
+    uint32_t reserved_354[128];
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[25];
+    uint32_t reserved_5b8[29];
+    volatile gpio_clock_gate_reg_reg_t clock_gate_reg;
+    uint32_t reserved_630[51];
+    volatile gpio_reg_date_reg_reg_t reg_date_reg;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/hwcrypto_reg.h

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __HWCRYPTO_REG_H__
+#define __HWCRYPTO_REG_H__
+
+#include "soc.h"
+
+#define SHA_MODE_SHA1       0
+#define SHA_MODE_SHA224     1
+#define SHA_MODE_SHA256     2
+
+/* SHA acceleration registers */
+#define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
+#define SHA_BLOCK_NUM_REG             ((DR_REG_SHA_BASE) + 0x0C)
+#define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x10)
+#define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x14)
+#define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x18)
+#define SHA_DMA_START_REG             ((DR_REG_SHA_BASE) + 0x1C)
+#define SHA_DMA_CONTINUE_REG          ((DR_REG_SHA_BASE) + 0x20)
+#define SHA_CLEAR_IRQ_REG             ((DR_REG_SHA_BASE) + 0x24)
+#define SHA_INT_ENA_REG               ((DR_REG_SHA_BASE) + 0x28)
+#define SHA_DATE_REG                  ((DR_REG_SHA_BASE) + 0x2C)
+
+#define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
+#define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
+
+#endif

components/soc/esp8684/include/soc/i2c_reg.h

@@ -0,0 +1,1252 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL remains low in master mode, in
+ *  I2C module clock cycles.
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FF
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FF
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 1;
+ *  0: direct output, 1: open drain output.
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 1;
+ *  0: direct output, 1: open drain output.
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  This register is used to select the sample mode.
+ *  1: sample SDA data on the SCL low level.
+ *  0: sample SDA data on the SCL high level.
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  This register is used to configure the ACK value that need to sent by master when
+ *  the rx_fifo_cnt has reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
+ *  the
+ *  module as an I2C Slave.
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Set this bit to start sending the data in txfifo.
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  This bit is used to control the sending mode for data needing to be sent.
+ *  1: send data from the least significant bit,
+ *  0: send data from the most significant bit.
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  This bit is used to control the storage mode for received data.
+ *  1: receive data from the least significant bit,
+ *  0: receive data from the most significant bit.
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the enable bit for arbitration_lost.
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  This register is used to reset the scl FMS.
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  synchronization bit
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for slave to send data automatically
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+
+/** I2C_SR_REG register
+ *  Describe I2C work status.
+ */
+#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001
+#define I2C_RESP_REC_S  0
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  When the I2C controller loses control of SCL line, this register changes to 1.
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001
+#define I2C_BUS_BUSY_S  4
+/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0;
+ *  This field represents the amount of data needed to be sent.
+ */
+#define I2C_RXFIFO_CNT    0x0000001F
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000001F
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0;
+ *  This field stores the amount of received data in RAM.
+ */
+#define I2C_TXFIFO_CNT    0x0000001F
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000001F
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  This field indicates the states of the I2C module state machine.
+ *  0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6:
+ *  Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  This field indicates the states of the state machine used to produce SCL.
+ *  0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data.
+ */
+#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  This register is used to configure the timeout for receiving a data bit in APB
+ *  clock cycles.
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001F
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001F
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for time out control.
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register.
+ */
+#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0;
+ *  This is the offset address of the APB reading from rxfifo
+ */
+#define I2C_RXFIFO_RADDR    0x0000000F
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000000F
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0;
+ *  This is the offset address of i2c module receiving data and writing to rxfifo.
+ */
+#define I2C_RXFIFO_WADDR    0x0000000F
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000000F
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0;
+ *  This is the offset address of i2c module reading from txfifo.
+ */
+#define I2C_TXFIFO_RADDR    0x0000000F
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000000F
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0;
+ *  This is the offset address of APB bus writing to txfifo.
+ */
+#define I2C_TXFIFO_WADDR    0x0000000F
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000000F
+#define I2C_TXFIFO_WADDR_S  15
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register.
+ */
+#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6;
+ *  The water mark threshold of rx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+ *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000000F
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000000F
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2;
+ *  The water mark threshold of tx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+ *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000000F
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000000F
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001
+#define I2C_NONFIFO_EN_S  10
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to reset rx-fifo.
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to reset tx-fifo.
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+ *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data.
+ */
+#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0;
+ *  The value of rx FIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FF
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FF
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001
+#define I2C_DET_START_INT_RAW_S  15
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001
+#define I2C_DET_START_INT_CLR_S  15
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001
+#define I2C_DET_START_INT_ENA_S  15
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001
+#define I2C_DET_START_INT_ST_S  15
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge.
+ */
+#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure the time to hold the data after the negative
+ *  edge of SCL, in I2C module clock cycles.
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FF
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FF
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge.
+ */
+#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SDA is sampled, in I2C module clock
+ *  cycles.
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FF
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FF
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL setup to high level and remains
+ *  high in master mode, in I2C module clock cycles.
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FF
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FF
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+ *  level in master mode, in I2C module clock cycles.
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007F
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007F
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the negative edge
+ *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
+ *  cycles.
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FF
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FF
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive
+ *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
+ *  clock cycles.
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FF
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FF
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the delay after the STOP condition,
+ *  in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FF
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FF
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive edge
+ *  of SCL and the positive edge of SDA, in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FF
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FF
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  When a pulse on the SCL input has smaller width than this register value
+ *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000F
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000F
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  When a pulse on the SDA input has smaller width than this register value
+ *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000F
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000F
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  This is the filter enable bit for SCL.
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the filter enable bit for SDA.
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_CLK_CONF_REG register
+ *  I2C CLK configuration register
+ */
+#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
+/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  the integral part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_NUM    0x000000FF
+#define I2C_SCLK_DIV_NUM_M  (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S)
+#define I2C_SCLK_DIV_NUM_V  0x000000FF
+#define I2C_SCLK_DIV_NUM_S  0
+/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
+ *  the numerator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_A    0x0000003F
+#define I2C_SCLK_DIV_A_M  (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S)
+#define I2C_SCLK_DIV_A_V  0x0000003F
+#define I2C_SCLK_DIV_A_S  8
+/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
+ *  the denominator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_B    0x0000003F
+#define I2C_SCLK_DIV_B_M  (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S)
+#define I2C_SCLK_DIV_B_V  0x0000003F
+#define I2C_SCLK_DIV_B_S  14
+/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
+ */
+#define I2C_SCLK_SEL    (BIT(20))
+#define I2C_SCLK_SEL_M  (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S)
+#define I2C_SCLK_SEL_V  0x00000001
+#define I2C_SCLK_SEL_S  20
+/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
+ *  The clock switch for i2c module
+ */
+#define I2C_SCLK_ACTIVE    (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S)
+#define I2C_SCLK_ACTIVE_V  0x00000001
+#define I2C_SCLK_ACTIVE_S  21
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 0. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND0    0x00003FFF
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFF
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 0 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 1. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND1    0x00003FFF
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFF
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 1 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 2. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND2    0x00003FFF
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFF
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 2 is done in I2C Master mode, this bit changes to high
+ *  Level.
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 3. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND3    0x00003FFF
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFF
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 3 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 4. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND4    0x00003FFF
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFF
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 4 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 5. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND5    0x00003FFF
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFF
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 5 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 6. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND6    0x00003FFF
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFF
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 6 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 7. It consists of three parts:
+ *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND7    0x00003FFF
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFF
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 7 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001F
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001F
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+ *  than 23
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001F
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001F
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+ *  equals to reg_scl_rst_slv_num[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode. Valid when
+ *  reg_scl_rst_slv_en is 1.
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001F
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001F
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+ *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+ *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 34628163;
+ *  This is the the version register.
+ */
+#define I2C_DATE    0xFFFFFFFF
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFF
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  This is the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFF
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFF
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  This is the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFF
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFF
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/i2c_struct.h

@@ -0,0 +1,1071 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL remains low in master mode, in
+         *  I2C module clock cycles.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure the time to hold the data after the negative
+         *  edge of SCL, in I2C module clock cycles.
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SDA is sampled, in I2C module clock
+         *  cycles.
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL setup to high level and remains
+         *  high in master mode, in I2C module clock cycles.
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+         *  level in master mode, in I2C module clock cycles.
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the negative edge
+         *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
+         *  cycles.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive
+         *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
+         *  clock cycles.
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the delay after the STOP condition,
+         *  in I2C module clock cycles.
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive edge
+         *  of SCL and the positive edge of SDA, in I2C module clock cycles.
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+         *  than 23
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 1;
+         *  0: direct output, 1: open drain output.
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 1;
+         *  0: direct output, 1: open drain output.
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  This register is used to select the sample mode.
+         *  1: sample SDA data on the SCL low level.
+         *  0: sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  This register is used to configure the ACK value that need to sent by master when
+         *  the rx_fifo_cnt has reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
+         *  the
+         *  module as an I2C Slave.
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Set this bit to start sending the data in txfifo.
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  This bit is used to control the sending mode for data needing to be sent.
+         *  1: send data from the least significant bit,
+         *  0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  This bit is used to control the storage mode for received data.
+         *  1: receive data from the least significant bit,
+         *  0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  This is the enable bit for arbitration_lost.
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  This register is used to reset the scl FMS.
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  synchronization bit
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for slave to send data automatically
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  This register is used to configure the timeout for receiving a data bit in APB
+         *  clock cycles.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for time out control.
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6;
+         *  The water mark threshold of rx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:4;
+        uint32_t reserved_4:1;
+        /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2;
+         *  The water mark threshold of tx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:4;
+        uint32_t reserved_9:1;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        uint32_t reserved_11:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to reset rx-fifo.
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to reset tx-fifo.
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+         *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  When a pulse on the SCL input has smaller width than this register value
+         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  When a pulse on the SDA input has smaller width than this register value
+         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  This is the filter enable bit for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  This is the filter enable bit for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of clk_conf register
+ *  I2C CLK configuration register
+ */
+typedef union {
+    struct {
+        /** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  the integral part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
+         *  the numerator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
+         *  the denominator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_sel : R/W; bitpos: [20]; default: 0;
+         *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
+         */
+        uint32_t sclk_sel:1;
+        /** sclk_active : R/W; bitpos: [21]; default: 1;
+         *  The clock switch for i2c module
+         */
+        uint32_t sclk_active:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i2c_clk_conf_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode. Valid when
+         *  reg_scl_rst_slv_en is 1.
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+         *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+         *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+         */
+        uint32_t resp_rec:1;
+        uint32_t reserved_1:2;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  When the I2C controller loses control of SCL line, this register changes to 1.
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        uint32_t reserved_5:3;
+        /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0;
+         *  This field represents the amount of data needed to be sent.
+         */
+        uint32_t rxfifo_cnt:5;
+        uint32_t reserved_13:5;
+        /** txfifo_cnt : RO; bitpos: [22:18]; default: 0;
+         *  This field stores the amount of received data in RAM.
+         */
+        uint32_t txfifo_cnt:5;
+        uint32_t reserved_23:1;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  This field indicates the states of the I2C module state machine.
+         *  0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6:
+         *  Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  This field indicates the states of the state machine used to produce SCL.
+         *  0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0;
+         *  This is the offset address of the APB reading from rxfifo
+         */
+        uint32_t rxfifo_raddr:4;
+        uint32_t reserved_4:1;
+        /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0;
+         *  This is the offset address of i2c module receiving data and writing to rxfifo.
+         */
+        uint32_t rxfifo_waddr:4;
+        uint32_t reserved_9:1;
+        /** txfifo_raddr : RO; bitpos: [13:10]; default: 0;
+         *  This is the offset address of i2c module reading from txfifo.
+         */
+        uint32_t txfifo_raddr:4;
+        uint32_t reserved_14:1;
+        /** txfifo_waddr : RO; bitpos: [18:15]; default: 0;
+         *  This is the offset address of APB bus writing to txfifo.
+         */
+        uint32_t txfifo_waddr:4;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : RO; bitpos: [7:0]; default: 0;
+         *  The value of rx FIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 0. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 0 is done in I2C Master mode, this bit changes to high
+         *  level.
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 1. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 1 is done in I2C Master mode, this bit changes to high
+         *  level.
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 2. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 2 is done in I2C Master mode, this bit changes to high
+         *  Level.
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 3. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 3 is done in I2C Master mode, this bit changes to high
+         *  level.
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 4. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 4 is done in I2C Master mode, this bit changes to high
+         *  level.
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 5. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 5 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 6. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 6 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 7. It consists of three parts:
+         *  op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 7 is done in I2C Master mode, this bit changes to high level.
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 34628163;
+         *  This is the the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  This is the I2C txfifo first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  This is the I2C rxfifo first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    uint32_t reserved_010;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    volatile i2c_clk_conf_reg_t clk_conf;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    uint32_t reserved_084[29];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/interrupt_core0_reg.h

@@ -0,0 +1,696 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_INTERRUPT_CORE0_REG_H_
+#define _SOC_INTERRUPT_CORE0_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define DR_REG_INTERRUPT_CORE0_BASE 				DR_REG_INTERRUPT_BASE
+
+#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/* INTERRUPT_CORE0_WIFI_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_M  ((INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S))
+#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/* INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP    0x0000001F
+#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S))
+#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/* INTERRUPT_CORE0_WIFI_PWR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_M  ((INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S))
+#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC)
+/* INTERRUPT_CORE0_WIFI_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_WIFI_BB_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_M  ((INTERRUPT_CORE0_WIFI_BB_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_BT_BB_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP    0x0000001F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
+/* INTERRUPT_CORE0_LP_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_LP_TIMER_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_M  ((INTERRUPT_CORE0_LP_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_INT_MAP_S))
+#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_COEX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_COEX_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_COEX_INT_MAP_M  ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S))
+#define INTERRUPT_CORE0_COEX_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_COEX_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/* INTERRUPT_CORE0_BLE_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_M  ((INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S))
+#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M  ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S))
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
+/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
+/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP    0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP    0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
+
+#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_UART_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
+/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_EFUSE_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
+/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_TG_T0_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
+/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
+/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_ECC_INT_MAP_M  ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
+#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ECC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
+/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP    0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
+/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP    0x0000001F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
+/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
+/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
+/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_CLK_EN_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
+/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INT_ENABLE    0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_TYPE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
+/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INT_TYPE    0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_M  ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
+#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
+/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INT_CLEAR    0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
+/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS    0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
+/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
+/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
+/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
+/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
+/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
+/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
+/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
+/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
+/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
+/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
+/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
+/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
+/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
+/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
+/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
+/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
+/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
+/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP    0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_CPU_INT_THRESH    0x0000000F
+#define INTERRUPT_CORE0_CPU_INT_THRESH_M  ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
+#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0xF
+#define INTERRUPT_CORE0_CPU_INT_THRESH_S  0
+
+#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
+/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
+/*description: Need add description.*/
+#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
+#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+
+#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */

components/soc/esp8684/include/soc/interrupt_reg.h

@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "interrupt_core0_reg.h"

components/soc/esp8684/include/soc/io_mux_reg.h

@@ -0,0 +1,281 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#pragma once
+#include "soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+
+#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_U0TXD_U
+
+#define FUNC_GPIO_GPIO                              1
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define U0RXD_GPIO_NUM               19
+#define U0TXD_GPIO_NUM               20
+
+#define SPI_HD_GPIO_NUM              12
+#define SPI_WP_GPIO_NUM              13
+#define SPI_CS0_GPIO_NUM             14
+#define SPI_CLK_GPIO_NUM             15
+#define SPI_D_GPIO_NUM               16
+#define SPI_Q_GPIO_NUM               17
+
+#define MAX_RTC_GPIO_NUM              5
+#define MAX_PAD_GPIO_NUM             20
+#define MAX_GPIO_NUM                 24
+#define DIG_IO_HOLD_BIT_SHIFT         0
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define PAD_POWER_SEL                               BIT(15)
+#define PAD_POWER_SEL_V                             0x1
+#define PAD_POWER_SEL_M                             BIT(15)
+#define PAD_POWER_SEL_S                             15
+
+#define PAD_POWER_SWITCH_DELAY                      0x7
+#define PAD_POWER_SWITCH_DELAY_V                    0x7
+#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S                    12
+
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+// definitions above are inherited from previous version of code, should double check
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_XTAL_32K_P_U           (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_P_GPIO0                                       1
+#define FUNC_XTAL_32K_P_GPIO0_0                                     0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U           (REG_IO_MUX_BASE + 0x8)
+#define FUNC_XTAL_32K_N_GPIO1                                       1
+#define FUNC_XTAL_32K_N_GPIO1_0                                     0
+
+#define PERIPHS_IO_MUX_GPIO2_U                (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_FSPIQ                                            2
+#define FUNC_GPIO2_GPIO2                                            1
+#define FUNC_GPIO2_GPIO2_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U               (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                            1
+#define FUNC_GPIO3_GPIO3_0                                          0
+
+#define PERIPHS_IO_MUX_MTMS_U                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTMS_FSPIHD                                            2
+#define FUNC_MTMS_GPIO4                                             1
+#define FUNC_MTMS_MTMS                                              0
+
+#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPIWP                                            2
+#define FUNC_MTDI_GPIO5                                             1
+#define FUNC_MTDI_MTDI                                              0
+
+#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_MTCK_FSPICLK                                           2
+#define FUNC_MTCK_GPIO6                                             1
+#define FUNC_MTCK_MTCK                                              0
+
+#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_MTDO_FSPID                                             2
+#define FUNC_MTDO_GPIO7                                             1
+#define FUNC_MTDO_MTDO                                              0
+
+#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8                                            1
+#define FUNC_GPIO8_GPIO8_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9                                            1
+#define FUNC_GPIO9_GPIO9_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_FSPICS0                                         2
+#define FUNC_GPIO10_GPIO10                                          1
+#define FUNC_GPIO10_GPIO10_0                                        0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x30)
+#define FUNC_VDD_SPI_GPIO11                                         1
+#define FUNC_VDD_SPI_GPIO11_0                                       0
+
+#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_SPIHD_GPIO12                                           1
+#define FUNC_SPIHD_SPIHD                                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_SPIWP_GPIO13                                           1
+#define FUNC_SPIWP_SPIWP                                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_SPICS0_GPIO14                                          1
+#define FUNC_SPICS0_SPICS0                                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICLK_GPIO15                                          1
+#define FUNC_SPICLK_SPICLK                                          0
+
+#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPID_GPIO16                                            1
+#define FUNC_SPID_SPID                                              0
+
+#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIQ_GPIO17                                            1
+#define FUNC_SPIQ_SPIQ                                              0
+
+#define PERIPHS_IO_MUX_GPIO18_U              (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_GPIO18_GPIO18                                          1
+#define FUNC_GPIO18_GPIO18_0                                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_U0RXD_GPIO19                                           1
+#define FUNC_U0RXD_U0RXD                                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_U0TXD_GPIO20                                           1
+#define FUNC_U0TXD_U0TXD                                            0
+
+#define IO_MUX_PIN_CTRL_REG          (REG_IO_MUX_BASE + 0x0)
+/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
+LK_OUT_out3 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT3    0x0000000F
+#define IO_MUX_CLK_OUT3_M  ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
+#define IO_MUX_CLK_OUT3_V  0xF
+#define IO_MUX_CLK_OUT3_S  8
+/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[7:4] ;default: 4'hf ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
+LK_OUT_out2 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT2    0x0000000F
+#define IO_MUX_CLK_OUT2_M  ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
+#define IO_MUX_CLK_OUT2_V  0xF
+#define IO_MUX_CLK_OUT2_S  4
+/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[3:0] ;default: 4'hf ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
+LK_OUT_out1 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT1    0x0000000F
+#define IO_MUX_CLK_OUT1_M  ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
+#define IO_MUX_CLK_OUT1_V  0xF
+#define IO_MUX_CLK_OUT1_S  0
+/* IO_MUX_DATE_REG : R/W ;bitpos:[27:0] ;default: 28'h2106190 ; */
+/*description: Version control register.*/
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0xFC)
+#define IO_MUX_DATE_REG_M  ((IO_MUX_DATE_REG_V)<<(IO_MUX_DATE_REG_S))
+#define IO_MUX_DATE_REG_V  0xFFFFFFF
+#define IO_MUX_DATE_REG_S  0
+
+#endif

components/soc/esp8684/include/soc/ledc_reg.h

@@ -0,0 +1,1218 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LEDC_REG_H_
+#define _SOC_LEDC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH0  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH0_S  16
+/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH0_S  15
+/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH0  0x000003FF
+#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
+#define LEDC_OVF_NUM_LSCH0_V  0x3FF
+#define LEDC_OVF_NUM_LSCH0_S  5
+/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH0  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V  0x1
+#define LEDC_PARA_UP_LSCH0_S  4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH0  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V  0x1
+#define LEDC_IDLE_LV_LSCH0_S  3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S  2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH0  0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V  0x3
+#define LEDC_TIMER_SEL_LSCH0_S  0
+
+#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH0  0x00003FFF
+#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V  0x3FFF
+#define LEDC_HPOINT_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH0  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V  0x1
+#define LEDC_DUTY_START_LSCH0_S  31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH0  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V  0x1
+#define LEDC_DUTY_INC_LSCH0_S  30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH0  0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S  20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S  10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH1  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH1_S  16
+/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH1_S  15
+/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH1  0x000003FF
+#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
+#define LEDC_OVF_NUM_LSCH1_V  0x3FF
+#define LEDC_OVF_NUM_LSCH1_S  5
+/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH1  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V  0x1
+#define LEDC_PARA_UP_LSCH1_S  4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH1  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V  0x1
+#define LEDC_IDLE_LV_LSCH1_S  3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S  2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH1  0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V  0x3
+#define LEDC_TIMER_SEL_LSCH1_S  0
+
+#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH1  0x00003FFF
+#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V  0x3FFF
+#define LEDC_HPOINT_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH1  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V  0x1
+#define LEDC_DUTY_START_LSCH1_S  31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH1  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V  0x1
+#define LEDC_DUTY_INC_LSCH1_S  30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH1  0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S  20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S  10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH2  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH2_S  16
+/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH2_S  15
+/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH2  0x000003FF
+#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
+#define LEDC_OVF_NUM_LSCH2_V  0x3FF
+#define LEDC_OVF_NUM_LSCH2_S  5
+/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH2  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V  0x1
+#define LEDC_PARA_UP_LSCH2_S  4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH2  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V  0x1
+#define LEDC_IDLE_LV_LSCH2_S  3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S  2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH2  0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V  0x3
+#define LEDC_TIMER_SEL_LSCH2_S  0
+
+#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH2  0x00003FFF
+#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V  0x3FFF
+#define LEDC_HPOINT_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH2  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V  0x1
+#define LEDC_DUTY_START_LSCH2_S  31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH2  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V  0x1
+#define LEDC_DUTY_INC_LSCH2_S  30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH2  0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S  20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S  10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH3  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH3_S  16
+/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH3_S  15
+/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH3  0x000003FF
+#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
+#define LEDC_OVF_NUM_LSCH3_V  0x3FF
+#define LEDC_OVF_NUM_LSCH3_S  5
+/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH3  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V  0x1
+#define LEDC_PARA_UP_LSCH3_S  4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH3  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V  0x1
+#define LEDC_IDLE_LV_LSCH3_S  3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S  2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH3  0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V  0x3
+#define LEDC_TIMER_SEL_LSCH3_S  0
+
+#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH3  0x00003FFF
+#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V  0x3FFF
+#define LEDC_HPOINT_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH3  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V  0x1
+#define LEDC_DUTY_START_LSCH3_S  31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH3  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V  0x1
+#define LEDC_DUTY_INC_LSCH3_S  30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH3  0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S  20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S  10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH4  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH4_S  16
+/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH4_S  15
+/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH4  0x000003FF
+#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
+#define LEDC_OVF_NUM_LSCH4_V  0x3FF
+#define LEDC_OVF_NUM_LSCH4_S  5
+/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH4  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V  0x1
+#define LEDC_PARA_UP_LSCH4_S  4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH4  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V  0x1
+#define LEDC_IDLE_LV_LSCH4_S  3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S  2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH4  0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V  0x3
+#define LEDC_TIMER_SEL_LSCH4_S  0
+
+#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH4  0x00003FFF
+#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V  0x3FFF
+#define LEDC_HPOINT_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH4  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V  0x1
+#define LEDC_DUTY_START_LSCH4_S  31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH4  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V  0x1
+#define LEDC_DUTY_INC_LSCH4_S  30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH4  0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S  20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S  10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH5  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH5_S  16
+/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH5_S  15
+/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH5  0x000003FF
+#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
+#define LEDC_OVF_NUM_LSCH5_V  0x3FF
+#define LEDC_OVF_NUM_LSCH5_S  5
+/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH5  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V  0x1
+#define LEDC_PARA_UP_LSCH5_S  4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH5  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V  0x1
+#define LEDC_IDLE_LV_LSCH5_S  3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S  2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH5  0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V  0x3
+#define LEDC_TIMER_SEL_LSCH5_S  0
+
+#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH5  0x00003FFF
+#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V  0x3FFF
+#define LEDC_HPOINT_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH5  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V  0x1
+#define LEDC_DUTY_START_LSCH5_S  31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH5  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V  0x1
+#define LEDC_DUTY_INC_LSCH5_S  30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH5  0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S  20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S  10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x00a0)
+/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_V  0x1
+#define LEDC_LSTIMER0_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER0  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_V  0x1
+#define LEDC_TICK_SEL_LSTIMER0_S  24
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER0_RST  (BIT(23))
+#define LEDC_LSTIMER0_RST_M  (BIT(23))
+#define LEDC_LSTIMER0_RST_V  0x1
+#define LEDC_LSTIMER0_RST_S  23
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PAUSE  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_V  0x1
+#define LEDC_LSTIMER0_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
+#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER0_S  4
+/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V  0xF
+#define LEDC_LSTIMER0_DUTY_RES_S  0
+
+#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x00a4)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_CNT  0x00003FFF
+#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V  0x3FFF
+#define LEDC_LSTIMER0_CNT_S  0
+
+#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x00a8)
+/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_V  0x1
+#define LEDC_LSTIMER1_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER1  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_V  0x1
+#define LEDC_TICK_SEL_LSTIMER1_S  24
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER1_RST  (BIT(23))
+#define LEDC_LSTIMER1_RST_M  (BIT(23))
+#define LEDC_LSTIMER1_RST_V  0x1
+#define LEDC_LSTIMER1_RST_S  23
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PAUSE  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_V  0x1
+#define LEDC_LSTIMER1_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
+#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER1_S  4
+/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V  0xF
+#define LEDC_LSTIMER1_DUTY_RES_S  0
+
+#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x00aC)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_CNT  0x00003FFF
+#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V  0x3FFF
+#define LEDC_LSTIMER1_CNT_S  0
+
+#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x00b0)
+/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_V  0x1
+#define LEDC_LSTIMER2_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER2  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_V  0x1
+#define LEDC_TICK_SEL_LSTIMER2_S  24
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER2_RST  (BIT(23))
+#define LEDC_LSTIMER2_RST_M  (BIT(23))
+#define LEDC_LSTIMER2_RST_V  0x1
+#define LEDC_LSTIMER2_RST_S  23
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PAUSE  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_V  0x1
+#define LEDC_LSTIMER2_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
+#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER2_S  4
+/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V  0xF
+#define LEDC_LSTIMER2_DUTY_RES_S  0
+
+#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x00b4)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_CNT  0x00003FFF
+#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V  0x3FFF
+#define LEDC_LSTIMER2_CNT_S  0
+
+#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x00b8)
+/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_V  0x1
+#define LEDC_LSTIMER3_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER3  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_V  0x1
+#define LEDC_TICK_SEL_LSTIMER3_S  24
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER3_RST  (BIT(23))
+#define LEDC_LSTIMER3_RST_M  (BIT(23))
+#define LEDC_LSTIMER3_RST_V  0x1
+#define LEDC_LSTIMER3_RST_S  23
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PAUSE  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_V  0x1
+#define LEDC_LSTIMER3_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
+#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER3_S  4
+/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V  0xF
+#define LEDC_LSTIMER3_DUTY_RES_S  0
+
+#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x00BC)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_CNT  0x00003FFF
+#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V  0x3FFF
+#define LEDC_LSTIMER3_CNT_S  0
+
+#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x00C0)
+/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_RAW    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_RAW    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  4
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S  3
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S  2
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S  1
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S  0
+
+#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x00c4)
+/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ST_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ST_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ST_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ST_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ST    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ST_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ST    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ST_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  4
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S  3
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S  2
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S  1
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S  0
+
+#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0xC8)
+/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ENA    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ENA    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  4
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S  3
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S  2
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S  1
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S  0
+
+#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0xCC)
+/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_CLR    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_CLR    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: reg_duty_chng_end_lsch5_int_clr..*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  4
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S  3
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S  2
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S  1
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S  0
+
+#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x00d0)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_CLK_EN  (BIT(31))
+#define LEDC_CLK_EN_M  (BIT(31))
+#define LEDC_CLK_EN_V  0x1
+#define LEDC_CLK_EN_S  31
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define LEDC_APB_CLK_SEL  0x00000003
+#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
+#define LEDC_APB_CLK_SEL_V  0x3
+#define LEDC_APB_CLK_SEL_S  0
+
+#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */
+/*description: */
+#define LEDC_DATE  0xFFFFFFFF
+#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V  0xFFFFFFFF
+#define LEDC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LEDC_REG_H_ */

components/soc/esp8684/include/soc/ledc_struct.h

@@ -0,0 +1,209 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LEDC_STRUCT_H_
+#define _SOC_LEDC_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct ledc_dev_s {
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t timer_sel                     :    2;  /*This field is used to select one of timers for channel $n.; ; 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3*/
+                    uint32_t sig_out_en                    :    1;  /*Set this bit to enable signal output on channel $n.*/
+                    uint32_t idle_lv                       :    1;  /*This bit is used to control the output value when channel $n is inactive (when LEDC_SIG_OUT_EN_CH$n is 0).*/
+                    uint32_t low_speed_update              :    1;  /*This bit is used to update LEDC_HPOINT_CH$n, LEDC_DUTY_START_CH$n, LEDC_SIG_OUT_EN_CH$n, LEDC_TIMER_SEL_CH$n, LEDC_DUTY_NUM_CH$n, LEDC_DUTY_CYCLE_CH$n, LEDC_DUTY_SCALE_CH$n, LEDC_DUTY_INC_CH$n, and LEDC_OVF_CNT_EN_CH$n fields for channel $n, and will be automatically cleared by hardware.*/
+                    uint32_t ovf_num                       :    10;  /*This register is used to configure the maximum times of overflow minus 1.; ; The LEDC_OVF_CNT_CH$n_INT interrupt will be triggered when channel $n overflows for (LEDC_OVF_NUM_CH$n + 1) times.*/
+                    uint32_t ovf_cnt_en                    :    1;  /*This bit is used to enable the ovf_cnt of channel $n.*/
+                    uint32_t ovf_cnt_rst                   :    1;  /*Set this bit to reset the ovf_cnt of channel $n.*/
+                    uint32_t reserved17                    :    15;  /*Reserved*/
+                };
+                uint32_t val;
+            } conf0;
+            union {
+                struct {
+                    uint32_t hpoint                        :    14;  /*The output value changes to high when the selected timers has reached the value specified by this register.*/
+                    uint32_t reserved14                    :    18;  /*Reserved*/
+                };
+                uint32_t val;
+            } hpoint;
+            union {
+                struct {
+                    uint32_t duty                          :    19;  /*This register is used to change the output duty by controlling the Lpoint.; ; The output value turns to low when the selected timers has reached the Lpoint.*/
+                    uint32_t reserved19                    :    13;  /*Reserved*/
+                };
+                uint32_t val;
+            } duty;
+            union {
+                struct {
+                    uint32_t duty_scale                    :    10;  /*This register is used to configure the changing step scale of duty on channel $n.*/
+                    uint32_t duty_cycle                    :    10;  /*The duty will change every LEDC_DUTY_CYCLE_CH$n on channel $n.*/
+                    uint32_t duty_num                      :    10;  /*This register is used to control the number of times the duty cycle will be changed.*/
+                    uint32_t duty_inc                      :    1;  /*This register is used to increase or decrease the duty of output signal on channel $n. 1: Increase; 0: Decrease.*/
+                    uint32_t duty_start                    :    1;  /*Other configured fields in LEDC_CH$n_CONF1_REG will start to take effect when this bit is set to 1.*/
+                };
+                uint32_t val;
+            } conf1;
+            union {
+                struct {
+                    uint32_t duty_read                     :    19;  /*This register stores the current duty of output signal on channel $n.*/
+                    uint32_t reserved19                    :    13;  /*Reserved*/
+                };
+                uint32_t val;
+            } duty_rd;
+        } channel[6];
+    } channel_group[1];
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t duty_resolution               :    4;  /*This register is used to control the range of the counter in timer $x.*/
+                    uint32_t clock_divider                 :    18;  /*This register is used to configure the divisor for the divider in timer $x.; ; The least significant eight bits represent the fractional part.*/
+                    uint32_t pause                         :    1;  /*This bit is used to suspend the counter in timer $x.*/
+                    uint32_t rst                           :    1;  /*This bit is used to reset timer $x. The counter will show 0 after reset.*/
+                    uint32_t tick_sel                      :    1;  /*This bit is used to select clock for timer $x. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.; ; 1'h0: SLOW_CLK 1'h1: REF_TICK*/
+                    uint32_t low_speed_update              :    1;  /*Set this bit to update LEDC_CLK_DIV_TIMER$x and LEDC_TIMER$x_DUTY_RES.*/
+                    uint32_t reserved26                    :    6;  /*Reserved*/
+                };
+                uint32_t val;
+            } conf;
+            union {
+                struct {
+                    uint32_t timer_cnt                     :    14;  /*This register stores the current counter value of timer $x.*/
+                    uint32_t reserved14                    :    18;  /*Reserved*/
+                };
+                uint32_t val;
+            } value;
+        } timer[4];
+    } timer_group[1];
+    union {
+        struct {
+            uint32_t lstimer0_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
+            uint32_t lstimer1_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
+            uint32_t lstimer2_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
+            uint32_t lstimer3_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
+            uint32_t duty_chng_end_ch0             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t duty_chng_end_ch1             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t duty_chng_end_ch2             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t duty_chng_end_ch3             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t duty_chng_end_ch4             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t duty_chng_end_ch5             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
+            uint32_t ovf_cnt_ch0                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t ovf_cnt_ch1                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t ovf_cnt_ch2                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t ovf_cnt_ch3                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t ovf_cnt_ch4                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t ovf_cnt_ch5                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t lstimer0_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
+            uint32_t lstimer1_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
+            uint32_t lstimer2_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
+            uint32_t lstimer3_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
+            uint32_t duty_chng_end_ch0             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t duty_chng_end_ch1             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t duty_chng_end_ch2             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t duty_chng_end_ch3             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t duty_chng_end_ch4             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t duty_chng_end_ch5             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
+            uint32_t ovf_cnt_ch0                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t ovf_cnt_ch1                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t ovf_cnt_ch2                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t ovf_cnt_ch3                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t ovf_cnt_ch4                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t ovf_cnt_ch5                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t lstimer0_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer1_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer2_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer3_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t duty_chng_end_ch0             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch1             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch2             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch3             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch4             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch5             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch0                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch1                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch2                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch3                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch4                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch5                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t lstimer0_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer1_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer2_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t lstimer3_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
+            uint32_t duty_chng_end_ch0             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch1             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch2             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch3             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch4             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t duty_chng_end_ch5             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch0                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch1                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch2                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch3                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch4                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t ovf_cnt_ch5                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t apb_clk_sel                   :    2;  /*This bit is used to select clock source for the 4 timers .; ; 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK*/
+            uint32_t reserved2                     :    29;  /*Reserved*/
+            uint32_t clk_en                        :    1;  /*This bit is used to control clock.; ; 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+        };
+        uint32_t val;
+    } conf;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t date;
+} ledc_dev_t;
+extern ledc_dev_t LEDC;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LEDC_STRUCT_H_ */

components/soc/esp8684/include/soc/mmu.h

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/cache_memory.h"
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined for flash mmap */
+#define SOC_MMU_REGIONS_COUNT                   1
+#define SOC_MMU_PAGES_PER_REGION                64
+#define SOC_MMU_IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
+#define SOC_MMU_ADDR_MASK                       MMU_ADDRESS_MASK
+#define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
+#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
+#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
+#define SOC_MMU_VADDR0_START_ADDR               (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
+#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/nrx_reg.h

@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
+#define NRX_CHAN_EST_FORCE_PU_S 7
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
+#define NRX_CHAN_EST_FORCE_PD_S 6
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
+#define NRX_RX_ROT_FORCE_PU_S 5
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
+#define NRX_RX_ROT_FORCE_PD_S 4
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
+#define NRX_VIT_FORCE_PU_S 3
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
+#define NRX_VIT_FORCE_PD_S 2
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
+#define NRX_DEMAP_FORCE_PU_S 1
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
+#define NRX_DEMAP_FORCE_PD_S 0

components/soc/esp8684/include/soc/periph_defs.h

@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PERIPH_LEDC_MODULE = 0,
+    PERIPH_UART0_MODULE,
+    PERIPH_UART1_MODULE,
+    PERIPH_USB_DEVICE_MODULE,
+    PERIPH_I2C0_MODULE,
+    PERIPH_TIMG0_MODULE,
+    PERIPH_TIMG1_MODULE,  //No timg1 on esp8684, please remove TODO: IDF-3825
+    PERIPH_UHCI0_MODULE,
+    PERIPH_RMT_MODULE,
+    PERIPH_SPI_MODULE,  //SPI1
+    PERIPH_SPI2_MODULE, //SPI2
+    PERIPH_TWAI_MODULE,
+    PERIPH_RNG_MODULE,
+    PERIPH_WIFI_MODULE,
+    PERIPH_BT_MODULE,
+    PERIPH_WIFI_BT_COMMON_MODULE,
+    PERIPH_BT_BASEBAND_MODULE,
+    PERIPH_BT_LC_MODULE,
+    PERIPH_RSA_MODULE,
+    PERIPH_AES_MODULE,
+    PERIPH_SHA_MODULE,
+    PERIPH_HMAC_MODULE,
+    PERIPH_DS_MODULE,
+    PERIPH_GDMA_MODULE,
+    PERIPH_SYSTIMER_MODULE,
+    PERIPH_SARADC_MODULE,
+    PERIPH_MODULE_MAX
+} periph_module_t;
+
+typedef enum {
+    ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
+    ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
+    ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
+    ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
+    ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
+    ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
+    ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
+    ETS_LP_TIMER_SOURCE,                       /**< interrupt of RWBT, level*/
+    ETS_COEX_SOURCE,                      /**< interrupt of RWBLE, level*/
+    ETS_BLE_TIMER_SOURCE,                        /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_BLE_SEC_SOURCE,                       /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_I2C_MASTER_SOURCE,                      /**< interrupt of I2C Master, level*/
+    ETS_APB_CTRL_INTR_SOURCE,                   /**< interrupt of APB ctrl, ?*/
+    ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
+    ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
+    ETS_SPI1_INTR_SOURCE,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
+    ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
+    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
+    ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
+    ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
+    ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
+    ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
+    ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
+    ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
+    ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
+    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
+    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
+    ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
+    ETS_ICACHE_SYNC0_INTR_SOURCE,               /**< interrupt of instruction cache sync done, LEVEL*/
+    ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
+    ETS_DMA_CH0_INTR_SOURCE,                    /**< interrupt of general DMA channel 0, LEVEL*/
+    ETS_SHA_INTR_SOURCE,                        /**< interrupt of SHA accelerator, level*/
+    ETS_ECC_INTR_SOURCE,                        /**< interrupt of ECC accelerator, level*/
+    ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
+    ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
+    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
+    ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
+    ETS_CACHE_CORE0_ACS_INTR_SOURCE,
+    ETS_MAX_INTR_SOURCE,
+} periph_interrput_t;
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/reset_reasons.h

@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+//+-----------------------------------------------Terminology---------------------------------------------+
+//|                                                                                                       |
+//| CPU Reset:    Reset CPU core only, once reset done, CPU will execute from reset vector                |
+//|                                                                                                       |
+//| Core Reset:   Reset the whole digital system except RTC sub-system                                    |
+//|                                                                                                       |
+//| System Reset: Reset the whole digital system, including RTC sub-system                                |
+//|                                                                                                       |
+//| Chip Reset:   Reset the whole chip, including the analog part                                         |
+//|                                                                                                       |
+//+-------------------------------------------------------------------------------------------------------+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
+ * @note refer to TRM: <Reset and Clock> chapter
+ */
+typedef enum {
+    RESET_REASON_CHIP_POWER_ON   = 0x01, // Power on reset
+    RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
+    RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
+    RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core
+    RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core
+    RESET_REASON_CPU0_MWDT0      = 0x0B, // Main watch dog 0 resets CPU 0
+    RESET_REASON_CPU0_SW         = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
+    RESET_REASON_CPU0_RTC_WDT    = 0x0D, // RTC watch dog resets CPU 0
+    RESET_REASON_SYS_BROWN_OUT   = 0x0F, // VDD voltage is not stable and resets the digital core
+    RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
+    RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
+    RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core
+    RESET_REASON_JTAG_RESET = 0x18,
+} soc_reset_reason_t;
+
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/rtc.h

@@ -0,0 +1,858 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock, and sleep functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ * - rtc_sleep: entry into sleep modes
+ * - rtc_init: initialization
+ */
+
+#define MHZ (1000000)
+
+#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
+
+#define RTC_SLOW_CLK_FREQ_150K      150000
+#define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_APPROX / 256)
+#define RTC_SLOW_CLK_FREQ_32K       32768
+
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DBIAS_SLP  0 //sleep dig_dbias & rtc_dbias
+#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
+#define RTC_CNTL_DBIAS_0V95 16
+#define RTC_CNTL_DBIAS_1V00 18
+#define RTC_CNTL_DBIAS_1V05 20
+#define RTC_CNTL_DBIAS_1V10 23
+#define RTC_CNTL_DBIAS_1V15 25
+#define RTC_CNTL_DBIAS_1V20 28
+#define RTC_CNTL_DBIAS_1V25 30
+#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
+
+#define DELAY_FAST_CLK_SWITCH           3
+#define DELAY_SLOW_CLK_SWITCH           300
+#define DELAY_8M_ENABLE                 50
+
+/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
+ * 10 cycles will take approximately 300 microseconds.
+ */
+#define XTAL_FREQ_EST_CYCLES            10
+
+#define DIG_DBIAS_80M   RTC_CNTL_DBIAS_1V20
+#define DIG_DBIAS_160M  RTC_CNTL_DBIAS_1V20
+
+#define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
+#define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00
+
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
+
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+
+/* Various delays to be programmed into power control state machines */
+#define RTC_CNTL_XTL_BUF_WAIT_SLP_US            (250)
+#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES        (1)
+#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES           (4)
+#define RTC_CNTL_WAKEUP_DELAY_CYCLES            (5)
+#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES    (1)
+#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES       (1)
+
+/*
+set sleep_init default param
+*/
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  3
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  0
+#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
+
+/*
+The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
+storing in efuse (based on ATE 5k ECO3 chips)
+*/
+#define K_RTC_MID_MUL10000 215
+#define K_DIG_MID_MUL10000 213
+#define V_RTC_MID_MUL10000  10800
+#define V_DIG_MID_MUL10000  10860
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_32M = 32,
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU frequency values
+ */
+typedef enum {
+    RTC_CPU_FREQ_XTAL = 0,      //!< Main XTAL frequency
+    RTC_CPU_FREQ_80M = 1,       //!< 80 MHz
+    RTC_CPU_FREQ_160M = 2,      //!< 160 MHz
+    RTC_CPU_FREQ_240M = 3,      //!< 240 MHz
+    RTC_CPU_FREQ_2M = 4,        //!< 2 MHz
+    RTC_CPU_320M_80M = 5,       //!< for test
+    RTC_CPU_320M_160M = 6,      //!< for test
+    RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
+} rtc_cpu_freq_t;
+
+/**
+ * @brief CPU clock source
+ */
+typedef enum {
+    RTC_CPU_FREQ_SRC_XTAL,  //!< XTAL
+    RTC_CPU_FREQ_SRC_PLL,   //!< PLL (480M or 320M)
+    RTC_CPU_FREQ_SRC_8M,    //!< Internal 8M RTC oscillator
+    RTC_CPU_FREQ_SRC_APLL   //!< APLL
+} rtc_cpu_freq_src_t;
+
+/**
+ * @brief CPU clock configuration structure
+ */
+typedef struct rtc_cpu_freq_config_s {
+    rtc_cpu_freq_src_t source;      //!< The clock from which CPU clock is derived
+    uint32_t source_freq_mhz;       //!< Source clock frequency
+    uint32_t div;                   //!< Divider, freq_mhz = source_freq_mhz / div
+    uint32_t freq_mhz;              //!< CPU clock frequency
+} rtc_cpu_freq_config_t;
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef enum {
+    RTC_SLOW_FREQ_RTC = 0,      //!< Internal 150 kHz RC oscillator
+    RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
+    RTC_SLOW_FREQ_8MD256 = 2,   //!< Internal 8 MHz RC oscillator, divided by 256
+} rtc_slow_freq_t;
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef enum {
+    RTC_FAST_FREQ_XTALD4 = 0,   //!< Main XTAL, divided by 4
+    RTC_FAST_FREQ_8M = 1,       //!< Internal 8 MHz RC oscillator
+} rtc_fast_freq_t;
+
+/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
+#define RTC_FAST_CLK_FREQ_APPROX 8500000
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
+    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
+    RTC_CAL_32K_XTAL = 2       //!< External 32 kHz XTAL
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;  //!< Main XTAL frequency
+    uint32_t cpu_freq_mhz : 10;    //!< CPU frequency to set, in MHz
+    rtc_fast_freq_t fast_freq : 1;  //!< RTC_FAST_CLK frequency to set
+    rtc_slow_freq_t slow_freq : 2;  //!< RTC_SLOW_CLK frequency to set
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;        //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
+    uint32_t slow_clk_dcap : 8;     //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;      //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = RTC_XTAL_FREQ_40M, \
+    .cpu_freq_mhz = 80, \
+    .fast_freq = RTC_FAST_FREQ_8M, \
+    .slow_freq = RTC_SLOW_FREQ_RTC, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+}
+
+typedef struct {
+    uint32_t dac : 6;
+    uint32_t dres : 3;
+    uint32_t dgm : 3;
+    uint32_t dbuf: 1;
+} x32k_config_t;
+
+#define X32K_CONFIG_DEFAULT() { \
+    .dac = 3, \
+    .dres = 3, \
+    .dgm = 3, \
+    .dbuf = 1, \
+}
+
+typedef struct {
+    uint16_t wifi_powerup_cycles : 7;
+    uint16_t wifi_wait_cycles : 9;
+    uint16_t bt_powerup_cycles : 7;
+    uint16_t bt_wait_cycles : 9;
+    uint16_t cpu_top_powerup_cycles : 7;
+    uint16_t cpu_top_wait_cycles : 9;
+    uint16_t dg_wrap_powerup_cycles : 7;
+    uint16_t dg_wrap_wait_cycles : 9;
+    uint16_t dg_peri_powerup_cycles : 7;
+    uint16_t dg_peri_wait_cycles : 9;
+} rtc_init_config_t;
+
+#define RTC_INIT_CONFIG_DEFAULT() { \
+    .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .bt_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
+}
+
+void rtc_clk_divider_set(uint32_t div);
+
+void rtc_clk_8m_divider_set(uint32_t div);
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external(void);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled(void);
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * Output from 8 MHz internal oscillator is passed into a configurable
+ * divider, which by default divides the input clock frequency by 256.
+ * Output of the divider may be used as RTC_SLOW_CLK source.
+ * Output of the divider is referred to in register descriptions and code as
+ * 8md256 or simply d256. Divider values other than 256 may be configured, but
+ * this facility is not currently needed, so is not exposed in the code.
+ *
+ * When 8MHz/256 divided output is not needed, the divider should be disabled
+ * to reduce power consumption.
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ * @param d256_en true to enable /256 divider
+ */
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled(void);
+
+/**
+ * @brief Get the state of /256 divider which is applied to 8MHz clock
+ * @return true if the divided output is enabled
+ */
+bool rtc_clk_8md256_enabled(void);
+
+/**
+ * @brief Enable or disable APLL
+ *
+ * Output frequency is given by the formula:
+ * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
+ *
+ * The dividend in this expression should be in the range of 240 - 600 MHz.
+ *
+ * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
+ *
+ * @param enable  true to enable, false to disable
+ * @param sdm0  frequency adjustment parameter, 0..255
+ * @param sdm1  frequency adjustment parameter, 0..255
+ * @param sdm2  frequency adjustment parameter, 0..63
+ * @param o_div  frequency divider, 0..31
+ */
+void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param slow_freq clock source (one of rtc_slow_freq_t values)
+ */
+void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of rtc_slow_freq_t values)
+ */
+rtc_slow_freq_t rtc_clk_slow_freq_get(void);
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
+ * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
+ * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz(void);
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param fast_freq clock source (one of rtc_fast_freq_t values)
+ */
+void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of rtc_fast_freq_t values)
+ */
+rtc_fast_freq_t rtc_clk_fast_freq_get(void);
+
+/**
+ * @brief Get CPU frequency config for a given frequency
+ * @param freq_mhz  Frequency in MHz
+ * @param[out] out_config Output, CPU frequency configuration structure
+ * @return true if frequency can be obtained, false otherwise
+ */
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This function sets CPU frequency according to the given configuration
+ * structure. It enables PLLs, if necessary.
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Switch CPU frequency (optimized for speed)
+ *
+ * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
+ * It works faster because it does not disable PLLs when switching from PLL to
+ * XTAL and does not enabled them when switching back. If PLL is not already
+ * enabled when this function is called to switch from XTAL to PLL frequency,
+ * or the PLL which is enabled is the wrong one, this function will fall back
+ * to calling rtc_clk_cpu_freq_set_config.
+ *
+ * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
+ * so it is less safe to use it e.g. from a panic handler (when memory might
+ * be corrupted).
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Get the currently used CPU frequency configuration
+ * @param[out] out_config  Output, CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU clock source to XTAL
+ *
+ * Short form for filling in rtc_cpu_freq_config_t structure and calling
+ * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
+ * Assumes that XTAL frequency has been determined — don't call in startup code.
+ */
+void rtc_clk_cpu_freq_set_xtal(void);
+
+/**
+ * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ *
+ * This function doesn't change any hardware clocks.
+ *
+ * Functions which perform frequency switching and change APB frequency call
+ * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
+ * (one of RTC general purpose retention registers). This should not normally
+ * be called from application code.
+ *
+ * @param apb_freq  new APB frequency, in Hz
+ */
+void rtc_clk_apb_freq_update(uint32_t apb_freq);
+
+/**
+ * @brief Get the current stored APB frequency.
+ * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get(void);
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
+ * @param cal_clk slow clock to be measured
+ * @param slow_clk_cycles number of slow clock cycles to average
+ * @return average ratio between XTAL frequency and slow clock frequency,
+ *         Q13.19 fixed point format, or 0 if calibration has timed out.
+ */
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get(void);
+
+uint64_t rtc_light_slp_time_get(void);
+
+uint64_t rtc_deep_slp_time_get(void);
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle(void);
+
+/**
+ * @brief Enable the rtc digital 8M clock
+ *
+ * This function is used to enable the digital rtc 8M clock to support peripherals.
+ * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
+ */
+void rtc_dig_clk8m_enable(void);
+
+/**
+ * @brief Disable the rtc digital 8M clock
+ *
+ * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
+ */
+void rtc_dig_clk8m_disable(void);
+
+/**
+ * @brief Calculate the real clock value after the clock calibration
+ *
+ * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
+ * @return Frequency of the clock in Hz
+ */
+uint32_t rtc_clk_freq_cal(uint32_t cal_val);
+
+/**
+ * @brief Power down flags for rtc_sleep_pd function
+ */
+typedef struct {
+    uint32_t dig_fpu : 1;    //!< Set to 1 to power UP digital part in sleep
+    uint32_t rtc_fpu : 1;    //!< Set to 1 to power UP RTC memories in sleep
+    uint32_t cpu_fpu : 1;    //!< Set to 1 to power UP digital memories and CPU in sleep
+    uint32_t i2s_fpu : 1;    //!< Set to 1 to power UP I2S in sleep
+    uint32_t bb_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
+    uint32_t nrx_fpu : 1;    //!< Set to 1 to power UP WiFi in sleep
+    uint32_t fe_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
+    uint32_t sram_fpu : 1;    //!< Set to 1 to power UP SRAM in sleep
+    uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
+} rtc_sleep_pu_config_t;
+
+/**
+ * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
+ */
+#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
+    .dig_fpu = (val), \
+    .rtc_fpu = (val), \
+    .cpu_fpu = (val), \
+    .i2s_fpu = (val), \
+    .bb_fpu = (val), \
+    .nrx_fpu = (val), \
+    .fe_fpu = (val), \
+    .sram_fpu = (val), \
+    .rom_ram_fpu = (val), \
+}
+
+void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
+
+/**
+ * @brief sleep configuration for rtc_sleep_init function
+ */
+typedef struct {
+    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
+    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
+    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
+    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
+    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
+    uint32_t wifi_pd_en : 1;            //!< power down WiFi
+    uint32_t bt_pd_en : 1;              //!< power down BT
+    uint32_t cpu_pd_en : 1;             //!< power down CPU, but not restart when lightsleep.
+    uint32_t int_8m_pd_en : 1;          //!< Power down Internal 8M oscillator
+    uint32_t dig_peri_pd_en : 1;        //!< power down digital peripherals
+    uint32_t deep_slp : 1;              //!< power down digital domain
+    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
+    uint32_t dig_dbias_wak : 5;         //!< set bias for digital domain, in active mode
+    uint32_t dig_dbias_slp : 5;         //!< set bias for digital domain, in sleep mode
+    uint32_t rtc_dbias_wak : 5;         //!< set bias for RTC domain, in active mode
+    uint32_t rtc_dbias_slp : 5;         //!< set bias for RTC domain, in sleep mode
+    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
+    uint32_t xtal_fpu : 1;              //!< keep main XTAL powered up in sleep
+    uint32_t deep_slp_reject : 1;
+    uint32_t light_slp_reject : 1;
+} rtc_sleep_config_t;
+
+/**
+ * Default initializer for rtc_sleep_config_t
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use) based on a combination of RTC_SLEEP_PD_x flags.
+ *
+ * @param RTC_SLEEP_PD_x flags combined using bitwise OR
+ */
+#define is_dslp(pd_flags)   ((pd_flags) & RTC_SLEEP_PD_DIG)
+#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
+    .lslp_mem_inf_fpu = 0, \
+    .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
+    .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
+    .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
+    .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
+    .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
+    .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
+    .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
+    .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
+    .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
+    .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
+    .wdt_flashboot_mod_en = 0, \
+    .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .dig_dbias_slp = is_dslp(sleep_flags)                   ? RTC_CNTL_DBIAS_SLP  \
+                   : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
+                   : RTC_CNTL_DBIAS_SLP, \
+    .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .rtc_dbias_slp = is_dslp(sleep_flags)                   ? RTC_CNTL_DBIAS_SLP  \
+                   : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
+                   : RTC_CNTL_DBIAS_SLP, \
+    .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
+    .xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
+    .deep_slp_reject = 1, \
+    .light_slp_reject = 1 \
+};
+#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
+#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
+#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
+#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
+#define RTC_SLEEP_PD_WIFI               BIT(6)  //!< Power down WIFI
+#define RTC_SLEEP_PD_BT                 BIT(7)  //!< Power down BT
+#define RTC_SLEEP_PD_CPU                BIT(8)  //!< Power down CPU when in lightsleep, but not restart
+#define RTC_SLEEP_PD_DIG_PERIPH         BIT(9)  //!< Power down DIG peripherals
+#define RTC_SLEEP_PD_INT_8M             BIT(10) //!< Power down Internal 8M oscillator
+#define RTC_SLEEP_PD_XTAL               BIT(11) //!< Power down main XTAL
+
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power control state machines to handle
+ * entry into light sleep or deep sleep mode, switches APB and CPU clock source
+ * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * rtc_sleep_start function. Software may do some other actions between
+ * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ * @param cfg sleep mode configuration
+ */
+void rtc_sleep_init(rtc_sleep_config_t cfg);
+
+/**
+ * @brief Low level initialize for rtc state machine waiting cycles after waking up
+ *
+ * This function configures the cycles chip need to wait for internal 8MHz
+ * oscillator and external 40MHz crystal. As we configure fixed time for waiting
+ * crystal, we need to pass period to calculate cycles. Now this function only
+ * used in lightsleep mode.
+ *
+ * @param slowclk_period re-calibrated slow clock period
+ */
+void rtc_sleep_low_init(uint32_t slowclk_period);
+
+/**
+ * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
+ * @param t value of RTC counter at which wakeup from sleep will happen;
+ *          only the lower 48 bits are used
+ */
+void rtc_sleep_set_wakeup_time(uint64_t t);
+
+#define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
+#define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup
+#define RTC_WIFI_TRIG_EN            BIT(5)  //!< WIFI wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN           BIT(6)  //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN           BIT(7)  //!< UART1 wakeup (light sleep only)
+#define RTC_BT_TRIG_EN              BIT(10) //!< BT wakeup (light sleep only)
+#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
+#define RTC_USB_TRIG_EN             BIT(14)
+#define RTC_BROWNOUT_DET_TRIG_EN    BIT(16)
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using rtc_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using rtc_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons:
+ *                      - RTC_CNTL_GPIO_REJECT_EN
+ *                      - RTC_CNTL_SDIO_REJECT_EN
+ *                    These flags are used to prevent entering sleep when e.g.
+ *                    an external host is communicating via SDIO slave
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
+
+/**
+ * @brief Enter deep sleep mode
+ *
+ * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
+ * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
+ * stub is valid to execute (if a wake address is set).
+ *
+ * No RAM is accessed while calculating the CRC and going into deep sleep, which makes
+ * this function safe to use even if the caller's stack is in RTC FAST memory.
+ *
+ * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
+ * have the same effect and takes less time as CRC calculation is skipped.
+ *
+ * @note This function should only be called after rtc_sleep_init() has been called to
+ * configure the system for deep sleep.
+ *
+ * @param wakeup_opt - same as for rtc_sleep_start
+ * @param reject_opt - same as for rtc_sleep_start
+ *
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
+
+/**
+ * RTC power and clock control initialization settings
+ */
+typedef struct {
+    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
+    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
+    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
+    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
+    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
+    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
+    uint32_t xtal_fpu : 1;
+    uint32_t bbpll_fpu : 1;
+    uint32_t cpu_waiti_clk_gate : 1;
+    uint32_t cali_ocode : 1;        //!< Calibrate Ocode to make bangap voltage more precise.
+} rtc_config_t;
+
+/**
+ * Default initializer of rtc_config_t.
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use).
+ */
+#define RTC_CONFIG_DEFAULT() {\
+    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
+    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
+    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
+    .clkctl_init = 1, \
+    .pwrctl_init = 1, \
+    .rtc_dboost_fpd = 1, \
+    .xtal_fpu = 0, \
+    .bbpll_fpu = 0, \
+    .cpu_waiti_clk_gate = 1, \
+    .cali_ocode = 0\
+}
+
+/**
+ * Initialize RTC clock and power control related functions
+ * @param cfg configuration options as rtc_config_t
+ */
+void rtc_init(rtc_config_t cfg);
+
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/rtc_cntl_reg.h

@@ -0,0 +1,1929 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
+/* RTC_CNTL_SW_SYS_RST :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset.*/
+#define RTC_CNTL_SW_SYS_RST    (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST :  ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO :  ;bitpos:[28] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_ANALOG_FORCE_ISO :  ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_XTL_EXT_CTR_SEL :  ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTL_EXT_CTR_SEL    0x00000007
+#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
+#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
+#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
+/* RTC_CNTL_XTL_EN_WAIT :  ;bitpos:[17:14] ;default: 4'd2 ; */
+/*description: wait bias_sleep and current source wakeup.*/
+#define RTC_CNTL_XTL_EN_WAIT    0x0000000F
+#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
+#define RTC_CNTL_XTL_EN_WAIT_V  0xF
+#define RTC_CNTL_XTL_EN_WAIT_S  14
+/* RTC_CNTL_XTL_FORCE_PU :  ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up.*/
+#define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down.*/
+#define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up.*/
+#define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down.*/
+#define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU :  ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU :  ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up.*/
+#define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down.*/
+#define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset.*/
+#define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_STALL_PROCPU_C0 :  ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
+RO CPU.*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
+/* RTC_CNTL_SLP_VAL_LO :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN :  ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit.*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits.*/
+#define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
+/* RTC_CNTL_TIME_UPDATE :  ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer.*/
+#define RTC_CNTL_TIME_UPDATE    (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIMER_SYS_RST :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time.*/
+#define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time.*/
+#define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time.*/
+#define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
+/* RTC_CNTL_TIMER_VALUE0_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
+/* RTC_CNTL_TIMER_VALUE0_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
+/* RTC_CNTL_SLEEP_EN :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit.*/
+#define RTC_CNTL_SLEEP_EN    (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit.*/
+#define RTC_CNTL_SLP_REJECT    (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP :  ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit.*/
+#define RTC_CNTL_SLP_WAKEUP    (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND :  ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication.*/
+#define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL :  ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge.*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause.*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu.*/
+#define RTC_CNTL_SW_CPU_INT    (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
+/* RTC_CNTL_PLL_BUF_WAIT :  ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+/* RTC_CNTL_XTL_BUF_WAIT :  ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+/* RTC_CNTL_CK8M_WAIT :  ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_CK8M_WAIT    0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+/* RTC_CNTL_CPU_STALL_WAIT :  ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc.*/
+#define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN :  ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit.*/
+#define RTC_CNTL_CPU_STALL_EN    (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF :  ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x24)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER :  ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER :  ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x28)
+/* RTC_CNTL_MIN_SLP_VAL :  ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc.*/
+#define RTC_CNTL_MIN_SLP_VAL    0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+#define RTC_CNTL_MIN_SLP_VAL_MIN 2
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
+/* RTC_CNTL_PLL_I2C_PU :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_PLL_I2C_PU    (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up.*/
+#define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU :  ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up.*/
+#define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU :  ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up.*/
+#define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_BBPLL_CAL_SLP_START :  ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep.*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_SAR_I2C_PU :  ;bitpos:[22] ;default: 1'b1 ; */
+/*description: PLLA force power up.*/
+#define RTC_CNTL_SAR_I2C_PU    (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_V  0x1
+#define RTC_CNTL_SAR_I2C_PU_S  22
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD :  ;bitpos:[18] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x30)
+/* RTC_CNTL_DRESET_MASK_PROCPU :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DRESET_MASK_PROCPU    (BIT(20))
+#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(20))
+#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_PROCPU_S  20
+/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: PROCPU OcdHaltOnReset.*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU    (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
+/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU :  ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel.*/
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU    (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
+/* RTC_CNTL_RESET_CAUSE_PROCPU :  ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU.*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
+/* RTC_CNTL_WAKEUP_ENA :  ;bitpos:[31:15] ;default: 17'b1100 ; */
+/*description: wakeup enable bitmap.*/
+#define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x38)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA : BIT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
+/* RTC_CNTL_SWD_INT_ENA : BIT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : BIT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : BIT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_WDT_INT_ENA : BIT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA : BIT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : BIT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
+/* RTC_CNTL_BBPLL_CAL_INT_RAW :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_RAW    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
+/* RTC_CNTL_SWD_INT_RAW :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw.*/
+#define RTC_CNTL_SWD_INT_RAW    (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_RAW :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw.*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw.*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_WDT_INT_RAW :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw.*/
+#define RTC_CNTL_WDT_INT_RAW    (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SLP_REJECT_INT_RAW :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw.*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x40)
+/* RTC_CNTL_BBPLL_CAL_INT_ST :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ST    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
+/* RTC_CNTL_SWD_INT_ST :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_ST    (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ST :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_WDT_INT_ST :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_ST    (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ST :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x44)
+/* RTC_CNTL_BBPLL_CAL_INT_CLR :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_CLR    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
+/* RTC_CNTL_SWD_INT_CLR :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_CLR    (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_CLR :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_WDT_INT_CLR :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_CLR    (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SLP_REJECT_INT_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x48)
+/* RTC_CNTL_SCRATCH0 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH0    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
+/* RTC_CNTL_SCRATCH1 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH1    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x50)
+/* RTC_CNTL_SCRATCH2 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH2    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x54)
+/* RTC_CNTL_SCRATCH3 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH3    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x58)
+/* RTC_CNTL_XTL_EXT_CTR_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level.*/
+#define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable filter for gpio wakeup event.*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep.*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep.*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA :  ;bitpos:[29:12] ;default: 17'd0 ; */
+/*description: sleep reject enable.*/
+#define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
+/* RTC_CNTL_CPUPERIOD_SEL :  ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_CPUPERIOD_SEL    0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option.*/
+#define RTC_CNTL_CPUSEL_CONF    (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
+/* RTC_CNTL_ANA_CLK_RTC_SEL :  ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 4.*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING :  ;bitpos:[28] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
+/* RTC_CNTL_CK8M_FORCE_PU :  ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up.*/
+#define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD :  ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down.*/
+#define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ :  ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ.*/
+#define RTC_CNTL_CK8M_DFREQ    0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+/* RTC_CNTL_CK8M_FORCE_NOGATING :  ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep.*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING :  ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep.*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL :  ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1.*/
+#define RTC_CNTL_CK8M_DIV_SEL    0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN :  ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN :  ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN :  ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV :  ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M.*/
+#define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M :  ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT.*/
+#define RTC_CNTL_ENB_CK8M    (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV :  ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128.*/
+#define RTC_CNTL_CK8M_DIV    0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD :  ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV :  ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANA_CLK_DIV    0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD :  ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
+/* RTC_CNTL_DBG_ATTEN_ACTIVE :  ;bitpos:[29:26] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DBG_ATTEN_ACTIVE    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_M  ((RTC_CNTL_DBG_ATTEN_ACTIVE_V)<<(RTC_CNTL_DBG_ATTEN_ACTIVE_S))
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_V  0xF
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_S  26
+/* RTC_CNTL_DBG_ATTEN_MONITOR :  ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in active state.*/
+#define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP :  ;bitpos:[21:18] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in sleep state.*/
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
+/* RTC_CNTL_BIAS_SLEEP_MONITOR :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: bias_sleep when rtc in monitor state.*/
+#define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP :  ;bitpos:[16] ;default: 1'b1 ; */
+/*description: bias_sleep when rtc in sleep_state.*/
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
+/* RTC_CNTL_PD_CUR_MONITOR :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in monitor state.*/
+#define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
+#define RTC_CNTL_PD_CUR_MONITOR_S  15
+/* RTC_CNTL_PD_CUR_DEEP_SLP :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in sleep_state.*/
+#define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
+/* RTC_CNTL_BIAS_BUF_MONITOR :  ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
+/* RTC_CNTL_BIAS_BUF_WAKE :  ;bitpos:[11] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
+#define RTC_CNTL_BIAS_BUF_WAKE_S  11
+/* RTC_CNTL_BIAS_BUF_IDLE :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
+#define RTC_CNTL_BIAS_BUF_IDLE_S  10
+/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN    (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
+/* RTC_CNTL_DG_VDD_DRV_B_SLP :  ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x74)
+/* RTC_CNTL_REGULATOR_FORCE_PU :  ;bitpos:[31] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
+.8v or lower ).*/
+#define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_SCK_DCAP :  ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP.*/
+#define RTC_CNTL_SCK_DCAP    0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+/* RTC_CNTL_DIG_REG_CAL_EN :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_REG_CAL_EN    (BIT(7))
+#define RTC_CNTL_DIG_REG_CAL_EN_M  (BIT(7))
+#define RTC_CNTL_DIG_REG_CAL_EN_V  0x1
+#define RTC_CNTL_DIG_REG_CAL_EN_S  7
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x78)
+/* RTC_CNTL_PAD_FORCE_HOLD :  ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold.*/
+#define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
+/* RTC_CNTL_DG_WRAP_PD_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_PU :  ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_LSLP_MEM_FORCE_PU :  ;bitpos:[5] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(5))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(5))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  5
+/* RTC_CNTL_LSLP_MEM_FORCE_PD :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  4
+/* RTC_CNTL_VDD_SPI_PD_EN :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PD_EN    (BIT(3))
+#define RTC_CNTL_VDD_SPI_PD_EN_M  (BIT(3))
+#define RTC_CNTL_VDD_SPI_PD_EN_V  0x1
+#define RTC_CNTL_VDD_SPI_PD_EN_S  3
+/* RTC_CNTL_VDD_SPI_PWR_FORCE :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PWR_FORCE    (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
+/* RTC_CNTL_VDD_SPI_PWR_DRV :  ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PWR_DRV    0x00000003
+#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
+#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
+#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x80)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO :  ;bitpos:[31] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO.*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_DG_PAD_FORCE_HOLD :  ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD :  ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO :  ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO :  ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD :  ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold.*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD :  ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON :  ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF :  ;bitpos:[7] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x84)
+/* RTC_CNTL_WDT_EN :  ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_EN    (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 :  ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG0    0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 :  ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG1    0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 :  ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG2    0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 :  ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG3    0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
+#define RTC_WDT_STG_SEL_RESET_RTC       4
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH :  ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length.*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH :  ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length.*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN :  ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot.*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU.*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_PAUSE_IN_SLP :  ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep.*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable.*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH :  ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width.*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x88)
+/* RTC_CNTL_WDT_STG0_HOLD :  ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
+/* RTC_CNTL_WDT_STG1_HOLD :  ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x90)
+/* RTC_CNTL_WDT_STG2_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x94)
+/* RTC_CNTL_WDT_STG3_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x98)
+/* RTC_CNTL_WDT_FEED :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_FEED    (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
+/* RTC_CNTL_WDT_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
+/* RTC_CNTL_SWD_AUTO_FEED_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes.*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disabel SWD.*/
+#define RTC_CNTL_SWD_DISABLE    (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd.*/
+#define RTC_CNTL_SWD_FEED    (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag.*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH :  ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd.*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_BYPASS_RST :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
+#define RTC_CNTL_SWD_BYPASS_RST_S  17
+/* RTC_CNTL_SWD_FEED_INT :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding.*/
+#define RTC_CNTL_SWD_FEED_INT    (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag.*/
+#define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
+/* RTC_CNTL_SWD_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 :  ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
+/* RTC_CNTL_SCRATCH4 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH4    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
+/* RTC_CNTL_SCRATCH5 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH5    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
+/* RTC_CNTL_SCRATCH6 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH6    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
+/* RTC_CNTL_SCRATCH7 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH7    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
+/* RTC_CNTL_MAIN_STATE :  ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status.*/
+#define RTC_CNTL_MAIN_STATE    0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state.*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state.*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL :  ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL :  ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M :  ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE :  ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power.*/
+#define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE :  ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process.*/
+#define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles.*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source.*/
+#define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON :  ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running.*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more.*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE :  ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done.*/
+#define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state.*/
+#define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state.*/
+#define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START :  ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work.*/
+#define RTC_CNTL_COCPU_STATE_START    (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done.*/
+#define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP :  ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state.*/
+#define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state.*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work.*/
+#define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down.*/
+#define RTC_CNTL_XPD_DIG    (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
+/* RTC_CNTL_LOW_POWER_DIAG1 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
+/* RTC_CNTL_GPIO_PIN5_HOLD :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_HOLD    (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
+/* RTC_CNTL_GPIO_PIN4_HOLD :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_HOLD    (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
+/* RTC_CNTL_GPIO_PIN3_HOLD :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_HOLD    (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
+/* RTC_CNTL_GPIO_PIN2_HOLD :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_HOLD    (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
+/* RTC_CNTL_GPIO_PIN1_HOLD :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_HOLD    (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
+/* RTC_CNTL_GPIO_PIN0_HOLD :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_HOLD    (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
+/* RTC_CNTL_DIG_PAD_HOLD :  ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
+/* RTC_CNTL_BROWN_OUT_DET :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA :  ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable brown out.*/
+#define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter.*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
+/* RTC_CNTL_BROWN_OUT_RST_SEL :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1:  4-pos reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
+/* RTC_CNTL_BROWN_OUT_RST_ENA :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT :  ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT :  ;bitpos:[13:4] ;default: 10'h1 ; */
+/*description: brown out interrupt wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
+/* RTC_CNTL_TIMER_VALUE1_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
+/* RTC_CNTL_TIMER_VALUE1_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
+/* RTC_CNTL_IO_MUX_RESET_DISABLE :  ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
+
+#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
+/* RTC_CNTL_REJECT_CAUSE :  ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: sleep reject cause.*/
+#define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT :  ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
+
+#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
+/* RTC_CNTL_WAKEUP_CAUSE :  ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: sleep wakeup cause.*/
+#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE :  ;bitpos:[31:8] ;default: 24'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer.*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
+#define RTC_CNTL_INT_ENA_RTC_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
+/* RTC_CNTL_SWD_INT_ENA_W1TS :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TS :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
+
+#define RTC_CNTL_INT_ENA_RTC_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
+/* RTC_CNTL_SWD_INT_ENA_W1TC :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TC :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
+
+#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
+/* RTC_CNTL_RETENTION_WAIT :  ;bitpos:[31:27] ;default: 5'd20 ; */
+/*description: wait cycles for rention operation.*/
+#define RTC_CNTL_RETENTION_WAIT    0x0000001F
+#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
+#define RTC_CNTL_RETENTION_WAIT_V  0x1F
+#define RTC_CNTL_RETENTION_WAIT_S  27
+/* RTC_CNTL_RETENTION_EN :  ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_EN    (BIT(26))
+#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_V  0x1
+#define RTC_CNTL_RETENTION_EN_S  26
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT :  ;bitpos:[25:22] ;default: 4'd3 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
+/* RTC_CNTL_RETENTION_DONE_WAIT :  ;bitpos:[21:19] ;default: 3'd2 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
+#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
+#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
+/* RTC_CNTL_RETENTION_CLK_SEL :  ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_CLK_SEL    (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
+#define RTC_CNTL_RETENTION_CLK_SEL_S  18
+
+#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
+/* RTC_CNTL_FIB_SEL :  ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: select use analog fib signal.*/
+#define RTC_CNTL_FIB_SEL    0x00000007
+#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
+#define RTC_CNTL_FIB_SEL_V  0x7
+#define RTC_CNTL_FIB_SEL_S  0
+
+#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
+/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE    (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
+/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE    (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
+/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE    (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
+/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE    (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
+/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE    (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
+/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE    (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
+/* RTC_CNTL_GPIO_PIN0_INT_TYPE :  ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
+/* RTC_CNTL_GPIO_PIN1_INT_TYPE :  ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
+/* RTC_CNTL_GPIO_PIN2_INT_TYPE :  ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
+/* RTC_CNTL_GPIO_PIN3_INT_TYPE :  ;bitpos:[16:14] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
+/* RTC_CNTL_GPIO_PIN4_INT_TYPE :  ;bitpos:[13:11] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
+/* RTC_CNTL_GPIO_PIN5_INT_TYPE :  ;bitpos:[10:8] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
+/* RTC_CNTL_GPIO_PIN_CLK_GATE :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN_CLK_GATE    (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
+/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR    (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
+/* RTC_CNTL_GPIO_WAKEUP_STATUS :  ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_WAKEUP_STATUS    0x0000003F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
+
+#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
+/* RTC_CNTL_DEBUG_SEL4 :  ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL4    0x0000001F
+#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
+#define RTC_CNTL_DEBUG_SEL4_V  0x1F
+#define RTC_CNTL_DEBUG_SEL4_S  27
+/* RTC_CNTL_DEBUG_SEL3 :  ;bitpos:[26:22] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL3    0x0000001F
+#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
+#define RTC_CNTL_DEBUG_SEL3_V  0x1F
+#define RTC_CNTL_DEBUG_SEL3_S  22
+/* RTC_CNTL_DEBUG_SEL2 :  ;bitpos:[21:17] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL2    0x0000001F
+#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
+#define RTC_CNTL_DEBUG_SEL2_V  0x1F
+#define RTC_CNTL_DEBUG_SEL2_S  17
+/* RTC_CNTL_DEBUG_SEL1 :  ;bitpos:[16:12] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL1    0x0000001F
+#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
+#define RTC_CNTL_DEBUG_SEL1_V  0x1F
+#define RTC_CNTL_DEBUG_SEL1_S  12
+/* RTC_CNTL_DEBUG_SEL0 :  ;bitpos:[11:7] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL0    0x0000001F
+#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
+#define RTC_CNTL_DEBUG_SEL0_V  0x1F
+#define RTC_CNTL_DEBUG_SEL0_S  7
+/* RTC_CNTL_DEBUG_BIT_SEL :  ;bitpos:[6:2] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_BIT_SEL    0x0000001F
+#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
+#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
+#define RTC_CNTL_DEBUG_BIT_SEL_S  2
+/* RTC_CNTL_DEBUG_12M_NO_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_12M_NO_GATING    (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
+#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
+
+#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x104)
+/* RTC_CNTL_GPIO_PIN0_FUN_SEL :  ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
+/* RTC_CNTL_GPIO_PIN1_FUN_SEL :  ;bitpos:[27:24] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
+/* RTC_CNTL_GPIO_PIN2_FUN_SEL :  ;bitpos:[23:20] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
+/* RTC_CNTL_GPIO_PIN3_FUN_SEL :  ;bitpos:[19:16] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
+/* RTC_CNTL_GPIO_PIN4_FUN_SEL :  ;bitpos:[15:12] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
+/* RTC_CNTL_GPIO_PIN5_FUN_SEL :  ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
+/* RTC_CNTL_GPIO_PIN0_MUX_SEL :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL    (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
+/* RTC_CNTL_GPIO_PIN1_MUX_SEL :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL    (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
+/* RTC_CNTL_GPIO_PIN2_MUX_SEL :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL    (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
+/* RTC_CNTL_GPIO_PIN3_MUX_SEL :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL    (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
+/* RTC_CNTL_GPIO_PIN4_MUX_SEL :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL    (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
+/* RTC_CNTL_GPIO_PIN5_MUX_SEL :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL    (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
+
+#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x108)
+/* RTC_CNTL_FORCE_XPD_SAR :  ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_FORCE_XPD_SAR    0x00000003
+#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
+#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
+#define RTC_CNTL_FORCE_XPD_SAR_S  30
+/* RTC_CNTL_SAR2_PWDET_CCT :  ;bitpos:[29:27] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SAR2_PWDET_CCT    0x00000007
+#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
+#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
+#define RTC_CNTL_SAR2_PWDET_CCT_S  27
+
+#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
+/* RTC_CNTL_SAR_DEBUG_SEL :  ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SAR_DEBUG_SEL    0x0000001F
+#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
+#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
+#define RTC_CNTL_SAR_DEBUG_SEL_S  27
+
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
+/* RTC_CNTL_DATE :  ;bitpos:[27:0] ;default: 28'h2107190 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DATE    0x0FFFFFFF
+#define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
+#define RTC_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */

components/soc/esp8684/include/soc/rtc_cntl_struct.h

@@ -0,0 +1,712 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_CNTL_STRUCT_H_
+#define _SOC_RTC_CNTL_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct rtc_cntl_dev_s{
+    union {
+        struct {
+            uint32_t reserved0                     :    2;  /*Reserved*/
+            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t reserved4                     :    1;  /*Reserved*/
+            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
+            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
+            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
+            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
+            uint32_t reserved18                    :    2;  /*Reserved*/
+            uint32_t ctr_sel                       :    3;  /*Need add desc*/
+            uint32_t reserved23                    :    2;  /*Reserved*/
+            uint32_t analog_force_iso              :    1;  /*Need add desc*/
+            uint32_t reserved26                    :    2;  /*Reserved*/
+            uint32_t analog_force_noiso            :    1;  /*Need add desc*/
+            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst                    :    1;  /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;
+    union {
+        struct {
+            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
+            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
+            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
+            uint32_t reserved30                    :    1;  /*Reserved*/
+            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time_low0;
+    union {
+        struct {
+            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } time_high0;
+    union {
+        struct {
+            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
+            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
+            uint32_t reserved2                     :    20;  /*Reserved*/
+            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge*/
+            uint32_t reserved23                    :    5;  /*Reserved*/
+            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
+            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
+            uint32_t slp_reject                    :    1;  /*leep reject bit*/
+            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    24;  /*Reserved*/
+            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t reserved0                     :    16;  /*Reserved*/
+            uint32_t dg_wrap_wait_timer            :    9;  /*Need add desc*/
+            uint32_t dg_wrap_powerup_timer         :    7;  /*Need add desc*/
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserved*/
+            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t i2c_reset_por_force_pd        :    1;  /*Need add desc*/
+            uint32_t i2c_reset_por_force_pu        :    1;  /*Need add desc*/
+            uint32_t reserved20                    :    2;  /*ReservedPLLA force power down*/
+            uint32_t sar_i2c_pu                    :    1;  /*PLLA force power up*/
+            uint32_t reserved23                    :    2;  /*Reserved*/
+            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
+            uint32_t reserved26                    :    1;  /*Reserved*/
+            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up*/
+            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up*/
+            uint32_t reserved29                    :    1;  /*Reserved*/
+            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up*/
+            uint32_t pll_i2c_pu                    :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
+            uint32_t reserved6                     :    7;  /*Reserved*/
+            uint32_t stat_vector_sel_procpu        :    1;  /*PRO CPU state vector sel*/
+            uint32_t reserved14                    :    5;  /*Reserved*/
+            uint32_t ocd_halt_on_reset_procpu      :    1;  /*PROCPU OcdHaltOnReset*/
+            uint32_t rtc_dreset_mask_procpu        :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t reserved0                     :    15;  /*Reserved*/
+            uint32_t rtc_wakeup_ena                :    17;  /*wakeup enable bitmap*/
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reservedenable SDIO idle interrupt*/
+            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reservedenable saradc2 interrupt*/
+            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenable touch timeout interrupt*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
+            uint32_t reserved2                     :    1;  /*ReservedSDIO idle interrupt raw*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
+            uint32_t reserved4                     :    5;  /*Reservedtouch inactive interrupt raw*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
+            uint32_t reserved11                    :    4;  /*Reservedsaradc2 interrupt raw*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
+            uint32_t reserved16                    :    4;  /*Reservedtouch timeout interrupt raw*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
+            uint32_t reserved16                    :    4;  /*Reserved*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
+            uint32_t reserved16                    :    4;  /*Reserved*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];
+    union {
+        struct {
+            uint32_t reserved0                     :    30;  /*Reserved*/
+            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level*/
+            uint32_t ctr_en                        :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;  /*Reserved*/
+            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    12;  /*Reserved*/
+            uint32_t rtc_sleep_reject_ena          :    18;  /*sleep reject enable*/
+            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    29;  /*Reserved*/
+            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
+            uint32_t cpuperiod_sel                 :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved*/
+            uint32_t efuse_clk_force_gating        :    1;  /*Need add desc*/
+            uint32_t efuse_clk_force_nogating      :    1;  /*Need add desc*/
+            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+            uint32_t ck8m_div                      :    2;  /*CK8M_D256_OUT divider. 00: div128*/
+            uint32_t enb_ck8m                      :    1;  /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div                  :    1;  /*1: CK8M_D256_OUT is actually CK8M*/
+            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en             :    1;  /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11                    :    1;  /*Reserved*/
+            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq                    :    8;  /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
+            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
+            uint32_t xtal_global_force_gating      :    1;  /*Need add desc*/
+            uint32_t xtal_global_force_nogating    :    1;  /*Need add desc*/
+            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 4*/
+            uint32_t ana_clk_rtc_sel               :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    22;  /*Reserved*/
+            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+            uint32_t rtc_ana_clk_div               :    8;  /*Need add desc*/
+            uint32_t slow_clk_next_edge            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t dg_vdd_drv_b_slp              :    8;  /*Need add desc*/
+            uint32_t dg_vdd_drv_b_slp_en           :    1;  /*Need add desc*/
+            uint32_t reserved9                     :    1;  /*Reserved*/
+            uint32_t bias_buf_idle                 :    1;  /*Need add desc*/
+            uint32_t bias_buf_wake                 :    1;  /*Need add desc*/
+            uint32_t bias_buf_deep_slp             :    1;  /*Need add desc*/
+            uint32_t bias_buf_monitor              :    1;  /*Need add desc*/
+            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
+            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
+            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
+            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
+            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
+            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in active state*/
+            uint32_t dbg_atten_active              :    4;  /*Need add desc*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*Reserved*/
+            uint32_t dig_cal_en                    :    1;  /*Need add desc*/
+            uint32_t reserved8                     :    6;  /*Reserved*/
+            uint32_t sck_dcap                      :    8;  /*SCK_DCAP*/
+            uint32_t reserved22                    :    8;  /*Reserved*/
+            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t reserved0                     :    21;  /*Reserved*/
+            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
+            uint32_t reserved22                    :    10;  /*Reserved*/
+        };
+        uint32_t val;
+    } pwc;
+    union {
+        struct {
+            uint32_t vdd_spi_pwr_drv               :    2;  /*Need add desc*/
+            uint32_t vdd_spi_pwr_force             :    1;  /*Need add desc*/
+            uint32_t vdd_spi_pd_en                 :    1;  /*Need add desc*/
+            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
+            uint32_t reserved6                     :    13;  /*Reserved*/
+            uint32_t dg_wrap_force_pd              :    1;  /*digital core force power down*/
+            uint32_t dg_wrap_force_pu              :    1;  /*digital core force power up*/
+            uint32_t reserved21                    :    10;  /*Reserved*/
+            uint32_t dg_wrap_pd_en                 :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*Reserved*/
+            uint32_t dig_iso_force_off             :    1;  /*Need add desc*/
+            uint32_t dig_iso_force_on              :    1;  /*Need add desc*/
+            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
+            uint32_t reserved16                    :    14;  /*Reserved*/
+            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso           :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
+            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
+            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
+            uint32_t reserved10                    :    1;  /*Reservedenable WDT reset APP CPU*/
+            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
+            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
+            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
+            uint32_t stg3                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg2                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg1                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg0                          :    3;  /*1: interrupt stage en*/
+            uint32_t en                            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;
+    uint32_t wdt_config2;
+    uint32_t wdt_config3;
+    uint32_t wdt_config4;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;  /*Reserved*/
+            uint32_t feed                          :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;
+    union {
+        struct {
+            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
+            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
+            uint32_t reserved2                     :    15;  /*Reserved*/
+            uint32_t swd_bypass_rst                :    1;  /*Need add desc*/
+            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
+            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
+            uint32_t swd_disable                   :    1;  /*disabel SWD*/
+            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t procpu_c1                     :    6;  /*Need add desc*/
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;
+    uint32_t store5;
+    uint32_t store6;
+    uint32_t store7;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserveddigital wrap iso*/
+            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
+            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
+            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
+            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
+            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
+            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;
+    union {
+        struct {
+            uint32_t rtc_gpio_pin0_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_hold            :    1;  /*Need add desc*/
+            uint32_t reserved6                     :    26;  /*Reserved*/
+        };
+        uint32_t val;
+    } pad_hold;
+    uint32_t dig_pad_hold;
+    union {
+        struct {
+            uint32_t reserved0                     :    4;  /*Reserved*/
+            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
+            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
+            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
+            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
+            uint32_t rst_sel                       :    1;  /*1:  4-pos reset*/
+            uint32_t ana_rst_en                    :    1;  /*Need add desc*/
+            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
+            uint32_t ena                           :    1;  /*enable brown out*/
+            uint32_t det                           :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t time_low1;
+    union {
+        struct {
+            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } time_high1;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t io_mux_reset_disable          :    1;  /*Need add desc*/
+            uint32_t reserved19                    :    13;  /*Reserved*/
+        };
+        uint32_t val;
+    } usb_conf;
+    union {
+        struct {
+            uint32_t reject_cause                  :    18;  /*sleep reject cause*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_reject_cause;
+    union {
+        struct {
+            uint32_t force_download_boot           :    1;  /*Need add desc*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } option1;
+    union {
+        struct {
+            uint32_t wakeup_cause                  :    17;  /*sleep wakeup cause*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_wakeup_cause;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserved*/
+            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
+        };
+        uint32_t val;
+    } ulp_cp_timer_1;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1ts            :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1tc            :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t retention_clk_sel             :    1;  /*Need add desc*/
+            uint32_t retention_done_wait           :    3;  /*Need add desc*/
+            uint32_t retention_clkoff_wait         :    4;  /*Need add desc*/
+            uint32_t retention_en                  :    1;  /*Need add desc*/
+            uint32_t retention_wait                :    5;  /*wait cycles for rention operation*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rtc_fib_sel                   :    3;  /*select use analog fib signal*/
+            uint32_t reserved3                     :    29;  /*Reserved*/
+        };
+        uint32_t val;
+    } fib_sel;
+    union {
+        struct {
+            uint32_t rtc_gpio_wakeup_status        :    6;  /*Need add desc*/
+            uint32_t rtc_gpio_wakeup_status_clr    :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin_clk_gate         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_wakeup_enable   :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } gpio_wakeup;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved*/
+            uint32_t rtc_debug_12m_no_gating       :    1;  /*Need add desc*/
+            uint32_t rtc_debug_bit_sel             :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel0                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel1                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel2                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel3                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel4                :    5;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_sel;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;  /*Reserved*/
+            uint32_t rtc_gpio_pin5_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_fun_sel         :    4;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_map;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t sar2_pwdet_cct                :    3;  /*Need add desc*/
+            uint32_t force_xpd_sar                 :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } sensor_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t sar_debug_sel                 :    5;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_sar_sel;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*Need add desc*/
+            uint32_t reserved28                    :    4;  /*Reserved*/
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_STRUCT_H_ */

components/soc/esp8684/include/soc/rtc_i2c_reg.h

@@ -0,0 +1,676 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_I2C_REG_H_
+#define _SOC_RTC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0000)
+/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 0*/
+#define RTC_I2C_SCL_LOW_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
+#define RTC_I2C_SCL_LOW_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_S  0
+
+#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x0004)
+/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: rtc i2c reg clk gating*/
+#define RTC_I2C_CLK_EN  (BIT(31))
+#define RTC_I2C_CLK_EN_M  (BIT(31))
+#define RTC_I2C_CLK_EN_V  0x1
+#define RTC_I2C_CLK_EN_S  31
+/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: rtc i2c sw reset*/
+#define RTC_I2C_RESET  (BIT(30))
+#define RTC_I2C_RESET_M  (BIT(30))
+#define RTC_I2C_RESET_V  0x1
+#define RTC_I2C_RESET_S  30
+/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_I2C_CTRL_CLK_GATE_EN  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_M  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_V  0x1
+#define RTC_I2C_CTRL_CLK_GATE_EN_S  29
+/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: receive lsb first*/
+#define RTC_I2C_RX_LSB_FIRST  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_M  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_V  0x1
+#define RTC_I2C_RX_LSB_FIRST_S  5
+/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: transit lsb first*/
+#define RTC_I2C_TX_LSB_FIRST  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_M  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_V  0x1
+#define RTC_I2C_TX_LSB_FIRST_S  4
+/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: force start*/
+#define RTC_I2C_TRANS_START  (BIT(3))
+#define RTC_I2C_TRANS_START_M  (BIT(3))
+#define RTC_I2C_TRANS_START_V  0x1
+#define RTC_I2C_TRANS_START_S  3
+/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1=master  0=slave*/
+#define RTC_I2C_MS_MODE  (BIT(2))
+#define RTC_I2C_MS_MODE_M  (BIT(2))
+#define RTC_I2C_MS_MODE_V  0x1
+#define RTC_I2C_MS_MODE_S  2
+/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SCL_FORCE_OUT  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_V  0x1
+#define RTC_I2C_SCL_FORCE_OUT_S  1
+/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SDA_FORCE_OUT  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_V  0x1
+#define RTC_I2C_SDA_FORCE_OUT_S  0
+
+#define RTC_I2C_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x0008)
+/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: scl last status*/
+#define RTC_I2C_SCL_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_STATE_LAST_M  ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
+#define RTC_I2C_SCL_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_STATE_LAST_S  28
+/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: i2c last main status*/
+#define RTC_I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_MAIN_STATE_LAST_M  ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
+#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
+/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: shifter content*/
+#define RTC_I2C_SHIFT  0x000000FF
+#define RTC_I2C_SHIFT_M  ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
+#define RTC_I2C_SHIFT_V  0xFF
+#define RTC_I2C_SHIFT_S  16
+/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: which operation is working*/
+#define RTC_I2C_OP_CNT  0x00000003
+#define RTC_I2C_OP_CNT_M  ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
+#define RTC_I2C_OP_CNT_V  0x3
+#define RTC_I2C_OP_CNT_S  6
+/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: One byte transit done*/
+#define RTC_I2C_BYTE_TRANS  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_M  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_V  0x1
+#define RTC_I2C_BYTE_TRANS_S  5
+/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: slave reg sub address*/
+#define RTC_I2C_SLAVE_ADDRESSED  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_M  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_V  0x1
+#define RTC_I2C_SLAVE_ADDRESSED_S  4
+/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: bus is busy*/
+#define RTC_I2C_BUS_BUSY  (BIT(3))
+#define RTC_I2C_BUS_BUSY_M  (BIT(3))
+#define RTC_I2C_BUS_BUSY_V  0x1
+#define RTC_I2C_BUS_BUSY_S  3
+/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: arbitration is lost*/
+#define RTC_I2C_ARB_LOST  (BIT(2))
+#define RTC_I2C_ARB_LOST_M  (BIT(2))
+#define RTC_I2C_ARB_LOST_V  0x1
+#define RTC_I2C_ARB_LOST_S  2
+/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: slave read or write*/
+#define RTC_I2C_SLAVE_RW  (BIT(1))
+#define RTC_I2C_SLAVE_RW_M  (BIT(1))
+#define RTC_I2C_SLAVE_RW_V  0x1
+#define RTC_I2C_SLAVE_RW_S  1
+/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: ack response*/
+#define RTC_I2C_ACK_REC  (BIT(0))
+#define RTC_I2C_ACK_REC_M  (BIT(0))
+#define RTC_I2C_ACK_REC_V  0x1
+#define RTC_I2C_ACK_REC_S  0
+
+#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x000c)
+/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
+/*description: time out threshold*/
+#define RTC_I2C_TIMEOUT  0x000FFFFF
+#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
+#define RTC_I2C_TIMEOUT_V  0xFFFFF
+#define RTC_I2C_TIMEOUT_S  0
+
+#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x0010)
+/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c 10bit mode enable*/
+#define RTC_I2C_ADDR_10BIT_EN  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_V  0x1
+#define RTC_I2C_ADDR_10BIT_EN_S  31
+/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: slave address*/
+#define RTC_I2C_SLAVE_ADDR  0x00007FFF
+#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
+#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
+#define RTC_I2C_SLAVE_ADDR_S  0
+
+#define RTC_I2C_SCL_HIGH_REG          (DR_REG_RTC_I2C_BASE + 0x0014)
+/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 1*/
+#define RTC_I2C_SCL_HIGH_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
+#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_S  0
+
+#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x0018)
+/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
+/*description: time period for SDA to toggle after SCL goes low*/
+#define RTC_I2C_SDA_DUTY_NUM  0x000FFFFF
+#define RTC_I2C_SDA_DUTY_NUM_M  ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
+#define RTC_I2C_SDA_DUTY_NUM_V  0xFFFFF
+#define RTC_I2C_SDA_DUTY_NUM_S  0
+
+#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x001c)
+/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to toggle after I2C start is triggered*/
+#define RTC_I2C_SCL_START_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
+#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_START_PERIOD_S  0
+
+#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0020)
+/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to stop after I2C end is triggered*/
+#define RTC_I2C_SCL_STOP_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
+#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_S  0
+
+#define RTC_I2C_INT_CLR_REG          (DR_REG_RTC_I2C_BASE + 0x0024)
+/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: clear detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_CLR  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_V  0x1
+#define RTC_I2C_DETECT_START_INT_CLR_S  8
+/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: clear transit load data complete interrupt*/
+#define RTC_I2C_TX_DATA_INT_CLR  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_TX_DATA_INT_CLR_S  7
+/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: clear receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_CLR  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_RX_DATA_INT_CLR_S  6
+/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: clear ack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_CLR  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_V  0x1
+#define RTC_I2C_ACK_ERR_INT_CLR_S  5
+/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clear time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_CLR  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_V  0x1
+#define RTC_I2C_TIMEOUT_INT_CLR_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: clear transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: clear master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: clear slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
+
+#define RTC_I2C_INT_RAW_REG          (DR_REG_RTC_I2C_BASE + 0x0028)
+/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt raw*/
+#define RTC_I2C_DETECT_START_INT_RAW  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_V  0x1
+#define RTC_I2C_DETECT_START_INT_RAW_S  8
+/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt raw*/
+#define RTC_I2C_TX_DATA_INT_RAW  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_TX_DATA_INT_RAW_S  7
+/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt raw*/
+#define RTC_I2C_RX_DATA_INT_RAW  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_RX_DATA_INT_RAW_S  6
+/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt raw*/
+#define RTC_I2C_ACK_ERR_INT_RAW  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_V  0x1
+#define RTC_I2C_ACK_ERR_INT_RAW_S  5
+/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt raw*/
+#define RTC_I2C_TIMEOUT_INT_RAW  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_V  0x1
+#define RTC_I2C_TIMEOUT_INT_RAW_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt raw*/
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt raw*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt raw*/
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt raw*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
+
+#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x002c)
+/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt state*/
+#define RTC_I2C_DETECT_START_INT_ST  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_V  0x1
+#define RTC_I2C_DETECT_START_INT_ST_S  8
+/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt state*/
+#define RTC_I2C_TX_DATA_INT_ST  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_V  0x1
+#define RTC_I2C_TX_DATA_INT_ST_S  7
+/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt state*/
+#define RTC_I2C_RX_DATA_INT_ST  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_V  0x1
+#define RTC_I2C_RX_DATA_INT_ST_S  6
+/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt state*/
+#define RTC_I2C_ACK_ERR_INT_ST  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ST_S  5
+/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt state*/
+#define RTC_I2C_TIMEOUT_INT_ST  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ST_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt state*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ST  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt state*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt state*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ST  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt state*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
+
+#define RTC_I2C_INT_ENA_REG          (DR_REG_RTC_I2C_BASE + 0x0030)
+/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_ENA  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_V  0x1
+#define RTC_I2C_DETECT_START_INT_ENA_S  8
+/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable transit data interrupt*/
+#define RTC_I2C_TX_DATA_INT_ENA  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_TX_DATA_INT_ENA_S  7
+/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_ENA  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_RX_DATA_INT_ENA_S  6
+/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable eack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_ENA  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ENA_S  5
+/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_ENA  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ENA_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
+
+#define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x0034)
+/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c done*/
+#define RTC_I2C_DONE  (BIT(31))
+#define RTC_I2C_DONE_M  (BIT(31))
+#define RTC_I2C_DONE_V  0x1
+#define RTC_I2C_DONE_S  31
+/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: data sent by slave*/
+#define RTC_I2C_SLAVE_TX_DATA  0x000000FF
+#define RTC_I2C_SLAVE_TX_DATA_M  ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
+#define RTC_I2C_SLAVE_TX_DATA_V  0xFF
+#define RTC_I2C_SLAVE_TX_DATA_S  8
+/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: data received*/
+#define RTC_I2C_RDATA  0x000000FF
+#define RTC_I2C_RDATA_M  ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
+#define RTC_I2C_RDATA_V  0xFF
+#define RTC_I2C_RDATA_S  0
+
+#define RTC_I2C_CMD0_REG          (DR_REG_RTC_I2C_BASE + 0x0038)
+/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command0_done*/
+#define RTC_I2C_COMMAND0_DONE  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_V  0x1
+#define RTC_I2C_COMMAND0_DONE_S  31
+/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command0*/
+#define RTC_I2C_COMMAND0  0x00003FFF
+#define RTC_I2C_COMMAND0_M  ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
+#define RTC_I2C_COMMAND0_V  0x3FFF
+#define RTC_I2C_COMMAND0_S  0
+
+#define RTC_I2C_CMD1_REG          (DR_REG_RTC_I2C_BASE + 0x003c)
+/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command1_done*/
+#define RTC_I2C_COMMAND1_DONE  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_V  0x1
+#define RTC_I2C_COMMAND1_DONE_S  31
+/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command1*/
+#define RTC_I2C_COMMAND1  0x00003FFF
+#define RTC_I2C_COMMAND1_M  ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
+#define RTC_I2C_COMMAND1_V  0x3FFF
+#define RTC_I2C_COMMAND1_S  0
+
+#define RTC_I2C_CMD2_REG          (DR_REG_RTC_I2C_BASE + 0x0040)
+/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command2_done*/
+#define RTC_I2C_COMMAND2_DONE  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_V  0x1
+#define RTC_I2C_COMMAND2_DONE_S  31
+/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
+/*description: command2*/
+#define RTC_I2C_COMMAND2  0x00003FFF
+#define RTC_I2C_COMMAND2_M  ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
+#define RTC_I2C_COMMAND2_V  0x3FFF
+#define RTC_I2C_COMMAND2_S  0
+
+#define RTC_I2C_CMD3_REG          (DR_REG_RTC_I2C_BASE + 0x0044)
+/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command3_done*/
+#define RTC_I2C_COMMAND3_DONE  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_V  0x1
+#define RTC_I2C_COMMAND3_DONE_S  31
+/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command3*/
+#define RTC_I2C_COMMAND3  0x00003FFF
+#define RTC_I2C_COMMAND3_M  ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
+#define RTC_I2C_COMMAND3_V  0x3FFF
+#define RTC_I2C_COMMAND3_S  0
+
+#define RTC_I2C_CMD4_REG          (DR_REG_RTC_I2C_BASE + 0x0048)
+/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command4_done*/
+#define RTC_I2C_COMMAND4_DONE  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_V  0x1
+#define RTC_I2C_COMMAND4_DONE_S  31
+/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command4*/
+#define RTC_I2C_COMMAND4  0x00003FFF
+#define RTC_I2C_COMMAND4_M  ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
+#define RTC_I2C_COMMAND4_V  0x3FFF
+#define RTC_I2C_COMMAND4_S  0
+
+#define RTC_I2C_CMD5_REG          (DR_REG_RTC_I2C_BASE + 0x004c)
+/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command5_done*/
+#define RTC_I2C_COMMAND5_DONE  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_V  0x1
+#define RTC_I2C_COMMAND5_DONE_S  31
+/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command5*/
+#define RTC_I2C_COMMAND5  0x00003FFF
+#define RTC_I2C_COMMAND5_M  ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
+#define RTC_I2C_COMMAND5_V  0x3FFF
+#define RTC_I2C_COMMAND5_S  0
+
+#define RTC_I2C_CMD6_REG          (DR_REG_RTC_I2C_BASE + 0x0050)
+/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command6_done*/
+#define RTC_I2C_COMMAND6_DONE  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_V  0x1
+#define RTC_I2C_COMMAND6_DONE_S  31
+/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command6*/
+#define RTC_I2C_COMMAND6  0x00003FFF
+#define RTC_I2C_COMMAND6_M  ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
+#define RTC_I2C_COMMAND6_V  0x3FFF
+#define RTC_I2C_COMMAND6_S  0
+
+#define RTC_I2C_CMD7_REG          (DR_REG_RTC_I2C_BASE + 0x0054)
+/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command7_done*/
+#define RTC_I2C_COMMAND7_DONE  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_V  0x1
+#define RTC_I2C_COMMAND7_DONE_S  31
+/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
+/*description: command7*/
+#define RTC_I2C_COMMAND7  0x00003FFF
+#define RTC_I2C_COMMAND7_M  ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
+#define RTC_I2C_COMMAND7_V  0x3FFF
+#define RTC_I2C_COMMAND7_S  0
+
+#define RTC_I2C_CMD8_REG          (DR_REG_RTC_I2C_BASE + 0x0058)
+/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command8_done*/
+#define RTC_I2C_COMMAND8_DONE  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_V  0x1
+#define RTC_I2C_COMMAND8_DONE_S  31
+/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command8*/
+#define RTC_I2C_COMMAND8  0x00003FFF
+#define RTC_I2C_COMMAND8_M  ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
+#define RTC_I2C_COMMAND8_V  0x3FFF
+#define RTC_I2C_COMMAND8_S  0
+
+#define RTC_I2C_CMD9_REG          (DR_REG_RTC_I2C_BASE + 0x005c)
+/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command9_done*/
+#define RTC_I2C_COMMAND9_DONE  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_V  0x1
+#define RTC_I2C_COMMAND9_DONE_S  31
+/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command9*/
+#define RTC_I2C_COMMAND9  0x00003FFF
+#define RTC_I2C_COMMAND9_M  ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
+#define RTC_I2C_COMMAND9_V  0x3FFF
+#define RTC_I2C_COMMAND9_S  0
+
+#define RTC_I2C_CMD10_REG          (DR_REG_RTC_I2C_BASE + 0x0060)
+/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command10_done*/
+#define RTC_I2C_COMMAND10_DONE  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_V  0x1
+#define RTC_I2C_COMMAND10_DONE_S  31
+/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command10*/
+#define RTC_I2C_COMMAND10  0x00003FFF
+#define RTC_I2C_COMMAND10_M  ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
+#define RTC_I2C_COMMAND10_V  0x3FFF
+#define RTC_I2C_COMMAND10_S  0
+
+#define RTC_I2C_CMD11_REG          (DR_REG_RTC_I2C_BASE + 0x0064)
+/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command11_done*/
+#define RTC_I2C_COMMAND11_DONE  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_V  0x1
+#define RTC_I2C_COMMAND11_DONE_S  31
+/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command11*/
+#define RTC_I2C_COMMAND11  0x00003FFF
+#define RTC_I2C_COMMAND11_M  ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
+#define RTC_I2C_COMMAND11_V  0x3FFF
+#define RTC_I2C_COMMAND11_S  0
+
+#define RTC_I2C_CMD12_REG          (DR_REG_RTC_I2C_BASE + 0x0068)
+/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command12_done*/
+#define RTC_I2C_COMMAND12_DONE  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_V  0x1
+#define RTC_I2C_COMMAND12_DONE_S  31
+/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command12*/
+#define RTC_I2C_COMMAND12  0x00003FFF
+#define RTC_I2C_COMMAND12_M  ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
+#define RTC_I2C_COMMAND12_V  0x3FFF
+#define RTC_I2C_COMMAND12_S  0
+
+#define RTC_I2C_CMD13_REG          (DR_REG_RTC_I2C_BASE + 0x006c)
+/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command13_done*/
+#define RTC_I2C_COMMAND13_DONE  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_V  0x1
+#define RTC_I2C_COMMAND13_DONE_S  31
+/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command13*/
+#define RTC_I2C_COMMAND13  0x00003FFF
+#define RTC_I2C_COMMAND13_M  ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
+#define RTC_I2C_COMMAND13_V  0x3FFF
+#define RTC_I2C_COMMAND13_S  0
+
+#define RTC_I2C_CMD14_REG          (DR_REG_RTC_I2C_BASE + 0x0070)
+/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command14_done*/
+#define RTC_I2C_COMMAND14_DONE  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_V  0x1
+#define RTC_I2C_COMMAND14_DONE_S  31
+/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command14*/
+#define RTC_I2C_COMMAND14  0x00003FFF
+#define RTC_I2C_COMMAND14_M  ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
+#define RTC_I2C_COMMAND14_V  0x3FFF
+#define RTC_I2C_COMMAND14_S  0
+
+#define RTC_I2C_CMD15_REG          (DR_REG_RTC_I2C_BASE + 0x0074)
+/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command15_done*/
+#define RTC_I2C_COMMAND15_DONE  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_V  0x1
+#define RTC_I2C_COMMAND15_DONE_S  31
+/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command15*/
+#define RTC_I2C_COMMAND15  0x00003FFF
+#define RTC_I2C_COMMAND15_M  ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
+#define RTC_I2C_COMMAND15_V  0x3FFF
+#define RTC_I2C_COMMAND15_S  0
+
+#define RTC_I2C_DATE_REG          (DR_REG_RTC_I2C_BASE + 0x00FC)
+/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
+/*description: */
+#define RTC_I2C_DATE  0x0FFFFFFF
+#define RTC_I2C_DATE_M  ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
+#define RTC_I2C_DATE_V  0xFFFFFFF
+#define RTC_I2C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_I2C_REG_H_ */

components/soc/esp8684/include/soc/rtc_i2c_struct.h

@@ -0,0 +1,219 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_I2C_STRUCT_H_
+#define _SOC_RTC_I2C_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct rtc_i2c_dev_s{
+    union {
+        struct {
+            uint32_t period:        20;             /*time period that scl = 0*/
+            uint32_t reserved20:    12;
+        };
+        uint32_t val;
+    } scl_low;
+    union {
+        struct {
+            uint32_t sda_force_out:        1;       /*1=push pull  0=open drain*/
+            uint32_t scl_force_out:        1;       /*1=push pull  0=open drain*/
+            uint32_t ms_mode:              1;       /*1=master  0=slave*/
+            uint32_t trans_start:          1;       /*force start*/
+            uint32_t tx_lsb_first:         1;       /*transit lsb first*/
+            uint32_t rx_lsb_first:         1;       /*receive lsb first*/
+            uint32_t reserved6:           23;
+            uint32_t i2c_ctrl_clk_gate_en: 1;
+            uint32_t i2c_reset:            1;       /*rtc i2c sw reset*/
+            uint32_t i2cclk_en:            1;       /*rtc i2c reg clk gating*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t ack_rec:             1;        /*ack response*/
+            uint32_t slave_rw:            1;        /*slave read or write*/
+            uint32_t arb_lost:            1;        /*arbitration is lost*/
+            uint32_t bus_busy:            1;        /*bus is busy*/
+            uint32_t slave_addressed:     1;        /*slave reg sub address*/
+            uint32_t byte_trans:          1;        /*One byte transit done*/
+            uint32_t op_cnt:              2;        /*which operation is working*/
+            uint32_t reserved8:           8;
+            uint32_t shift:               8;        /*shifter content*/
+            uint32_t scl_main_state_last: 3;        /*i2c last main status*/
+            uint32_t reserved27:          1;
+            uint32_t scl_state_last:      3;        /*scl last status*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t time_out:  20;                 /*time out threshold*/
+            uint32_t reserved20:12;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr:         15;              /*slave address*/
+            uint32_t reserved15:   16;
+            uint32_t en_10bit:      1;              /*i2c 10bit mode enable*/
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t period:         20;            /*time period that scl = 1*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_high;
+    union {
+        struct {
+            uint32_t sda_duty_num:20;               /*time period for SDA to toggle after SCL goes low*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } sda_duty;
+    union {
+        struct {
+            uint32_t scl_start_period:20;           /*time period for SCL to toggle after I2C start is triggered*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } scl_start_period;
+    union {
+        struct {
+            uint32_t scl_stop_period:20;            /*time period for SCL to stop after I2C end is triggered*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_stop_period;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*clear slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*clear arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*clear master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*clear transit complete interrupt*/
+            uint32_t time_out:                 1;   /*clear time out interrupt*/
+            uint32_t ack_err:                  1;   /*clear ack error interrupt*/
+            uint32_t rx_data:                  1;   /*clear receive data interrupt*/
+            uint32_t tx_data:                  1;   /*clear transit load data complete interrupt*/
+            uint32_t detect_start:             1;   /*clear detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*slave transit complete interrupt raw*/
+            uint32_t arbitration_lost:         1;   /*arbitration lost interrupt raw*/
+            uint32_t master_tran_comp:         1;   /*master transit complete interrupt raw*/
+            uint32_t trans_complete:           1;   /*transit complete interrupt raw*/
+            uint32_t time_out:                 1;   /*time out interrupt raw*/
+            uint32_t ack_err:                  1;   /*ack error interrupt raw*/
+            uint32_t rx_data:                  1;   /*receive data interrupt raw*/
+            uint32_t tx_data:                  1;   /*transit data interrupt raw*/
+            uint32_t detect_start:             1;   /*detect start interrupt raw*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slave_tran_comp:         1;    /*slave transit complete interrupt state*/
+            uint32_t arbitration_lost:        1;    /*arbitration lost interrupt state*/
+            uint32_t master_tran_comp:        1;    /*master transit complete interrupt state*/
+            uint32_t trans_complete:          1;    /*transit complete interrupt state*/
+            uint32_t time_out:                1;    /*time out interrupt state*/
+            uint32_t ack_err:                 1;    /*ack error interrupt state*/
+            uint32_t rx_data:                 1;    /*receive data interrupt state*/
+            uint32_t tx_data:                 1;    /*transit data interrupt state*/
+            uint32_t detect_start:            1;    /*detect start interrupt state*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*enable slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*enable arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*enable master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*enable transit complete interrupt*/
+            uint32_t time_out:                 1;   /*enable time out interrupt*/
+            uint32_t ack_err:                  1;   /*enable eack error interrupt*/
+            uint32_t rx_data:                  1;   /*enable receive data interrupt*/
+            uint32_t tx_data:                  1;   /*enable transit data interrupt*/
+            uint32_t detect_start:             1;   /*enable detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t i2c_rdata:     8;              /*data received*/
+            uint32_t slave_tx_data: 8;              /*data sent by slave*/
+            uint32_t reserved16:   15;
+            uint32_t i2c_done:      1;              /*i2c done*/
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t command0:     14;              /*command0*/
+            uint32_t reserved14:   17;
+            uint32_t done:          1;              /*command0_done*/
+        };
+        uint32_t val;
+    } command[16];
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t i2c_date:  28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_i2c_dev_t;
+extern rtc_i2c_dev_t RTC_I2C;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_I2C_STRUCT_H_ */

components/soc/esp8684/include/soc/sensitive_reg.h

@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_REG_H_
+#define _SOC_SENSITIVE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SENSITIVE_ROM_TABLE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x0)
+/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_ROM_TABLE_LOCK    (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_M  (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_V  0x1
+#define SENSITIVE_ROM_TABLE_LOCK_S  0
+
+#define SENSITIVE_ROM_TABLE_REG          (DR_REG_SENSITIVE_BASE + 0x4)
+/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_ROM_TABLE    0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_M  ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
+#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x8)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0xC)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST    (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x10)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK    (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x14)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */
+/*description: Need add description.*/
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM    0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE    (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x18)
+/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP    (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S  3
+/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM    0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x1C)
+/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x20)
+/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
+/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
+/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
+/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_I_TAG_RD_ACS    (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x24)
+/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x28)
+/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_WR_ACS_S  1
+/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PRO_MMU_RD_ACS    (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_RD_ACS_S  0
+
+#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x2C)
+/* SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x30)
+/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S  1
+/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+
+#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x34)
+/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+
+#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x38)
+/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add description.*/
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_XTS_AES_KEY_UPDATE_REG          (DR_REG_SENSITIVE_BASE + 0x3C)
+/* SENSITIVE_XTS_AES_KEY_UPDATE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to update xts_aes key.*/
+#define SENSITIVE_XTS_AES_KEY_UPDATE    (BIT(0))
+#define SENSITIVE_XTS_AES_KEY_UPDATE_M  (BIT(0))
+#define SENSITIVE_XTS_AES_KEY_UPDATE_V  0x1
+#define SENSITIVE_XTS_AES_KEY_UPDATE_S  0
+
+#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x40)
+/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Need add description.*/
+#define SENSITIVE_CLK_EN    (BIT(0))
+#define SENSITIVE_CLK_EN_M  (BIT(0))
+#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_S  0
+
+#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106301 ; */
+/*description: Need add description.*/
+#define SENSITIVE_DATE    0x0FFFFFFF
+#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
+#define SENSITIVE_DATE_V  0xFFFFFFF
+#define SENSITIVE_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_REG_H_ */

components/soc/esp8684/include/soc/sensitive_struct.h

@@ -0,0 +1,1152 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_STRUCT_H_
+#define _SOC_SENSITIVE_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct sensitive_dev_s{
+    union {
+        struct {
+            uint32_t rom_table_lock                :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } rom_table_lock;
+    uint32_t rom_table;
+    union {
+        struct {
+            uint32_t apb_peripheral_access_lock    :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_peripheral_access_0;
+    union {
+        struct {
+            uint32_t apb_peripheral_access_split_burst:    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } apb_peripheral_access_1;
+    union {
+        struct {
+            uint32_t internal_sram_usage_lock      :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } internal_sram_usage_0;
+    union {
+        struct {
+            uint32_t internal_sram_usage_cpu_cache :    1;  /*Need add description*/
+            uint32_t internal_sram_usage_cpu_sram  :    3;  /*Need add description*/
+            uint32_t reserved4                     :    28;  /*Reserved*/
+        };
+        uint32_t val;
+    } internal_sram_usage_1;
+    union {
+        struct {
+            uint32_t internal_sram_usage_mac_dump_sram:    3;  /*Need add description*/
+            uint32_t internal_sram_alloc_mac_dump  :    1;  /*Need add description*/
+            uint32_t reserved4                     :    28;  /*Reserved*/
+        };
+        uint32_t val;
+    } internal_sram_usage_3;
+    union {
+        struct {
+            uint32_t cache_tag_access_lock         :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_tag_access_0;
+    union {
+        struct {
+            uint32_t pro_i_tag_rd_acs              :    1;  /*Need add description*/
+            uint32_t pro_i_tag_wr_acs              :    1;  /*Need add description*/
+            uint32_t pro_d_tag_rd_acs              :    1;  /*Need add description*/
+            uint32_t pro_d_tag_wr_acs              :    1;  /*Need add description*/
+            uint32_t reserved4                     :    28;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_tag_access_1;
+    union {
+        struct {
+            uint32_t cache_mmu_access_lock         :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_mmu_access_0;
+    union {
+        struct {
+            uint32_t pro_mmu_rd_acs                :    1;  /*Need add description*/
+            uint32_t pro_mmu_wr_acs                :    1;  /*Need add description*/
+            uint32_t reserved2                     :    30;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_mmu_access_1;
+    union {
+        struct {
+            uint32_t pif_access_monitor_lock       :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } pif_access_monitor_0;
+    union {
+        struct {
+            uint32_t pif_access_monitor_nonword_violate_clr:    1;  /*Need add description*/
+            uint32_t pif_access_monitor_nonword_violate_en:    1;  /*Need add description*/
+            uint32_t reserved2                     :    30;  /*Reserved*/
+        };
+        uint32_t val;
+    } pif_access_monitor_1;
+    union {
+        struct {
+            uint32_t pif_access_monitor_nonword_violate_intr:    1;  /*Need add description*/
+            uint32_t pif_access_monitor_nonword_violate_status_hsize:    2;  /*Need add description*/
+            uint32_t reserved3                     :    29;  /*Reserved*/
+        };
+        uint32_t val;
+    } pif_access_monitor_2;
+    uint32_t pif_access_monitor_3;
+    union {
+        struct {
+            uint32_t xts_aes_key_update            :    1;  /*Set this bit to update xts_aes key*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } xts_aes_key_update;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Need add description*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t sensitive_date                :    28;  /*Need add description*/
+            uint32_t reserved28                    :    4;  /*Reserved*/
+        };
+        uint32_t val;
+    } date;
+} sensitive_dev_t;
+extern sensitive_dev_t SENSITIVE;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_STRUCT_H_ */

components/soc/esp8684/include/soc/soc.h

@@ -0,0 +1,278 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include "esp_assert.h"
+#include "esp_bit_defs.h"
+#endif
+
+#include "sdkconfig.h"
+
+#define PRO_CPU_NUM (0)
+#define DR_REG_SYSTEM_BASE                      0x600c0000
+#define DR_REG_SENSITIVE_BASE                   0x600c1000
+#define DR_REG_INTERRUPT_BASE                   0x600c2000
+#define DR_REG_EXTMEM_BASE                      0x600c4000 // CACHE_CONFIG
+#define DR_REG_MMU_TABLE                        0x600c5000
+#define DR_REG_SHA_BASE                         0x6003b000
+#define DR_REG_GDMA_BASE                        0x6003f000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
+#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
+#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
+#define DR_REG_DPORT_END                        0x600d3FFC
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_SPI1_BASE                        0x60002000
+#define DR_REG_SPI0_BASE                        0x60003000
+#define DR_REG_GPIO_BASE                        0x60004000
+#define DR_REG_FE2_BASE                         0x60005000
+#define DR_REG_FE_BASE                          0x60006000
+#define DR_REG_RTCCNTL_BASE                     0x60008000
+#define DR_REG_IO_MUX_BASE                      0x60009000
+#define DR_REG_RTC_I2C_BASE                     0x6000e000
+#define DR_REG_UART1_BASE                       0x60010000
+#define DR_REG_I2C_EXT_BASE                     0x60013000
+#define DR_REG_LEDC_BASE                        0x60019000
+#define DR_REG_EFUSE_BASE                       0x60008800
+#define DR_REG_NRX_BASE                         0x6001CC00
+#define DR_REG_BB_BASE                          0x6001D000
+#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
+#define DR_REG_SYSTIMER_BASE                    0x60023000
+#define DR_REG_SPI2_BASE                        0x60024000
+#define DR_REG_SYSCON_BASE                      0x60026000
+#define DR_REG_APB_SARADC_BASE                  0x60040000
+#define DR_REG_WDEVLE_BASE                      0x60045000
+#define DR_REG_ETM_BIT_BASE                     0x6004B000
+#define DR_REG_BLE_TIMER_BASE                   0x6004B800
+#define DR_REG_BLE_SEC_BASE                     0x6004C000
+#define DR_REG_COEX_BIT_BASE                    0x6004C400
+#define DR_REG_I2C_MST_BASE                     0x6004E800
+
+#define DR_REG_RTC_BLE_TIMER_BASE( i )          ( \
+                                                    ( (i) == 0 ) ?      ( 0x6004E000 ) : \
+                                                    ( (i) == 1 ) ?      ( 0x6004E100 ) : \
+                                                    ( (i) == 2 ) ?      ( 0x6004E200 ) : \
+                                                    0 \
+                                                )
+
+
+#define REG_UHCI_BASE(i)                        (DR_REG_UHCI0_BASE - (i) * 0x8000)
+#define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x10000)
+#define REG_UART_AHB_BASE(i)                    (0x60000000 + (i) * 0x10000)
+#define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr)
+
+#ifndef __ASSEMBLER__
+#define BIT(nr)                 (1UL << (nr))
+#else
+#define BIT(nr)                 (1 << (nr))
+#endif
+
+#ifndef __ASSEMBLER__
+
+//write value to register
+#define REG_WRITE(_r, _v) ({                                                                                           \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        })
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            (*(volatile uint32_t *)(_r));                                                                              \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
+        })
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
+        })
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
+            (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
+        })
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
+            (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
+        })
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) ({                                                                                   \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        })
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        })
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        })
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
+            (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
+        })
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  UART_CLK_FREQ_ROM                           ( 40*1000000)
+#define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#define  APB_CLK_FREQ                                ( 40*1000000 )
+#define  REF_CLK_FREQ                                ( 1000000 )
+#define  RTC_CLK_FREQ                                (20*1000000)
+#define  XTAL_CLK_FREQ                               (40*1000000)
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 4
+#define  SPI_CLK_DIV                                 4
+#define  TICKS_PER_US_ROM                            40              // CPU is 40MHz
+#define  GPIO_MATRIX_DELAY_NS                        0
+//}}
+
+/* Overall memory map */
+#define SOC_DROM_LOW    0x3C000000
+#define SOC_DROM_HIGH   0x3C800000
+#define SOC_IROM_LOW    0x42000000
+#define SOC_IROM_HIGH   0x42400000
+#define SOC_IROM_MASK_LOW  0x40000000
+#define SOC_IROM_MASK_HIGH 0x40060000
+#define SOC_DROM_MASK_LOW 0x3FF00000
+#define SOC_DROM_MASK_HIGH 0x3FF20000
+#define SOC_IRAM_LOW    0x4037C000
+#define SOC_IRAM_HIGH   0x403C0000
+#define SOC_DRAM_LOW    0x3FCA0000
+#define SOC_DRAM_HIGH   0x3FCE0000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW    0x40380000
+#define SOC_DIRAM_IRAM_HIGH   0x403C0000
+#define SOC_DIRAM_DRAM_LOW    0x3FCA0000
+#define SOC_DIRAM_DRAM_HIGH   0x3FCE0000
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW  0x3FC88000
+#define SOC_DMA_HIGH 0x3FD00000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW     0x3FC88000
+#define SOC_BYTE_ACCESSIBLE_HIGH    0x3FD00000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW        0x3FCA0000
+#define SOC_MEM_INTERNAL_HIGH       0x3FCE0000
+#define SOC_MEM_INTERNAL_LOW1       0x4037C000
+#define SOC_MEM_INTERNAL_HIGH1      0x403C0000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START         0x3fcebf10
+
+//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
+//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
+
+//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
+
+#define ETS_T1_WDT_INUM                         24 // Remove TODO: IDF-4246
+#define ETS_CACHEERR_INUM                       25
+#define ETS_MEMPROT_ERR_INUM                    26
+#define ETS_DPORT_INUM                          28
+
+//CPU0 Max valid interrupt number
+#define ETS_MAX_INUM                            31
+
+//CPU0 Interrupt number used in ROM, should be cancelled in SDK
+#define ETS_SLC_INUM                            1
+#define ETS_UART0_INUM                          5
+#define ETS_UART1_INUM                          5
+#define ETS_SPI2_INUM                           1
+//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
+#define ETS_GPIO_INUM       4
+
+//Other interrupt number should be managed by the user
+
+//Invalid interrupt for number interrupt matrix
+#define ETS_INVALID_INUM                        0
+
+//Interrupt medium level, used for INT WDT for example
+#define SOC_INTERRUPT_LEVEL_MEDIUM              4

components/soc/esp8684/include/soc/soc_caps.h

@@ -0,0 +1,270 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// The long term plan is to have a single soc_caps.h for each peripheral.
+// During the refactoring and multichip support development process, we
+// seperate these information into periph_caps.h for each peripheral and
+// include them here.
+
+#pragma once
+
+#define SOC_CPU_CORES_NUM               1
+#define SOC_GDMA_SUPPORTED              1
+#define SOC_BT_SUPPORTED                1
+#define SOC_DIG_SIGN_SUPPORTED          1
+#define SOC_HMAC_SUPPORTED              1
+#define SOC_ASYNC_MEMCPY_SUPPORTED      1
+
+/*-------------------------- COMMON CAPS ---------------------------------------*/
+#define SOC_SUPPORTS_SECURE_DL_MODE     1
+#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
+#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
+#define SOC_RTC_FAST_MEM_SUPPORTED      0
+#define SOC_RTC_SLOW_MEM_SUPPORTED      0
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY             0
+#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
+
+/*-------------------------- AES CAPS -----------------------------------------*/
+#define SOC_AES_SUPPORT_DMA     (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_AES_GDMA            (1)
+
+/*-------------------------- ADC CAPS -------------------------------*/
+#define SOC_ADC_PERIPH_NUM                      (2)
+#define SOC_ADC_PATT_LEN_MAX                    (16)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         ((PERIPH_NUM==0)? 5 : 1)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (5)
+#define SOC_ADC_MAX_BITWIDTH                    (12)
+#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
+#define SOC_ADC_DIGI_FILTER_NUM                 (2)
+#define SOC_ADC_DIGI_MONITOR_NUM                (2)
+#define SOC_ADC_HW_CALIBRATION_V1               (1) /*!< support HW offset calibration */
+#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM)    1
+//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+
+/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
+#define SOC_APB_BACKUP_DMA              (1)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_BREAKPOINTS_NUM         2
+#define SOC_CPU_WATCHPOINTS_NUM         2
+#define SOC_CPU_HAS_FLEXIBLE_INTC       1
+
+#define SOC_CPU_WATCHPOINT_SIZE         0x80000000 // bytes
+
+/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
+/** The maximum length of a Digital Signature in bits. */
+#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
+
+/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
+#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
+
+/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
+    See TRM DS chapter for more details */
+#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
+
+/*-------------------------- GDMA CAPS -------------------------------------*/
+#define SOC_GDMA_GROUPS                 (1) // Number of GDMA groups
+#define SOC_GDMA_PAIRS_PER_GROUP        (3) // Number of GDMA pairs in each group
+#define SOC_GDMA_TX_RX_SHARE_INTERRUPT  (1) // TX and RX channel in the same pair will share the same interrupt source number
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP8684 has 1 GPIO peripheral
+#define SOC_GPIO_PORT               (1)
+#define SOC_GPIO_PIN_COUNT          (21)
+
+// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
+// On ESP8684, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
+#define GPIO_SUPPORTS_RTC_INDEPENDENT       (1)
+// Force hold is a new function of ESP8684
+#define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
+// GPIO0~5 on ESP8684 can support chip deep sleep wakeup
+#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+
+// GPIO19 on ESP8684 is invalid.
+#define SOC_GPIO_VALID_GPIO_MASK        (((1U<<SOC_GPIO_PIN_COUNT) - 1) & (~(BIT19)))
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
+
+// Support to configure sleep status
+#define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// TODO IDF-3918
+#define SOC_I2C_NUM                 (1)
+
+#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
+
+#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+#define SOC_I2C_SUPPORT_XTAL        (1)
+#define SOC_I2C_SUPPORT_RTC         (1)
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+// TODO IDF-3896
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+#define SOC_LEDC_CHANNEL_NUM         (6)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
+
+/*--------------------------- RMT CAPS ---------------------------------------*/
+#define SOC_RMT_GROUPS                  (1)  /*!< One RMT group */
+#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2)  /*!< Number of channels that capable of Transmit */
+#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2)  /*!< Number of channels that capable of Receive */
+#define SOC_RMT_CHANNELS_PER_GROUP      (4)  /*!< Total 4 channels */
+#define SOC_RMT_MEM_WORDS_PER_CHANNEL   (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_SUPPORT_RX_PINGPONG     (1)  /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION (1)  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT   (1)  /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_SYNCHRO      (1)  /*!< Support coordinate a group of TX channels to start simultaneously */
+#define SOC_RMT_SUPPORT_XTAL            (1)  /*!< Support set XTAL clock as the RMT clock source */
+
+/*-------------------------- RTC CAPS --------------------------------------*/
+#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH       (128)
+#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM        (108)
+#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN      (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
+#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE      (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
+
+#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE  (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+/* No dedicated RTCIO subsystem on ESP8684. RTC functions are still supported
+ * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
+#define SOC_RTCIO_PIN_COUNT    0
+
+/*--------------------------- RSA CAPS ---------------------------------------*/
+#define SOC_RSA_MAX_BIT_LEN    (3072)
+
+/*--------------------------- SHA CAPS ---------------------------------------*/
+
+/* Max amount of bytes in a single DMA operation is 4095,
+   for SHA this means that the biggest safe amount of bytes is
+   31 blocks of 128 bytes = 3968
+*/
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
+
+/* The SHA engine is able to resume hashing from a user */
+#define SOC_SHA_SUPPORT_RESUME          (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_SHA_GDMA             (1)
+
+/* Supported HW algorithms */
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+
+/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
+#define SOC_SIGMADELTA_NUM         (1) // 1 sigma-delta peripheral
+#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
+
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM          2
+#define SOC_SPI_PERIPH_CS_NUM(i)    6
+
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
+
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
+
+// Peripheral supports output given level during its "dummy phase"
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+#define SOC_SPI_MAX_PRE_DIVIDER 16
+
+/*-------------------------- SPI MEM CAPS ---------------------------------------*/
+#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
+#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
+#define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
+#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
+#define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
+
+
+/*-------------------------- SYSTIMER CAPS ----------------------------------*/
+#define SOC_SYSTIMER_COUNTER_NUM           (2)  // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM             (3)  // Number of alarm units
+#define SOC_SYSTIMER_BIT_WIDTH_LO          (32) // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI          (20) // Bit width of systimer high part
+#define SOC_SYSTIMER_FIXED_TICKS_US        (16) // Number of ticks per microsecond is fixed
+#define SOC_SYSTIMER_INT_LEVEL             (1)  // Systimer peripheral uses level interrupt
+#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1)  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+
+/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
+#define SOC_TIMER_GROUPS                  (1)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
+#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
+
+/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
+#define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP8684 */
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+// TODO IDF-3897
+
+/*-------------------------- Flash Encryption CAPS----------------------------*/
+#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (32)
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP8684 has 2 UARTs
+#define SOC_UART_NUM                (2)
+
+#define SOC_UART_FIFO_LEN           (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX        (5000000)  /*!< Max bit rate supported by UART */
+
+#define SOC_UART_SUPPORT_RTC_CLK    (1)
+#define SOC_UART_SUPPORT_XTAL_CLK   (1)
+
+// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
+#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
+
+/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
+#define SOC_WIFI_HW_TSF                 (1)
+
+/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
+#define SOC_COEX_HW_PTI                 (1)
+
+/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
+#define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
+#define SOC_MAC_BB_PD_MEM_SIZE          (192*4)
+
+/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
+#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
+
+/*-------------------------- Power Management CAPS ----------------------------*/
+#define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+
+#define SOC_PM_SUPPORT_BT_WAKEUP        (1)
+
+#define SOC_PM_SUPPORT_CPU_PD           (1)
+
+#define SOC_PM_SUPPORT_WIFI_PD          (1)
+
+#define SOC_PM_SUPPORT_BT_PD            (1)

components/soc/esp8684/include/soc/soc_pins.h

@@ -0,0 +1,16 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
+#pragma once
+
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"

components/soc/esp8684/include/soc/spi_mem_reg.h

@@ -0,0 +1,1270 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble..*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
+tion  will be triggered when the bit is set. The bit will be cleared once the op
+eration done .1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
+e or high performance mode and obtains the devices ID. The bit will be cleared o
+nce the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
+ion done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
+peration done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_MSPI_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation sta
+te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
+ate, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_MSPI_ST    0x0000000F
+#define SPI_MEM_MSPI_ST_M  ((SPI_MEM_MSPI_ST_V)<<(SPI_MEM_MSPI_ST_S))
+#define SPI_MEM_MSPI_ST_V  0xF
+#define SPI_MEM_MSPI_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI1 master FSM..*/
+#define SPI_MEM_MST_ST    0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
+isable..*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable..*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_DUAL    (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller..*/
+#define SPI_MEM_FDUMMY_OUT    (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_V  0x1
+#define SPI_MEM_FDUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI0 RX FIFO reset signal..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
+12) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is alwasy on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: Spi cs signal is delayed to inactive by spi clock this bits are combined with sp
+i_mem_cs_hold bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_
+setup bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit in 1-division mode..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+1: enable 0: disable..*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
+: enable 0: disable..*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode
+..*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle.*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting i
+s done..*/
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA    (BIT(6))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(6))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  6
+/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done..*/
+#define SPI_MEM_CSPI_ST_TRANS_END    (BIT(5))
+#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(5))
+#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_S  5
+/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting
+is done..*/
+#define SPI_MEM_TRANS_END_INT_ENA    (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TRANS_END_INT_ENA_S  4
+/* SPI_MEM_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_mst_st controlled transmitting is done..*/
+#define SPI_MEM_TRANS_END    (BIT(3))
+#define SPI_MEM_TRANS_END_M  (BIT(3))
+#define SPI_MEM_TRANS_END_V  0x1
+#define SPI_MEM_TRANS_END_S  3
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, Cache access enable, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_REQ_EN    (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME    0x0000001F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
+/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GR
+ANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDM
+A sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define SPI_MEM_EM_ST    0x00000007
+#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
+#define SPI_MEM_EM_ST_V  0x7
+#define SPI_MEM_EM_ST_S  4
+/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
+ state, 2: send command state, 3: send address state, 4: wait state, 5: read dat
+a state, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_CSPI_ST    0x0000000F
+#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
+#define SPI_MEM_CSPI_ST_V  0xF
+#define SPI_MEM_CSPI_ST_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command to wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR).*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+ it will be treated as check pass..*/
+#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
+s of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PES_END_EN    (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+ of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PER_END_EN    (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
+hen check flash SUS/SUS1/SUS2 status bit.*/
+#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
+2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
+#define SPI_MEM_PESR_END_MSK    0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
+pplication should send PER after PES is done..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ suspend command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase resume command is sent. 0: SPI1 does not wait after program erase
+resume command is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered whe
+n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable..*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable..*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
+/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
+..*/
+#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  8
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
+/*description: Program/Erase resume command..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
+#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
+#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend, only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
+/* SPI_MEM_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN3_MODE    0x00000003
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x3
+#define SPI_MEM_DIN3_MODE_S  6
+/* SPI_MEM_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN2_MODE    0x00000003
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x3
+#define SPI_MEM_DIN2_MODE_S  4
+/* SPI_MEM_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN1_MODE    0x00000003
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x3
+#define SPI_MEM_DIN1_MODE_S  2
+/* SPI_MEM_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN0_MODE    0x00000003
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x3
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
+/* SPI_MEM_DIN3_NUM : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN3_NUM    (BIT(3))
+#define SPI_MEM_DIN3_NUM_M  (BIT(3))
+#define SPI_MEM_DIN3_NUM_V  0x1
+#define SPI_MEM_DIN3_NUM_S  3
+/* SPI_MEM_DIN2_NUM : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN2_NUM    (BIT(2))
+#define SPI_MEM_DIN2_NUM_M  (BIT(2))
+#define SPI_MEM_DIN2_NUM_V  0x1
+#define SPI_MEM_DIN2_NUM_S  2
+/* SPI_MEM_DIN1_NUM : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN1_NUM    (BIT(1))
+#define SPI_MEM_DIN1_NUM_M  (BIT(1))
+#define SPI_MEM_DIN1_NUM_V  0x1
+#define SPI_MEM_DIN1_NUM_S  1
+/* SPI_MEM_DIN0_NUM : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN0_NUM    (BIT(0))
+#define SPI_MEM_DIN0_NUM_M  (BIT(0))
+#define SPI_MEM_DIN0_NUM_V  0x1
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
+/* SPI_MEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  5
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  5
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is loosing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  5
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
+E is sent and flash is already idle. 0: Others..*/
+#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  5
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_CLK_EN    (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
+/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
+s 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz
+. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz.
+3: Not used. When the digital system clock selects PLL clock and the frequency o
+f PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (
+clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (c
+lk) 160MHz. 3: Not used..*/
+#define SPI_MEM_SPI01_CLK_SEL    0x00000003
+#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
+#define SPI_MEM_SPI01_CLK_SEL_V  0x3
+#define SPI_MEM_SPI01_CLK_SEL_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106191 ; */
+/*description: SPI register version..*/
+#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */

components/soc/esp8684/include/soc/spi_mem_struct.h

@@ -0,0 +1,576 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_STRUCT_H_
+#define _SOC_SPI_MEM_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_mem_dev_s{
+    union {
+        struct {
+            uint32_t mst_st                        :    4;  /*The current status of SPI1 master FSM.*/
+            uint32_t slv_st                        :    4;  /*The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t reserved8                     :    9;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t fdummy_out                    :    1;  /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4                     :    3;  /*reserved*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    18;  /*reserved*/
+            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time                  :    5;  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reserved10                    :    15;  /*reserved*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
+            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
+            uint32_t clk_equ_sysclk                :    1;  /*Set this bit in 1-division mode.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved6                     :    20;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t mst_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
+            uint32_t mst_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
+            uint32_t slv_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+            uint32_t slv_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
+            uint32_t reserved7                     :    2;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t req_en                        :    1;  /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
+            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
+            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
+            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    union {
+        struct {
+            uint32_t spi0_slv_st                   :    4;  /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t spi0_mst_st                   :    3;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
+            uint32_t cspi_lock_delay_time          :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_cmd                     :    8;  /*The command to wait flash idle(RDSR).*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
+            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_per_command             :    8;  /*Program/Erase resume command.*/
+            uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } sus_status;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t spi01_clk_sel                 :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. */
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } core_clk_sel;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_STRUCT_H_ */

components/soc/esp8684/include/soc/spi_pins.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_SPI_PINS_H_
+#define _SOC_SPI_PINS_H_
+
+#define SPI_FUNC_NUM            0
+#define SPI_IOMUX_PIN_NUM_HD    12
+#define SPI_IOMUX_PIN_NUM_CS    14
+#define SPI_IOMUX_PIN_NUM_MOSI  16
+#define SPI_IOMUX_PIN_NUM_CLK   15
+#define SPI_IOMUX_PIN_NUM_MISO  17
+#define SPI_IOMUX_PIN_NUM_WP    13
+
+#define SPI2_FUNC_NUM           2
+#define SPI2_IOMUX_PIN_NUM_MISO 2
+#define SPI2_IOMUX_PIN_NUM_HD   4
+#define SPI2_IOMUX_PIN_NUM_WP   5
+#define SPI2_IOMUX_PIN_NUM_CLK  6
+#define SPI2_IOMUX_PIN_NUM_MOSI 7
+#define SPI2_IOMUX_PIN_NUM_CS   10
+
+#endif

components/soc/esp8684/include/soc/spi_reg.h

@@ -0,0 +1,1750 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define REG_SPI_BASE(i)     (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
+/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. Can not b
+e changed by CONF_buf..*/
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (BIT(24))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  24
+/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
+clock domain, which is only used in SPI master mode..*/
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (BIT(23))
+#define SPI_UPDATE_V  0x1
+#define SPI_UPDATE_S  23
+/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
+#define SPI_CONF_BITLEN    0x0003FFFF
+#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
+#define SPI_CONF_BITLEN_V  0x3FFFF
+#define SPI_CONF_BITLEN_S  0
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Address to slave. Can be configured in CONF state..*/
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
+figured in CONF state..*/
+#define SPI_WR_BIT_ORDER    0x00000003
+#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
+#define SPI_WR_BIT_ORDER_V  0x3
+#define SPI_WR_BIT_ORDER_S  25
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
+tate..*/
+#define SPI_RD_BIT_ORDER    0x00000003
+#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
+#define SPI_RD_BIT_ORDER_V  0x3
+#define SPI_RD_BIT_ORDER_S  23
+/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
+an be configured in CONF state..*/
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (BIT(21))
+#define SPI_WP_POL_V  0x1
+#define SPI_WP_POL_S  21
+/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
+nfigured in CONF state..*/
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (BIT(20))
+#define SPI_HOLD_POL_V  0x1
+#define SPI_HOLD_POL_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_OCT : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (BIT(16))
+#define SPI_FREAD_OCT_V  0x1
+#define SPI_FREAD_OCT_S  16
+/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (BIT(15))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
+an be configured in CONF state..*/
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FCMD_OCT : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (BIT(10))
+#define SPI_FCMD_OCT_V  0x1
+#define SPI_FCMD_OCT_S  10
+/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (BIT(9))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  9
+/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (BIT(8))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  8
+/* SPI_FADDR_OCT : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (BIT(7))
+#define SPI_FADDR_OCT_V  0x1
+#define SPI_FADDR_OCT_S  7
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
+e, the FSPI bus signals are output. Can be configured in CONF state..*/
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
+em clock. Can be configured in CONF state..*/
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
+e..*/
+#define SPI_CLKDIV_PRE    0x0000000F
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0xF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
+(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
+#define SPI_CLKCNT_N    0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+must be 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_H    0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
+e 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_L    0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
+te..*/
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
+te..*/
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
+..*/
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
+tate..*/
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ CONF state..*/
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
+e 0: disable.  Can be configured in CONF state..*/
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ 0: disable. Can be configured in CONF state..*/
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
+re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (BIT(17))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  17
+/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+ is not seg-trans mode. Can be configured in CONF state..*/
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (BIT(15))
+#define SPI_USR_CONF_NXT_V  0x1
+#define SPI_USR_CONF_NXT_S  15
+/* SPI_FWRITE_OCT : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (BIT(14))
+#define SPI_FWRITE_OCT_V  0x1
+#define SPI_FWRITE_OCT_S  14
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
+n be configured in CONF state..*/
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+= !spi_ck_i. 1:rsck = spi_ck_i..*/
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
+ured in CONF state..*/
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+= spi_ck_i. 1:tsck = !spi_ck_i..*/
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_OPI_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others
+. Can be configured in CONF state..*/
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (BIT(4))
+#define SPI_OPI_MODE_V  0x1
+#define SPI_OPI_MODE_S  4
+/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
+. Can be configured in CONF state..*/
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (BIT(3))
+#define SPI_QPI_MODE_V  0x1
+#define SPI_QPI_MODE_S  3
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_ADDR_BITLEN    0x0000001F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x1F
+#define SPI_USR_ADDR_BITLEN_S  27
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ Can be configured in CONF state..*/
+#define SPI_CS_HOLD_TIME    0x0000001F
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1F
+#define SPI_CS_HOLD_TIME_S  22
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
+p bit. Can be configured in CONF state..*/
+#define SPI_CS_SETUP_TIME    0x0000001F
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1F
+#define SPI_CS_SETUP_TIME_S  17
+/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+ in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_V  0x1
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
+num-1). Can be configured in CONF state..*/
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
+aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
+r is valid in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command. Can be configured in CONF state..*/
+#define SPI_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
+/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: The value of these bits is the configured SPI transmission data bit length in ma
+ster mode DMA controlled transfer or CPU controlled transfer. The value is also
+the configured bit length in slave mode DMA RX controlled transfer. The register
+ value shall be (bit_num-1). Can be configured in CONF state..*/
+#define SPI_MS_DATA_BITLEN    0x0003FFFF
+#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
+#define SPI_MS_DATA_BITLEN_V  0x3FFFF
+#define SPI_MS_DATA_BITLEN_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
+:  spi quad input swap disable. Can be configured in CONF state..*/
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
+onfigured in CONF state..*/
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_DQS_IDLE_EDGE : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The default value of spi_dqs. Can be configured in CONF state..*/
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (BIT(24))
+#define SPI_DQS_IDLE_EDGE_V  0x1
+#define SPI_DQS_IDLE_EDGE_S  24
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+CONF state..*/
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_CMD_DTR_EN : HRO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/
+4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi
+gured in CONF state..*/
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (BIT(19))
+#define SPI_CMD_DTR_EN_V  0x1
+#define SPI_CMD_DTR_EN_S  19
+/* SPI_ADDR_DTR_EN : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
+/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co
+nfigured in CONF state..*/
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (BIT(18))
+#define SPI_ADDR_DTR_EN_V  0x1
+#define SPI_ADDR_DTR_EN_S  18
+/* SPI_DATA_DTR_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas
+ter 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
+ode. Can be configured in CONF state..*/
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (BIT(17))
+#define SPI_DATA_DTR_EN_V  0x1
+#define SPI_DATA_DTR_EN_S  17
+/* SPI_CLK_DATA_DTR_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master D
+TR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19..*/
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_V  0x1
+#define SPI_CLK_DATA_DTR_EN_S  16
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
+lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
+#define SPI_MASTER_CS_POL    0x0000003F
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x3F
+#define SPI_MASTER_CS_POL_S  7
+/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (BIT(6))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  6
+/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (BIT(5))
+#define SPI_CS5_DIS_V  0x1
+#define SPI_CS5_DIS_S  5
+/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (BIT(4))
+#define SPI_CS4_DIS_V  0x1
+#define SPI_CS4_DIS_S  4
+/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (BIT(3))
+#define SPI_CS3_DIS_V  0x1
+#define SPI_CS3_DIS_S  3
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
+/* SPI_TIMING_HCLK_ACTIVE : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
+ONF state..*/
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_V  0x1
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+/* SPI_DIN7_MODE : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN7_MODE    0x00000003
+#define SPI_DIN7_MODE_M  ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
+#define SPI_DIN7_MODE_V  0x3
+#define SPI_DIN7_MODE_S  14
+/* SPI_DIN6_MODE : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN6_MODE    0x00000003
+#define SPI_DIN6_MODE_M  ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S))
+#define SPI_DIN6_MODE_V  0x3
+#define SPI_DIN6_MODE_S  12
+/* SPI_DIN5_MODE : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN5_MODE    0x00000003
+#define SPI_DIN5_MODE_M  ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
+#define SPI_DIN5_MODE_V  0x3
+#define SPI_DIN5_MODE_S  10
+/* SPI_DIN4_MODE : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN4_MODE    0x00000003
+#define SPI_DIN4_MODE_M  ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
+#define SPI_DIN4_MODE_V  0x3
+#define SPI_DIN4_MODE_S  8
+/* SPI_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN3_MODE    0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN2_MODE    0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN1_MODE    0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN0_MODE    0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
+/* SPI_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN7_NUM    0x00000003
+#define SPI_DIN7_NUM_M  ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
+#define SPI_DIN7_NUM_V  0x3
+#define SPI_DIN7_NUM_S  14
+/* SPI_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN6_NUM    0x00000003
+#define SPI_DIN6_NUM_M  ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
+#define SPI_DIN6_NUM_V  0x3
+#define SPI_DIN6_NUM_S  12
+/* SPI_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN5_NUM    0x00000003
+#define SPI_DIN5_NUM_M  ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S))
+#define SPI_DIN5_NUM_V  0x3
+#define SPI_DIN5_NUM_S  10
+/* SPI_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN4_NUM    0x00000003
+#define SPI_DIN4_NUM_M  ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
+#define SPI_DIN4_NUM_V  0x3
+#define SPI_DIN4_NUM_S  8
+/* SPI_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN3_NUM    0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN2_NUM    0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN1_NUM    0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN0_NUM    0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
+/* SPI_D_DQS_MODE : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+be configured in CONF state..*/
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (BIT(8))
+#define SPI_D_DQS_MODE_V  0x1
+#define SPI_D_DQS_MODE_S  8
+/* SPI_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (BIT(7))
+#define SPI_DOUT7_MODE_V  0x1
+#define SPI_DOUT7_MODE_S  7
+/* SPI_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (BIT(6))
+#define SPI_DOUT6_MODE_V  0x1
+#define SPI_DOUT6_MODE_S  6
+/* SPI_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (BIT(5))
+#define SPI_DOUT5_MODE_V  0x1
+#define SPI_DOUT5_MODE_S  5
+/* SPI_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (BIT(4))
+#define SPI_DOUT4_MODE_V  0x1
+#define SPI_DOUT4_MODE_S  4
+/* SPI_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (BIT(3))
+#define SPI_DOUT3_MODE_V  0x1
+#define SPI_DOUT3_MODE_S  3
+/* SPI_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (BIT(2))
+#define SPI_DOUT2_MODE_V  0x1
+#define SPI_DOUT2_MODE_S  2
+/* SPI_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (BIT(1))
+#define SPI_DOUT1_MODE_V  0x1
+#define SPI_DOUT1_MODE_S  1
+/* SPI_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (BIT(0))
+#define SPI_DOUT0_MODE_V  0x1
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
+/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+DMA controlled mode transfer..*/
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (BIT(31))
+#define SPI_DMA_AFIFO_RST_V  0x1
+#define SPI_DMA_AFIFO_RST_S  31
+/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ controlled mode transfer and master mode transfer..*/
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (BIT(30))
+#define SPI_BUF_AFIFO_RST_V  0x1
+#define SPI_BUF_AFIFO_RST_S  30
+/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+slave mode transfer..*/
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (BIT(29))
+#define SPI_RX_AFIFO_RST_V  0x1
+#define SPI_RX_AFIFO_RST_S  29
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI DMA controlled send data mode..*/
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (BIT(28))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  28
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (BIT(27))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  27
+/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
+o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
+ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
+e in seg-trans..*/
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (BIT(21))
+#define SPI_RX_EOF_EN_V  0x1
+#define SPI_RX_EOF_EN_S  21
+/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
+mpty_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
+_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
+a. 0: DMA RX FIFO is ready for receiving data..*/
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
+#define SPI_DMA_INFIFO_FULL_V  0x1
+#define SPI_DMA_INFIFO_FULL_S  1
+/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
+ 0: DMA TX FIFO is ready for sending data..*/
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
+/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (BIT(20))
+#define SPI_APP1_INT_ENA_V  0x1
+#define SPI_APP1_INT_ENA_S  20
+/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (BIT(19))
+#define SPI_APP2_INT_ENA_V  0x1
+#define SPI_APP2_INT_ENA_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_V  0x1
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_V  0x1
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_V  0x1
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_V  0x1
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
+/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (BIT(20))
+#define SPI_APP1_INT_CLR_V  0x1
+#define SPI_APP1_INT_CLR_S  20
+/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (BIT(19))
+#define SPI_APP2_INT_CLR_V  0x1
+#define SPI_APP2_INT_CLR_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_V  0x1
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_V  0x1
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_V  0x1
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_V  0x1
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
+/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (BIT(20))
+#define SPI_APP1_INT_RAW_V  0x1
+#define SPI_APP1_INT_RAW_S  20
+/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (BIT(19))
+#define SPI_APP2_INT_RAW_V  0x1
+#define SPI_APP2_INT_RAW_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ write-full error when SPI inputs data in master mode. 0: Others..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ current SPI slave HD mode transmission is not supported. 0: Others..*/
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
+s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
+ is bigger than 63. 0: Others..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
+er is error in the DMA seg-conf-trans. 0: others..*/
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
+plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
+ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
+not ended or not occurred..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ ended. 0: others..*/
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_V  0x1
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_V  0x1
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_V  0x1
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_V  0x1
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ master mode and send out all 0 in slave mode.  0: Others..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+the receive data.  0: Others..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
+/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (BIT(20))
+#define SPI_APP1_INT_ST_V  0x1
+#define SPI_APP1_INT_ST_S  20
+/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (BIT(19))
+#define SPI_APP2_INT_ST_V  0x1
+#define SPI_APP2_INT_ST_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_V  0x1
+#define SPI_TRANS_DONE_INT_ST_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_V  0x1
+#define SPI_SLV_CMDA_INT_ST_S  7
+/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_V  0x1
+#define SPI_SLV_CMD9_INT_ST_S  6
+/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_V  0x1
+#define SPI_SLV_CMD8_INT_ST_S  5
+/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_V  0x1
+#define SPI_SLV_CMD7_INT_ST_S  4
+/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_V  0x1
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_V  0x1
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+
+#define SPI_DMA_INT_SET_REG(i)          (REG_SPI_BASE(i) + 0x44)
+/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (BIT(20))
+#define SPI_APP1_INT_SET_V  0x1
+#define SPI_APP1_INT_SET_S  20
+/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (BIT(19))
+#define SPI_APP2_INT_SET_V  0x1
+#define SPI_APP2_INT_SET_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x1
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_V  0x1
+#define SPI_TRANS_DONE_INT_SET_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_V  0x1
+#define SPI_SLV_CMDA_INT_SET_S  7
+/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_V  0x1
+#define SPI_SLV_CMD9_INT_SET_S  6
+/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_V  0x1
+#define SPI_SLV_CMD8_INT_SET_S  5
+/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_V  0x1
+#define SPI_SLV_CMD7_INT_SET_S  4
+/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_V  0x1
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_V  0x1
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF0    0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF1    0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF2    0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF3    0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF4    0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF5    0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF6    0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF7    0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF8    0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF9    0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
+/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF10    0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
+/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF11    0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
+/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF12    0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
+/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF13    0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
+/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF14    0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
+/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF15    0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
+/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
+ns will start. 0: This is not seg-trans mode..*/
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (BIT(28))
+#define SPI_USR_CONF_V  0x1
+#define SPI_USR_CONF_S  28
+/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
+onfigured in CONF state..*/
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (BIT(27))
+#define SPI_SOFT_RESET_V  0x1
+#define SPI_SOFT_RESET_S  27
+/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (BIT(26))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  26
+/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
+/*description: The magic value of BM table in master DMA seg-trans..*/
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
+#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in CPU controlled mode(Wr_BUF). 0: others.*/
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n CPU controlled mode(Rd_BUF). 0: others.*/
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in DMA controlled mode(Wr_DMA). 0: others.*/
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n DMA controlled mode(Rd_DMA). 0: others.*/
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
+dge   0: output data at tsck posedge.*/
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+ 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
+#define SPI_CLK_MODE    0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
+/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: In the slave mode it is the value of address..*/
+#define SPI_SLV_LAST_ADDR    0x0000003F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x3F
+#define SPI_SLV_LAST_ADDR_S  26
+/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of command..*/
+#define SPI_SLV_LAST_COMMAND    0x000000FF
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0xFF
+#define SPI_SLV_LAST_COMMAND_S  18
+/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: The transferred data bit length in SPI slave FD and HD mode..*/
+#define SPI_SLV_DATA_BITLEN    0x0003FFFF
+#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
+#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
+#define SPI_SLV_DATA_BITLEN_S  0
+
+#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
+/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
+M. 0: XTAL CLK..*/
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (BIT(2))
+#define SPI_MST_CLK_SEL_V  0x1
+#define SPI_MST_CLK_SEL_S  2
+/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to power on the SPI module clock..*/
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
+#define SPI_MST_CLK_ACTIVE_V  0x1
+#define SPI_MST_CLK_ACTIVE_S  1
+/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (BIT(0))
+#define SPI_CLK_EN_V  0x1
+#define SPI_CLK_EN_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106070 ; */
+/*description: SPI register version..*/
+#define SPI_DATE    0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */

components/soc/esp8684/include/soc/spi_struct.h

@@ -0,0 +1,420 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_STRUCT_H_
+#define _SOC_SPI_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct spi_dev_s{
+    union {
+        struct {
+            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    5;  /*reserved*/
+            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved11                    :    3;  /*reserved*/
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t fread_oct                     :    1;  /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
+            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
+            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    9;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved1                     :    2;  /*reserved*/
+            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
+            uint32_t opi_mode                      :    1;  /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
+            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_oct                    :    1;  /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
+            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    6;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*reserved*/
+            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
+            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
+            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    11;  /*reserved*/
+            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } ms_dlen;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
+            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
+            uint32_t reserved13                    :    3;  /*reserved*/
+            uint32_t clk_data_dtr_en               :    1;  /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. */
+            uint32_t data_dtr_en                   :    1;  /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
+            uint32_t addr_dtr_en                   :    1;  /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
+            uint32_t cmd_dtr_en                    :    1;  /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
+            uint32_t reserved20                    :    3;  /*reserved*/
+            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
+            uint32_t dqs_idle_edge                 :    1;  /*The default value of spi_dqs. Can be configured in CONF state.*/
+            uint32_t reserved25                    :    4;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din4_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din5_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din6_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din7_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout4_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout5_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout6_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout7_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t d_dqs_mode                    :    1;  /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t dma_outfifo_empty             :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
+            uint32_t dma_infifo_full               :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
+            uint32_t reserved2                     :    16;  /*reserved*/
+            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
+            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
+            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
+            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
+            uint32_t reserved22                    :    5;  /*reserved*/
+            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
+            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
+            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
+            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
+            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
+            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
+            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
+            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
+            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
+            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
+            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
+            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
+            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
+            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
+            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
+            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
+            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
+            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
+            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
+            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
+            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
+            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t infifo_full_err_int_set       :    1;  /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err_int_set     :    1;  /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi_int_set                :    1;  /*The software set bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi_int_set                :    1;  /*The software set bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7_int_set                  :    1;  /*The software set bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8_int_set                  :    1;  /*The software set bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9_int_set                  :    1;  /*The software set bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda_int_set                  :    1;  /*The software set bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done_int_set            :    1;  /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done_int_set    :    1;  /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err_int_set         :    1;  /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err_int_set          :    1;  /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err_int_set               :    1;  /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err_int_set:    1;  /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err_int_set:    1;  /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2_int_set                  :    1;  /*The software set bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1_int_set                  :    1;  /*The software set bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_set;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t data_buf[16];
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
+            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
+            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
+            uint32_t reserved4                     :    4;  /*reserved*/
+            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
+            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
+            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
+            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
+            uint32_t reserved12                    :    10;  /*reserved*/
+            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
+            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
+            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
+            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
+            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
+            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } clk_gate;
+    uint32_t reserved_ec;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_STRUCT_H_ */

components/soc/esp8684/include/soc/syscon_reg.h

@@ -0,0 +1,636 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: reg_rst_tick_cnt.*/
+#define SYSCON_RST_TICK_CNT    (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: reg_clk_en.*/
+#define SYSCON_CLK_EN    (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: reg_clk_320m_en.*/
+#define SYSCON_CLK_320M_EN    (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: reg_pre_div_cnt.*/
+#define SYSCON_PRE_DIV_CNT    0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: reg_tick_enable.*/
+#define SYSCON_TICK_ENABLE    (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: reg_ck8m_tick_num.*/
+#define SYSCON_CK8M_TICK_NUM    0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: reg_xtal_tick_num.*/
+#define SYSCON_XTAL_TICK_NUM    0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: reg_clk_xtal_oen.*/
+#define SYSCON_CLK_XTAL_OEN    (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: reg_clk40x_bb_oen.*/
+#define SYSCON_CLK40X_BB_OEN    (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: reg_clk_dac_cpu_oen.*/
+#define SYSCON_CLK_DAC_CPU_OEN    (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: reg_clk_adc_inf_oen.*/
+#define SYSCON_CLK_ADC_INF_OEN    (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_clk_320m_oen.*/
+#define SYSCON_CLK_320M_OEN    (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: reg_clk160_oen.*/
+#define SYSCON_CLK160_OEN    (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_clk80_oen.*/
+#define SYSCON_CLK80_OEN    (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: reg_clk_bb_oen.*/
+#define SYSCON_CLK_BB_OEN    (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_clk44_oen.*/
+#define SYSCON_CLK44_OEN    (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: reg_clk22_oen.*/
+#define SYSCON_CLK22_OEN    (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_clk20_oen.*/
+#define SYSCON_CLK20_OEN    (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg.*/
+#define SYSCON_WIFI_BB_CFG    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg_2.*/
+#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: reg_wifi_clk_en.*/
+#define SYSCON_WIFI_CLK_EN    0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_rst.*/
+#define SYSCON_WIFI_RST    0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
+/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSTEM_WIFI_CLK_EN  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
+#define SYSTEM_WIFI_CLK_EN_V  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_S  0
+
+/* Mask for all Wifi clock bits, 6 */
+#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
+#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
+#define SYSTEM_WIFI_CLK_BT_EN  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
+#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_S  0
+/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
+#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
+
+/* Digital team to check */
+//bluetooth baseband bit11
+#define SYSTEM_BT_BASEBAND_EN  BIT(11)
+//bluetooth LC bit16 and bit17
+#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
+
+/* Remaining single bit clock masks */
+#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT5  BIT(5)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
+#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
+#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
+
+#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
+#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
+/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSTEM_BB_RST           BIT(0)
+#define SYSTEM_FE_RST           BIT(1)
+#define SYSTEM_MAC_RST          BIT(2)
+#define SYSTEM_BT_RST           BIT(3)
+#define SYSTEM_BTMAC_RST        BIT(4)
+#define SYSTEM_SDIO_RST         BIT(5)
+#define SYSTEM_EMAC_RST         BIT(7)
+#define SYSTEM_MACPWR_RST       BIT(8)
+#define SYSTEM_RW_BTMAC_RST     BIT(9)
+#define SYSTEM_RW_BTLP_RST      BIT(10)
+#define BLE_REG_REST_BIT        BIT(11)
+#define BLE_PWR_REG_REST_BIT    BIT(12)
+#define BLE_BB_REG_REST_BIT     BIT(13)
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: reg_peri_io_swap.*/
+#define SYSCON_PERI_IO_SWAP    0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_ext_mem_pms_lock.*/
+#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace0_attr.*/
+#define SYSCON_FLASH_ACE0_ATTR    0x00000003
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x3
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace1_attr.*/
+#define SYSCON_FLASH_ACE1_ATTR    0x00000003
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x3
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace2_attr.*/
+#define SYSCON_FLASH_ACE2_ATTR    0x00000003
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x3
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace3_attr.*/
+#define SYSCON_FLASH_ACE3_ATTR    0x00000003
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x3
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_flash_ace0_addr_s.*/
+#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: reg_flash_ace1_addr_s.*/
+#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: reg_flash_ace2_addr_s.*/
+#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
+/*description: reg_flash_ace3_addr_s.*/
+#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace0_size.*/
+#define SYSCON_FLASH_ACE0_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace1_size.*/
+#define SYSCON_FLASH_ACE1_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace2_size.*/
+#define SYSCON_FLASH_ACE2_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace3_size.*/
+#define SYSCON_FLASH_ACE3_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
+/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: reg_spi_mem_reject_cde.*/
+#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001F
+#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_clr.*/
+#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_int.*/
+#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
+/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_spi_mem_reject_addr.*/
+#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: reg_sdio_win_access_en.*/
+#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_andor.*/
+#define SYSCON_REDCY_ANDOR    (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig0.*/
+#define SYSCON_REDCY_SIG0    0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_nandor.*/
+#define SYSCON_REDCY_NANDOR    (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig1.*/
+#define SYSCON_REDCY_SIG1    0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
+/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_freq_mem_force_pd.*/
+#define SYSCON_FREQ_MEM_FORCE_PD    (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_M  (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PD_S  7
+/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_freq_mem_force_pu.*/
+#define SYSCON_FREQ_MEM_FORCE_PU    (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_M  (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PU_S  6
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: reg_dc_mem_force_pd.*/
+#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_dc_mem_force_pu.*/
+#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: reg_pbus_mem_force_pd.*/
+#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_pbus_mem_force_pu.*/
+#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_agc_mem_force_pd.*/
+#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_agc_mem_force_pu.*/
+#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
+/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reg_nobypass_cpu_iso_rst.*/
+#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: reg_retention_link_addr.*/
+#define SYSCON_RETENTION_LINK_ADDR    0x07FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
+#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_S  0
+
+#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA4)
+/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
+hen only when have access the sram have clock.*/
+#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x0000000F
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  3
+/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
+en only when have access the rom have clock.*/
+#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000007
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x7
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+
+#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xA8)
+/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power down.*/
+#define SYSCON_SRAM_POWER_DOWN    0x0000000F
+#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
+#define SYSCON_SRAM_POWER_DOWN_V  0xF
+#define SYSCON_SRAM_POWER_DOWN_S  3
+/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power down.*/
+#define SYSCON_ROM_POWER_DOWN    0x00000007
+#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
+#define SYSCON_ROM_POWER_DOWN_V  0x7
+#define SYSCON_ROM_POWER_DOWN_S  0
+
+#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xAC)
+/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power up.*/
+#define SYSCON_SRAM_POWER_UP    0x0000000F
+#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
+#define SYSCON_SRAM_POWER_UP_V  0xF
+#define SYSCON_SRAM_POWER_UP_S  3
+/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power up.*/
+#define SYSCON_ROM_POWER_UP    0x00000007
+#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
+#define SYSCON_ROM_POWER_UP_V  0x7
+#define SYSCON_ROM_POWER_UP_S  0
+
+#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0xB0)
+/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: reg_rnd_data.*/
+#define SYSCON_RND_DATA    0xFFFFFFFF
+#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
+#define SYSCON_RND_DATA_V  0xFFFFFFFF
+#define SYSCON_RND_DATA_S  0
+
+#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0xB4)
+/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: reg_peri_backup_ena.*/
+#define SYSCON_PERI_BACKUP_ENA    (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ENA_S  31
+/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reg_peri_backup_to_mem.*/
+#define SYSCON_PERI_BACKUP_TO_MEM    (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
+#define SYSCON_PERI_BACKUP_TO_MEM_S  30
+/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: reg_peri_backup_start.*/
+#define SYSCON_PERI_BACKUP_START    (BIT(29))
+#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_V  0x1
+#define SYSCON_PERI_BACKUP_START_S  29
+/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: reg_peri_backup_size.*/
+#define SYSCON_PERI_BACKUP_SIZE    0x000003FF
+#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
+#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
+#define SYSCON_PERI_BACKUP_SIZE_S  19
+/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: reg_peri_backup_tout_thres.*/
+#define SYSCON_PERI_BACKUP_TOUT_THRES    0x000003FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
+#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
+/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: reg_peri_backup_burst_limit.*/
+#define SYSCON_PERI_BACKUP_BURST_LIMIT    0x0000001F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
+/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: reg_peri_backup_flow_err.*/
+#define SYSCON_PERI_BACKUP_FLOW_ERR    0x00000003
+#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
+#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
+#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
+
+#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0xB8)
+/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_apb_start_addr.*/
+#define SYSCON_BACKUP_APB_START_ADDR    0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
+#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0xBC)
+/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_mem_start_addr.*/
+#define SYSCON_BACKUP_MEM_START_ADDR    0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
+#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0xC0)
+/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_raw.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_raw.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0xC4)
+/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_st.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_ST    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_st.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_ST    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0xC8)
+/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_ena.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_ena.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0xD0)
+/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_clr.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_clr.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
+/*description: reg_dateVersion control.*/
+#define SYSCON_DATE    0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */

components/soc/esp8684/include/soc/syscon_struct.h

@@ -0,0 +1,480 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSCON_STRUCT_H_
+#define _SOC_SYSCON_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct syscon_dev_s{
+    union {
+        struct {
+            uint32_t pre_div                       :    10;  /*reg_pre_div_cnt*/
+            uint32_t clk_320m_en                   :    1;  /*reg_clk_320m_en*/
+            uint32_t clk_en                        :    1;  /*reg_clk_en*/
+            uint32_t rst_tick                      :    1;  /*reg_rst_tick_cnt*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t xtal_tick                     :    8;  /*reg_xtal_tick_num*/
+            uint32_t ck8m_tick                     :    8;  /*reg_ck8m_tick_num*/
+            uint32_t tick_enable                   :    1;  /*reg_tick_enable*/
+            uint32_t reserved17                    :    15;  /*Reserved.*/
+        };
+        uint32_t val;
+    } tick_conf;
+    union {
+        struct {
+            uint32_t clk20_oen                     :    1;  /*reg_clk20_oen*/
+            uint32_t clk22_oen                     :    1;  /*reg_clk22_oen*/
+            uint32_t clk44_oen                     :    1;  /*reg_clk44_oen*/
+            uint32_t clk_bb_oen                    :    1;  /*reg_clk_bb_oen*/
+            uint32_t clk80_oen                     :    1;  /*reg_clk80_oen*/
+            uint32_t clk160_oen                    :    1;  /*reg_clk160_oen*/
+            uint32_t clk_320m_oen                  :    1;  /*reg_clk_320m_oen*/
+            uint32_t clk_adc_inf_oen               :    1;  /*reg_clk_adc_inf_oen*/
+            uint32_t clk_dac_cpu_oen               :    1;  /*reg_clk_dac_cpu_oen*/
+            uint32_t clk40x_bb_oen                 :    1;  /*reg_clk40x_bb_oen*/
+            uint32_t clk_xtal_oen                  :    1;  /*reg_clk_xtal_oen*/
+            uint32_t reserved11                    :    21;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clk_out_en;
+    uint32_t wifi_bb_cfg;
+    uint32_t wifi_bb_cfg_2;
+    uint32_t wifi_clk_en;
+    uint32_t wifi_rst_en;
+    union {
+        struct {
+            uint32_t peri_io_swap                  :    8;  /*reg_peri_io_swap*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } host_inf_sel;
+    union {
+        struct {
+            uint32_t ext_mem_pms_lock              :    1;  /*reg_ext_mem_pms_lock*/
+            uint32_t reserved1                     :    31;  /*Reserved.*/
+        };
+        uint32_t val;
+    } ext_mem_pms_lock;
+    uint32_t reserved_24;
+    union {
+        struct {
+            uint32_t flash_ace0_attr               :    2;  /*reg_flash_ace0_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace0_attr;
+    union {
+        struct {
+            uint32_t flash_ace1_attr               :    2;  /*reg_flash_ace1_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace1_attr;
+    union {
+        struct {
+            uint32_t flash_ace2_attr               :    2;  /*reg_flash_ace2_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace2_attr;
+    union {
+        struct {
+            uint32_t flash_ace3_attr               :    2;  /*reg_flash_ace3_attr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace3_attr;
+    uint32_t flash_ace0_addr;
+    uint32_t flash_ace1_addr;
+    uint32_t flash_ace2_addr;
+    uint32_t flash_ace3_addr;
+    union {
+        struct {
+            uint32_t flash_ace0_size               :    13;  /*reg_flash_ace0_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace0_size;
+    union {
+        struct {
+            uint32_t flash_ace1_size               :    13;  /*reg_flash_ace1_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace1_size;
+    union {
+        struct {
+            uint32_t flash_ace2_size               :    13;  /*reg_flash_ace2_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace2_size;
+    union {
+        struct {
+            uint32_t flash_ace3_size               :    13;  /*reg_flash_ace3_size*/
+            uint32_t reserved13                    :    19;  /*Reserved.*/
+        };
+        uint32_t val;
+    } flash_ace3_size;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    union {
+        struct {
+            uint32_t spi_mem_reject_int            :    1;  /*reg_spi_mem_reject_int*/
+            uint32_t spi_mem_reject_clr            :    1;  /*reg_spi_mem_reject_clr*/
+            uint32_t spi_mem_reject_cde            :    5;  /*reg_spi_mem_reject_cde*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } spi_mem_pms_ctrl;
+    uint32_t spi_mem_reject_addr;
+    union {
+        struct {
+            uint32_t sdio_win_access_en            :    1;  /*reg_sdio_win_access_en*/
+            uint32_t reserved1                     :    31;  /*Reserved.*/
+        };
+        uint32_t val;
+    } sdio_ctrl;
+    union {
+        struct {
+            uint32_t redcy_sig0                    :    31;  /*reg_redcy_sig0*/
+            uint32_t redcy_andor                   :    1;  /*reg_redcy_andor*/
+        };
+        uint32_t val;
+    } redcy_sig0;
+    union {
+        struct {
+            uint32_t redcy_sig1                    :    31;  /*reg_redcy_sig1*/
+            uint32_t redcy_nandor                  :    1;  /*reg_redcy_nandor*/
+        };
+        uint32_t val;
+    } redcy_sig1;
+    union {
+        struct {
+            uint32_t agc_mem_force_pu              :    1;  /*reg_agc_mem_force_pu*/
+            uint32_t agc_mem_force_pd              :    1;  /*reg_agc_mem_force_pd*/
+            uint32_t pbus_mem_force_pu             :    1;  /*reg_pbus_mem_force_pu*/
+            uint32_t pbus_mem_force_pd             :    1;  /*reg_pbus_mem_force_pd*/
+            uint32_t dc_mem_force_pu               :    1;  /*reg_dc_mem_force_pu*/
+            uint32_t dc_mem_force_pd               :    1;  /*reg_dc_mem_force_pd*/
+            uint32_t freq_mem_force_pu             :    1;  /*reg_freq_mem_force_pu*/
+            uint32_t freq_mem_force_pd             :    1;  /*reg_freq_mem_force_pd*/
+            uint32_t reserved8                     :    24;  /*Reserved.*/
+        };
+        uint32_t val;
+    } front_end_mem_pd;
+    union {
+        struct {
+            uint32_t retention_link_addr           :    27;  /*reg_retention_link_addr*/
+            uint32_t nobypass_cpu_iso_rst          :    1;  /*reg_nobypass_cpu_iso_rst*/
+            uint32_t reserved28                    :    4;  /*Reserved.*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rom_clkgate_force_on          :    3;  /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/
+            uint32_t sram_clkgate_force_on         :    4;  /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } clkgate_force_on;
+    union {
+        struct {
+            uint32_t rom_power_down                :    3;  /*Set 1 to let rom power down*/
+            uint32_t sram_power_down               :    4;  /*Set 1 to let sram power down*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } mem_power_down;
+    union {
+        struct {
+            uint32_t rom_power_up                  :    3;  /*Set 1 to let rom power up*/
+            uint32_t sram_power_up                 :    4;  /*Set 1 to let sram power up*/
+            uint32_t reserved7                     :    25;  /*Reserved.*/
+        };
+        uint32_t val;
+    } mem_power_up;
+    uint32_t rnd_data;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved.*/
+            uint32_t peri_backup_flow_err          :    2;  /*reg_peri_backup_flow_err*/
+            uint32_t reserved3                     :    1;  /*Reserved.*/
+            uint32_t peri_backup_burst_limit       :    5;  /*reg_peri_backup_burst_limit*/
+            uint32_t peri_backup_tout_thres        :    10;  /*reg_peri_backup_tout_thres*/
+            uint32_t peri_backup_size              :    10;  /*reg_peri_backup_size*/
+            uint32_t peri_backup_start             :    1;  /*reg_peri_backup_start*/
+            uint32_t peri_backup_to_mem            :    1;  /*reg_peri_backup_to_mem*/
+            uint32_t peri_backup_ena               :    1;  /*reg_peri_backup_ena*/
+        };
+        uint32_t val;
+    } peri_backup_config;
+    uint32_t peri_backup_addr;
+    uint32_t peri_backup_mem_addr;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_raw*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_raw*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_raw;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_st*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_st*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_st;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_ena*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_ena*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_ena;
+    uint32_t reserved_cc;
+    union {
+        struct {
+            uint32_t peri_backup_done              :    1;  /*reg_peri_backup_done_int_clr*/
+            uint32_t peri_backup_err               :    1;  /*reg_peri_backup_err_int_clr*/
+            uint32_t reserved2                     :    30;  /*Reserved.*/
+        };
+        uint32_t val;
+    } peri_backup_int_clr;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t date;
+} syscon_dev_t;
+extern syscon_dev_t SYSCON;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_STRUCT_H_ */

components/soc/esp8684/include/soc/system_reg.h

@@ -0,0 +1,722 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_REG_H_
+#define _SOC_SYSTEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x0)
+/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set 1 to open dedicated_gpio module clk.*/
+#define SYSTEM_CLK_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set 1 to open assist_debug module clock.*/
+#define SYSTEM_CLK_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0x4)
+/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Set 1 to let dedicated_gpio module reset.*/
+#define SYSTEM_RST_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set 1 to let assist_debug module reset.*/
+#define SYSTEM_RST_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x8)
+/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: This field used to set delay cycle when cpu enter waiti mode, after delay waiti_
+clk will close.*/
+#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
+#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
+/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Set 1 to force cpu_waiti_clk enable..*/
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
+/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: This field used to sel pll frequent..*/
+#define SYSTEM_PLL_FREQ_SEL    (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_V  0x1
+#define SYSTEM_PLL_FREQ_SEL_S  2
+/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: This field used to sel cpu clock frequent..*/
+#define SYSTEM_CPUPERIOD_SEL    0x00000003
+#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
+#define SYSTEM_CPUPERIOD_SEL_V  0x3
+#define SYSTEM_CPUPERIOD_SEL_S  0
+
+#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0xC)
+/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set 1 to mask memory power down..*/
+#define SYSTEM_LSLP_MEM_PD_MASK    (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
+#define SYSTEM_LSLP_MEM_PD_MASK_S  0
+
+#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x10)
+/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: Set 1 to enable ADC2_ARB clock.*/
+#define SYSTEM_ADC2_ARB_CLK_EN    (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
+#define SYSTEM_ADC2_ARB_CLK_EN_S  30
+/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set 1 to enable SYSTEMTIMER clock.*/
+#define SYSTEM_SYSTIMER_CLK_EN    (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
+#define SYSTEM_SYSTIMER_CLK_EN_S  29
+/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: Set 1 to enable APB_SARADC clock.*/
+#define SYSTEM_APB_SARADC_CLK_EN    (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
+#define SYSTEM_APB_SARADC_CLK_EN_S  28
+/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set 1 to enable UART_MEM clock.*/
+#define SYSTEM_UART_MEM_CLK_EN    (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_V  0x1
+#define SYSTEM_UART_MEM_CLK_EN_S  24
+/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: Set 1 to enable TIMERGROUP clock.*/
+#define SYSTEM_TIMERGROUP_CLK_EN    (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP_CLK_EN_S  13
+/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set 1 to enable LEDC clock.*/
+#define SYSTEM_LEDC_CLK_EN    (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_V  0x1
+#define SYSTEM_LEDC_CLK_EN_S  11
+/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set 1 to enable I2C_EXT0 clock.*/
+#define SYSTEM_I2C_EXT0_CLK_EN    (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT0_CLK_EN_S  7
+/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set 1 to enable SPI2 clock.*/
+#define SYSTEM_SPI2_CLK_EN    (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_V  0x1
+#define SYSTEM_SPI2_CLK_EN_S  6
+/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Set 1 to enable UART1 clock.*/
+#define SYSTEM_UART1_CLK_EN    (BIT(5))
+#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_V  0x1
+#define SYSTEM_UART1_CLK_EN_S  5
+/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set 1 to enable UART clock.*/
+#define SYSTEM_UART_CLK_EN    (BIT(2))
+#define SYSTEM_UART_CLK_EN_M  (BIT(2))
+#define SYSTEM_UART_CLK_EN_V  0x1
+#define SYSTEM_UART_CLK_EN_S  2
+/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set 1 to enable SPI01 clock.*/
+#define SYSTEM_SPI01_CLK_EN    (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_V  0x1
+#define SYSTEM_SPI01_CLK_EN_S  1
+
+#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x14)
+/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set 1 to enable TSENS clock.*/
+#define SYSTEM_TSENS_CLK_EN    (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_M  (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_V  0x1
+#define SYSTEM_TSENS_CLK_EN_S  10
+/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set 1 to enable DMA clock.*/
+#define SYSTEM_DMA_CLK_EN    (BIT(6))
+#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_V  0x1
+#define SYSTEM_DMA_CLK_EN_S  6
+/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set 1 to enable SHA clock.*/
+#define SYSTEM_CRYPTO_SHA_CLK_EN    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
+/* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to enable ECC clock.*/
+#define SYSTEM_CRYPTO_ECC_CLK_EN    (BIT(1))
+#define SYSTEM_CRYPTO_ECC_CLK_EN_M  (BIT(1))
+#define SYSTEM_CRYPTO_ECC_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_ECC_CLK_EN_S  1
+
+#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x18)
+/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set 1 to let ADC2_ARB reset.*/
+#define SYSTEM_ADC2_ARB_RST    (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_V  0x1
+#define SYSTEM_ADC2_ARB_RST_S  30
+/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set 1 to let SYSTIMER reset.*/
+#define SYSTEM_SYSTIMER_RST    (BIT(29))
+#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_V  0x1
+#define SYSTEM_SYSTIMER_RST_S  29
+/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set 1 to let APB_SARADC reset.*/
+#define SYSTEM_APB_SARADC_RST    (BIT(28))
+#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_V  0x1
+#define SYSTEM_APB_SARADC_RST_S  28
+/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set 1 to let UART_MEM reset.*/
+#define SYSTEM_UART_MEM_RST    (BIT(24))
+#define SYSTEM_UART_MEM_RST_M  (BIT(24))
+#define SYSTEM_UART_MEM_RST_V  0x1
+#define SYSTEM_UART_MEM_RST_S  24
+/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set 1 to let TIMERGROUP reset.*/
+#define SYSTEM_TIMERGROUP_RST    (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_V  0x1
+#define SYSTEM_TIMERGROUP_RST_S  13
+/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set 1 to let LEDC reset.*/
+#define SYSTEM_LEDC_RST    (BIT(11))
+#define SYSTEM_LEDC_RST_M  (BIT(11))
+#define SYSTEM_LEDC_RST_V  0x1
+#define SYSTEM_LEDC_RST_S  11
+/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set 1 to let I2C_EXT0 reset.*/
+#define SYSTEM_I2C_EXT0_RST    (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_V  0x1
+#define SYSTEM_I2C_EXT0_RST_S  7
+/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set 1 to let SPI2 reset.*/
+#define SYSTEM_SPI2_RST    (BIT(6))
+#define SYSTEM_SPI2_RST_M  (BIT(6))
+#define SYSTEM_SPI2_RST_V  0x1
+#define SYSTEM_SPI2_RST_S  6
+/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set 1 to let UART1 reset.*/
+#define SYSTEM_UART1_RST    (BIT(5))
+#define SYSTEM_UART1_RST_M  (BIT(5))
+#define SYSTEM_UART1_RST_V  0x1
+#define SYSTEM_UART1_RST_S  5
+/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set 1 to let UART reset.*/
+#define SYSTEM_UART_RST    (BIT(2))
+#define SYSTEM_UART_RST_M  (BIT(2))
+#define SYSTEM_UART_RST_V  0x1
+#define SYSTEM_UART_RST_S  2
+/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to let SPI01 reset.*/
+#define SYSTEM_SPI01_RST    (BIT(1))
+#define SYSTEM_SPI01_RST_M  (BIT(1))
+#define SYSTEM_SPI01_RST_V  0x1
+#define SYSTEM_SPI01_RST_S  1
+
+#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x1C)
+/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set 1 to let TSENS reset.*/
+#define SYSTEM_TSENS_RST    (BIT(10))
+#define SYSTEM_TSENS_RST_M  (BIT(10))
+#define SYSTEM_TSENS_RST_V  0x1
+#define SYSTEM_TSENS_RST_S  10
+/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set 1 to let DMA reset.*/
+#define SYSTEM_DMA_RST    (BIT(6))
+#define SYSTEM_DMA_RST_M  (BIT(6))
+#define SYSTEM_DMA_RST_V  0x1
+#define SYSTEM_DMA_RST_S  6
+/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set 1 to let CRYPTO_SHA reset.*/
+#define SYSTEM_CRYPTO_SHA_RST    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_V  0x1
+#define SYSTEM_CRYPTO_SHA_RST_S  2
+/* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set 1 to let CRYPTO_ECC reset.*/
+#define SYSTEM_CRYPTO_ECC_RST    (BIT(1))
+#define SYSTEM_CRYPTO_ECC_RST_M  (BIT(1))
+#define SYSTEM_CRYPTO_ECC_RST_V  0x1
+#define SYSTEM_CRYPTO_ECC_RST_S  1
+
+#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x20)
+/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: This field is lower power clock frequent division factor.*/
+#define SYSTEM_BT_LPCK_DIV_NUM    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
+#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_NUM_S  0
+
+#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x24)
+/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set 1 to enable RTC low power clock.*/
+#define SYSTEM_LPCLK_RTC_EN    (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_V  0x1
+#define SYSTEM_LPCLK_RTC_EN_S  28
+/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set 1 to select xtal32k clock as low power clock.*/
+#define SYSTEM_LPCLK_SEL_XTAL32K    (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
+/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set 1 to select xtal clock as rtc low power clock.*/
+#define SYSTEM_LPCLK_SEL_XTAL    (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL_S  26
+/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: Set 1 to select 8m clock as rtc low power clock.*/
+#define SYSTEM_LPCLK_SEL_8M    (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_V  0x1
+#define SYSTEM_LPCLK_SEL_8M_S  25
+/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set 1 to select rtc-slow clock as rtc low power clock.*/
+#define SYSTEM_LPCLK_SEL_RTC_SLOW    (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
+/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: This field is lower power clock frequent division factor a.*/
+#define SYSTEM_BT_LPCK_DIV_A    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
+#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_A_S  12
+/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: This field is lower power clock frequent division factor b.*/
+#define SYSTEM_BT_LPCK_DIV_B    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
+#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_B_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x28)
+/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to generate cpu interrupt 0.*/
+#define SYSTEM_CPU_INTR_FROM_CPU_0    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x2C)
+/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to generate cpu interrupt 1.*/
+#define SYSTEM_CPU_INTR_FROM_CPU_1    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x30)
+/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to generate cpu interrupt 2.*/
+#define SYSTEM_CPU_INTR_FROM_CPU_2    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x34)
+/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to generate cpu interrupt 3.*/
+#define SYSTEM_CPU_INTR_FROM_CPU_3    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
+
+#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x38)
+/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set 1 to force power down RSA memory. This bit has the highest priority..*/
+#define SYSTEM_RSA_MEM_FORCE_PD    (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PD_S  2
+/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to force power up RSA memory. This bit has the second highest priority..*/
+#define SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PU_S  1
+/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Si
+gnature occupies the RSA. This bit is invalid..*/
+#define SYSTEM_RSA_MEM_PD    (BIT(0))
+#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_V  0x1
+#define SYSTEM_RSA_MEM_PD_S  0
+
+#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x3C)
+/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to let EDMA reset.*/
+#define SYSTEM_EDMA_RESET    (BIT(1))
+#define SYSTEM_EDMA_RESET_M  (BIT(1))
+#define SYSTEM_EDMA_RESET_V  0x1
+#define SYSTEM_EDMA_RESET_S  1
+/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set 1 to enable EDMA clock..*/
+#define SYSTEM_EDMA_CLK_ON    (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_V  0x1
+#define SYSTEM_EDMA_CLK_ON_S  0
+
+#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x40)
+/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set 1 to let dcache reset.*/
+#define SYSTEM_DCACHE_RESET    (BIT(3))
+#define SYSTEM_DCACHE_RESET_M  (BIT(3))
+#define SYSTEM_DCACHE_RESET_V  0x1
+#define SYSTEM_DCACHE_RESET_S  3
+/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set 1 to enable dcache clock.*/
+#define SYSTEM_DCACHE_CLK_ON    (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_V  0x1
+#define SYSTEM_DCACHE_CLK_ON_S  2
+/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to let icache reset.*/
+#define SYSTEM_ICACHE_RESET    (BIT(1))
+#define SYSTEM_ICACHE_RESET_M  (BIT(1))
+#define SYSTEM_ICACHE_RESET_V  0x1
+#define SYSTEM_ICACHE_RESET_S  1
+/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set 1 to enable icache clock.*/
+#define SYSTEM_ICACHE_CLK_ON    (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_V  0x1
+#define SYSTEM_ICACHE_CLK_ON_S  0
+
+#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x44)
+/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set 1 to enable download manual encrypt.*/
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set 1 to enable download G0CB decrypt.*/
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set 1 to enable download DB encrypt..*/
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to enable the SPI manual encrypt..*/
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+
+#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x48)
+/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: This bit stores the status of RTC memory CRC.1 means finished..*/
+#define SYSTEM_RTC_MEM_CRC_FINISH    (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
+#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
+/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
+/*description: This field is used to set length of RTC memory for CRC based on start address..*/
+#define SYSTEM_RTC_MEM_CRC_LEN    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_LEN_S  20
+/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
+/*description: This field is used to set address of RTC memory for CRC..*/
+#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
+/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to start the CRC of RTC memory.*/
+#define SYSTEM_RTC_MEM_CRC_START    (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_V  0x1
+#define SYSTEM_RTC_MEM_CRC_START_S  8
+
+#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x4C)
+/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: This field stores the CRC result of RTC memory..*/
+#define SYSTEM_RTC_MEM_CRC_RES    0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_S  0
+
+#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x50)
+/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_redundant_eco_result.*/
+#define SYSTEM_REDUNDANT_ECO_RESULT    (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
+#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
+/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_redundant_eco_drive.*/
+#define SYSTEM_REDUNDANT_ECO_DRIVE    (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
+#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
+
+#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x54)
+/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_clk_en.*/
+#define SYSTEM_CLK_EN    (BIT(0))
+#define SYSTEM_CLK_EN_M  (BIT(0))
+#define SYSTEM_CLK_EN_V  0x1
+#define SYSTEM_CLK_EN_S  0
+
+#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x58)
+/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: reg_clk_div_en.*/
+#define SYSTEM_CLK_DIV_EN    (BIT(19))
+#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_V  0x1
+#define SYSTEM_CLK_DIV_EN_S  19
+/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
+/*description: This field is used to read xtal frequency in MHz..*/
+#define SYSTEM_CLK_XTAL_FREQ    0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
+#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
+#define SYSTEM_CLK_XTAL_FREQ_S  12
+/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: This field is used to select soc clock..*/
+#define SYSTEM_SOC_CLK_SEL    0x00000003
+#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
+#define SYSTEM_SOC_CLK_SEL_V  0x3
+#define SYSTEM_SOC_CLK_SEL_S  10
+/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: This field is used to set the count of prescaler of XTAL_CLK..*/
+#define SYSTEM_PRE_DIV_CNT    0x000003FF
+#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
+#define SYSTEM_PRE_DIV_CNT_V  0x3FF
+#define SYSTEM_PRE_DIV_CNT_S  0
+
+#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x5C)
+/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: reg_mem_vt_sel.*/
+#define SYSTEM_MEM_VT_SEL    0x00000003
+#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
+#define SYSTEM_MEM_VT_SEL_V  0x3
+#define SYSTEM_MEM_VT_SEL_S  22
+/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
+/*description: reg_mem_timing_err_cnt.*/
+#define SYSTEM_MEM_TIMING_ERR_CNT    0x0000FFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
+#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
+/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: reg_mem_pvt_monitor_en.*/
+#define SYSTEM_MEM_PVT_MONITOR_EN    (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
+#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
+/* SYSTEM_MEM_ERR_CNT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: reg_mem_err_cnt_clr.*/
+#define SYSTEM_MEM_ERR_CNT_CLR    (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
+#define SYSTEM_MEM_ERR_CNT_CLR_S  4
+/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
+/*description: reg_mem_path_len.*/
+#define SYSTEM_MEM_PATH_LEN    0x0000000F
+#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
+#define SYSTEM_MEM_PATH_LEN_V  0xF
+#define SYSTEM_MEM_PATH_LEN_S  0
+
+#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x60)
+/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_comb_pvt_monitor_en_lvt.*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT    (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  7
+/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: reg_comb_err_cnt_clr_lvt.*/
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT    (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  6
+/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: reg_comb_path_len_lvt.*/
+#define SYSTEM_COMB_PATH_LEN_LVT    0x0000003F
+#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
+#define SYSTEM_COMB_PATH_LEN_LVT_V  0x3F
+#define SYSTEM_COMB_PATH_LEN_LVT_S  0
+
+#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x64)
+/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_comb_pvt_monitor_en_nvt.*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT    (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  7
+/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: reg_comb_err_cnt_clr_nvt.*/
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT    (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  6
+/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: reg_comb_path_len_nvt.*/
+#define SYSTEM_COMB_PATH_LEN_NVT    0x0000003F
+#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
+#define SYSTEM_COMB_PATH_LEN_NVT_V  0x3F
+#define SYSTEM_COMB_PATH_LEN_NVT_S  0
+
+#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x68)
+/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_comb_pvt_monitor_en_hvt.*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT    (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(7))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  7
+/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: reg_comb_err_cnt_clr_hvt.*/
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT    (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(6))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  6
+/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: reg_comb_path_len_hvt.*/
+#define SYSTEM_COMB_PATH_LEN_HVT    0x0000003F
+#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
+#define SYSTEM_COMB_PATH_LEN_HVT_V  0x3F
+#define SYSTEM_COMB_PATH_LEN_HVT_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x6C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_lvt_site0.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x70)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_nvt_site0.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x74)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_hvt_site0.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x78)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_lvt_site1.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x7C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_nvt_site1.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x80)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_hvt_site1.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x84)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_lvt_site2.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x88)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_nvt_site2.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x8C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_hvt_site2.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x90)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_lvt_site3.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x94)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_nvt_site3.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x98)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: reg_comb_timing_err_cnt_hvt_site3.*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
+
+#define SYSTEM_REG_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
+/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
+/*description: reg_system_reg_date.*/
+#define SYSTEM_DATE    0x0FFFFFFF
+#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
+#define SYSTEM_DATE_V  0xFFFFFFF
+#define SYSTEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_REG_H_ */

components/soc/esp8684/include/soc/system_struct.h

@@ -0,0 +1,1404 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_STRUCT_H_
+#define _SOC_SYSTEM_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct system_dev_s {
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t clk_en_assist_debug           :    1;  /*Set 1 to open assist_debug module clock*/
+            uint32_t clk_en_dedicated_gpio         :    1;  /*Set 1 to open dedicated_gpio module clk*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_clk_en;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t rst_en_assist_debug           :    1;  /*Set 1 to let assist_debug module reset*/
+            uint32_t rst_en_dedicated_gpio         :    1;  /*Set 1 to let dedicated_gpio module reset*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_rst_en;
+    union {
+        struct {
+            uint32_t cpuperiod_sel                 :    2;  /*This field used to sel cpu clock frequent.*/
+            uint32_t pll_freq_sel                  :    1;  /*This field used to sel pll frequent.*/
+            uint32_t cpu_wait_mode_force_on        :    1;  /*Set 1 to force cpu_waiti_clk enable.*/
+            uint32_t cpu_waiti_delay_num           :    4;  /*This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_per_conf;
+    union {
+        struct {
+            uint32_t lslp_mem_pd_mask              :    1;  /*Set 1 to mask memory power down.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pd_mask;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t spi01_clk_en                  :    1;  /*Set 1 to enable SPI01 clock*/
+            uint32_t uart_clk_en                   :    1;  /*Set 1 to enable UART clock*/
+            uint32_t reserved3                     :    1;  /*reserved*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t uart1_clk_en                  :    1;  /*Set 1 to enable UART1 clock*/
+            uint32_t spi2_clk_en                   :    1;  /*Set 1 to enable SPI2 clock*/
+            uint32_t i2c_ext0_clk_en               :    1;  /*Set 1 to enable I2C_EXT0 clock*/
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t reserved10                    :    1;  /*reserved*/
+            uint32_t ledc_clk_en                   :    1;  /*Set 1 to enable LEDC clock*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t timergroup_clk_en             :    1;  /*Set 1 to enable TIMERGROUP clock*/
+            uint32_t reserved14                    :    1;  /*reserved*/
+            uint32_t reserved15                    :    1;  /*reserved*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t reserved18                    :    1;  /*reserved*/
+            uint32_t reserved19                    :    1;  /*reserved*/
+            uint32_t reserved20                    :    1;  /*reserved*/
+            uint32_t reserved21                    :    1;  /*reserved*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t reserved23                    :    1;  /*reserved*/
+            uint32_t uart_mem_clk_en               :    1;  /*Set 1 to enable UART_MEM clock*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reserved26                    :    1;  /*reserved*/
+            uint32_t reserved27                    :    1;  /*reserved*/
+            uint32_t apb_saradc_clk_en             :    1;  /*Set 1 to enable APB_SARADC clock*/
+            uint32_t systimer_clk_en               :    1;  /*Set 1 to enable SYSTEMTIMER clock*/
+            uint32_t adc2_arb_clk_en               :    1;  /*Set 1 to enable ADC2_ARB clock*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_clk_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t crypto_ecc_clk_en             :    1;  /*Set 1 to enable ECC clock*/
+            uint32_t crypto_sha_clk_en             :    1;  /*Set 1 to enable SHA clock*/
+            uint32_t reserved3                     :    1;  /*reserved*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t reserved5                     :    1;  /*reserved*/
+            uint32_t dma_clk_en                    :    1;  /*Set 1 to enable DMA clock*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t tsens_clk_en                  :    1;  /*Set 1 to enable TSENS clock*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_clk_en1;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t spi01_rst                     :    1;  /*Set 1 to let SPI01 reset*/
+            uint32_t uart_rst                      :    1;  /*Set 1 to let UART reset*/
+            uint32_t reserved3                     :    1;  /*reserved*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t uart1_rst                     :    1;  /*Set 1 to let UART1 reset*/
+            uint32_t spi2_rst                      :    1;  /*Set 1 to let SPI2 reset*/
+            uint32_t i2c_ext0_rst                  :    1;  /*Set 1 to let I2C_EXT0 reset*/
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t reserved10                    :    1;  /*reserved*/
+            uint32_t ledc_rst                      :    1;  /*Set 1 to let LEDC reset*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t timergroup_rst                :    1;  /*Set 1 to let TIMERGROUP reset*/
+            uint32_t reserved14                    :    1;  /*reserved*/
+            uint32_t reserved15                    :    1;  /*reserved*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t reserved18                    :    1;  /*reserved*/
+            uint32_t reserved19                    :    1;  /*reserved*/
+            uint32_t reserved20                    :    1;  /*reserved*/
+            uint32_t reserved21                    :    1;  /*reserved*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t reserved23                    :    1;  /*reserved*/
+            uint32_t uart_mem_rst                  :    1;  /*Set 1 to let UART_MEM reset*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reserved26                    :    1;  /*reserved*/
+            uint32_t reserved27                    :    1;  /*reserved*/
+            uint32_t apb_saradc_rst                :    1;  /*Set 1 to let APB_SARADC reset*/
+            uint32_t systimer_rst                  :    1;  /*Set 1 to let SYSTIMER reset*/
+            uint32_t adc2_arb_rst                  :    1;  /*Set 1 to let ADC2_ARB reset*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_rst_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t crypto_ecc_rst                :    1;  /*Set 1 to let CRYPTO_ECC reset*/
+            uint32_t crypto_sha_rst                :    1;  /*Set 1 to let CRYPTO_SHA reset*/
+            uint32_t reserved3                     :    1;  /*reserved*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t reserved5                     :    1;  /*reserved*/
+            uint32_t dma_rst                       :    1;  /*Set 1 to let DMA reset*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t tsens_rst                     :    1;  /*Set 1 to let TSENS reset*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_rst_en1;
+    union {
+        struct {
+            uint32_t bt_lpck_div_num               :    12;  /*This field is lower power clock frequent division factor*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_int;
+    union {
+        struct {
+            uint32_t bt_lpck_div_b                 :    12;  /*This field is lower power clock frequent division factor b*/
+            uint32_t bt_lpck_div_a                 :    12;  /*This field is lower power clock frequent division factor a*/
+            uint32_t lpclk_sel_rtc_slow            :    1;  /*Set 1 to select rtc-slow clock as rtc low power clock*/
+            uint32_t lpclk_sel_8m                  :    1;  /*Set 1 to select 8m clock as rtc low power clock*/
+            uint32_t lpclk_sel_xtal                :    1;  /*Set 1 to select xtal clock as rtc low power clock*/
+            uint32_t lpclk_sel_xtal32k             :    1;  /*Set 1 to select xtal32k clock as low power clock*/
+            uint32_t lpclk_rtc_en                  :    1;  /*Set 1 to enable RTC low power clock*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_frac;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_0           :    1;  /*Set 1 to generate cpu interrupt 0*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_0;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_1           :    1;  /*Set 1 to generate cpu interrupt 1*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_1;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_2           :    1;  /*Set 1 to generate cpu interrupt 2*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_2;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_3           :    1;  /*Set 1 to generate cpu interrupt 3*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_3;
+    union {
+        struct {
+            uint32_t rsa_mem_pd                    :    1;  /*Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid.*/
+            uint32_t rsa_mem_force_pu              :    1;  /*Set 1 to force power up RSA memory. This bit has the second highest priority.*/
+            uint32_t rsa_mem_force_pd              :    1;  /*Set 1 to force power down RSA memory. This bit has the highest priority.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } rsa_pd_ctrl;
+    union {
+        struct {
+            uint32_t edma_clk_on                   :    1;  /*Set 1 to enable EDMA clock.*/
+            uint32_t edma_reset                    :    1;  /*Set 1 to let EDMA reset*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } edma_ctrl;
+    union {
+        struct {
+            uint32_t icache_clk_on                 :    1;  /*Set 1 to enable icache clock*/
+            uint32_t icache_reset                  :    1;  /*Set 1 to let icache reset*/
+            uint32_t dcache_clk_on                 :    1;  /*Set 1 to enable dcache clock*/
+            uint32_t dcache_reset                  :    1;  /*Set 1 to let dcache reset*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_control;
+    union {
+        struct {
+            uint32_t enable_spi_manual_encrypt     :    1;  /*Set 1 to enable the SPI manual encrypt.*/
+            uint32_t enable_download_db_encrypt    :    1;  /*Set 1 to enable download DB encrypt.*/
+            uint32_t enable_download_g0cb_decrypt  :    1;  /*Set 1 to enable download G0CB decrypt*/
+            uint32_t enable_download_manual_encrypt:    1;  /*Set 1 to enable download manual encrypt*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } external_device_encrypt_decrypt_control;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*fast memory crc register*/
+            uint32_t rtc_mem_crc_start             :    1;  /*Set 1 to start the CRC of RTC memory*/
+            uint32_t rtc_mem_crc_addr              :    11;  /*This field is used to set address of RTC memory for CRC.*/
+            uint32_t rtc_mem_crc_len               :    11;  /*This field is used to set length of RTC memory for CRC based on start address.*/
+            uint32_t rtc_mem_crc_finish            :    1;  /*This bit stores the status of RTC memory CRC.1 means finished.*/
+        };
+        uint32_t val;
+    } rtc_fastmem_config;
+    uint32_t rtc_fastmem_crc;
+    union {
+        struct {
+            uint32_t redundant_eco_drive           :    1;  /*reg_redundant_eco_drive*/
+            uint32_t redundant_eco_result          :    1;  /*reg_redundant_eco_result*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } redundant_eco_ctrl;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*reg_clk_en*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t pre_div_cnt                   :    10;  /*This field is used to set the count of prescaler of XTAL_CLK.*/
+            uint32_t soc_clk_sel                   :    2;  /*This field is used to select soc clock.*/
+            uint32_t clk_xtal_freq                 :    7;  /*This field is used to read xtal frequency in MHz.*/
+            uint32_t clk_div_en                    :    1;  /*reg_clk_div_en*/
+            uint32_t reserved20                    :    12;  /*reserved*/
+        };
+        uint32_t val;
+    } sysclk_conf;
+    union {
+        struct {
+            uint32_t mem_path_len                  :    4;  /*reg_mem_path_len*/
+            uint32_t mem_err_cnt_clr               :    1;  /*reg_mem_err_cnt_clr*/
+            uint32_t mem_pvt_monitor_en            :    1;  /*reg_mem_pvt_monitor_en*/
+            uint32_t mem_timing_err_cnt            :    16;  /*reg_mem_timing_err_cnt*/
+            uint32_t mem_vt_sel                    :    2;  /*reg_mem_vt_sel*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pvt;
+    union {
+        struct {
+            uint32_t comb_path_len_lvt             :    6;  /*reg_comb_path_len_lvt*/
+            uint32_t comb_err_cnt_clr_lvt          :    1;  /*reg_comb_err_cnt_clr_lvt*/
+            uint32_t comb_pvt_monitor_en_lvt       :    1;  /*reg_comb_pvt_monitor_en_lvt*/
+            uint32_t reserved8                     :    18;  /*reserved*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_lvt_conf;
+    union {
+        struct {
+            uint32_t comb_path_len_nvt             :    6;  /*reg_comb_path_len_nvt*/
+            uint32_t comb_err_cnt_clr_nvt          :    1;  /*reg_comb_err_cnt_clr_nvt*/
+            uint32_t comb_pvt_monitor_en_nvt       :    1;  /*reg_comb_pvt_monitor_en_nvt*/
+            uint32_t reserved8                     :    18;  /*reserved*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_nvt_conf;
+    union {
+        struct {
+            uint32_t comb_path_len_hvt             :    6;  /*reg_comb_path_len_hvt*/
+            uint32_t comb_err_cnt_clr_hvt          :    1;  /*reg_comb_err_cnt_clr_hvt*/
+            uint32_t comb_pvt_monitor_en_hvt       :    1;  /*reg_comb_pvt_monitor_en_hvt*/
+            uint32_t reserved8                     :    18;  /*reserved*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_hvt_conf;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site0 :    16;  /*reg_comb_timing_err_cnt_lvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site0 :    16;  /*reg_comb_timing_err_cnt_nvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site0 :    16;  /*reg_comb_timing_err_cnt_hvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site1 :    16;  /*reg_comb_timing_err_cnt_lvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site1 :    16;  /*reg_comb_timing_err_cnt_nvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site1 :    16;  /*reg_comb_timing_err_cnt_hvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site2 :    16;  /*reg_comb_timing_err_cnt_lvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site2 :    16;  /*reg_comb_timing_err_cnt_nvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site2 :    16;  /*reg_comb_timing_err_cnt_hvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site3 :    16;  /*reg_comb_timing_err_cnt_lvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site3;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site3 :    16;  /*reg_comb_timing_err_cnt_nvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site3;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site3 :    16;  /*reg_comb_timing_err_cnt_hvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site3;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t system_date                   :    28;  /*reg_system_reg_date*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} system_dev_t;
+extern system_dev_t SYSTEM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_STRUCT_H_ */

components/soc/esp8684/include/soc/systimer_reg.h

@@ -0,0 +1,415 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTIMER_REG_H_
+#define _SOC_SYSTIMER_REG_H_
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SYSTIMER_CONF_REG          (DR_REG_SYSTIMER_BASE + 0x0)
+/* SYSTIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: register file clk gating.*/
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (BIT(31))
+#define SYSTIMER_CLK_EN_V  0x1
+#define SYSTIMER_CLK_EN_S  31
+/* SYSTIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: timer unit0 work enable.*/
+#define SYSTIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_UNIT0_WORK_EN_M  (BIT(30))
+#define SYSTIMER_UNIT0_WORK_EN_V  0x1
+#define SYSTIMER_UNIT0_WORK_EN_S  30
+/* SYSTIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: timer unit1 work enable.*/
+#define SYSTIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_UNIT1_WORK_EN_M  (BIT(29))
+#define SYSTIMER_UNIT1_WORK_EN_V  0x1
+#define SYSTIMER_UNIT1_WORK_EN_S  29
+/* SYSTIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: If timer unit0 is stalled when core0 stalled.*/
+#define SYSTIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_UNIT0_CORE0_STALL_EN_M  (BIT(28))
+#define SYSTIMER_UNIT0_CORE0_STALL_EN_V  0x1
+#define SYSTIMER_UNIT0_CORE0_STALL_EN_S  28
+/* SYSTIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: If timer unit0 is stalled when core1 stalled.*/
+#define SYSTIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_UNIT0_CORE1_STALL_EN_M  (BIT(27))
+#define SYSTIMER_UNIT0_CORE1_STALL_EN_V  0x1
+#define SYSTIMER_UNIT0_CORE1_STALL_EN_S  27
+/* SYSTIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: If timer unit1 is stalled when core0 stalled.*/
+#define SYSTIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_UNIT1_CORE0_STALL_EN_M  (BIT(26))
+#define SYSTIMER_UNIT1_CORE0_STALL_EN_V  0x1
+#define SYSTIMER_UNIT1_CORE0_STALL_EN_S  26
+/* SYSTIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: If timer unit1 is stalled when core1 stalled.*/
+#define SYSTIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_UNIT1_CORE1_STALL_EN_M  (BIT(25))
+#define SYSTIMER_UNIT1_CORE1_STALL_EN_V  0x1
+#define SYSTIMER_UNIT1_CORE1_STALL_EN_S  25
+/* SYSTIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: target0 work enable.*/
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_V  0x1
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/* SYSTIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: target1 work enable.*/
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_V  0x1
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/* SYSTIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: target2 work enable.*/
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_V  0x1
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/* SYSTIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: systimer clock force on.*/
+#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_M  (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x1
+#define SYSTIMER_SYSTIMER_CLK_FO_S  0
+
+#define SYSTIMER_UNIT0_OP_REG          (DR_REG_SYSTIMER_BASE + 0x4)
+/* SYSTIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: update timer_unit0.*/
+#define SYSTIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_UNIT0_UPDATE_M  (BIT(30))
+#define SYSTIMER_UNIT0_UPDATE_V  0x1
+#define SYSTIMER_UNIT0_UPDATE_S  30
+/* SYSTIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: timer value is sync and valid.*/
+#define SYSTIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_UNIT0_VALUE_VALID_M  (BIT(29))
+#define SYSTIMER_UNIT0_VALUE_VALID_V  0x1
+#define SYSTIMER_UNIT0_VALUE_VALID_S  29
+
+#define SYSTIMER_UNIT1_OP_REG          (DR_REG_SYSTIMER_BASE + 0x8)
+/* SYSTIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: update timer unit1.*/
+#define SYSTIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_UNIT1_UPDATE_M  (BIT(30))
+#define SYSTIMER_UNIT1_UPDATE_V  0x1
+#define SYSTIMER_UNIT1_UPDATE_S  30
+/* SYSTIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: timer value is sync and valid.*/
+#define SYSTIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_UNIT1_VALUE_VALID_M  (BIT(29))
+#define SYSTIMER_UNIT1_VALUE_VALID_V  0x1
+#define SYSTIMER_UNIT1_VALUE_VALID_S  29
+
+#define SYSTIMER_UNIT0_LOAD_HI_REG          (DR_REG_SYSTIMER_BASE + 0xC)
+/* SYSTIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer unit0 load high 20 bits.*/
+#define SYSTIMER_UNIT0_LOAD_HI    0x000FFFFF
+#define SYSTIMER_UNIT0_LOAD_HI_M  ((SYSTIMER_UNIT0_LOAD_HI_V)<<(SYSTIMER_UNIT0_LOAD_HI_S))
+#define SYSTIMER_UNIT0_LOAD_HI_V  0xFFFFF
+#define SYSTIMER_UNIT0_LOAD_HI_S  0
+
+#define SYSTIMER_UNIT0_LOAD_LO_REG          (DR_REG_SYSTIMER_BASE + 0x10)
+/* SYSTIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer unit0 load low 32 bits.*/
+#define SYSTIMER_UNIT0_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_UNIT0_LOAD_LO_M  ((SYSTIMER_UNIT0_LOAD_LO_V)<<(SYSTIMER_UNIT0_LOAD_LO_S))
+#define SYSTIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_UNIT0_LOAD_LO_S  0
+
+#define SYSTIMER_UNIT1_LOAD_HI_REG          (DR_REG_SYSTIMER_BASE + 0x14)
+/* SYSTIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer unit1 load high 20 bits.*/
+#define SYSTIMER_UNIT1_LOAD_HI    0x000FFFFF
+#define SYSTIMER_UNIT1_LOAD_HI_M  ((SYSTIMER_UNIT1_LOAD_HI_V)<<(SYSTIMER_UNIT1_LOAD_HI_S))
+#define SYSTIMER_UNIT1_LOAD_HI_V  0xFFFFF
+#define SYSTIMER_UNIT1_LOAD_HI_S  0
+
+#define SYSTIMER_UNIT1_LOAD_LO_REG          (DR_REG_SYSTIMER_BASE + 0x18)
+/* SYSTIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer unit1 load low 32 bits.*/
+#define SYSTIMER_UNIT1_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_UNIT1_LOAD_LO_M  ((SYSTIMER_UNIT1_LOAD_LO_V)<<(SYSTIMER_UNIT1_LOAD_LO_S))
+#define SYSTIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_UNIT1_LOAD_LO_S  0
+
+#define SYSTIMER_TARGET0_HI_REG          (DR_REG_SYSTIMER_BASE + 0x1C)
+/* SYSTIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget0 high 20 bits.*/
+#define SYSTIMER_TARGET0_HI    0x000FFFFF
+#define SYSTIMER_TARGET0_HI_M  ((SYSTIMER_TARGET0_HI_V)<<(SYSTIMER_TARGET0_HI_S))
+#define SYSTIMER_TARGET0_HI_V  0xFFFFF
+#define SYSTIMER_TARGET0_HI_S  0
+
+#define SYSTIMER_TARGET0_LO_REG          (DR_REG_SYSTIMER_BASE + 0x20)
+/* SYSTIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget0 low 32 bits.*/
+#define SYSTIMER_TARGET0_LO    0xFFFFFFFF
+#define SYSTIMER_TARGET0_LO_M  ((SYSTIMER_TARGET0_LO_V)<<(SYSTIMER_TARGET0_LO_S))
+#define SYSTIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET0_LO_S  0
+
+#define SYSTIMER_TARGET1_HI_REG          (DR_REG_SYSTIMER_BASE + 0x24)
+/* SYSTIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget1 high 20 bits.*/
+#define SYSTIMER_TARGET1_HI    0x000FFFFF
+#define SYSTIMER_TARGET1_HI_M  ((SYSTIMER_TARGET1_HI_V)<<(SYSTIMER_TARGET1_HI_S))
+#define SYSTIMER_TARGET1_HI_V  0xFFFFF
+#define SYSTIMER_TARGET1_HI_S  0
+
+#define SYSTIMER_TARGET1_LO_REG          (DR_REG_SYSTIMER_BASE + 0x28)
+/* SYSTIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget1 low 32 bits.*/
+#define SYSTIMER_TARGET1_LO    0xFFFFFFFF
+#define SYSTIMER_TARGET1_LO_M  ((SYSTIMER_TARGET1_LO_V)<<(SYSTIMER_TARGET1_LO_S))
+#define SYSTIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET1_LO_S  0
+
+#define SYSTIMER_TARGET2_HI_REG          (DR_REG_SYSTIMER_BASE + 0x2C)
+/* SYSTIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget2 high 20 bits.*/
+#define SYSTIMER_TARGET2_HI    0x000FFFFF
+#define SYSTIMER_TARGET2_HI_M  ((SYSTIMER_TARGET2_HI_V)<<(SYSTIMER_TARGET2_HI_S))
+#define SYSTIMER_TARGET2_HI_V  0xFFFFF
+#define SYSTIMER_TARGET2_HI_S  0
+
+#define SYSTIMER_TARGET2_LO_REG          (DR_REG_SYSTIMER_BASE + 0x30)
+/* SYSTIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget2 low 32 bits.*/
+#define SYSTIMER_TARGET2_LO    0xFFFFFFFF
+#define SYSTIMER_TARGET2_LO_M  ((SYSTIMER_TARGET2_LO_V)<<(SYSTIMER_TARGET2_LO_S))
+#define SYSTIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET2_LO_S  0
+
+#define SYSTIMER_TARGET0_CONF_REG          (DR_REG_SYSTIMER_BASE + 0x34)
+/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare.*/
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x1
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+/* SYSTIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target0 to period mode.*/
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x1
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/* SYSTIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target0 period.*/
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_M  ((SYSTIMER_TARGET0_PERIOD_V)<<(SYSTIMER_TARGET0_PERIOD_S))
+#define SYSTIMER_TARGET0_PERIOD_V  0x3FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_S  0
+
+#define SYSTIMER_TARGET1_CONF_REG          (DR_REG_SYSTIMER_BASE + 0x38)
+/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare.*/
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x1
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+/* SYSTIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target1 to period mode.*/
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x1
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/* SYSTIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target1 period.*/
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_M  ((SYSTIMER_TARGET1_PERIOD_V)<<(SYSTIMER_TARGET1_PERIOD_S))
+#define SYSTIMER_TARGET1_PERIOD_V  0x3FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_S  0
+
+#define SYSTIMER_TARGET2_CONF_REG          (DR_REG_SYSTIMER_BASE + 0x3C)
+/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare.*/
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x1
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+/* SYSTIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target2 to period mode.*/
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x1
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/* SYSTIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target2 period.*/
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_M  ((SYSTIMER_TARGET2_PERIOD_V)<<(SYSTIMER_TARGET2_PERIOD_S))
+#define SYSTIMER_TARGET2_PERIOD_V  0x3FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_S  0
+
+#define SYSTIMER_UNIT0_VALUE_HI_REG          (DR_REG_SYSTIMER_BASE + 0x40)
+/* SYSTIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer read value high 20bits.*/
+#define SYSTIMER_UNIT0_VALUE_HI    0x000FFFFF
+#define SYSTIMER_UNIT0_VALUE_HI_M  ((SYSTIMER_UNIT0_VALUE_HI_V)<<(SYSTIMER_UNIT0_VALUE_HI_S))
+#define SYSTIMER_UNIT0_VALUE_HI_V  0xFFFFF
+#define SYSTIMER_UNIT0_VALUE_HI_S  0
+
+#define SYSTIMER_UNIT0_VALUE_LO_REG          (DR_REG_SYSTIMER_BASE + 0x44)
+/* SYSTIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer read value low 32bits.*/
+#define SYSTIMER_UNIT0_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_UNIT0_VALUE_LO_M  ((SYSTIMER_UNIT0_VALUE_LO_V)<<(SYSTIMER_UNIT0_VALUE_LO_S))
+#define SYSTIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_UNIT0_VALUE_LO_S  0
+
+#define SYSTIMER_UNIT1_VALUE_HI_REG          (DR_REG_SYSTIMER_BASE + 0x48)
+/* SYSTIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer read value high 20bits.*/
+#define SYSTIMER_UNIT1_VALUE_HI    0x000FFFFF
+#define SYSTIMER_UNIT1_VALUE_HI_M  ((SYSTIMER_UNIT1_VALUE_HI_V)<<(SYSTIMER_UNIT1_VALUE_HI_S))
+#define SYSTIMER_UNIT1_VALUE_HI_V  0xFFFFF
+#define SYSTIMER_UNIT1_VALUE_HI_S  0
+
+#define SYSTIMER_UNIT1_VALUE_LO_REG          (DR_REG_SYSTIMER_BASE + 0x4C)
+/* SYSTIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer read value low 32bits.*/
+#define SYSTIMER_UNIT1_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_UNIT1_VALUE_LO_M  ((SYSTIMER_UNIT1_VALUE_LO_V)<<(SYSTIMER_UNIT1_VALUE_LO_S))
+#define SYSTIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_UNIT1_VALUE_LO_S  0
+
+#define SYSTIMER_COMP0_LOAD_REG          (DR_REG_SYSTIMER_BASE + 0x50)
+/* SYSTIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp0 sync enable signal.*/
+#define SYSTIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_COMP0_LOAD_M  (BIT(0))
+#define SYSTIMER_COMP0_LOAD_V  0x1
+#define SYSTIMER_COMP0_LOAD_S  0
+
+#define SYSTIMER_COMP1_LOAD_REG          (DR_REG_SYSTIMER_BASE + 0x54)
+/* SYSTIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp1 sync enable signal.*/
+#define SYSTIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_COMP1_LOAD_M  (BIT(0))
+#define SYSTIMER_COMP1_LOAD_V  0x1
+#define SYSTIMER_COMP1_LOAD_S  0
+
+#define SYSTIMER_COMP2_LOAD_REG          (DR_REG_SYSTIMER_BASE + 0x58)
+/* SYSTIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp2 sync enable signal.*/
+#define SYSTIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_COMP2_LOAD_M  (BIT(0))
+#define SYSTIMER_COMP2_LOAD_V  0x1
+#define SYSTIMER_COMP2_LOAD_S  0
+
+#define SYSTIMER_UNIT0_LOAD_REG          (DR_REG_SYSTIMER_BASE + 0x5C)
+/* SYSTIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer unit0 sync enable signal.*/
+#define SYSTIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_UNIT0_LOAD_M  (BIT(0))
+#define SYSTIMER_UNIT0_LOAD_V  0x1
+#define SYSTIMER_UNIT0_LOAD_S  0
+
+#define SYSTIMER_UNIT1_LOAD_REG          (DR_REG_SYSTIMER_BASE + 0x60)
+/* SYSTIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer unit1 sync enable signal.*/
+#define SYSTIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_UNIT1_LOAD_M  (BIT(0))
+#define SYSTIMER_UNIT1_LOAD_V  0x1
+#define SYSTIMER_UNIT1_LOAD_S  0
+
+#define SYSTIMER_INT_ENA_REG          (DR_REG_SYSTIMER_BASE + 0x64)
+/* SYSTIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 enable.*/
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_V  0x1
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+/* SYSTIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 enable.*/
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_V  0x1
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/* SYSTIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 enable.*/
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_V  0x1
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+
+#define SYSTIMER_INT_RAW_REG          (DR_REG_SYSTIMER_BASE + 0x68)
+/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 raw.*/
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_V  0x1
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 raw.*/
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_V  0x1
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 raw.*/
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_V  0x1
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+
+#define SYSTIMER_INT_CLR_REG          (DR_REG_SYSTIMER_BASE + 0x6C)
+/* SYSTIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 clear.*/
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_V  0x1
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+/* SYSTIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 clear.*/
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_V  0x1
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/* SYSTIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 clear.*/
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_V  0x1
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+
+#define SYSTIMER_INT_ST_REG          (DR_REG_SYSTIMER_BASE + 0x70)
+/* SYSTIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 status.*/
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_V  0x1
+#define SYSTIMER_TARGET2_INT_ST_S  2
+/* SYSTIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 status.*/
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_V  0x1
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/* SYSTIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 status.*/
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_V  0x1
+#define SYSTIMER_TARGET0_INT_ST_S  0
+
+#define SYSTIMER_DATE_REG          (DR_REG_SYSTIMER_BASE + 0xFC)
+/* SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */
+/*description: systimer register version.*/
+#define SYSTIMER_DATE    0xFFFFFFFF
+#define SYSTIMER_DATE_M  ((SYSTIMER_DATE_V)<<(SYSTIMER_DATE_S))
+#define SYSTIMER_DATE_V  0xFFFFFFFF
+#define SYSTIMER_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/systimer_struct.h

@@ -0,0 +1,381 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Configuration Register */
+/** Type of conf register
+ *  SYSTIMER_CONF.
+ */
+typedef union {
+    struct {
+        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
+         *  systimer clock force on
+         */
+        uint32_t systimer_clk_fo: 1;
+        uint32_t reserved_1: 21;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en: 1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en: 1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en: 1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en: 1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en: 1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en: 1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en: 1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en: 1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en: 1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+/** Type of unit_op register
+ *  SYSTIMER_UNIT_OP.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  reg_timer_unit0_value_valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit0
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved_32: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 32 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+/** Type of target register
+ *  SYSTIMER_TARGET.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 32 bit
+             */
+            uint32_t timer_target_hi: 20;
+
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+/** Type of target_conf register
+ *  SYSTIMER_TARGET_CONF.
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+/** Type of unit_value_hi register
+ *  SYSTIMER_UNIT_VALUE_HI.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of comp_load register
+ *  SYSTIMER_COMP_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp load value
+         */
+        uint32_t timer_comp_load: 1;
+
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+/** Interrupt Register */
+/** Type of int_ena register
+ *  SYSTIMER_INT_ENA.
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena: 1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena: 1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena: 1;
+
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  SYSTIMER_INT_RAW.
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw: 1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw: 1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw: 1;
+
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  SYSTIMER_INT_CLR.
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr: 1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr: 1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr: 1;
+
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  SYSTIMER_INT_ST.
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_target0_int_st
+         */
+        uint32_t target0_int_st: 1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_target1_int_st
+         */
+        uint32_t target1_int_st: 1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  reg_target2_int_st
+         */
+        uint32_t target2_int_st: 1;
+
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** Version Register */
+/** Type of date register
+ *  SYSTIMER_DATE.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33579377;
+         *  reg_date
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    uint32_t reserved_074;
+    uint32_t reserved_078;
+    uint32_t reserved_07c;
+    uint32_t reserved_080;
+    uint32_t reserved_084;
+    uint32_t reserved_088;
+    uint32_t reserved_08c;
+    uint32_t reserved_090;
+    uint32_t reserved_094;
+    uint32_t reserved_098;
+    uint32_t reserved_09c;
+    uint32_t reserved_0a0;
+    uint32_t reserved_0a4;
+    uint32_t reserved_0a8;
+    uint32_t reserved_0ac;
+    uint32_t reserved_0b0;
+    uint32_t reserved_0b4;
+    uint32_t reserved_0b8;
+    uint32_t reserved_0bc;
+    uint32_t reserved_0c0;
+    uint32_t reserved_0c4;
+    uint32_t reserved_0c8;
+    uint32_t reserved_0cc;
+    uint32_t reserved_0d0;
+    uint32_t reserved_0d4;
+    uint32_t reserved_0d8;
+    uint32_t reserved_0dc;
+    uint32_t reserved_0e0;
+    uint32_t reserved_0e4;
+    uint32_t reserved_0e8;
+    uint32_t reserved_0ec;
+    uint32_t reserved_0f0;
+    uint32_t reserved_0f4;
+    uint32_t reserved_0f8;
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/timer_group_reg.h

@@ -0,0 +1,580 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
+
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
+#define TIMG_WDT_RESET_LENGTH_100_NS    0
+#define TIMG_WDT_RESET_LENGTH_200_NS    1
+#define TIMG_WDT_RESET_LENGTH_300_NS    2
+#define TIMG_WDT_RESET_LENGTH_400_NS    3
+#define TIMG_WDT_RESET_LENGTH_500_NS    4
+#define TIMG_WDT_RESET_LENGTH_800_NS    5
+#define TIMG_WDT_RESET_LENGTH_1600_NS   6
+#define TIMG_WDT_RESET_LENGTH_3200_NS   7
+
+/** TIMG_T0CONFIG_REG register
+ *  Timer 0 configuration register
+ */
+#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
+/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
+ *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
+ *  clock of timer group.
+ */
+#define TIMG_T0_USE_XTAL    (BIT(9))
+#define TIMG_T0_USE_XTAL_M  (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
+#define TIMG_T0_USE_XTAL_V  0x00000001U
+#define TIMG_T0_USE_XTAL_S  9
+/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  When set, the alarm is enabled. This bit is automatically cleared once an
+ *  alarm occurs.
+ */
+#define TIMG_T0_ALARM_EN    (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
+#define TIMG_T0_ALARM_EN_V  0x00000001U
+#define TIMG_T0_ALARM_EN_S  10
+/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  When set, Timer 0 's clock divider counter will be reset.
+ */
+#define TIMG_T0_DIVCNT_RST    (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
+#define TIMG_T0_DIVCNT_RST_V  0x00000001U
+#define TIMG_T0_DIVCNT_RST_S  12
+/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Timer 0 clock (T0_clk) prescaler value.
+ */
+#define TIMG_T0_DIVIDER    0x0000FFFFU
+#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
+#define TIMG_T0_DIVIDER_V  0x0000FFFFU
+#define TIMG_T0_DIVIDER_S  13
+/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  When set, timer 0 auto-reload at alarm is enabled.
+ */
+#define TIMG_T0_AUTORELOAD    (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
+#define TIMG_T0_AUTORELOAD_V  0x00000001U
+#define TIMG_T0_AUTORELOAD_S  29
+/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  When set, the timer 0 time-base counter will increment every clock tick. When
+ *  cleared, the timer 0 time-base counter will decrement.
+ */
+#define TIMG_T0_INCREASE    (BIT(30))
+#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
+#define TIMG_T0_INCREASE_V  0x00000001U
+#define TIMG_T0_INCREASE_S  30
+/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, the timer 0 time-base counter is enabled.
+ */
+#define TIMG_T0_EN    (BIT(31))
+#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
+#define TIMG_T0_EN_V  0x00000001U
+#define TIMG_T0_EN_S  31
+
+/** TIMG_T0LO_REG register
+ *  Timer 0 current value, low 32 bits
+ */
+#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
+/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
+ *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
+ *  of timer 0 can be read here.
+ */
+#define TIMG_T0_LO    0xFFFFFFFFU
+#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
+#define TIMG_T0_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LO_S  0
+
+/** TIMG_T0HI_REG register
+ *  Timer $x current value, high 22 bits
+ */
+#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
+/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
+ *  After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
+ *  of timer $x can be read here.
+ */
+#define TIMG_T0_HI    0x003FFFFFU
+#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
+#define TIMG_T0_HI_V  0x003FFFFFU
+#define TIMG_T0_HI_S  0
+
+/** TIMG_T0UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
+ */
+#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
+/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
+ */
+#define TIMG_T0_UPDATE    (BIT(31))
+#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
+#define TIMG_T0_UPDATE_V  0x00000001U
+#define TIMG_T0_UPDATE_S  31
+
+/** TIMG_T0ALARMLO_REG register
+ *  Timer $x alarm value, low 32 bits
+ */
+#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
+/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Timer $x alarm trigger time-base counter value, low 32 bits.
+ */
+#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T0_ALARM_LO_S  0
+
+/** TIMG_T0ALARMHI_REG register
+ *  Timer $x alarm value, high bits
+ */
+#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
+/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Timer $x alarm trigger time-base counter value, high 22 bits.
+ */
+#define TIMG_T0_ALARM_HI    0x003FFFFFU
+#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
+#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T0_ALARM_HI_S  0
+
+/** TIMG_T0LOADLO_REG register
+ *  Timer $x reload value, low 32 bits
+ */
+#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
+/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Low 32 bits of the value that a reload will load onto timer $x time-base
+ *  Counter.
+ */
+#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_LO_S  0
+
+/** TIMG_T0LOADHI_REG register
+ *  Timer $x reload value, high 22 bits
+ */
+#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
+/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  High 22 bits of the value that a reload will load onto timer $x time-base
+ *  counter.
+ */
+#define TIMG_T0_LOAD_HI    0x003FFFFFU
+#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
+#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T0_LOAD_HI_S  0
+
+/** TIMG_T0LOAD_REG register
+ *  Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
+ */
+#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
+/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
+ *
+ *  Write any value to trigger a timer $x time-base counter reload.
+ */
+#define TIMG_T0_LOAD    0xFFFFFFFFU
+#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
+#define TIMG_T0_LOAD_V  0xFFFFFFFFU
+#define TIMG_T0_LOAD_S  0
+
+/** TIMG_WDTCONFIG0_REG register
+ *  Watchdog timer configuration register
+ */
+#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
+/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
+ *  WDT reset CPU enable.
+ */
+#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
+ *  When set, Flash boot protection is enabled.
+ */
+#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
+ *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
+ *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+ *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+ */
+#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
+ *  choose WDT clock:0-apb_clk; 1-xtal_clk.
+ */
+#define TIMG_WDT_USE_XTAL    (BIT(21))
+#define TIMG_WDT_USE_XTAL_M  (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
+#define TIMG_WDT_USE_XTAL_V  0x00000001U
+#define TIMG_WDT_USE_XTAL_S  21
+/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
+ *  update the WDT configuration registers
+ */
+#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
+ *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG3    0x00000003U
+#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
+#define TIMG_WDT_STG3_V  0x00000003U
+#define TIMG_WDT_STG3_S  23
+/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
+ *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG2    0x00000003U
+#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
+#define TIMG_WDT_STG2_V  0x00000003U
+#define TIMG_WDT_STG2_S  25
+/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
+ *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG1    0x00000003U
+#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
+#define TIMG_WDT_STG1_V  0x00000003U
+#define TIMG_WDT_STG1_S  27
+/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
+ *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+ */
+#define TIMG_WDT_STG0    0x00000003U
+#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
+#define TIMG_WDT_STG0_V  0x00000003U
+#define TIMG_WDT_STG0_S  29
+/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
+ *  When set, MWDT is enabled.
+ */
+#define TIMG_WDT_EN    (BIT(31))
+#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
+#define TIMG_WDT_EN_V  0x00000001U
+#define TIMG_WDT_EN_S  31
+
+/** TIMG_WDTCONFIG1_REG register
+ *  Watchdog timer prescaler register
+ */
+#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
+/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
+ *  When set, WDT 's clock divider counter will be reset.
+ */
+#define TIMG_WDT_DIVCNT_RST    (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
+#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
+#define TIMG_WDT_DIVCNT_RST_S  0
+/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
+ *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+ *  TIMG_WDT_CLK_PRESCALE.
+ */
+#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
+#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+/** TIMG_WDTCONFIG2_REG register
+ *  Watchdog timer stage 0 timeout value
+ */
+#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
+/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
+ *  Stage 0 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG0_HOLD_S  0
+
+/** TIMG_WDTCONFIG3_REG register
+ *  Watchdog timer stage 1 timeout value
+ */
+#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
+/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
+ *  Stage 1 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG1_HOLD_S  0
+
+/** TIMG_WDTCONFIG4_REG register
+ *  Watchdog timer stage 2 timeout value
+ */
+#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
+/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 2 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG2_HOLD_S  0
+
+/** TIMG_WDTCONFIG5_REG register
+ *  Watchdog timer stage 3 timeout value
+ */
+#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
+/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
+ *  Stage 3 timeout value, in MWDT clock cycles.
+ */
+#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
+#define TIMG_WDT_STG3_HOLD_S  0
+
+/** TIMG_WDTFEED_REG register
+ *  Write to feed the watchdog timer
+ */
+#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
+/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to feed the MWDT. (WO)
+ */
+#define TIMG_WDT_FEED    0xFFFFFFFFU
+#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
+#define TIMG_WDT_FEED_V  0xFFFFFFFFU
+#define TIMG_WDT_FEED_S  0
+
+/** TIMG_WDTWPROTECT_REG register
+ *  Watchdog write protect register
+ */
+#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
+/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ *  If the register contains a different value than its reset value, write
+ *  protection is enabled.
+ */
+#define TIMG_WDT_WKEY    0xFFFFFFFFU
+#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
+#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
+#define TIMG_WDT_WKEY_S  0
+
+/** TIMG_RTCCALICFG_REG register
+ *  RTC calibration configure register
+ */
+#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
+/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
+#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
+ *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+ */
+#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
+#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_RDY    (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
+#define TIMG_RTC_CALI_RDY_V  0x00000001U
+#define TIMG_RTC_CALI_RDY_S  15
+/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_MAX    0x00007FFFU
+#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
+#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
+#define TIMG_RTC_CALI_MAX_S  16
+/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_START    (BIT(31))
+#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
+#define TIMG_RTC_CALI_START_V  0x00000001U
+#define TIMG_RTC_CALI_START_S  31
+
+/** TIMG_RTCCALICFG1_REG register
+ *  RTC calibration configure1 register
+ */
+#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
+/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
+ *  Reserved
+ */
+#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
+#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_VALUE_S  7
+
+/** TIMG_INT_ENA_TIMERS_REG register
+ *  Interrupt enable bits
+ */
+#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
+/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ENA    (BIT(0))
+#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
+#define TIMG_T0_INT_ENA_V  0x00000001U
+#define TIMG_T0_INT_ENA_S  0
+/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ENA    (BIT(1))
+#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
+#define TIMG_WDT_INT_ENA_V  0x00000001U
+#define TIMG_WDT_INT_ENA_S  1
+
+/** TIMG_INT_RAW_TIMERS_REG register
+ *  Raw interrupt status
+ */
+#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
+/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_RAW    (BIT(0))
+#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
+#define TIMG_T0_INT_RAW_V  0x00000001U
+#define TIMG_T0_INT_RAW_S  0
+/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_RAW    (BIT(1))
+#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
+#define TIMG_WDT_INT_RAW_V  0x00000001U
+#define TIMG_WDT_INT_RAW_S  1
+
+/** TIMG_INT_ST_TIMERS_REG register
+ *  Masked interrupt status
+ */
+#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
+/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_ST    (BIT(0))
+#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
+#define TIMG_T0_INT_ST_V  0x00000001U
+#define TIMG_T0_INT_ST_S  0
+/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_ST    (BIT(1))
+#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
+#define TIMG_WDT_INT_ST_V  0x00000001U
+#define TIMG_WDT_INT_ST_S  1
+
+/** TIMG_INT_CLR_TIMERS_REG register
+ *  Interrupt clear bits
+ */
+#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
+/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the TIMG_T$x_INT interrupt.
+ */
+#define TIMG_T0_INT_CLR    (BIT(0))
+#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
+#define TIMG_T0_INT_CLR_V  0x00000001U
+#define TIMG_T0_INT_CLR_S  0
+/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the TIMG_WDT_INT interrupt.
+ */
+#define TIMG_WDT_INT_CLR    (BIT(1))
+#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
+#define TIMG_WDT_INT_CLR_V  0x00000001U
+#define TIMG_WDT_INT_CLR_S  1
+
+/** TIMG_RTCCALICFG2_REG register
+ *  Timer group calibration register
+ */
+#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
+/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
+ *  RTC calibration timeout indicator
+ */
+#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
+#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
+ *  Cycles that release calibration timeout reset
+ */
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
+ *  Threshold value for the RTC calibration timer. If the calibration timer's value
+ *  exceeds this threshold, a timeout is triggered.
+ */
+#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+
+/** TIMG_NTIMERS_DATE_REG register
+ *  Timer version control register
+ */
+#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
+/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
+ *  Timer version control register
+ */
+#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
+#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
+#define TIMG_NTIMGS_DATE_S  0
+
+/** TIMG_REGCLK_REG register
+ *  Timer group clock gate register
+ */
+#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
+/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
+ *  enable WDT's clock
+ */
+#define TIMG_WDT_CLK_IS_ACTIVE    (BIT(29))
+#define TIMG_WDT_CLK_IS_ACTIVE_M  (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
+#define TIMG_WDT_CLK_IS_ACTIVE_V  0x00000001U
+#define TIMG_WDT_CLK_IS_ACTIVE_S  29
+/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
+ *  enable Timer $x's clock
+ */
+#define TIMG_TIMER_CLK_IS_ACTIVE    (BIT(30))
+#define TIMG_TIMER_CLK_IS_ACTIVE_M  (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
+#define TIMG_TIMER_CLK_IS_ACTIVE_V  0x00000001U
+#define TIMG_TIMER_CLK_IS_ACTIVE_S  30
+/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+ *  Registers can not be read or written to by software.
+ */
+#define TIMG_CLK_EN    (BIT(31))
+#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
+#define TIMG_CLK_EN_V  0x00000001U
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/timer_group_struct.h

@@ -0,0 +1,561 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: tx Control and configuration registers */
+/** Type of txconfig register
+ *  Timer x configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** tx_use_xtal : R/W; bitpos: [9]; default: 0;
+         *  1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
+         *  clock of timer group.
+         */
+        uint32_t tx_use_xtal:1;
+        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
+         *  When set, the alarm is enabled. This bit is automatically cleared once an
+         *  alarm occurs.
+         */
+        uint32_t tx_alarm_en:1;
+        uint32_t reserved_11:1;
+        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
+         *  When set, Timer x 's clock divider counter will be reset.
+         */
+        uint32_t tx_divcnt_rst:1;
+        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
+         *  Timer x clock (Tx_clk) prescaler value.
+         */
+        uint32_t tx_divider:16;
+        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
+         *  When set, timer x auto-reload at alarm is enabled.
+         */
+        uint32_t tx_autoreload:1;
+        /** tx_increase : R/W; bitpos: [30]; default: 1;
+         *  When set, the timer x time-base counter will increment every clock tick. When
+         *  cleared, the timer x time-base counter will decrement.
+         */
+        uint32_t tx_increase:1;
+        /** tx_en : R/W; bitpos: [31]; default: 0;
+         *  When set, the timer x time-base counter is enabled.
+         */
+        uint32_t tx_en:1;
+    };
+    uint32_t val;
+} timg_txconfig_reg_t;
+
+/** Type of txlo register
+ *  Timer x current value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_lo : RO; bitpos: [31:0]; default: 0;
+         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
+         *  of timer x can be read here.
+         */
+        uint32_t tx_lo:32;
+    };
+    uint32_t val;
+} timg_txlo_reg_t;
+
+/** Type of txhi register
+ *  Timer $x current value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_hi : RO; bitpos: [21:0]; default: 0;
+         *  After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
+         *  of timer $x can be read here.
+         */
+        uint32_t tx_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txhi_reg_t;
+
+/** Type of txupdate register
+ *  Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
+         *  After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
+         */
+        uint32_t tx_update:1;
+    };
+    uint32_t val;
+} timg_txupdate_reg_t;
+
+/** Type of txalarmlo register
+ *  Timer $x alarm value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Timer $x alarm trigger time-base counter value, low 32 bits.
+         */
+        uint32_t tx_alarm_lo:32;
+    };
+    uint32_t val;
+} timg_txalarmlo_reg_t;
+
+/** Type of txalarmhi register
+ *  Timer $x alarm value, high bits
+ */
+typedef union {
+    struct {
+        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
+         *  Timer $x alarm trigger time-base counter value, high 22 bits.
+         */
+        uint32_t tx_alarm_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txalarmhi_reg_t;
+
+/** Type of txloadlo register
+ *  Timer $x reload value, low 32 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
+         *  Low 32 bits of the value that a reload will load onto timer $x time-base
+         *  Counter.
+         */
+        uint32_t tx_load_lo:32;
+    };
+    uint32_t val;
+} timg_txloadlo_reg_t;
+
+/** Type of txloadhi register
+ *  Timer $x reload value, high 22 bits
+ */
+typedef union {
+    struct {
+        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
+         *  High 22 bits of the value that a reload will load onto timer $x time-base
+         *  counter.
+         */
+        uint32_t tx_load_hi:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} timg_txloadhi_reg_t;
+
+/** Type of txload register
+ *  Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
+ */
+typedef union {
+    struct {
+        /** tx_load : WT; bitpos: [31:0]; default: 0;
+         *
+         *  Write any value to trigger a timer $x time-base counter reload.
+         */
+        uint32_t tx_load:32;
+    };
+    uint32_t val;
+} timg_txload_reg_t;
+
+
+/** Group: WDT Control and configuration registers */
+/** Type of wdtconfig0 register
+ *  Watchdog timer configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_appcpu_reset_en:1;
+        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
+         *  WDT reset CPU enable.
+         */
+        uint32_t wdt_procpu_reset_en:1;
+        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
+         *  When set, Flash boot protection is enabled.
+         */
+        uint32_t wdt_flashboot_mod_en:1;
+        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
+         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_sys_reset_length:3;
+        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
+         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
+         */
+        uint32_t wdt_cpu_reset_length:3;
+        /** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
+         *  choose WDT clock:0-apb_clk; 1-xtal_clk.
+         */
+        uint32_t wdt_use_xtal:1;
+        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
+         *  update the WDT configuration registers
+         */
+        uint32_t wdt_conf_update_en:1;
+        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
+         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg3:2;
+        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
+         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg2:2;
+        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
+         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg1:2;
+        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
+         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+         */
+        uint32_t wdt_stg0:2;
+        /** wdt_en : R/W; bitpos: [31]; default: 0;
+         *  When set, MWDT is enabled.
+         */
+        uint32_t wdt_en:1;
+    };
+    uint32_t val;
+} timg_wdtconfig0_reg_t;
+
+/** Type of wdtconfig1 register
+ *  Watchdog timer prescaler register
+ */
+typedef union {
+    struct {
+        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
+         *  When set, WDT 's clock divider counter will be reset.
+         */
+        uint32_t wdt_divcnt_rst:1;
+        uint32_t reserved_1:15;
+        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
+         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+         *  TIMG_WDT_CLK_PRESCALE.
+         */
+        uint32_t wdt_clk_prescale:16;
+    };
+    uint32_t val;
+} timg_wdtconfig1_reg_t;
+
+/** Type of wdtconfig2 register
+ *  Watchdog timer stage 0 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
+         *  Stage 0 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig2_reg_t;
+
+/** Type of wdtconfig3 register
+ *  Watchdog timer stage 1 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
+         *  Stage 1 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig3_reg_t;
+
+/** Type of wdtconfig4 register
+ *  Watchdog timer stage 2 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 2 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig4_reg_t;
+
+/** Type of wdtconfig5 register
+ *  Watchdog timer stage 3 timeout value
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
+         *  Stage 3 timeout value, in MWDT clock cycles.
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} timg_wdtconfig5_reg_t;
+
+/** Type of wdtfeed register
+ *  Write to feed the watchdog timer
+ */
+typedef union {
+    struct {
+        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
+         *  Write any value to feed the MWDT. (WO)
+         */
+        uint32_t wdt_feed:32;
+    };
+    uint32_t val;
+} timg_wdtfeed_reg_t;
+
+/** Type of wdtwprotect register
+ *  Watchdog write protect register
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
+         *  If the register contains a different value than its reset value, write
+         *  protection is enabled.
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} timg_wdtwprotect_reg_t;
+
+
+/** Group: RTC CALI Control and configuration registers */
+/** Type of rtccalicfg register
+ *  RTC calibration configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t rtc_cali_start_cycling:1;
+        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
+         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         */
+        uint32_t rtc_cali_clk_sel:2;
+        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t rtc_cali_rdy:1;
+        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
+         *  Reserved
+         */
+        uint32_t rtc_cali_max:15;
+        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t rtc_cali_start:1;
+    };
+    uint32_t val;
+} timg_rtccalicfg_reg_t;
+
+/** Type of rtccalicfg1 register
+ *  RTC calibration configure1 register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t rtc_cali_cycling_data_vld:1;
+        uint32_t reserved_1:6;
+        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
+         *  Reserved
+         */
+        uint32_t rtc_cali_value:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg1_reg_t;
+
+/** Type of rtccalicfg2 register
+ *  Timer group calibration register
+ */
+typedef union {
+    struct {
+        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
+         *  RTC calibration timeout indicator
+         */
+        uint32_t rtc_cali_timeout:1;
+        uint32_t reserved_1:2;
+        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
+         *  Cycles that release calibration timeout reset
+         */
+        uint32_t rtc_cali_timeout_rst_cnt:4;
+        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
+         *  Threshold value for the RTC calibration timer. If the calibration timer's value
+         *  exceeds this threshold, a timeout is triggered.
+         */
+        uint32_t rtc_cali_timeout_thres:25;
+    };
+    uint32_t val;
+} timg_rtccalicfg2_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_ena_timers register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** tx_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t tx_int_ena:1;
+        /** wdt_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} timg_int_ena_timers_reg_t;
+
+/** Type of int_raw_timers register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** tx_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t tx_int_raw:1;
+        /** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} timg_int_raw_timers_reg_t;
+
+/** Type of int_st_timers register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** tx_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
+         */
+        uint32_t tx_int_st:1;
+        /** wdt_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} timg_int_st_timers_reg_t;
+
+/** Type of int_clr_timers register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** tx_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the TIMG_T$x_INT interrupt.
+         */
+        uint32_t tx_int_clr:1;
+        /** wdt_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the TIMG_WDT_INT interrupt.
+         */
+        uint32_t wdt_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} timg_int_clr_timers_reg_t;
+
+
+/** Group: Version register */
+/** Type of ntimers_date register
+ *  Timer version control register
+ */
+typedef union {
+    struct {
+        /** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
+         *  Timer version control register
+         */
+        uint32_t ntimgs_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} timg_ntimers_date_reg_t;
+
+
+/** Group: Clock configuration registers */
+/** Type of regclk register
+ *  Timer group clock gate register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
+         *  enable WDT's clock
+         */
+        uint32_t wdt_clk_is_active:1;
+        /** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
+         *  enable Timer $x's clock
+         */
+        uint32_t timer_clk_is_active:1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
+         *  Registers can not be read or written to by software.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} timg_regclk_reg_t;
+
+typedef struct {
+    volatile timg_txconfig_reg_t config;
+    volatile timg_txlo_reg_t lo;
+    volatile timg_txhi_reg_t hi;
+    volatile timg_txupdate_reg_t update;
+    volatile timg_txalarmlo_reg_t alarmlo;
+    volatile timg_txalarmhi_reg_t alarmhi;
+    volatile timg_txloadlo_reg_t loadlo;
+    volatile timg_txloadhi_reg_t loadhi;
+    volatile timg_txload_reg_t load;
+} timg_hwtimer_reg_t;
+
+
+typedef struct timg_dev_t {
+    volatile timg_hwtimer_reg_t hw_timer[1];
+    uint32_t reserved_024[9];
+    volatile timg_wdtconfig0_reg_t wdtconfig0;
+    volatile timg_wdtconfig1_reg_t wdtconfig1;
+    volatile timg_wdtconfig2_reg_t wdtconfig2;
+    volatile timg_wdtconfig3_reg_t wdtconfig3;
+    volatile timg_wdtconfig4_reg_t wdtconfig4;
+    volatile timg_wdtconfig5_reg_t wdtconfig5;
+    volatile timg_wdtfeed_reg_t wdtfeed;
+    volatile timg_wdtwprotect_reg_t wdtwprotect;
+    volatile timg_rtccalicfg_reg_t rtccalicfg;
+    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
+    volatile timg_int_ena_timers_reg_t int_ena_timers;
+    volatile timg_int_raw_timers_reg_t int_raw_timers;
+    volatile timg_int_st_timers_reg_t int_st_timers;
+    volatile timg_int_clr_timers_reg_t int_clr_timers;
+    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
+    uint32_t reserved_084[29];
+    volatile timg_ntimers_date_reg_t ntimers_date;
+    volatile timg_regclk_reg_t regclk;
+} timg_dev_t;
+
+extern timg_dev_t TIMERG0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp8684/include/soc/uart_channel.h

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_UART_CHANNEL_H
+#define _SOC_UART_CHANNEL_H
+
+//UART channels
+#define UART_GPIO1_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  1
+#define UART_GPIO3_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  3
+#define UART_GPIO19_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  19
+#define UART_GPIO22_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  22
+
+#define UART_TXD_GPIO1_DIRECT_CHANNEL   UART_GPIO1_DIRECT_CHANNEL
+#define UART_RXD_GPIO3_DIRECT_CHANNEL   UART_GPIO3_DIRECT_CHANNEL
+#define UART_CTS_GPIO19_DIRECT_CHANNEL  UART_GPIO19_DIRECT_CHANNEL
+#define UART_RTS_GPIO22_DIRECT_CHANNEL  UART_GPIO22_DIRECT_CHANNEL
+
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO9_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  9
+#define UART_GPIO6_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  6
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  11
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+#define UART_CTS_GPIO6_DIRECT_CHANNEL   UART_GPIO6_DIRECT_CHANNEL
+#define UART_RTS_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+
+#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_TXD_DIRECT_GPIO_NUM  17
+#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_RXD_DIRECT_GPIO_NUM  16
+#define UART_GPIO8_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_CTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO7_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_RTS_DIRECT_GPIO_NUM  7
+
+#define UART_TXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
+#define UART_RXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
+#define UART_CTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_RTS_GPIO7_DIRECT_CHANNEL   UART_GPIO7_DIRECT_CHANNEL
+
+#endif

components/soc/esp8684/include/soc/uart_pins.h

@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/io_mux_reg.h"
+
+/* Specify the number of pins for UART */
+#define SOC_UART_PINS_COUNT  (4)
+
+/* Specify the GPIO pin number for each UART signal in the IOMUX */
+#define U0RXD_GPIO_NUM 19
+#define U0TXD_GPIO_NUM 20
+#define U0RTS_GPIO_NUM (-1)
+#define U0CTS_GPIO_NUM (-1)
+
+#define U1RXD_GPIO_NUM (-1)
+#define U1TXD_GPIO_NUM (-1)
+#define U1RTS_GPIO_NUM (-1)
+#define U1CTS_GPIO_NUM (-1)
+
+/* The following defines are necessary for reconfiguring the UART
+ * to use IOMUX, at runtime. */
+#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
+#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
+/* No func for the following pins, they shall not be used */
+#define U0RTS_MUX_FUNC  (-1)
+#define U0CTS_MUX_FUNC  (-1)
+/* Same goes for UART1 */
+#define U1TXD_MUX_FUNC  (-1)
+#define U1RXD_MUX_FUNC  (-1)
+#define U1RTS_MUX_FUNC  (-1)
+#define U1CTS_MUX_FUNC  (-1)

components/soc/esp8684/include/soc/uart_reg.h

@@ -0,0 +1,1255 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: UART $n accesses FIFO via this register..*/
+#define UART_RXFIFO_RD_BYTE    0x000000FF
+#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V  0xFF
+#define UART_RXFIFO_RD_BYTE_S  0
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when input rxd edge changes more time
+s than what reg_active_threshold specifies in light sleeping mode..*/
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (BIT(19))
+#define UART_WAKEUP_INT_RAW_V  0x1
+#define UART_WAKEUP_INT_RAW_S  19
+/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the configured
+at_cmd char..*/
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when detects a clash between transmit
+ter and receiver in rs485 mode..*/
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V  0x1
+#define UART_RS485_CLASH_INT_RAW_S  17
+/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
+ror from the echo of transmitter in rs485 mode..*/
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a parity error
+from the echo of transmitter in rs485 mode..*/
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has send out all dat
+a in FIFO..*/
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (BIT(14))
+#define UART_TX_DONE_INT_RAW_V  0x1
+#define UART_TX_DONE_INT_RAW_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has kept the shortes
+t duration after sending the  last data..*/
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter completes  sending
+NULL characters, after all data in Tx-FIFO are sent..*/
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a glitch in the
+ middle of a start bit..*/
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V  0x1
+#define UART_GLITCH_DET_INT_RAW_S  11
+/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives Xoff char when
+ uart_sw_flow_con_en is set to 1..*/
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V  0x1
+#define UART_SW_XOFF_INT_RAW_S  10
+/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when
+uart_sw_flow_con_en is set to 1..*/
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (BIT(9))
+#define UART_SW_XON_INT_RAW_V  0x1
+#define UART_SW_XON_INT_RAW_S  9
+/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver takes more time than rx
+_tout_thrhd to receive a byte..*/
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a 0 after the s
+top bit..*/
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (BIT(7))
+#define UART_BRK_DET_INT_RAW_V  0x1
+#define UART_BRK_DET_INT_RAW_S  7
+/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the edge change
+ of CTSn signal..*/
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V  0x1
+#define UART_CTS_CHG_INT_RAW_S  6
+/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the edge change
+ of DSRn signal..*/
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V  0x1
+#define UART_DSR_CHG_INT_RAW_S  5
+/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives more data than
+ the FIFO can store..*/
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V  0x1
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
+ror ..*/
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V  0x1
+#define UART_FRM_ERR_INT_RAW_S  3
+/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a parity error
+in the data..*/
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V  0x1
+#define UART_PARITY_ERR_INT_RAW_S  2
+/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
+/*description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ less than what txfifo_empty_thrhd specifies ..*/
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives more data than
+ what rxfifo_full_thrhd specifies..*/
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set t
+o 1..*/
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (BIT(19))
+#define UART_WAKEUP_INT_ST_V  0x1
+#define UART_WAKEUP_INT_ST_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is se
+t to 1..*/
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set t
+o 1..*/
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V  0x1
+#define UART_RS485_CLASH_INT_ST_S  17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is se
+t to 1..*/
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V  0x1
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ set to 1..*/
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1..*/
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (BIT(14))
+#define UART_TX_DONE_INT_ST_V  0x1
+#define UART_TX_DONE_INT_ST_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
+a is set to 1..*/
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set t
+o 1..*/
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+1..*/
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V  0x1
+#define UART_GLITCH_DET_INT_ST_S  11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1..*/
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (BIT(10))
+#define UART_SW_XOFF_INT_ST_V  0x1
+#define UART_SW_XOFF_INT_ST_S  10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1..*/
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (BIT(9))
+#define UART_SW_XON_INT_ST_V  0x1
+#define UART_SW_XON_INT_ST_S  9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set t
+o 1..*/
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V  0x1
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1..*/
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (BIT(7))
+#define UART_BRK_DET_INT_ST_V  0x1
+#define UART_BRK_DET_INT_ST_S  7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1..*/
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (BIT(6))
+#define UART_CTS_CHG_INT_ST_V  0x1
+#define UART_CTS_CHG_INT_ST_S  6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1..*/
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (BIT(5))
+#define UART_DSR_CHG_INT_ST_V  0x1
+#define UART_DSR_CHG_INT_ST_S  5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+1..*/
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V  0x1
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1..*/
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (BIT(3))
+#define UART_FRM_ERR_INT_ST_V  0x1
+#define UART_FRM_ERR_INT_ST_S  3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+1..*/
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V  0x1
+#define UART_PARITY_ERR_INT_ST_S  2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is s
+et to 1..*/
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set t
+o 1..*/
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_S  0
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart_wakeup_int_st register..*/
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (BIT(19))
+#define UART_WAKEUP_INT_ENA_V  0x1
+#define UART_WAKEUP_INT_ENA_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the enable bit for at_cmd_char_det_int_st register..*/
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_clash_int_st register..*/
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V  0x1
+#define UART_RS485_CLASH_INT_ENA_S  17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register..*/
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register..*/
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_done_int_st register..*/
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (BIT(14))
+#define UART_TX_DONE_INT_ENA_V  0x1
+#define UART_TX_DONE_INT_ENA_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_idle_done_int_st register..*/
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_done_int_st register..*/
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the enable bit for glitch_det_int_st register..*/
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V  0x1
+#define UART_GLITCH_DET_INT_ENA_S  11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xoff_int_st register..*/
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V  0x1
+#define UART_SW_XOFF_INT_ENA_S  10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xon_int_st register..*/
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (BIT(9))
+#define UART_SW_XON_INT_ENA_V  0x1
+#define UART_SW_XON_INT_ENA_S  9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_tout_int_st register..*/
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the enable bit for brk_det_int_st register..*/
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (BIT(7))
+#define UART_BRK_DET_INT_ENA_V  0x1
+#define UART_BRK_DET_INT_ENA_S  7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the enable bit for cts_chg_int_st register..*/
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V  0x1
+#define UART_CTS_CHG_INT_ENA_S  6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the enable bit for dsr_chg_int_st register..*/
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V  0x1
+#define UART_DSR_CHG_INT_ENA_S  5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_ovf_int_st register..*/
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V  0x1
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the enable bit for frm_err_int_st register..*/
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V  0x1
+#define UART_FRM_ERR_INT_ENA_S  3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the enable bit for parity_err_int_st register..*/
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V  0x1
+#define UART_PARITY_ERR_INT_ENA_S  2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the enable bit for txfifo_empty_int_st register..*/
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register..*/
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the uart_wakeup_int_raw interrupt..*/
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (BIT(19))
+#define UART_WAKEUP_INT_CLR_V  0x1
+#define UART_WAKEUP_INT_CLR_S  19
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt..*/
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt..*/
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V  0x1
+#define UART_RS485_CLASH_INT_CLR_S  17
+/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt..*/
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt..*/
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_done_int_raw interrupt..*/
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (BIT(14))
+#define UART_TX_DONE_INT_CLR_V  0x1
+#define UART_TX_DONE_INT_CLR_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt..*/
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt...*/
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the glitch_det_int_raw interrupt..*/
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V  0x1
+#define UART_GLITCH_DET_INT_CLR_S  11
+/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xoff_int_raw interrupt..*/
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V  0x1
+#define UART_SW_XOFF_INT_CLR_S  10
+/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt..*/
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (BIT(9))
+#define UART_SW_XON_INT_CLR_V  0x1
+#define UART_SW_XON_INT_CLR_S  9
+/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt..*/
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the brk_det_int_raw interrupt..*/
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (BIT(7))
+#define UART_BRK_DET_INT_CLR_V  0x1
+#define UART_BRK_DET_INT_CLR_S  7
+/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the cts_chg_int_raw interrupt..*/
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V  0x1
+#define UART_CTS_CHG_INT_CLR_S  6
+/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt..*/
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V  0x1
+#define UART_DSR_CHG_INT_CLR_S  5
+/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt..*/
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V  0x1
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear frm_err_int_raw interrupt..*/
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V  0x1
+#define UART_FRM_ERR_INT_CLR_S  3
+/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear parity_err_int_raw interrupt..*/
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V  0x1
+#define UART_PARITY_ERR_INT_CLR_S  2
+/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt..*/
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt..*/
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: The decimal part of the frequency divider factor..*/
+#define UART_CLKDIV_FRAG    0x0000000F
+#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V  0xF
+#define UART_CLKDIV_FRAG_S  20
+/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2b6 ; */
+/*description: The integral part of the frequency divider factor..*/
+#define UART_CLKDIV    0x00000FFF
+#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V  0xFFF
+#define UART_CLKDIV_S  0
+
+#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable Rx signal filter..*/
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (BIT(8))
+#define UART_GLITCH_FILT_EN_V  0x1
+#define UART_GLITCH_FILT_EN_S  8
+/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
+/*description: when input pulse width is lower than this value, the pulse is ignored..*/
+#define UART_GLITCH_FILT    0x000000FF
+#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V  0xFF
+#define UART_GLITCH_FILT_S  0
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
+/*description: This bit represents the  level of the internal uart txd signal..*/
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (BIT(31))
+#define UART_TXD_V  0x1
+#define UART_TXD_S  31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart rts signal..*/
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (BIT(30))
+#define UART_RTSN_V  0x1
+#define UART_RTSN_S  30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart dtr signal..*/
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (BIT(29))
+#define UART_DTRN_V  0x1
+#define UART_DTRN_S  29
+/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
+/*description: Stores the byte number of data in Tx-FIFO..*/
+#define UART_TXFIFO_CNT    0x000003FF
+#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V  0x3FF
+#define UART_TXFIFO_CNT_S  16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: This register represent the  level value of the internal uart rxd signal..*/
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (BIT(15))
+#define UART_RXD_V  0x1
+#define UART_RXD_S  15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
+/*description: This register represent the level value of the internal uart cts signal..*/
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (BIT(14))
+#define UART_CTSN_V  0x1
+#define UART_CTSN_S  14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The register represent the level value of the internal uart dsr signal..*/
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (BIT(13))
+#define UART_DSRN_V  0x1
+#define UART_DSRN_S  13
+/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: Stores the byte number of valid data in Rx-FIFO..*/
+#define UART_RXFIFO_CNT    0x000003FF
+#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V  0x3FF
+#define UART_RXFIFO_CNT_S  0
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
+/*description: UART memory clock gate enable signal..*/
+#define UART_MEM_CLK_EN    (BIT(28))
+#define UART_MEM_CLK_EN_M  (BIT(28))
+#define UART_MEM_CLK_EN_V  0x1
+#define UART_MEM_CLK_EN_S  28
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This is the enable bit for detecting baudrate..*/
+#define UART_AUTOBAUD_EN    (BIT(27))
+#define UART_AUTOBAUD_EN_M  (BIT(27))
+#define UART_AUTOBAUD_EN_V  0x1
+#define UART_AUTOBAUD_EN_S  27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver s
+tores the data even if the  received data is wrong..*/
+#define UART_ERR_WR_MASK    (BIT(26))
+#define UART_ERR_WR_MASK_M  (BIT(26))
+#define UART_ERR_WR_MASK_V  0x1
+#define UART_ERR_WR_MASK_S  26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
+tes registers..*/
+#define UART_CLK_EN    (BIT(25))
+#define UART_CLK_EN_M  (BIT(25))
+#define UART_CLK_EN_V  0x1
+#define UART_CLK_EN_S  25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dtr signal..*/
+#define UART_DTR_INV    (BIT(24))
+#define UART_DTR_INV_M  (BIT(24))
+#define UART_DTR_INV_V  0x1
+#define UART_DTR_INV_S  24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rts signal..*/
+#define UART_RTS_INV    (BIT(23))
+#define UART_RTS_INV_M  (BIT(23))
+#define UART_RTS_INV_V  0x1
+#define UART_RTS_INV_S  23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart txd signal..*/
+#define UART_TXD_INV    (BIT(22))
+#define UART_TXD_INV_M  (BIT(22))
+#define UART_TXD_INV_V  0x1
+#define UART_TXD_INV_S  22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dsr signal..*/
+#define UART_DSR_INV    (BIT(21))
+#define UART_DSR_INV_M  (BIT(21))
+#define UART_DSR_INV_V  0x1
+#define UART_DSR_INV_S  21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart cts signal..*/
+#define UART_CTS_INV    (BIT(20))
+#define UART_CTS_INV_M  (BIT(20))
+#define UART_CTS_INV_V  0x1
+#define UART_CTS_INV_S  20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rxd signal..*/
+#define UART_RXD_INV    (BIT(19))
+#define UART_RXD_INV_M  (BIT(19))
+#define UART_RXD_INV_V  0x1
+#define UART_RXD_INV_S  19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart transmit-FIFO..*/
+#define UART_TXFIFO_RST    (BIT(18))
+#define UART_TXFIFO_RST_M  (BIT(18))
+#define UART_TXFIFO_RST_V  0x1
+#define UART_TXFIFO_RST_S  18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart receive-FIFO..*/
+#define UART_RXFIFO_RST    (BIT(17))
+#define UART_RXFIFO_RST_M  (BIT(17))
+#define UART_RXFIFO_RST_V  0x1
+#define UART_RXFIFO_RST_S  17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to enable IrDA protocol..*/
+#define UART_IRDA_EN    (BIT(16))
+#define UART_IRDA_EN_M  (BIT(16))
+#define UART_IRDA_EN_V  0x1
+#define UART_IRDA_EN_S  16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control function for transmitter..*/
+#define UART_TX_FLOW_EN    (BIT(15))
+#define UART_TX_FLOW_EN_M  (BIT(15))
+#define UART_TX_FLOW_EN_V  0x1
+#define UART_TX_FLOW_EN_S  15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart loopback test mode..*/
+#define UART_LOOPBACK    (BIT(14))
+#define UART_LOOPBACK_M  (BIT(14))
+#define UART_LOOPBACK_V  0x1
+#define UART_LOOPBACK_S  14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of IrDA receiver..*/
+#define UART_IRDA_RX_INV    (BIT(13))
+#define UART_IRDA_RX_INV_M  (BIT(13))
+#define UART_IRDA_RX_INV_V  0x1
+#define UART_IRDA_RX_INV_S  13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of  IrDA transmitter..*/
+#define UART_IRDA_TX_INV    (BIT(12))
+#define UART_IRDA_TX_INV_M  (BIT(12))
+#define UART_IRDA_TX_INV_V  0x1
+#define UART_IRDA_TX_INV_S  12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA tr
+ansmitter's 11th bit to 0..*/
+#define UART_IRDA_WCTL    (BIT(11))
+#define UART_IRDA_WCTL_M  (BIT(11))
+#define UART_IRDA_WCTL_V  0x1
+#define UART_IRDA_WCTL_S  11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the start enable bit for IrDA transmitter..*/
+#define UART_IRDA_TX_EN    (BIT(10))
+#define UART_IRDA_TX_EN_M  (BIT(10))
+#define UART_IRDA_TX_EN_V  0x1
+#define UART_IRDA_TX_EN_S  10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable IrDA loopback mode..*/
+#define UART_IRDA_DPLX    (BIT(9))
+#define UART_IRDA_DPLX_M  (BIT(9))
+#define UART_IRDA_DPLX_V  0x1
+#define UART_IRDA_DPLX_S  9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enbale transmitter to  send NULL when the process of sending dat
+a is done..*/
+#define UART_TXD_BRK    (BIT(8))
+#define UART_TXD_BRK_M  (BIT(8))
+#define UART_TXD_BRK_V  0x1
+#define UART_TXD_BRK_S  8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This register is used to configure the software dtr signal which is used in soft
+ware flow control..*/
+#define UART_SW_DTR    (BIT(7))
+#define UART_SW_DTR_M  (BIT(7))
+#define UART_SW_DTR_V  0x1
+#define UART_SW_DTR_S  7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register is used to configure the software rts signal which is used in soft
+ware flow control..*/
+#define UART_SW_RTS    (BIT(6))
+#define UART_SW_RTS_M  (BIT(6))
+#define UART_SW_RTS_V  0x1
+#define UART_SW_RTS_S  6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: This register is used to set the length of  stop bit..*/
+#define UART_STOP_BIT_NUM    0x00000003
+#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V  0x3
+#define UART_STOP_BIT_NUM_S  4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: This register is used to set the length of data..*/
+#define UART_BIT_NUM    0x00000003
+#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V  0x3
+#define UART_BIT_NUM_S  2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart parity check..*/
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (BIT(1))
+#define UART_PARITY_EN_V  0x1
+#define UART_PARITY_EN_S  1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register is used to configure the parity check mode..*/
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (BIT(0))
+#define UART_PARITY_V  0x1
+#define UART_PARITY_S  0
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: This is the enble bit for uart receiver's timeout function..*/
+#define UART_RX_TOUT_EN    (BIT(21))
+#define UART_RX_TOUT_EN_M  (BIT(21))
+#define UART_RX_TOUT_EN_V  0x1
+#define UART_RX_TOUT_EN_S  21
+/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This is the flow enable bit for UART receiver..*/
+#define UART_RX_FLOW_EN    (BIT(20))
+#define UART_RX_FLOW_EN_M  (BIT(20))
+#define UART_RX_FLOW_EN_V  0x1
+#define UART_RX_FLOW_EN_S  20
+/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/
+#define UART_RX_TOUT_FLOW_DIS    (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_V  0x1
+#define UART_RX_TOUT_FLOW_DIS_S  19
+/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Disable UART Rx data overflow detect..*/
+#define UART_DIS_RX_DAT_OVF    (BIT(18))
+#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_V  0x1
+#define UART_DIS_RX_DAT_OVF_S  18
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
+/*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le
+ss than this register value..*/
+#define UART_TXFIFO_EMPTY_THRHD    0x000001FF
+#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
+#define UART_TXFIFO_EMPTY_THRHD_S  9
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
+/*description: It will produce rxfifo_full_int interrupt when receiver receives more data than
+this register value..*/
+#define UART_RXFIFO_FULL_THRHD    0x000001FF
+#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V  0x1FF
+#define UART_RXFIFO_FULL_THRHD_S  0
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the value of the minimum duration time of the low level pul
+se. It is used in baud rate-detect process..*/
+#define UART_LOWPULSE_MIN_CNT    0x00000FFF
+#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V  0xFFF
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores  the value of the maxinum duration time for the high level
+pulse. It is used in baud rate-detect process..*/
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFF
+#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the count of rxd edge change. It is used in baud rate-detec
+t process..*/
+#define UART_RXD_EDGE_CNT    0x000003FF
+#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V  0x3FF
+#define UART_RXD_EDGE_CNT_S  0
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to send Xoff char. It is cleared by hardware automatically..*/
+#define UART_SEND_XOFF    (BIT(5))
+#define UART_SEND_XOFF_M  (BIT(5))
+#define UART_SEND_XOFF_V  0x1
+#define UART_SEND_XOFF_S  5
+/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to send Xon char. It is cleared by hardware automatically..*/
+#define UART_SEND_XON    (BIT(4))
+#define UART_SEND_XON_M  (BIT(4))
+#define UART_SEND_XON_V  0x1
+#define UART_SEND_XON_S  4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to stop the  transmitter from sending data..*/
+#define UART_FORCE_XOFF    (BIT(3))
+#define UART_FORCE_XOFF_M  (BIT(3))
+#define UART_FORCE_XOFF_V  0x1
+#define UART_FORCE_XOFF_S  3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable the transmitter to go on sending data..*/
+#define UART_FORCE_XON    (BIT(2))
+#define UART_FORCE_XON_M  (BIT(2))
+#define UART_FORCE_XON_V  0x1
+#define UART_FORCE_XON_S  2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to remove flow control char from the received data..*/
+#define UART_XONOFF_DEL    (BIT(1))
+#define UART_XONOFF_DEL_M  (BIT(1))
+#define UART_XONOFF_DEL_V  0x1
+#define UART_XONOFF_DEL_S  1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable software flow control. It is used with register sw_xon or
+ sw_xoff..*/
+#define UART_SW_FLOW_CON_EN    (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (BIT(0))
+#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_S  0
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: The uart is activated from light sleeping mode when the input rxd edge changes m
+ore times than this register value..*/
+#define UART_ACTIVE_THRESHOLD    0x000003FF
+#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V  0x3FF
+#define UART_ACTIVE_THRESHOLD_S  0
+
+#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
+/*description: This register stores the Xoff flow control char..*/
+#define UART_XOFF_CHAR    0x000000FF
+#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V  0xFF
+#define UART_XOFF_CHAR_S  9
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
+/*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl
+ow_con_en set to 1, it will send a Xoff char..*/
+#define UART_XOFF_THRESHOLD    0x000001FF
+#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V  0x1FF
+#define UART_XOFF_THRESHOLD_S  0
+
+#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
+/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
+/*description: This register stores the Xon flow control char..*/
+#define UART_XON_CHAR    0x000000FF
+#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V  0xFF
+#define UART_XON_CHAR_S  9
+/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl
+ow_con_en set to 1, it will send a Xon char..*/
+#define UART_XON_THRESHOLD    0x000001FF
+#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V  0x1FF
+#define UART_XON_THRESHOLD_S  0
+
+#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
+/*description: This register is used to configure the number of 0 to be sent after the process
+of sending data is done. It is active when txd_brk is set to 1..*/
+#define UART_TX_BRK_NUM    0x000000FF
+#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V  0xFF
+#define UART_TX_BRK_NUM_S  0
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: This register is used to configure the duration time between transfers..*/
+#define UART_TX_IDLE_NUM    0x000003FF
+#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V  0x3FF
+#define UART_TX_IDLE_NUM_S  10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: It will produce frame end signal when receiver takes more time to receive one by
+te data than this register value..*/
+#define UART_RX_IDLE_THRHD    0x000003FF
+#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V  0x3FF
+#define UART_RX_IDLE_THRHD_S  0
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4C)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: This register is used to delay the transmitter's internal data signal..*/
+#define UART_RS485_TX_DLY_NUM    0x0000000F
+#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V  0xF
+#define UART_RS485_TX_DLY_NUM_S  6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This register is used to delay the receiver's internal data signal..*/
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V  0x1
+#define UART_RS485_RX_DLY_NUM_S  5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy..*/
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (BIT(4))
+#define UART_RS485RXBY_TX_EN_V  0x1
+#define UART_RS485RXBY_TX_EN_S  4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver could receive data when the transmitter is trans
+mitting data in rs485 mode..*/
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (BIT(3))
+#define UART_RS485TX_RX_EN_V  0x1
+#define UART_RS485TX_RX_EN_S  3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit..*/
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (BIT(2))
+#define UART_DL1_EN_V  0x1
+#define UART_DL1_EN_S  2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit..*/
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (BIT(1))
+#define UART_DL0_EN_V  0x1
+#define UART_DL0_EN_S  1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to choose the rs485 mode..*/
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (BIT(0))
+#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_S  0
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the idle duration time before the first at_cm
+d is received by receiver..*/
+#define UART_PRE_IDLE_NUM    0x0000FFFF
+#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V  0xFFFF
+#define UART_PRE_IDLE_NUM_S  0
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the duration time between the last at_cmd and
+ the next data..*/
+#define UART_POST_IDLE_NUM    0x0000FFFF
+#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V  0xFFFF
+#define UART_POST_IDLE_NUM_S  0
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
+/*description: This register is used to configure the duration time between the at_cmd chars..*/
+#define UART_RX_GAP_TOUT    0x0000FFFF
+#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V  0xFFFF
+#define UART_RX_GAP_TOUT_S  0
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5C)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: This register is used to configure the num of continuous at_cmd chars received b
+y receiver..*/
+#define UART_CHAR_NUM    0x000000FF
+#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V  0xFF
+#define UART_CHAR_NUM_S  8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: This register is used to configure the content of at_cmd char..*/
+#define UART_AT_CMD_CHAR    0x000000FF
+#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V  0xFF
+#define UART_AT_CMD_CHAR_S  0
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
+/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to force power up UART memory..*/
+#define UART_MEM_FORCE_PU    (BIT(27))
+#define UART_MEM_FORCE_PU_M  (BIT(27))
+#define UART_MEM_FORCE_PU_V  0x1
+#define UART_MEM_FORCE_PU_S  27
+/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to force power down UART memory..*/
+#define UART_MEM_FORCE_PD    (BIT(26))
+#define UART_MEM_FORCE_PD_M  (BIT(26))
+#define UART_MEM_FORCE_PD_V  0x1
+#define UART_MEM_FORCE_PD_S  26
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
+/*description: This register is used to configure the threshold time that receiver takes to rec
+eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t
+akes more time to receive one byte with rx_tout_en set to 1..*/
+#define UART_RX_TOUT_THRHD    0x000003FF
+#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V  0x3FF
+#define UART_RX_TOUT_THRHD_S  16
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
+/*description: This register is used to configure the maximum amount of data that can be receiv
+ed  when hardware flow control works..*/
+#define UART_RX_FLOW_THRHD    0x000001FF
+#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V  0x1FF
+#define UART_RX_FLOW_THRHD_S  7
+/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
+/*description: This register is used to configure the amount of mem allocated for transmit-FIFO
+. The default number is 128 bytes..*/
+#define UART_TX_SIZE    0x00000007
+#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V  0x7
+#define UART_TX_SIZE_S  4
+/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
+/*description: This register is used to configure the amount of mem allocated for receive-FIFO.
+ The default number is 128 bytes..*/
+#define UART_RX_SIZE    0x00000007
+#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V  0x7
+#define UART_RX_SIZE_S  1
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
+/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx
+-FIFO_Ctrl..*/
+#define UART_TX_RADDR    0x000003FF
+#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
+#define UART_TX_RADDR_V  0x3FF
+#define UART_TX_RADDR_S  11
+/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+via APB..*/
+#define UART_APB_TX_WADDR    0x000003FF
+#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
+#define UART_APB_TX_WADDR_V  0x3FF
+#define UART_APB_TX_WADDR_S  0
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
+/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
+/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-F
+IFO. UART0 is 10'h100. UART1 is 10'h180..*/
+#define UART_RX_WADDR    0x000003FF
+#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
+#define UART_RX_WADDR_V  0x3FF
+#define UART_RX_WADDR_S  11
+/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: This register stores the offset address in RX-FIFO when software reads data from
+ Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180..*/
+#define UART_APB_RX_RADDR    0x000003FF
+#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
+#define UART_APB_RX_RADDR_V  0x3FF
+#define UART_APB_RX_RADDR_S  0
+
+#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6C)
+/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: This is the status register of transmitter..*/
+#define UART_ST_UTX_OUT    0x0000000F
+#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V  0xF
+#define UART_ST_UTX_OUT_S  4
+/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: This is the status register of receiver..*/
+#define UART_ST_URX_OUT    0x0000000F
+#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V  0xF
+#define UART_ST_URX_OUT_S  0
+
+#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the minimal input clock count between two positive edges. I
+t is used in boudrate-detect process..*/
+#define UART_POSEDGE_MIN_CNT    0x00000FFF
+#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V  0xFFF
+#define UART_POSEDGE_MIN_CNT_S  0
+
+#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the minimal input clock count between two negative edges. I
+t is used in boudrate-detect process..*/
+#define UART_NEGEDGE_MIN_CNT    0x00000FFF
+#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V  0xFFF
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
+/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Rx..*/
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (BIT(27))
+#define UART_RX_RST_CORE_V  0x1
+#define UART_RX_RST_CORE_S  27
+/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Tx..*/
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (BIT(26))
+#define UART_TX_RST_CORE_V  0x1
+#define UART_TX_RST_CORE_S  26
+/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Rx clock..*/
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (BIT(25))
+#define UART_RX_SCLK_EN_V  0x1
+#define UART_RX_SCLK_EN_S  25
+/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx clock..*/
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (BIT(24))
+#define UART_TX_SCLK_EN_V  0x1
+#define UART_TX_SCLK_EN_S  24
+/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Tx/Rx..*/
+#define UART_RST_CORE    (BIT(23))
+#define UART_RST_CORE_M  (BIT(23))
+#define UART_RST_CORE_V  0x1
+#define UART_RST_CORE_S  23
+/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx/Rx clock..*/
+#define UART_SCLK_EN    (BIT(22))
+#define UART_SCLK_EN_M  (BIT(22))
+#define UART_SCLK_EN_V  0x1
+#define UART_SCLK_EN_S  22
+/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
+/*description: UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL..*/
+#define UART_SCLK_SEL    0x00000003
+#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
+#define UART_SCLK_SEL_V  0x3
+#define UART_SCLK_SEL_S  20
+/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
+/*description: The integral part of the frequency divider factor..*/
+#define UART_SCLK_DIV_NUM    0x000000FF
+#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
+#define UART_SCLK_DIV_NUM_V  0xFF
+#define UART_SCLK_DIV_NUM_S  12
+/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
+/*description: The numerator of the frequency divider factor..*/
+#define UART_SCLK_DIV_A    0x0000003F
+#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
+#define UART_SCLK_DIV_A_V  0x3F
+#define UART_SCLK_DIV_A_S  6
+/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: The  denominator of the frequency divider factor..*/
+#define UART_SCLK_DIV_B    0x0000003F
+#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
+#define UART_SCLK_DIV_B_V  0x3F
+#define UART_SCLK_DIV_B_S  0
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7C)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
+/*description: This is the version register..*/
+#define UART_DATE    0xFFFFFFFF
+#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V  0xFFFFFFFF
+#define UART_DATE_S  0
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
+/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software write 1 would synchronize registers into UART Core clock domain and wou
+ld be cleared by hardware after synchronization is done..*/
+#define UART_UPDATE    (BIT(31))
+#define UART_UPDATE_M  (BIT(31))
+#define UART_UPDATE_V  0x1
+#define UART_UPDATE_S  31
+/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit used to select synchronize mode. 1: Registers are auto synchronized int
+o UART Core clock and UART core should be keep the same with APB clock. 0: After
+ configure registers, software needs to write 1 to UART_REG_UPDATE to synchroniz
+e registers..*/
+#define UART_HIGH_SPEED    (BIT(30))
+#define UART_HIGH_SPEED_M  (BIT(30))
+#define UART_HIGH_SPEED_V  0x1
+#define UART_HIGH_SPEED_S  30
+/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
+/*description: This register is used to configure the uart_id..*/
+#define UART_ID    0x3FFFFFFF
+#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V  0x3FFFFFFF
+#define UART_ID_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_REG_H_ */

components/soc/esp8684/include/soc/uart_struct.h

@@ -0,0 +1,402 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UART_STRUCT_H_
+#define _SOC_UART_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct uart_dev_s {
+    union {
+        struct {
+            uint32_t rw_byte                       :    32;  /*UART $n accesses FIFO via this register.*/
+        };
+        uint32_t val;
+    } ahb_fifo;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
+            uint32_t txfifo_empty                  :    1;  /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+            uint32_t parity_err                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
+            uint32_t frm_err                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
+            uint32_t rxfifo_ovf                    :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
+            uint32_t dsr_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
+            uint32_t cts_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
+            uint32_t brk_det                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
+            uint32_t rxfifo_tout                   :    1;  /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
+            uint32_t sw_xon                        :    1;  /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t sw_xoff                       :    1;  /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t glitch_det                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
+            uint32_t tx_brk_done                   :    1;  /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
+            uint32_t tx_done                       :    1;  /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
+            uint32_t rs485_parity_err              :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_frm_err                 :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_clash                   :    1;  /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
+            uint32_t at_cmd_char_det               :    1;  /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
+            uint32_t wakeup                        :    1;  /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
+            uint32_t txfifo_empty                  :    1;  /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
+            uint32_t parity_err                    :    1;  /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
+            uint32_t frm_err                       :    1;  /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+            uint32_t rxfifo_ovf                    :    1;  /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
+            uint32_t dsr_chg                       :    1;  /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+            uint32_t cts_chg                       :    1;  /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+            uint32_t brk_det                       :    1;  /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+            uint32_t rxfifo_tout                   :    1;  /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
+            uint32_t sw_xon                        :    1;  /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+            uint32_t sw_xoff                       :    1;  /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+            uint32_t glitch_det                    :    1;  /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
+            uint32_t tx_brk_done                   :    1;  /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
+            uint32_t tx_done                       :    1;  /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+            uint32_t rs485_parity_err              :    1;  /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
+            uint32_t rs485_frm_err                 :    1;  /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
+            uint32_t rs485_clash                   :    1;  /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
+            uint32_t at_cmd_char_det               :    1;  /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
+            uint32_t wakeup                        :    1;  /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t txfifo_empty                  :    1;  /*This is the enable bit for txfifo_empty_int_st register.*/
+            uint32_t parity_err                    :    1;  /*This is the enable bit for parity_err_int_st register.*/
+            uint32_t frm_err                       :    1;  /*This is the enable bit for frm_err_int_st register.*/
+            uint32_t rxfifo_ovf                    :    1;  /*This is the enable bit for rxfifo_ovf_int_st register.*/
+            uint32_t dsr_chg                       :    1;  /*This is the enable bit for dsr_chg_int_st register.*/
+            uint32_t cts_chg                       :    1;  /*This is the enable bit for cts_chg_int_st register.*/
+            uint32_t brk_det                       :    1;  /*This is the enable bit for brk_det_int_st register.*/
+            uint32_t rxfifo_tout                   :    1;  /*This is the enable bit for rxfifo_tout_int_st register.*/
+            uint32_t sw_xon                        :    1;  /*This is the enable bit for sw_xon_int_st register.*/
+            uint32_t sw_xoff                       :    1;  /*This is the enable bit for sw_xoff_int_st register.*/
+            uint32_t glitch_det                    :    1;  /*This is the enable bit for glitch_det_int_st register.*/
+            uint32_t tx_brk_done                   :    1;  /*This is the enable bit for tx_brk_done_int_st register.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This is the enable bit for tx_brk_idle_done_int_st register.*/
+            uint32_t tx_done                       :    1;  /*This is the enable bit for tx_done_int_st register.*/
+            uint32_t rs485_parity_err              :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_frm_err                 :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_clash                   :    1;  /*This is the enable bit for rs485_clash_int_st register.*/
+            uint32_t at_cmd_char_det               :    1;  /*This is the enable bit for at_cmd_char_det_int_st register.*/
+            uint32_t wakeup                        :    1;  /*This is the enable bit for uart_wakeup_int_st register.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+            uint32_t txfifo_empty                  :    1;  /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
+            uint32_t parity_err                    :    1;  /*Set this bit to clear parity_err_int_raw interrupt.*/
+            uint32_t frm_err                       :    1;  /*Set this bit to clear frm_err_int_raw interrupt.*/
+            uint32_t rxfifo_ovf                    :    1;  /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+            uint32_t dsr_chg                       :    1;  /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
+            uint32_t cts_chg                       :    1;  /*Set this bit to clear the cts_chg_int_raw interrupt.*/
+            uint32_t brk_det                       :    1;  /*Set this bit to clear the brk_det_int_raw interrupt.*/
+            uint32_t rxfifo_tout                   :    1;  /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+            uint32_t sw_xon                        :    1;  /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t sw_xoff                       :    1;  /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
+            uint32_t glitch_det                    :    1;  /*Set this bit to clear the glitch_det_int_raw interrupt.*/
+            uint32_t tx_brk_done                   :    1;  /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+            uint32_t tx_brk_idle_done              :    1;  /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+            uint32_t tx_done                       :    1;  /*Set this bit to clear the tx_done_int_raw interrupt.*/
+            uint32_t rs485_parity_err              :    1;  /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+            uint32_t rs485_frm_err                 :    1;  /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+            uint32_t rs485_clash                   :    1;  /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
+            uint32_t at_cmd_char_det               :    1;  /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+            uint32_t wakeup                        :    1;  /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t div_int                       :    12;  /*The integral part of the frequency divider factor.*/
+            uint32_t reserved12                    :    8;
+            uint32_t div_frag                      :    4;  /*The decimal part of the frequency divider factor.*/
+            uint32_t reserved24                    :    8;  /*Reserved*/
+        };
+        uint32_t val;
+    } clk_div;
+    union {
+        struct {
+            uint32_t glitch_filt                   :    8;  /*when input pulse width is lower than this value, the pulse is ignored.*/
+            uint32_t glitch_filt_en                :    1;  /*Set this bit to enable Rx signal filter.*/
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } rx_filt;
+    union {
+        struct {
+            uint32_t rxfifo_cnt                    :    10;  /*Stores the byte number of valid data in Rx-FIFO.*/
+            uint32_t reserved10                    :    3;
+            uint32_t dsrn                          :    1;  /*The register represent the level value of the internal uart dsr signal.*/
+            uint32_t ctsn                          :    1;  /*This register represent the level value of the internal uart cts signal.*/
+            uint32_t rxd                           :    1;  /*This register represent the  level value of the internal uart rxd signal.*/
+            uint32_t txfifo_cnt                    :    10;  /*Stores the byte number of data in Tx-FIFO.*/
+            uint32_t reserved26                    :    3;  /*Reserved*/
+            uint32_t dtrn                          :    1;  /*This bit represents the level of the internal uart dtr signal.*/
+            uint32_t rtsn                          :    1;  /*This bit represents the level of the internal uart rts signal.*/
+            uint32_t txd                           :    1;  /*This bit represents the  level of the internal uart txd signal.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t parity                        :    1;  /*This register is used to configure the parity check mode.*/
+            uint32_t parity_en                     :    1;  /*Set this bit to enable uart parity check.*/
+            uint32_t bit_num                       :    2;  /*This register is used to set the length of data.*/
+            uint32_t stop_bit_num                  :    2;  /*This register is used to set the length of  stop bit.*/
+            uint32_t sw_rts                        :    1;  /*This register is used to configure the software rts signal which is used in software flow control.*/
+            uint32_t sw_dtr                        :    1;  /*This register is used to configure the software dtr signal which is used in software flow control.*/
+            uint32_t txd_brk                       :    1;  /*Set this bit to enbale transmitter to  send NULL when the process of sending data is done.*/
+            uint32_t irda_dplx                     :    1;  /*Set this bit to enable IrDA loopback mode.*/
+            uint32_t irda_tx_en                    :    1;  /*This is the start enable bit for IrDA transmitter.*/
+            uint32_t irda_wctl                     :    1;  /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+            uint32_t irda_tx_inv                   :    1;  /*Set this bit to invert the level of  IrDA transmitter.*/
+            uint32_t irda_rx_inv                   :    1;  /*Set this bit to invert the level of IrDA receiver.*/
+            uint32_t loopback                      :    1;  /*Set this bit to enable uart loopback test mode.*/
+            uint32_t tx_flow_en                    :    1;  /*Set this bit to enable flow control function for transmitter.*/
+            uint32_t irda_en                       :    1;  /*Set this bit to enable IrDA protocol.*/
+            uint32_t rxfifo_rst                    :    1;  /*Set this bit to reset the uart receive-FIFO.*/
+            uint32_t txfifo_rst                    :    1;  /*Set this bit to reset the uart transmit-FIFO.*/
+            uint32_t rxd_inv                       :    1;  /*Set this bit to inverse the level value of uart rxd signal.*/
+            uint32_t cts_inv                       :    1;  /*Set this bit to inverse the level value of uart cts signal.*/
+            uint32_t dsr_inv                       :    1;  /*Set this bit to inverse the level value of uart dsr signal.*/
+            uint32_t txd_inv                       :    1;  /*Set this bit to inverse the level value of uart txd signal.*/
+            uint32_t rts_inv                       :    1;  /*Set this bit to inverse the level value of uart rts signal.*/
+            uint32_t dtr_inv                       :    1;  /*Set this bit to inverse the level value of uart dtr signal.*/
+            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t err_wr_mask                   :    1;  /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
+            uint32_t autobaud_en                   :    1;  /*This is the enable bit for detecting baudrate.*/
+            uint32_t mem_clk_en                    :    1;  /*UART memory clock gate enable signal.*/
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rxfifo_full_thrhd             :    9;  /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
+            uint32_t txfifo_empty_thrhd            :    9;  /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
+            uint32_t dis_rx_dat_ovf                :    1;  /*Disable UART Rx data overflow detect. */
+            uint32_t rx_tout_flow_dis              :    1;  /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+            uint32_t rx_flow_en                    :    1;  /*This is the flow enable bit for UART receiver.*/
+            uint32_t rx_tout_en                    :    1;  /*This is the enble bit for uart receiver's timeout function.*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } lowpulse;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } highpulse;
+    union {
+        struct {
+            uint32_t edge_cnt                      :    10;  /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } rxd_cnt;
+    union {
+        struct {
+            uint32_t sw_flow_con_en                :    1;  /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
+            uint32_t xonoff_del                    :    1;  /*Set this bit to remove flow control char from the received data.*/
+            uint32_t force_xon                     :    1;  /*Set this bit to enable the transmitter to go on sending data.*/
+            uint32_t force_xoff                    :    1;  /*Set this bit to stop the  transmitter from sending data.*/
+            uint32_t send_xon                      :    1;  /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
+            uint32_t send_xoff                     :    1;  /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+            uint32_t reserved6                     :    26;  /*Reserved*/
+        };
+        uint32_t val;
+    } flow_conf;
+    union {
+        struct {
+            uint32_t active_threshold              :    10;  /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } sleep_conf;
+    union {
+        struct {
+            uint32_t xoff_threshold                :    9;  /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
+            uint32_t xoff_char                     :    8;  /*This register stores the Xoff flow control char.*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf0;
+    union {
+        struct {
+            uint32_t xon_threshold                 :    9;  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
+            uint32_t xon_char                      :    8;  /*This register stores the Xon flow control char.*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf1;
+    union {
+        struct {
+            uint32_t tx_brk_num                    :    8;  /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } txbrk_conf;
+    union {
+        struct {
+            uint32_t rx_idle_thrhd                 :    10;  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
+            uint32_t tx_idle_num                   :    10;  /*This register is used to configure the duration time between transfers.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } idle_conf;
+    union {
+        struct {
+            uint32_t en                            :    1;  /*Set this bit to choose the rs485 mode.*/
+            uint32_t dl0_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t dl1_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t tx_rx_en                      :    1;  /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.  */
+            uint32_t rx_busy_tx_en                 :    1;  /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
+            uint32_t rx_dly_num                    :    1;  /*This register is used to delay the receiver's internal data signal.*/
+            uint32_t tx_dly_num                    :    4;  /*This register is used to delay the transmitter's internal data signal.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } rs485_conf;
+    union {
+        struct {
+            uint32_t pre_idle_num                  :    16;  /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_precnt;
+    union {
+        struct {
+            uint32_t post_idle_num                 :    16;  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_postcnt;
+    union {
+        struct {
+            uint32_t rx_gap_tout                   :    16;  /*This register is used to configure the duration time between the at_cmd chars.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_gaptout;
+    union {
+        struct {
+            uint32_t data                          :    8;  /*This register is used to configure the content of at_cmd char.*/
+            uint32_t char_num                      :    8;  /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_char;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t rx_size                       :    3;  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
+            uint32_t tx_size                       :    3;  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
+            uint32_t rx_flow_thrhd                 :    9;  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
+            uint32_t rx_tout_thrhd                 :    10;  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+            uint32_t force_pd                      :    1;  /*Set this bit to force power down UART memory.*/
+            uint32_t force_pu                      :    1;  /*Set this bit to force power up UART memory.*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } mem_conf;
+    union {
+        struct {
+            uint32_t apb_tx_waddr                  :    10;  /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t tx_raddr                      :    10;  /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } mem_tx_status;
+    union {
+        struct {
+            uint32_t apb_rx_raddr                  :    10;  /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t rx_waddr                      :    10;  /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } mem_rx_status;
+    union {
+        struct {
+            uint32_t st_urx_out                    :    4;  /*This is the status register of receiver.*/
+            uint32_t st_utx_out                    :    4;  /*This is the status register of transmitter.*/
+            uint32_t reserved8                     :    24;  /*Reserved*/
+        };
+        uint32_t val;
+    } fsm_status;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } pospulse;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } negpulse;
+    union {
+        struct {
+            uint32_t sclk_div_b                    :    6;  /*The  denominator of the frequency divider factor.*/
+            uint32_t sclk_div_a                    :    6;  /*The numerator of the frequency divider factor.*/
+            uint32_t sclk_div_num                  :    8;  /*The integral part of the frequency divider factor.*/
+            uint32_t sclk_sel                      :    2;  /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
+            uint32_t sclk_en                       :    1;  /*Set this bit to enable UART Tx/Rx clock.*/
+            uint32_t rst_core                      :    1;  /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
+            uint32_t tx_sclk_en                    :    1;  /*Set this bit to enable UART Tx clock.*/
+            uint32_t rx_sclk_en                    :    1;  /*Set this bit to enable UART Rx clock.*/
+            uint32_t tx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Tx.*/
+            uint32_t rx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Rx.*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } clk_conf;
+    uint32_t date;
+    union {
+        struct {
+            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
+            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
+            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
+        };
+        uint32_t val;
+    } id;
+} uart_dev_t;
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_STRUCT_H_ */

components/soc/esp8684/include/soc/wdev_reg.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc.h"
+
+/* Hardware random number generator register */
+#define WDEV_RND_REG 0x600260b0

components/soc/esp8684/interrupts.c

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/interrupts.h"
+
+const char *const esp_isr_names[] = {
+    [0] = "WIFI_MAC",
+    [1] = "WIFI_MAC_NMI",
+    [2] = "WIFI_PWR",
+    [3] = "WIFI_BB",
+    [4] = "BT_MAC",
+    [5] = "BT_BB",
+    [6] = "BT_BB_NMI",
+    [7] = "LP_TIMER",
+    [8] = "COEX",
+    [9] = "BLE_TIMER",
+    [10] = "BLE_SEC",
+    [11] = "I2C_MST",
+    [12] = "APB_CTRL",
+    [13] = "GPIO_INTR_PRO",
+    [14] = "GPIO_INTR_PRO_NMI",
+    [15] = "SPI_INTR_1",
+    [16] = "SPI_INTR_2",
+    [17] = "UART",
+    [18] = "UART1",
+    [19] = "LEDC",
+    [20] = "EFUSE",
+    [21] = "RTC_CORE",
+    [22] = "I2C_EXT0",
+    [23] = "TG0_T0_LEVEL",
+    [24] = "TG0_WDT_LEVEL",
+    [25] = "CACHE_IA",
+    [26] = "SYSTIMER_TARGET0_EDGE",
+    [27] = "SYSTIMER_TARGET1_EDGE",
+    [28] = "SYSTIMER_TARGET2_EDGE",
+    [29] = "SPI_MEM_REJECT_CACHE",
+    [30] = "ICACHE_PRELOAD0",
+    [31] = "ICACHE_SYNC0",
+    [32] = "APB_ADC",
+    [33] = "DMA_CH0",
+    [34] = "SHA",
+    [35] = "ECC",
+    [36] = "ETS_FROM_CPU_INTR0",
+    [37] = "ETS_FROM_CPU_INTR1",
+    [38] = "ETS_FROM_CPU_INTR2",
+    [39] = "ETS_FROM_CPU_INTR3",
+    [40] = "ETS_ASSIST_DEBUG",
+    [41] = "ETS_CORE0_PIF_PMS_SIZE",
+    [42] = "ETS_CACHE_CORE0_ACS",
+};

components/soc/esp8684/ld/esp8684.peripherals.ld

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+PROVIDE ( UART0 = 0x60000000 );
+PROVIDE ( UART1 = 0x60010000 );
+PROVIDE ( SPIMEM1 = 0x60002000 );
+PROVIDE ( SPIMEM0 = 0x60003000 );
+PROVIDE ( GPIO = 0x60004000 );
+PROVIDE ( SIGMADELTA = 0x60004f00 );
+PROVIDE ( RTCCNTL = 0x60008000 );
+PROVIDE ( RTCIO = 0x60008400 );
+PROVIDE ( HINF = 0x6000B000 );
+PROVIDE ( I2C0  = 0x60013000 );
+PROVIDE ( HOST = 0x60015000 );
+PROVIDE ( RMT = 0x60016000 );
+PROVIDE ( RMTMEM = 0x60016400 );
+PROVIDE ( PCNT = 0x60017000 );
+PROVIDE ( SLC = 0x60018000 );
+PROVIDE ( LEDC = 0x60019000 );
+PROVIDE ( TIMERG0 = 0x6001F000 );
+PROVIDE ( SYSTIMER = 0x60023000 );
+PROVIDE ( GPSPI2  = 0x60024000 );
+PROVIDE ( GPSPI3  = 0x60025000 );
+PROVIDE ( SYSCON = 0x60026000 );
+PROVIDE ( APB_SARADC = 0x60040000 );
+PROVIDE ( GDMA    = 0x6003F000 );

components/soc/esp8684/ledc_periph.c

@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ledc_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every LEDC peripheral: GPIO signals
+*/
+const ledc_signal_conn_t ledc_periph_signal[1] = {
+	{
+        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
+	}
+};

components/soc/esp8684/rmt_periph.c

@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/rmt_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const rmt_signal_conn_t rmt_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_RMT_MODULE,
+            .irq = ETS_RMT_INTR_SOURCE,
+            .channels = {
+                [0] = {
+                    .tx_sig = RMT_SIG_OUT0_IDX,
+                    .rx_sig = -1
+                },
+                [1] = {
+                    .tx_sig = RMT_SIG_OUT1_IDX,
+                    .rx_sig = -1
+                },
+                [2] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN0_IDX
+                },
+                [3] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN1_IDX
+                },
+            }
+        }
+    }
+};

components/soc/esp8684/spi_periph.c

@@ -0,0 +1,63 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/spi_periph.h"
+#include "stddef.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        .spiclk_out = SPICLK_OUT_MUX_IDX,
+        .spiclk_in = 0,/* SPI clock is not an input signal*/
+        .spid_out = SPID_OUT_IDX,
+        .spiq_out = SPIQ_OUT_IDX,
+        .spiwp_out = SPIWP_OUT_IDX,
+        .spihd_out = SPIHD_OUT_IDX,
+        .spid_in = SPID_IN_IDX,
+        .spiq_in = SPIQ_IN_IDX,
+        .spiwp_in = SPIWP_IN_IDX,
+        .spihd_in = SPIHD_IN_IDX,
+        .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
+        .spics_in = 0,/* SPI cs is not an input signal*/
+        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI1_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI_MODULE,
+        .hw = (spi_dev_t *) &SPIMEM1,
+        .func = SPI_FUNC_NUM,
+    }, {
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI2_MODULE,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM,
+    }
+};

components/soc/esp8684/timer_periph.c

@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/timer_periph.h"
+
+const timer_group_signal_conn_t timer_group_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_TIMG0_MODULE,
+            .timer_irq_id = {
+                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
+            }
+        },
+    }
+};

components/soc/esp8684/uart_periph.c

@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/uart_periph.h"
+
+/*
+ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+   {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U0TXD_GPIO_NUM,
+                .iomux_func = U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = U0TXD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U0RXD_GPIO_NUM,
+                .iomux_func = U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = U0RXD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U0RTS_GPIO_NUM,
+                .iomux_func = U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = U0RTS_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U0CTS_GPIO_NUM,
+                .iomux_func = U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = U0CTS_IN_IDX,
+            }
+        },
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+
+    {
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U1TXD_GPIO_NUM,
+                .iomux_func = U1TXD_MUX_FUNC,
+                .input = 0,
+                .signal = U1TXD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U1RXD_GPIO_NUM,
+                .iomux_func = U1RXD_MUX_FUNC,
+                .input = 1,
+                .signal = U1RXD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U1RTS_GPIO_NUM,
+                .iomux_func = U1RTS_MUX_FUNC,
+                .input = 0,
+                .signal = U1RTS_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U1CTS_GPIO_NUM,
+                .iomux_func = U1CTS_MUX_FUNC,
+                .input = 1,
+                .signal = U1CTS_IN_IDX,
+            },
+        },
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    },
+};

components/soc/include/soc/lldesc.h

@@ -1,16 +1,8 @@
-// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 #include <stdbool.h>
@@ -26,6 +18,8 @@
 #include "esp32c3/rom/lldesc.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/lldesc.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/lldesc.h"
 #endif
 
 //the size field has 12 bits, but 0 not for 4096.

components/soc/include/soc/soc_memory_types.h

@@ -1,16 +1,8 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 #include <stdlib.h>
@@ -54,7 +46,10 @@ inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
 #if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
         || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
 #endif
-        || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
+#if SOC_RTC_FAST_MEM_SUPPORTED
+        || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH)
+#endif
+    ;
 }
 
 inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
@@ -81,7 +76,11 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
 inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
     bool r;
     r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
+
+#if SOC_RTC_SLOW_MEM_SUPPORTED
     r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
+#endif
+
 #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
     /* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
      * for single core configuration (where it gets added to system heap) following
@@ -124,6 +123,7 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
     return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
 }
 
+#if SOC_RTC_FAST_MEM_SUPPORTED
 inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
     return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH);
 }
@@ -131,10 +131,14 @@ inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
 inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) {
     return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
 }
+#endif
 
+#if !CONFIG_IDF_TARGET_ESP8684
+// 	IDF-3901
 inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) {
     return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
 }
+#endif
 
 /* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM