esp32: move crosscore int

components/esp32/CMakeLists.txt

@@ -14,7 +14,6 @@ else()
     set(srcs
         "cache_sram_mmu.c"
         "clk.c"
-        "crosscore_int.c"
         "dport_access.c"
         "esp_himem.c"
         "spiram.c"

components/esp32c3/CMakeLists.txt

@@ -12,7 +12,6 @@ else()
     # Regular app build
 
     set(srcs "clk.c"
-             "crosscore_int.c"
              "dport_access.c"
              "esp_hmac.c"
              "esp_ds.c"

components/esp32c3/crosscore_int.c

@@ -1,100 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdint.h>
-#include "esp_attr.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "soc/periph_defs.h"
-#include "soc/system_reg.h"
-#include "hal/cpu_hal.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/portmacro.h"
-
-#define REASON_YIELD BIT(0)
-#define REASON_FREQ_SWITCH BIT(1)
-#define REASON_PRINT_BACKTRACE BIT(2)
-
-static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
-static volatile uint32_t reason[portNUM_PROCESSORS];
-
-// TODO ESP32-C3 IDF-2449
-static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
-{
-    portYIELD_FROM_ISR();
-}
-
-static void IRAM_ATTR esp_crosscore_isr(void *arg)
-{
-    uint32_t my_reason_val;
-    //A pointer to the correct reason array item is passed to this ISR.
-    volatile uint32_t *my_reason = arg;
-
-    //Clear the interrupt first.
-    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
-    //Grab the reason and clear it.
-    portENTER_CRITICAL_ISR(&reason_spinlock);
-    my_reason_val = *my_reason;
-    *my_reason = 0;
-    portEXIT_CRITICAL_ISR(&reason_spinlock);
-
-    //Check what we need to do.
-    if (my_reason_val & REASON_YIELD) {
-        esp_crosscore_isr_handle_yield();
-    }
-    if (my_reason_val & REASON_FREQ_SWITCH) {
-        /* Nothing to do here; the frequency switch event was already
-         * handled by a hook in xtensa_vectors.S. Could be used in the future
-         * to allow DFS features without the extra latency of the ISR hook.
-         */
-    }
-    // TODO: ESP32-C3 IDF-2986
-    // if (my_reason_val & REASON_PRINT_BACKTRACE) {
-    //     esp_backtrace_print(100);
-    // }
-}
-
-// Initialize the crosscore interrupt on this core.
-void esp_crosscore_int_init(void)
-{
-    portENTER_CRITICAL(&reason_spinlock);
-    reason[cpu_hal_get_core_id()] = 0;
-    portEXIT_CRITICAL(&reason_spinlock);
-    ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
-}
-
-static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
-{
-    assert(core_id < portNUM_PROCESSORS);
-    //Mark the reason we interrupt the other CPU
-    portENTER_CRITICAL(&reason_spinlock);
-    reason[core_id] |= reason_mask;
-    portEXIT_CRITICAL(&reason_spinlock);
-    //Poke the other CPU.
-    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_YIELD);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
-}

components/esp32s2/CMakeLists.txt

@@ -13,7 +13,6 @@ else()
 
     set(srcs "memprot.c"
              "clk.c"
-             "crosscore_int.c"
              "dport_access.c"
              "spiram.c"
              "spiram_psram.c"

components/esp32s2/crosscore_int.c

@@ -1,109 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdint.h>
-#include <string.h>
-
-#include "esp_attr.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "esp_debug_helpers.h"
-
-#include "soc/cpu.h"
-#include "soc/dport_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/periph_defs.h"
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "freertos/queue.h"
-
-
-#define REASON_YIELD            BIT(0)
-#define REASON_FREQ_SWITCH      BIT(1)
-#define REASON_PRINT_BACKTRACE  BIT(2)
-
-static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
-static volatile uint32_t reason;
-
-/*
-ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
-the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
-*/
-static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
-{
-    portYIELD_FROM_ISR();
-}
-
-static void IRAM_ATTR esp_crosscore_isr(void *arg) {
-    uint32_t my_reason_val;
-    //A pointer to the correct reason item is passed to this ISR.
-    volatile uint32_t *my_reason=arg;
-
-    //Clear the interrupt first.
-    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
-    //Grab the reason and clear it.
-    portENTER_CRITICAL_ISR(&reason_spinlock);
-    my_reason_val=*my_reason;
-    *my_reason=0;
-    portEXIT_CRITICAL_ISR(&reason_spinlock);
-
-    //Check what we need to do.
-    if (my_reason_val & REASON_YIELD) {
-        esp_crosscore_isr_handle_yield();
-    }
-    if (my_reason_val & REASON_FREQ_SWITCH) {
-        /* Nothing to do here; the frequency switch event was already
-         * handled by a hook in xtensa_vectors.S. Could be used in the future
-         * to allow DFS features without the extra latency of the ISR hook.
-         */
-    }
-    if (my_reason_val & REASON_PRINT_BACKTRACE) {
-        esp_backtrace_print(100);
-    }
-}
-
-//Initialize the crosscore interrupt on this core.
-void esp_crosscore_int_init(void) {
-    portENTER_CRITICAL(&reason_spinlock);
-    reason = 0;
-    portEXIT_CRITICAL(&reason_spinlock);
-    ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason, NULL));
-}
-
-static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
-    assert(core_id<portNUM_PROCESSORS);
-    //Mark the reason we interrupt the current CPU
-    portENTER_CRITICAL(&reason_spinlock);
-    reason |= reason_mask;
-    portEXIT_CRITICAL(&reason_spinlock);
-    //Poke the current CPU.
-    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_YIELD);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
-}

components/esp32s3/CMakeLists.txt

@@ -13,7 +13,6 @@ else()
     # Regular app build
 
     set(srcs "clk.c"
-             "crosscore_int.c"
              "dport_access.c"
              "esp_crypto_lock.c"
              "memprot.c"

components/esp32s3/crosscore_int.c

@@ -1,111 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdint.h>
-#include "esp_attr.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "esp_debug_helpers.h"
-#include "soc/periph_defs.h"
-#include "soc/system_reg.h"
-#include "hal/cpu_hal.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/portmacro.h"
-
-#define REASON_YIELD            BIT(0)
-#define REASON_FREQ_SWITCH      BIT(1)
-#define REASON_PRINT_BACKTRACE  BIT(2)
-
-static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
-static volatile uint32_t reason[portNUM_PROCESSORS];
-
-static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
-{
-    portYIELD_FROM_ISR();
-}
-
-static void IRAM_ATTR esp_crosscore_isr(void *arg)
-{
-    uint32_t my_reason_val;
-    //A pointer to the correct reason array item is passed to this ISR.
-    volatile uint32_t *my_reason = arg;
-
-    //Clear the interrupt first.
-    if (cpu_hal_get_core_id() == 0) {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
-    } else {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
-    }
-    //Grab the reason and clear it.
-    portENTER_CRITICAL_ISR(&reason_spinlock);
-    my_reason_val = *my_reason;
-    *my_reason = 0;
-    portEXIT_CRITICAL_ISR(&reason_spinlock);
-
-    //Check what we need to do.
-    if (my_reason_val & REASON_YIELD) {
-        esp_crosscore_isr_handle_yield();
-    }
-    if (my_reason_val & REASON_FREQ_SWITCH) {
-        /* Nothing to do here; the frequency switch event was already
-         * handled by a hook in xtensa_vectors.S. Could be used in the future
-         * to allow DFS features without the extra latency of the ISR hook.
-         */
-    }
-    if (my_reason_val & REASON_PRINT_BACKTRACE) {
-        esp_backtrace_print(100);
-    }
-}
-
-// Initialize the crosscore interrupt on this core.
-void esp_crosscore_int_init(void)
-{
-    portENTER_CRITICAL(&reason_spinlock);
-    reason[cpu_hal_get_core_id()] = 0;
-    portEXIT_CRITICAL(&reason_spinlock);
-    if (cpu_hal_get_core_id() == 0) {
-        ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
-    } else {
-        ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[1], NULL));
-    }
-}
-
-static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
-{
-    assert(core_id < portNUM_PROCESSORS);
-    //Mark the reason we interrupt the other CPU
-    portENTER_CRITICAL(&reason_spinlock);
-    reason[core_id] |= reason_mask;
-    portEXIT_CRITICAL(&reason_spinlock);
-    //Poke the other CPU.
-    if (core_id == 0) {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
-    } else {
-        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
-    }
-}
-
-void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_YIELD);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
-}
-
-void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
-{
-    esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
-}

components/esp_system/CMakeLists.txt

@@ -10,7 +10,8 @@ if(BOOTLOADER_BUILD)
     # Bootloader relies on some Kconfig options defined in esp_system.
     idf_component_register(SRCS "${srcs}")
 else()
-    list(APPEND srcs "esp_err.c"
+    list(APPEND srcs "crosscore_int.c"
+            "esp_err.c"
             "freertos_hooks.c"
             "intr_alloc.c"
             "int_wdt.c"

components/esp32/crosscore_int.c → components/esp_system/crosscore_int.c

@@ -12,30 +12,31 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 #include <stdint.h>
-#include <string.h>
-
 #include "esp_attr.h"
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
 #include "esp_debug_helpers.h"
+#include "soc/periph_defs.h"
 
-#include "soc/cpu.h"
-#include "soc/dport_reg.h"
-#include "soc/gpio_periph.h"
-#include "soc/rtc_periph.h"
-
+#include "hal/cpu_hal.h"
 #include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "freertos/queue.h"
+#include "freertos/portmacro.h"
 
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#include "soc/dport_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+#include "soc/system_reg.h"
+#endif
 
 #define REASON_YIELD            BIT(0)
 #define REASON_FREQ_SWITCH      BIT(1)
+
+#if !CONFIG_IDF_TARGET_ESP32C3
 #define REASON_PRINT_BACKTRACE  BIT(2)
+#endif
 
 static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
-static volatile uint32_t reason[ portNUM_PROCESSORS ];
+static volatile uint32_t reason[portNUM_PROCESSORS];
 
 /*
 ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
@@ -52,11 +53,24 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
     volatile uint32_t *my_reason=arg;
 
     //Clear the interrupt first.
-    if (xPortGetCoreID()==0) {
+#if CONFIG_IDF_TARGET_ESP32
+    if (cpu_hal_get_core_id()==0) {
         DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
     } else {
         DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2
+    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
+#elif CONFIG_IDF_TARGET_ESP32S3
+    if (cpu_hal_get_core_id()==0) {
+        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
+    } else {
+        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
+    }
+#elif CONFIG_IDF_TARGET_ESP32C3
+    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
+#endif
+
     //Grab the reason and clear it.
     portENTER_CRITICAL_ISR(&reason_spinlock);
     my_reason_val=*my_reason;
@@ -73,24 +87,30 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
          * to allow DFS features without the extra latency of the ISR hook.
          */
     }
+#if !CONFIG_IDF_TARGET_ESP32C3 // IDF-2986
     if (my_reason_val & REASON_PRINT_BACKTRACE) {
         esp_backtrace_print(100);
     }
+#endif
 }
 
 //Initialize the crosscore interrupt on this core. Call this once
 //on each active core.
 void esp_crosscore_int_init(void) {
     portENTER_CRITICAL(&reason_spinlock);
-    reason[xPortGetCoreID()]=0;
+    reason[cpu_hal_get_core_id()]=0;
     portEXIT_CRITICAL(&reason_spinlock);
-    esp_err_t err __attribute__((unused));
-    if (xPortGetCoreID()==0) {
+    esp_err_t err __attribute__((unused)) = ESP_OK;
+#if portNUM_PROCESSORS > 1
+    if (cpu_hal_get_core_id()==0) {
         err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
     } else {
         err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
     }
-    assert(err == ESP_OK);
+#else
+    err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
+#endif
+    ESP_ERROR_CHECK(err);
 }
 
 static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
@@ -100,11 +120,23 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
     reason[core_id] |= reason_mask;
     portEXIT_CRITICAL_ISR(&reason_spinlock);
     //Poke the other CPU.
+#if CONFIG_IDF_TARGET_ESP32
     if (core_id==0) {
         DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
     } else {
         DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
     }
+#elif CONFIG_IDF_TARGET_ESP32S2
+    DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
+#elif CONFIG_IDF_TARGET_ESP32S3
+    if (core_id==0) {
+        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
+    } else {
+        WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
+    }
+#elif CONFIG_IDF_TARGET_ESP32C3
+    WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
+#endif
 }
 
 void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
@@ -117,7 +149,9 @@ void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
     esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
 }
 
+#if !CONFIG_IDF_TARGET_ESP32C3
 void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
 }
+#endif

components/esp_system/include/esp_private/crosscore_int.h

@@ -14,6 +14,8 @@
 #ifndef __ESP_CROSSCORE_INT_H
 #define __ESP_CROSSCORE_INT_H
 
+#include "sdkconfig.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -54,6 +56,8 @@ void esp_crosscore_int_send_yield(int core_id);
  */
 void esp_crosscore_int_send_freq_switch(int core_id);
 
+
+#if !CONFIG_IDF_TARGET_ESP32C3
 /**
  * Send an interrupt to a CPU indicating it should print its current backtrace
  *
@@ -63,6 +67,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
  * @param core_id Core that should print its backtrace
  */
 void esp_crosscore_int_send_print_backtrace(int core_id);
+#endif
 
 #ifdef __cplusplus
 }