Merge branch 'feature/support_esp32s3_deepsleep' into 'master'

support esp32s3 deepsleep

Closes IDF-2691, IDF-4057, WIFI-3926, WIFI-3927, and IDF-3703

See merge request espressif/esp-idf!14812

.gitlab/ci/target-test.yml

@@ -727,7 +727,7 @@ UT_C3_SDSPI:
 
 UT_S3:
   extends: .unit_test_esp32s3_template
-  parallel: 29
+  parallel: 30
   tags:
     - ESP32S3_IDF
     - UT_T1_1

components/esp32c3/Kconfig

@@ -192,23 +192,4 @@ menu "ESP32C3-Specific"
             If enabled, this disables the linking of binary libraries in the application build. Note
             that after enabling this Wi-Fi/Bluetooth will not work.
 
-    config ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND
-        bool "light sleep GPIO reset workaround"
-        default y
-        select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
-        help
-            ESP32C3 will reset at wake-up if GPIO is received a small electrostatic pulse during
-            light sleep, with specific condition
-
-            - GPIO needs to be configured as input-mode only
-            - The pin receives a small electrostatic pulse, and reset occurs when the pulse
-              voltage is higher than 6 V
-
-            For GPIO set to input mode only, it is not a good practice to leave it open/floating,
-            The hardware design needs to controlled it with determined supply or ground voltage
-            is necessary.
-
-            This option provides a software workaround for this issue. Configure to isolate all
-            GPIO pins in sleep state.
-
 endmenu  # ESP32C3-Specific

components/esp_hw_support/Kconfig

@@ -34,6 +34,25 @@ menu "Hardware Settings"
             bool
             default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
 
+        config ESP_SLEEP_GPIO_RESET_WORKAROUND
+            bool "light sleep GPIO reset workaround"
+            default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+            select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
+            help
+                esp32c3 and esp32s3 will reset at wake-up if GPIO is received a small electrostatic
+                pulse during light sleep, with specific condition
+
+                - GPIO needs to be configured as input-mode only
+                - The pin receives a small electrostatic pulse, and reset occurs when the pulse
+                  voltage is higher than 6 V
+
+                For GPIO set to input mode only, it is not a good practice to leave it open/floating,
+                The hardware design needs to controlled it with determined supply or ground voltage
+                is necessary.
+
+                This option provides a software workaround for this issue. Configure to isolate all
+                GPIO pins in sleep state.
+
         config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
             bool "PSRAM leakage current workaround in light sleep"
             depends on SPIRAM

components/esp_hw_support/sdkconfig.rename

@@ -6,3 +6,4 @@ CONFIG_TWO_UNIVERSAL_MAC_ADDRESS                        CONFIG_ESP32_UNIVERSAL_M
 CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS                       CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
 
 CONFIG_ESP_SYSTEM_PD_FLASH                              CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
+CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND         CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND

components/esp_hw_support/sleep_modes.c

@@ -188,12 +188,41 @@ static void touch_wakeup_prepare(void);
 static void esp_deep_sleep_wakeup_prepare(void);
 #endif
 
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
+
+static void RTC_IRAM_ATTR __attribute__((used, noinline)) esp_wake_stub_start(void)
+{
+    if (wake_stub_fn_handler) {
+        (*wake_stub_fn_handler)();
+    }
+}
+
+/* We must have a default deep sleep wake stub entry function, which must be
+ * located at the start address of the RTC fast memory, and its implementation
+ * must be simple enough to ensure that there is no litteral data before the
+ * wake stub entry, otherwise, the litteral data before the wake stub entry
+ * will not be CRC checked. */
+static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void)
+{
+#define _SYM2STR(s) # s
+#define SYM2STR(s)  _SYM2STR(s)
+    // call4 has a larger effective addressing range (-524284 to 524288 bytes),
+    // which is sufficient for instruction addressing in RTC fast memory.
+    __asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
+}
+#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+
 /* Wake from deep sleep stub
    See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
 */
 esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
 {
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+    esp_deep_sleep_wake_stub_fn_t stub_ptr = wake_stub_fn_handler;
+#else
     esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
+#endif
     if (!esp_ptr_executable(stub_ptr)) {
         return NULL;
     }
@@ -202,7 +231,11 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
 
 void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
 {
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+    wake_stub_fn_handler = new_stub;
+#else
     REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
+#endif
 }
 
 void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
@@ -315,15 +348,6 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     // For deep sleep, wait for the contents of UART FIFO to be sent.
     bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
 
-#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    /* Currently only safe to use deep sleep wake stub & RTC memory as heap in single core mode.
-
-       For ESP32-S3, either disable ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP in config or find a way to set the
-       deep sleep wake stub to NULL.
-     */
-    assert(!deep_sleep || esp_get_deep_sleep_wake_stub() == NULL);
-#endif
-
     if (deep_sleep) {
         flush_uarts();
     } else {
@@ -416,18 +440,27 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
          */
         portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
 
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+        extern char _rtc_text_start[];
+#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
+        extern char _rtc_noinit_end[];
+        size_t rtc_fast_length = (size_t)_rtc_noinit_end - (size_t)_rtc_text_start;
+#else
+        extern char _rtc_force_fast_end[];
+        size_t rtc_fast_length = (size_t)_rtc_force_fast_end - (size_t)_rtc_text_start;
+#endif
+        esp_rom_set_rtc_wake_addr((esp_rom_wake_func_t)esp_wake_stub_entry, rtc_fast_length);
+        result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu);
+#else
 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
         /* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
-#if CONFIG_IDF_TARGET_ESP32S3//TODO: WIFI-3542
-        result = 0;
-#else
         set_rtc_memory_crc();
         result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu);
-#endif
 #else
         /* Otherwise, need to call the dedicated soc function for this */
         result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
 #endif
+#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
 
         portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
     } else {
@@ -466,11 +499,17 @@ void IRAM_ATTR esp_deep_sleep_start(void)
     esp_brownout_disable();
 #endif //CONFIG_IDF_TARGET_ESP32S2
 
+    esp_sync_counters_rtc_and_frc();
+
+    /* Disable interrupts and stall another core in case another task writes
+     * to RTC memory while we calculate RTC memory CRC.
+     */
+    portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
+    esp_ipc_isr_stall_other_cpu();
+
     // record current RTC time
     s_config.rtc_ticks_at_sleep_start = rtc_time_get();
 
-    // record current RTC time
-    esp_sync_counters_rtc_and_frc();
     // Configure wake stub
     if (esp_get_deep_sleep_wake_stub() == NULL) {
         esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
@@ -502,6 +541,9 @@ void IRAM_ATTR esp_deep_sleep_start(void)
     while (1) {
         ;
     }
+    // Never returns here
+    esp_ipc_isr_release_other_cpu();
+    portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
 }
 
 /**

components/esp_rom/include/esp32s3/rom/rtc.h

@@ -1,16 +1,8 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -62,6 +54,7 @@ extern "C" {
 #define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
 #define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
 #define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
+#define RTC_ENTRY_LENGTH_REG    RTC_CNTL_STORE5_REG
 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
@@ -173,16 +166,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
+typedef void (* esp_rom_wake_func_t)(void);
+
+/**
+  * @brief Read stored RTC wake function address
+  *
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
+  *
+  * @param  None
+  *
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
+  */
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Store new RTC wake function address
   *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
   *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
   *
-  * @return uint32_t : CRC32 result
+  * @return None
   */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
 
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
@@ -202,26 +210,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *

components/esp_system/Kconfig

@@ -87,11 +87,7 @@ menu "ESP System Settings"
 
     config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
         bool "Enable RTC fast memory for dynamic allocations"
-        default y if IDF_TARGET_ESP32
-        default y if IDF_TARGET_ESP32S2
-        default y if IDF_TARGET_ESP32C3
-        default n if IDF_TARGET_ESP32S3  # TODO
-        default y if IDF_TARGET_ESP32H2
+        default y
         depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
         help
             This config option allows to add RTC fast memory region to system heap with capability

components/esp_system/ld/esp32s3/memory.ld.in

@@ -103,7 +103,7 @@ MEMORY
   /**
    * RTC fast memory (same block as above), viewed from data bus
    */
-  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000
+  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
 
   /**
    * RTC slow memory (data accessible). Persists over deep sleep.

components/esp_system/ld/esp32s3/sections.ld.in

@@ -18,6 +18,8 @@ SECTIONS
   .rtc.text :
   {
     . = ALIGN(4);
+    _rtc_text_start = ABSOLUTE(.);
+    *(.rtc.entry.text)
 
     mapping[rtc_text]
 

components/esp_system/startup.c

@@ -434,7 +434,7 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
 {
     esp_timer_init();
 
-#if CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND && !CONFIG_PM_SLP_DISABLE_GPIO
+#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND && !CONFIG_PM_SLP_DISABLE_GPIO
     // Configure to isolate (disable the Input/Output/Pullup/Pulldown
     // function of the pin) all GPIO pins in sleep state
     esp_sleep_config_gpio_isolate();

components/esp_system/test/test_sleep.c

@@ -1,3 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #include "unity.h"
 #include <sys/time.h>
 #include <sys/param.h>
@@ -20,8 +26,6 @@
 #include "esp_rom_sys.h"
 #include "esp_timer.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -284,8 +288,10 @@ static void check_wake_stub(void)
 {
     TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
     TEST_ASSERT_EQUAL_HEX32((uint32_t) &wake_stub, s_wake_stub_var);
+#if !CONFIG_IDF_TARGET_ESP32S3
     /* ROM code clears wake stub entry address */
     TEST_ASSERT_NULL(esp_get_deep_sleep_wake_stub());
+#endif
 }
 
 TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub", "[deepsleep][reset=DEEPSLEEP_RESET]",
@@ -318,7 +324,12 @@ static void prepare_wake_stub_from_rtc(void)
        a memory capability (as it's an implementation detail). So to test this we need to allocate
        the stack statically.
     */
+#if CONFIG_IDF_TARGET_ESP32S3
+    uint8_t *sleep_stack = (uint8_t *)heap_caps_malloc(1024, MALLOC_CAP_RTCRAM);
+    TEST_ASSERT((uint32_t)sleep_stack >= SOC_RTC_DRAM_LOW && (uint32_t)sleep_stack < SOC_RTC_DRAM_HIGH);
+#else
     static RTC_FAST_ATTR uint8_t sleep_stack[1024];
+#endif
     static RTC_FAST_ATTR StaticTask_t sleep_task;
 
     /* normally BSS like sleep_stack will be cleared on reset, but RTC memory is not cleared on
@@ -423,7 +434,7 @@ __attribute__((unused)) static uint32_t get_cause(void)
     return wakeup_cause;
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
 // Fails on S2 IDF-2903
 
 // This test case verifies deactivation of trigger for wake up sources
@@ -498,7 +509,7 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
     // Disable ext0 wakeup source, as this might interfere with other tests
     ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
 }
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
 
 #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
@@ -537,8 +548,6 @@ static void check_time_deepsleep(void)
 
 TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep);
 
-#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
 static void gpio_deepsleep_wakeup_config(void)
 {

components/heap/include/esp_heap_caps.h

@@ -1,16 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #pragma once
 
 #include <stdint.h>
@@ -41,6 +34,7 @@ extern "C" {
 #define MALLOC_CAP_DEFAULT          (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call
 #define MALLOC_CAP_IRAM_8BIT        (1<<13) ///< Memory must be in IRAM and allow unaligned access
 #define MALLOC_CAP_RETENTION        (1<<14)
+#define MALLOC_CAP_RTCRAM           (1<<15) ///< Memory must be in RTC fast memory
 
 #define MALLOC_CAP_INVALID          (1<<31) ///< Memory can't be used / list end marker
 

components/heap/port/esp32s3/memory_layout.c

@@ -1,16 +1,9 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #ifndef BOOTLOADER_BUILD
 
 #include <stdint.h>
@@ -46,6 +39,8 @@ const soc_memory_type_desc_t soc_memory_types[] = {
     { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
     // Type 5: DRAM which is not DMA accesible
     { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
+    // Type 6: RTC Fast RAM
+    { "RTCRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
 };
 
 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@@ -78,13 +73,13 @@ const soc_memory_region_t soc_memory_regions[] = {
     { 0x3C000000, 0x4000,  5, 0}
 #endif
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50000000, 0x2000,  4, 0}, //Fast RTC memory
+    { 0x600fe000, 0x2000,  6, 0}, //Fast RTC memory
 #endif
 };
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
 
-extern int _data_start, _heap_start, _iram_start, _iram_end; // defined in sections.ld.in
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; // defined in sections.ld.in
 
 /**
  * Reserved memory regions.
@@ -115,4 +110,13 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_dat
 SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
 #endif
 
+// RTC Fast RAM region
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+#ifdef CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
+#else
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
+#endif
+#endif
+
 #endif // BOOTLOADER_BUILD

components/soc/esp32s3/include/soc/soc_caps.h

@@ -1,3 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 // The long term plan is to have a single soc_caps.h for all peripherals.
 // During the refactoring and multichip support development process, we
 // separate these information into periph_caps.h for each peripheral and
@@ -287,6 +293,9 @@
 
 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP    (1)     /*!<Supports waking up from touch pad trigger */
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY   (1)
+
+
 /*-------------------------- Flash Encryption CAPS----------------------------*/
 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (64)
 

tools/ci/check_copyright_ignore.txt

@@ -1050,7 +1050,6 @@ components/esp_rom/include/esp32s3/rom/miniz.h
 components/esp_rom/include/esp32s3/rom/opi_flash.h
 components/esp_rom/include/esp32s3/rom/rom_layout.h
 components/esp_rom/include/esp32s3/rom/rsa_pss.h
-components/esp_rom/include/esp32s3/rom/rtc.h
 components/esp_rom/include/esp32s3/rom/secure_boot.h
 components/esp_rom/include/esp32s3/rom/sha.h
 components/esp_rom/include/esp32s3/rom/spi_flash.h
@@ -1165,7 +1164,6 @@ components/esp_system/stack_check.c
 components/esp_system/system_time.c
 components/esp_system/test/test_delay.c
 components/esp_system/test/test_reset_reason.c
-components/esp_system/test/test_sleep.c
 components/esp_system/test/test_stack_check.c
 components/esp_system/test/test_system_time.c
 components/esp_system/test_eh_frame_parser/eh_frame_parser_impl.h
@@ -1737,7 +1735,6 @@ components/heap/heap_tlsf.h
 components/heap/heap_tlsf_block_functions.h
 components/heap/heap_tlsf_config.h
 components/heap/heap_trace_standalone.c
-components/heap/include/esp_heap_caps.h
 components/heap/include/esp_heap_caps_init.h
 components/heap/include/esp_heap_task_info.h
 components/heap/include/esp_heap_trace.h
@@ -1753,7 +1750,6 @@ components/heap/port/esp32/memory_layout.c
 components/heap/port/esp32c3/memory_layout.c
 components/heap/port/esp32h2/memory_layout.c
 components/heap/port/esp32s2/memory_layout.c
-components/heap/port/esp32s3/memory_layout.c
 components/heap/port/memory_layout_utils.c
 components/heap/test/test_aligned_alloc_caps.c
 components/heap/test/test_allocator_timings.c
@@ -2616,7 +2612,6 @@ components/soc/esp32s3/include/soc/sensitive_reg.h
 components/soc/esp32s3/include/soc/sensitive_struct.h
 components/soc/esp32s3/include/soc/sigmadelta_caps.h
 components/soc/esp32s3/include/soc/soc.h
-components/soc/esp32s3/include/soc/soc_caps.h
 components/soc/esp32s3/include/soc/soc_ulp.h
 components/soc/esp32s3/include/soc/spi_mem_reg.h
 components/soc/esp32s3/include/soc/spi_mem_struct.h