Merge branch 'bugfix/fix_touch_sensor_measure_start_wait_time' into 'master'

Bugfix(Touch):  fix the touch sensor wait cycle after wakeup from sleep

See merge request espressif/esp-idf!13116

components/esp_hw_support/port/esp32s2/rtc_init.c

@@ -66,6 +66,8 @@ void rtc_init(rtc_config_t cfg)
     /* Reset RTC bias to default value (needed if waking up from deep sleep) */
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
     REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
+    /* Recover default wait cycle for touch or COCPU after wakeup from deep sleep. */
+    REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
 
     if (cfg.clkctl_init) {
         //clear CMMU clock force on

components/esp_hw_support/port/esp32s2/rtc_sleep.c

@@ -126,6 +126,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
 
     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
+    /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */
+    REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP);
 }
 
 void rtc_sleep_low_init(uint32_t slowclk_period)
@@ -143,8 +145,6 @@ void rtc_sleep_set_wakeup_time(uint64_t t)
 /* Read back 'reject' status when waking from light or deep sleep */
 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
 
-static const unsigned DEEP_SLEEP_TOUCH_WAIT_CYCLE = 0xFF;
-
 uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
 {
     REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
@@ -153,9 +153,6 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
         REG_SET_BIT(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN);
     }
 
-    /* Set wait cycle for touch or COCPU after deep sleep. */
-    REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, DEEP_SLEEP_TOUCH_WAIT_CYCLE);
-
     /* Start entry into sleep mode */
     SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
 
@@ -213,23 +210,17 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
                  "s32i a2, %4, 0\n"
                  "memw\n"
 
-                 /* Set wait cycle for touch or COCPU after deep sleep (can be moved to C code part?) */
+                 /* Set register bit to go into deep sleep */
                  "l32i a2, %5, 0\n"
-                 "and a2, a2, %6\n"
-                 "or a2, a2, %7\n"
+                 "or   a2, a2, %6\n"
                  "s32i a2, %5, 0\n"
-
-                 /* Set register bit to go into deep sleep */
-                 "l32i a2, %8, 0\n"
-                 "or   a2, a2, %9\n"
-                 "s32i a2, %8, 0\n"
                  "memw\n"
 
                  /* Wait for sleep reject interrupt (never finishes if successful) */
                  ".Lwaitsleep:"
                  "memw\n"
-                 "l32i a2, %10, 0\n"
-                 "and a2, a2, %11\n"
+                 "l32i a2, %7, 0\n"
+                 "and a2, a2, %8\n"
                  "beqz a2, .Lwaitsleep\n"
 
                  :
@@ -240,13 +231,10 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
                    "r" (DPORT_RTC_MEM_CRC_START), // %2
                    "r" (DPORT_RTC_FASTMEM_CRC_REG), // %3
                    "r" (RTC_MEMORY_CRC_REG), // %4
-                   "r" (RTC_CNTL_TIMER2_REG), // %5
-                   "r" (~RTC_CNTL_ULPCP_TOUCH_START_WAIT_M), // %6
-                   "r" (DEEP_SLEEP_TOUCH_WAIT_CYCLE << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S), // %7
-                   "r" (RTC_CNTL_STATE0_REG), // %8
-                   "r" (RTC_CNTL_SLEEP_EN), // %9
-                   "r" (RTC_CNTL_INT_RAW_REG), // %10
-                   "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %11
+                   "r" (RTC_CNTL_STATE0_REG), // %5
+                   "r" (RTC_CNTL_SLEEP_EN), // %6
+                   "r" (RTC_CNTL_INT_RAW_REG), // %7
+                   "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
                  : "a2" // working register
                  );
 
@@ -265,5 +253,9 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
         rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
         rtc_sleep_pd(pd_cfg);
     }
+
+    /* Recover default wait cycle for touch or COCPU after wakeup. */
+    REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
+
     return reject;
 }

components/soc/esp32s2/include/soc/rtc.h

@@ -113,6 +113,9 @@ extern "C" {
 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
 #define RTC_CNTL_SCK_DCAP_DEFAULT   255
 
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP    (0xFF)
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT     (0x10)
+
 /*
 set sleep_init default param
 */