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@@ -58,6 +58,7 @@ void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
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uint32_t irom_load_addr,
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uint32_t irom_size,
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uint32_t entry_addr);
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+static void update_flash_config(struct flash_hdr* pfhdr);
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void IRAM_ATTR call_start_cpu0()
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@@ -258,7 +259,7 @@ void bootloader_main()
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memset(&bs, 0, sizeof(bs));
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ESP_LOGI(TAG, "compile time " __TIME__ );
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- /* close watch dog here */
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+ /* disable watch dog here */
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REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
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SPIUnlock();
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@@ -269,6 +270,8 @@ void bootloader_main()
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print_flash_info(&fhdr);
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+ update_flash_config(&fhdr);
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+
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if (!load_partition_table(&bs, PARTITION_ADD)) {
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ESP_LOGE(TAG, "load partition table error!");
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return;
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@@ -364,7 +367,7 @@ void unpack_load_app(const partition_pos_t* partition)
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uint32_t irom_size = 0;
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/* Reload the RTC memory sections whenever a non-deepsleep reset
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- is occuring */
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+ is occurring */
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bool load_rtc_memory = rtc_get_reset_reason(0) != DEEPSLEEP_RESET;
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ESP_LOGD(TAG, "bin_header: %u %u %u %u %08x", image_header.magic,
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@@ -482,6 +485,36 @@ void IRAM_ATTR set_cache_and_start_app(
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(*entry)();
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}
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+static void update_flash_config(struct flash_hdr* pfhdr)
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+{
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+ uint32_t size;
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+ switch(pfhdr->spi_size) {
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+ case SPI_SIZE_1MB:
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+ size = 1;
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+ break;
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+ case SPI_SIZE_2MB:
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+ size = 2;
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+ break;
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+ case SPI_SIZE_4MB:
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+ size = 4;
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+ break;
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+ case SPI_SIZE_8MB:
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+ size = 8;
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+ break;
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+ case SPI_SIZE_16MB:
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+ size = 16;
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+ break;
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+ default:
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+ size = 2;
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+ }
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+ Cache_Read_Disable( 0 );
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+ // Set flash chip size
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+ SPIParamCfg(g_rom_flashchip.deviceId, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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+ // TODO: set mode
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+ // TODO: set frequency
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+ Cache_Flush(0);
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+ Cache_Read_Enable( 0 );
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+}
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void print_flash_info(struct flash_hdr* pfhdr)
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{
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