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@@ -53,8 +53,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
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#if CONFIG_IDF_TARGET_ESP32S2
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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- esp_rom_delay_us(20);
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- CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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@@ -75,8 +73,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
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#elif CONFIG_IDF_TARGET_ESP32S3
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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- esp_rom_delay_us(20);
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- CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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