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@@ -92,23 +92,28 @@ void IRAM_ATTR call_start_cpu0()
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//Clear bss
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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- /* completely reset MMU for both CPUs
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- (in case serial bootloader was running) */
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- Cache_Read_Disable(0);
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- Cache_Read_Disable(1);
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- Cache_Flush(0);
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- Cache_Flush(1);
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- mmu_init(0);
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- mmu_init(1);
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- /* (above steps probably unnecessary for most serial bootloader
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- usage, all that's absolutely needed is that we unmask DROM0
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- cache on the following two lines - normal ROM boot exits with
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- DROM0 cache unmasked, but serial bootloader exits with it
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- masked. However can't hurt to be thorough and reset
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- everything.)
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- */
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- REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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- REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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+ /* completely reset MMU for both CPUs
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+ (in case serial bootloader was running) */
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+ Cache_Read_Disable(0);
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+ Cache_Read_Disable(1);
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+ Cache_Flush(0);
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+ Cache_Flush(1);
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+ mmu_init(0);
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+ REG_SET_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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+ mmu_init(1);
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+ REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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+ /* (above steps probably unnecessary for most serial bootloader
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+ usage, all that's absolutely needed is that we unmask DROM0
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+ cache on the following two lines - normal ROM boot exits with
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+ DROM0 cache unmasked, but serial bootloader exits with it
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+ masked. However can't hurt to be thorough and reset
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+ everything.)
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+
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+ The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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+ necessary to work around a hardware bug.
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+ */
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+ REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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+ REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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bootloader_main();
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}
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