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We reserve 4KB Slow RTC memory to save RF calibation result and BT NVS data.
If not all these Slow RTC momory Blocks are used, we will open the other parts.
jack 9 lat temu
rodzic
commit
4e092be6d6

+ 2 - 2
components/esp32/include/rom/rtc.h

@@ -44,8 +44,8 @@ extern "C" {
   *************************************************************************************
   *************************************************************************************
   *     rtc memory addr         type    size            usage
   *     rtc memory addr         type    size            usage
   *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
   *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
-  *     0x3ff61000+SIZE_CP      Slow    6144-SIZE_CP
-  *     0x3ff62800              Slow    2048            Reserved
+  *     0x3ff61000+SIZE_CP      Slow    4096-SIZE_CP
+  *     0x3ff62800              Slow    4096            Reserved
   *
   *
   *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
   *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
   *
   *

+ 1 - 1
components/esp32/ld/esp32.ld

@@ -48,7 +48,7 @@ MEMORY
      Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
      Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
   */
   rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
   rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
-                                     len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
+                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
 }
 }
 
 
 /* Heap ends at top of dram0_0_seg */
 /* Heap ends at top of dram0_0_seg */