spi_flash: add unit tests for qio mode

components/spi_flash/test/test_esp_flash.c

@@ -579,7 +579,7 @@ static bool is_mxic_chip(esp_flash_t* chip)
     return (spi_flash_chip_mxic_probe(chip, flash_id)==ESP_OK);
 }
 
-static void test_toggle_qe(esp_flash_t* chip)
+IRAM_ATTR NOINLINE_ATTR static void test_toggle_qe(esp_flash_t* chip)
 {
     bool qe;
     if (chip == NULL) {
@@ -592,7 +592,7 @@ static void test_toggle_qe(esp_flash_t* chip)
     bool allow_failure = is_winbond_chip(chip) || is_mxic_chip(chip);
 
     for (int i = 0; i < 4; i ++) {
-        ESP_LOGI(TAG, "write qe: %d->%d", qe, !qe);
+        esp_rom_printf(DRAM_STR("write qe: %d->%d\n"), qe, !qe);
         qe = !qe;
         chip->read_mode = qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD;
         ret = esp_flash_set_io_mode(chip, qe);

components/spi_flash/test/test_spi_flash.c

@@ -14,6 +14,15 @@
 #include "esp_log.h"
 #include "esp_rom_sys.h"
 
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#endif
+
 struct flash_test_ctx {
     uint32_t offset;
     bool fail;
@@ -379,3 +388,31 @@ TEST_CASE("spi_flash deadlock with high priority busy-waiting task", "[spi_flash
     TEST_ASSERT_EQUAL_INT(uxTaskPriorityGet(NULL), UNITY_FREERTOS_PRIORITY);
 }
 #endif // portNUM_PROCESSORS > 1
+
+TEST_CASE("WEL is cleared after boot", "[spi_flash]")
+{
+    extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
+    uint32_t status;
+    esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status);
+
+    TEST_ASSERT((status & 0x2) == 0);
+}
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
+// ISSI chip has its QE bit on other chips' BP4, which may get cleared by accident
+TEST_CASE("rom unlock will not erase QE bit", "[spi_flash]")
+{
+    extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
+    uint32_t status;
+    printf("dev_id: %08X \n", g_rom_spiflash_chip.device_id);
+
+    if (((g_rom_spiflash_chip.device_id >> 16) & 0xff) != 0x9D) {
+        TEST_IGNORE_MESSAGE("This test is only for ISSI chips. Ignore.");
+    }
+    esp_rom_spiflash_unlock();
+    esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status);
+    printf("status: %08x\n", status);
+
+    TEST_ASSERT(status & 0x40);
+}
+#endif

tools/ci/config/target-test.yml

@@ -432,7 +432,7 @@ UT_001:
 
 UT_002:
   extends: .unit_test_template
-  parallel: 12
+  parallel: 13
   tags:
     - ESP32_IDF
     - UT_T1_1
@@ -586,7 +586,7 @@ UT_034:
 
 UT_035:
   extends: .unit_test_s2_template
-  parallel: 41
+  parallel: 43
   tags:
     - ESP32S2_IDF
     - UT_T1_1

tools/unit-test-app/configs/spi_flash_qio

@@ -0,0 +1,2 @@
+TEST_COMPONENTS=spi_flash
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y

tools/unit-test-app/configs/spi_flash_qio_s2

@@ -0,0 +1,3 @@
+TEST_COMPONENTS=spi_flash
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_IDF_TARGET="esp32s2"