efuse: Fixes eFuse timesettings issue on esp32c3

components/efuse/esp32c3/esp_efuse_utility.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -51,26 +51,44 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
     {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
 };
 
-#ifndef CONFIG_EFUSE_VIRTUAL
 // Update Efuse timing configuration
 static esp_err_t esp_efuse_set_timing(void)
 {
-    // efuse clock is fixed in ESP32-C3, so the ets_efuse_set_timing() function
-    // takes an argument for compatibility with older ROM functions but it's ignored.
-    int res = ets_efuse_set_timing(0);
-    assert(res == 0);
-    (void)res;
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190);
+    return ESP_OK;
+}
 
-    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x60);
+static void efuse_read(void)
+{
+    esp_efuse_set_timing();
+    REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE);
+    REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD);
 
-    return ESP_OK;
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { }
+    /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { }
+}
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+static void efuse_program(esp_efuse_block_t block)
+{
+    esp_efuse_set_timing();
+
+    REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE);
+
+    REG_WRITE(EFUSE_CMD_REG, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
+
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { };
+
+    ets_efuse_clear_program_registers();
+    efuse_read();
 }
 #endif // ifndef CONFIG_EFUSE_VIRTUAL
 
 // Efuse read operation: copies data from physical efuses to efuse read registers.
 void esp_efuse_utility_clear_program_registers(void)
 {
-    ets_efuse_read();
+    efuse_read();
     ets_efuse_clear_program_registers();
 }
 
@@ -104,7 +122,7 @@ void esp_efuse_utility_burn_chip(void)
                     }
                     int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
                     memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
-                    ets_efuse_program(num_block);
+                    efuse_program(num_block);
                     break;
                 }
             }

components/soc/esp32c3/include/soc/efuse_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_EFUSE_REG_H_
 #define _SOC_EFUSE_REG_H_
 
@@ -1867,6 +1859,9 @@ extern "C" {
 #define EFUSE_OP_CODE_V  0xFFFF
 #define EFUSE_OP_CODE_S  0
 
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_READ_OP_CODE  0x5aa5
+
 #define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
 /* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
 /*description: Indicates the number of error bits during programming BLOCK0.*/

tools/ci/check_copyright_ignore.txt

@@ -1634,7 +1634,6 @@ components/soc/esp32c3/include/soc/bb_reg.h
 components/soc/esp32c3/include/soc/boot_mode.h
 components/soc/esp32c3/include/soc/clkout_channel.h
 components/soc/esp32c3/include/soc/dport_access.h
-components/soc/esp32c3/include/soc/efuse_reg.h
 components/soc/esp32c3/include/soc/efuse_struct.h
 components/soc/esp32c3/include/soc/extmem_reg.h
 components/soc/esp32c3/include/soc/fe_reg.h