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@@ -106,31 +106,33 @@ static portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
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//with an incrementing cpu.intno value.
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static void insert_vector_desc(vector_desc_t *to_insert)
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{
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- vector_desc_t *vd=vector_desc_head;
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- vector_desc_t *prev=NULL;
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- while(vd!=NULL) {
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+ vector_desc_t *vd = vector_desc_head;
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+ vector_desc_t *prev = NULL;
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+ while(vd != NULL) {
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if (vd->cpu > to_insert->cpu) break;
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if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) break;
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- prev=vd;
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- vd=vd->next;
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+ prev = vd;
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+ vd = vd->next;
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}
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- if ((vector_desc_head==NULL) || (prev==NULL)) {
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+ if ((vector_desc_head == NULL) || (prev == NULL)) {
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//First item
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to_insert->next = vd;
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- vector_desc_head=to_insert;
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+ vector_desc_head = to_insert;
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} else {
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- prev->next=to_insert;
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- to_insert->next=vd;
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+ prev->next = to_insert;
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+ to_insert->next = vd;
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}
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}
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//Returns a vector_desc entry for an intno/cpu, or NULL if none exists.
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static vector_desc_t *find_desc_for_int(int intno, int cpu)
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{
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- vector_desc_t *vd=vector_desc_head;
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- while(vd!=NULL) {
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- if (vd->cpu==cpu && vd->intno==intno) break;
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- vd=vd->next;
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+ vector_desc_t *vd = vector_desc_head;
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+ while(vd != NULL) {
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+ if (vd->cpu == cpu && vd->intno == intno) {
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+ break;
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+ }
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+ vd = vd->next;
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}
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return vd;
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}
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@@ -140,13 +142,15 @@ static vector_desc_t *find_desc_for_int(int intno, int cpu)
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//it into the list. Returns NULL on malloc fail.
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static vector_desc_t *get_desc_for_int(int intno, int cpu)
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{
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- vector_desc_t *vd=find_desc_for_int(intno, cpu);
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- if (vd==NULL) {
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- vector_desc_t *newvd=heap_caps_malloc(sizeof(vector_desc_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
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- if (newvd==NULL) return NULL;
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+ vector_desc_t *vd = find_desc_for_int(intno, cpu);
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+ if (vd == NULL) {
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+ vector_desc_t *newvd = heap_caps_malloc(sizeof(vector_desc_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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+ if (newvd == NULL) {
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+ return NULL;
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+ }
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memset(newvd, 0, sizeof(vector_desc_t));
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- newvd->intno=intno;
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- newvd->cpu=cpu;
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+ newvd->intno = intno;
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+ newvd->cpu = cpu;
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insert_vector_desc(newvd);
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return newvd;
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} else {
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@@ -157,42 +161,52 @@ static vector_desc_t *get_desc_for_int(int intno, int cpu)
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//Returns a vector_desc entry for an source, the cpu parameter is used to tell GPIO_INT and GPIO_NMI from different CPUs
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static vector_desc_t * find_desc_for_source(int source, int cpu)
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{
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- vector_desc_t *vd=vector_desc_head;
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- while(vd!=NULL) {
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- if ( !(vd->flags & VECDESC_FL_SHARED) ) {
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- if ( vd->source == source && cpu == vd->cpu ) break;
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- } else if ( vd->cpu == cpu ) {
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+ vector_desc_t *vd = vector_desc_head;
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+ while(vd != NULL) {
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+ if (!(vd->flags & VECDESC_FL_SHARED)) {
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+ if (vd->source == source && cpu == vd->cpu) {
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+ break;
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+ }
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+ } else if (vd->cpu == cpu) {
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// check only shared vds for the correct cpu, otherwise skip
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bool found = false;
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shared_vector_desc_t *svd = vd->shared_vec_info;
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- assert(svd != NULL );
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+ assert(svd != NULL);
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while(svd) {
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- if ( svd->source == source ) {
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+ if (svd->source == source) {
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found = true;
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break;
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}
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svd = svd->next;
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}
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- if ( found ) break;
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+ if (found) {
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+ break;
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+ }
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}
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- vd=vd->next;
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+ vd = vd->next;
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}
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return vd;
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}
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esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
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{
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- if (intno>31) return ESP_ERR_INVALID_ARG;
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- if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG;
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+ if (intno>31) {
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+ return ESP_ERR_INVALID_ARG;
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+ }
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+ if (cpu >= SOC_CPU_CORES_NUM) {
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+ return ESP_ERR_INVALID_ARG;
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+ }
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portENTER_CRITICAL(&spinlock);
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- vector_desc_t *vd=get_desc_for_int(intno, cpu);
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- if (vd==NULL) {
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+ vector_desc_t *vd = get_desc_for_int(intno, cpu);
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+ if (vd == NULL) {
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portEXIT_CRITICAL(&spinlock);
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return ESP_ERR_NO_MEM;
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}
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- vd->flags=VECDESC_FL_SHARED;
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- if (is_int_ram) vd->flags|=VECDESC_FL_INIRAM;
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+ vd->flags = VECDESC_FL_SHARED;
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+ if (is_int_ram) {
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+ vd->flags |= VECDESC_FL_INIRAM;
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+ }
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portEXIT_CRITICAL(&spinlock);
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return ESP_OK;
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@@ -200,16 +214,20 @@ esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
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esp_err_t esp_intr_reserve(int intno, int cpu)
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{
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- if (intno>31) return ESP_ERR_INVALID_ARG;
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- if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG;
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+ if (intno > 31) {
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+ return ESP_ERR_INVALID_ARG;
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+ }
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+ if (cpu >= SOC_CPU_CORES_NUM) {
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+ return ESP_ERR_INVALID_ARG;
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+ }
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portENTER_CRITICAL(&spinlock);
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- vector_desc_t *vd=get_desc_for_int(intno, cpu);
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- if (vd==NULL) {
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+ vector_desc_t *vd = get_desc_for_int(intno, cpu);
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+ if (vd == NULL) {
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portEXIT_CRITICAL(&spinlock);
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return ESP_ERR_NO_MEM;
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}
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- vd->flags=VECDESC_FL_RESERVED;
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+ vd->flags = VECDESC_FL_RESERVED;
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portEXIT_CRITICAL(&spinlock);
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return ESP_OK;
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@@ -226,45 +244,45 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
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ALCHLOG("....Unusable: reserved");
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return false;
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}
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- if (intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_SPECIAL && force==-1) {
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+ if (intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_SPECIAL && force == -1) {
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ALCHLOG("....Unusable: special-purpose int");
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return false;
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}
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#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
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- //Check if the interrupt level is acceptable
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- if (!(flags&(1<<intr_desc.priority))) {
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- ALCHLOG("....Unusable: incompatible level");
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+ //Check if the interrupt priority is acceptable
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+ if (!(flags & (1 << intr_desc.priority))) {
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+ ALCHLOG("....Unusable: incompatible priority");
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return false;
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}
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//check if edge/level type matches what we want
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- if (((flags&ESP_INTR_FLAG_EDGE) && (intr_desc.type==ESP_CPU_INTR_TYPE_LEVEL)) ||
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- (((!(flags&ESP_INTR_FLAG_EDGE)) && (intr_desc.type==ESP_CPU_INTR_TYPE_EDGE)))) {
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+ if (((flags & ESP_INTR_FLAG_EDGE) && (intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL)) ||
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+ (((!(flags & ESP_INTR_FLAG_EDGE)) && (intr_desc.type == ESP_CPU_INTR_TYPE_EDGE)))) {
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ALCHLOG("....Unusable: incompatible trigger type");
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return false;
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}
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#endif
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//check if interrupt is reserved at runtime
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- if (vd->flags&VECDESC_FL_RESERVED) {
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+ if (vd->flags & VECDESC_FL_RESERVED) {
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ALCHLOG("....Unusable: reserved at runtime.");
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return false;
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}
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//Ints can't be both shared and non-shared.
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- assert(!((vd->flags&VECDESC_FL_SHARED)&&(vd->flags&VECDESC_FL_NONSHARED)));
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+ assert(!((vd->flags & VECDESC_FL_SHARED) && (vd->flags & VECDESC_FL_NONSHARED)));
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//check if interrupt already is in use by a non-shared interrupt
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- if (vd->flags&VECDESC_FL_NONSHARED) {
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+ if (vd->flags & VECDESC_FL_NONSHARED) {
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ALCHLOG("....Unusable: already in (non-shared) use.");
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return false;
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}
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// check shared interrupt flags
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- if (vd->flags&VECDESC_FL_SHARED ) {
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- if (flags&ESP_INTR_FLAG_SHARED) {
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- bool in_iram_flag=((flags&ESP_INTR_FLAG_IRAM)!=0);
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- bool desc_in_iram_flag=((vd->flags&VECDESC_FL_INIRAM)!=0);
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+ if (vd->flags & VECDESC_FL_SHARED) {
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+ if (flags & ESP_INTR_FLAG_SHARED) {
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+ bool in_iram_flag = ((flags & ESP_INTR_FLAG_IRAM) != 0);
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+ bool desc_in_iram_flag = ((vd->flags & VECDESC_FL_INIRAM) != 0);
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//Bail out if int is shared, but iram property doesn't match what we want.
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- if ((vd->flags&VECDESC_FL_SHARED) && (desc_in_iram_flag!=in_iram_flag)) {
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+ if ((vd->flags & VECDESC_FL_SHARED) && (desc_in_iram_flag != in_iram_flag)) {
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ALCHLOG("....Unusable: shared but iram prop doesn't match");
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return false;
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}
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@@ -289,7 +307,7 @@ static int get_available_int(int flags, int cpu, int force, int source)
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{
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int x;
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int best=-1;
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- int bestLevel=9;
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+ int bestPriority=9;
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int bestSharedCt=INT_MAX;
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//Default vector desc, for vectors not in the linked list
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@@ -297,32 +315,34 @@ static int get_available_int(int flags, int cpu, int force, int source)
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memset(&empty_vect_desc, 0, sizeof(vector_desc_t));
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//Level defaults to any low/med interrupt
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- if (!(flags&ESP_INTR_FLAG_LEVELMASK)) flags|=ESP_INTR_FLAG_LOWMED;
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+ if (!(flags & ESP_INTR_FLAG_LEVELMASK)) {
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+ flags |= ESP_INTR_FLAG_LOWMED;
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+ }
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ALCHLOG("get_available_int: try to find existing. Cpu: %d, Source: %d", cpu, source);
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vector_desc_t *vd = find_desc_for_source(source, cpu);
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- if ( vd ) {
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+ if (vd) {
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// if existing vd found, don't need to search any more.
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ALCHLOG("get_avalible_int: existing vd found. intno: %d", vd->intno);
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if ( force != -1 && force != vd->intno ) {
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ALCHLOG("get_avalible_int: intr forced but not matach existing. existing intno: %d, force: %d", vd->intno, force);
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- } else if ( !is_vect_desc_usable(vd, flags, cpu, force) ) {
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+ } else if (!is_vect_desc_usable(vd, flags, cpu, force)) {
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ALCHLOG("get_avalible_int: existing vd invalid.");
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} else {
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best = vd->intno;
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}
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return best;
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}
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- if (force!=-1) {
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+ if (force != -1) {
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ALCHLOG("get_available_int: try to find force. Cpu: %d, Source: %d, Force: %d", cpu, source, force);
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//if force assigned, don't need to search any more.
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vd = find_desc_for_int(force, cpu);
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- if (vd == NULL ) {
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+ if (vd == NULL) {
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//if existing vd not found, just check the default state for the intr.
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empty_vect_desc.intno = force;
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vd = &empty_vect_desc;
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}
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- if ( is_vect_desc_usable(vd, flags, cpu, force) ) {
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+ if (is_vect_desc_usable(vd, flags, cpu, force)) {
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best = vd->intno;
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} else {
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ALCHLOG("get_avalible_int: forced vd invalid.");
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@@ -332,53 +352,55 @@ static int get_available_int(int flags, int cpu, int force, int source)
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ALCHLOG("get_free_int: start looking. Current cpu: %d", cpu);
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//No allocated handlers as well as forced intr, iterate over the 32 possible interrupts
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- for (x=0; x<32; x++) {
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+ for (x = 0; x < 32; x++) {
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//Grab the vector_desc for this vector.
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- vd=find_desc_for_int(x, cpu);
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- if (vd==NULL) {
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+ vd = find_desc_for_int(x, cpu);
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+ if (vd == NULL) {
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empty_vect_desc.intno = x;
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- vd=&empty_vect_desc;
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+ vd = &empty_vect_desc;
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}
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esp_cpu_intr_desc_t intr_desc;
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esp_cpu_intr_get_desc(cpu, x, &intr_desc);
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- ALCHLOG("Int %d reserved %d level %d %s hasIsr %d",
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+ ALCHLOG("Int %d reserved %d priority %d %s hasIsr %d",
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x, intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD, intr_desc.priority,
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- intr_desc.type==ESP_CPU_INTR_TYPE_LEVEL?"LEVEL":"EDGE", esp_cpu_intr_has_handler(x));
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+ intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL? "LEVEL" : "EDGE", esp_cpu_intr_has_handler(x));
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- if ( !is_vect_desc_usable(vd, flags, cpu, force) ) continue;
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+ if (!is_vect_desc_usable(vd, flags, cpu, force)) {
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+ continue;
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+ }
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|
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- if (flags&ESP_INTR_FLAG_SHARED) {
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+ if (flags & ESP_INTR_FLAG_SHARED) {
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//We're allocating a shared int.
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//See if int already is used as a shared interrupt.
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- if (vd->flags&VECDESC_FL_SHARED) {
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+ if (vd->flags & VECDESC_FL_SHARED) {
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|
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//We can use this already-marked-as-shared interrupt. Count the already attached isrs in order to see
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//how useful it is.
|
|
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- int no=0;
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- shared_vector_desc_t *svdesc=vd->shared_vec_info;
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- while (svdesc!=NULL) {
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+ int no = 0;
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+ shared_vector_desc_t *svdesc = vd->shared_vec_info;
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+ while (svdesc != NULL) {
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no++;
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- svdesc=svdesc->next;
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+ svdesc = svdesc->next;
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}
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- if (no<bestSharedCt || bestLevel>intr_desc.priority) {
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+ if (no<bestSharedCt || bestPriority > intr_desc.priority) {
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|
|
//Seems like this shared vector is both okay and has the least amount of ISRs already attached to it.
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|
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- best=x;
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|
|
- bestSharedCt=no;
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|
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- bestLevel=intr_desc.priority;
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+ best = x;
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+ bestSharedCt = no;
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+ bestPriority = intr_desc.priority;
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|
ALCHLOG("...int %d more usable as a shared int: has %d existing vectors", x, no);
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} else {
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|
ALCHLOG("...worse than int %d", best);
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}
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|
|
} else {
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|
|
- if (best==-1) {
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+ if (best == -1) {
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|
|
//We haven't found a feasible shared interrupt yet. This one is still free and usable, even if
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//not marked as shared.
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|
|
//Remember it in case we don't find any other shared interrupt that qualifies.
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|
|
- if (bestLevel>intr_desc.priority) {
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|
|
- best=x;
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|
|
- bestLevel=intr_desc.priority;
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|
|
+ if (bestPriority > intr_desc.priority) {
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|
|
+ best = x;
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|
|
+ bestPriority = intr_desc.priority;
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|
|
ALCHLOG("...int %d usable as a new shared int", x);
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|
|
}
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|
|
} else {
|
|
|
@@ -387,9 +409,9 @@ static int get_available_int(int flags, int cpu, int force, int source)
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|
|
}
|
|
|
} else {
|
|
|
//Seems this interrupt is feasible. Select it and break out of the loop; no need to search further.
|
|
|
- if (bestLevel>intr_desc.priority) {
|
|
|
- best=x;
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|
|
- bestLevel=intr_desc.priority;
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|
|
+ if (bestPriority > intr_desc.priority) {
|
|
|
+ best = x;
|
|
|
+ bestPriority = intr_desc.priority;
|
|
|
} else {
|
|
|
ALCHLOG("...worse than int %d", best);
|
|
|
}
|
|
|
@@ -404,13 +426,13 @@ static int get_available_int(int flags, int cpu, int force, int source)
|
|
|
//Common shared isr handler. Chain-call all ISRs.
|
|
|
static void IRAM_ATTR shared_intr_isr(void *arg)
|
|
|
{
|
|
|
- vector_desc_t *vd=(vector_desc_t*)arg;
|
|
|
- shared_vector_desc_t *sh_vec=vd->shared_vec_info;
|
|
|
+ vector_desc_t *vd = (vector_desc_t*)arg;
|
|
|
+ shared_vector_desc_t *sh_vec = vd->shared_vec_info;
|
|
|
portENTER_CRITICAL_ISR(&spinlock);
|
|
|
while(sh_vec) {
|
|
|
if (!sh_vec->disabled) {
|
|
|
if ((sh_vec->statusreg == NULL) || (*sh_vec->statusreg & sh_vec->statusmask)) {
|
|
|
- traceISR_ENTER(sh_vec->source+ETS_INTERNAL_INTR_SOURCE_OFF);
|
|
|
+ traceISR_ENTER(sh_vec->source + ETS_INTERNAL_INTR_SOURCE_OFF);
|
|
|
sh_vec->isr(sh_vec->arg);
|
|
|
// check if we will return to scheduler or to interrupted task after ISR
|
|
|
if (!os_task_switch_is_pended(esp_cpu_get_core_id())) {
|
|
|
@@ -418,7 +440,7 @@ static void IRAM_ATTR shared_intr_isr(void *arg)
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
- sh_vec=sh_vec->next;
|
|
|
+ sh_vec = sh_vec->next;
|
|
|
}
|
|
|
portEXIT_CRITICAL_ISR(&spinlock);
|
|
|
}
|
|
|
@@ -427,9 +449,9 @@ static void IRAM_ATTR shared_intr_isr(void *arg)
|
|
|
//Common non-shared isr handler wrapper.
|
|
|
static void IRAM_ATTR non_shared_intr_isr(void *arg)
|
|
|
{
|
|
|
- non_shared_isr_arg_t *ns_isr_arg=(non_shared_isr_arg_t*)arg;
|
|
|
+ non_shared_isr_arg_t *ns_isr_arg = (non_shared_isr_arg_t*)arg;
|
|
|
portENTER_CRITICAL_ISR(&spinlock);
|
|
|
- traceISR_ENTER(ns_isr_arg->source+ETS_INTERNAL_INTR_SOURCE_OFF);
|
|
|
+ traceISR_ENTER(ns_isr_arg->source + ETS_INTERNAL_INTR_SOURCE_OFF);
|
|
|
// FIXME: can we call ISR and check os_task_switch_is_pended() after releasing spinlock?
|
|
|
// when CONFIG_APPTRACE_SV_ENABLE = 0 ISRs for non-shared IRQs are called without spinlock
|
|
|
ns_isr_arg->isr(ns_isr_arg->isr_arg);
|
|
|
@@ -446,16 +468,24 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
|
|
|
void *arg, intr_handle_t *ret_handle)
|
|
|
{
|
|
|
intr_handle_data_t *ret=NULL;
|
|
|
- int force=-1;
|
|
|
+ int force = -1;
|
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %u): checking args", esp_cpu_get_core_id());
|
|
|
//Shared interrupts should be level-triggered.
|
|
|
- if ((flags&ESP_INTR_FLAG_SHARED) && (flags&ESP_INTR_FLAG_EDGE)) return ESP_ERR_INVALID_ARG;
|
|
|
+ if ((flags & ESP_INTR_FLAG_SHARED) && (flags & ESP_INTR_FLAG_EDGE)) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
//You can't set an handler / arg for a non-C-callable interrupt.
|
|
|
- if ((flags&ESP_INTR_FLAG_HIGH) && (handler)) return ESP_ERR_INVALID_ARG;
|
|
|
+ if ((flags & ESP_INTR_FLAG_HIGH) && (handler)) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
//Shared ints should have handler and non-processor-local source
|
|
|
- if ((flags&ESP_INTR_FLAG_SHARED) && (!handler || source<0)) return ESP_ERR_INVALID_ARG;
|
|
|
+ if ((flags & ESP_INTR_FLAG_SHARED) && (!handler || source<0)) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
//Statusreg should have a mask
|
|
|
- if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
|
|
|
+ if (intrstatusreg && !intrstatusmask) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
//If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
|
|
|
//ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
|
|
|
//we need to make sure the interrupt is connected to the CPU0.
|
|
|
@@ -472,70 +502,84 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
|
|
|
}
|
|
|
|
|
|
//Default to prio 1 for shared interrupts. Default to prio 1, 2 or 3 for non-shared interrupts.
|
|
|
- if ((flags&ESP_INTR_FLAG_LEVELMASK)==0) {
|
|
|
- if (flags&ESP_INTR_FLAG_SHARED) {
|
|
|
- flags|=ESP_INTR_FLAG_LEVEL1;
|
|
|
+ if ((flags & ESP_INTR_FLAG_LEVELMASK) == 0) {
|
|
|
+ if (flags & ESP_INTR_FLAG_SHARED) {
|
|
|
+ flags |= ESP_INTR_FLAG_LEVEL1;
|
|
|
} else {
|
|
|
- flags|=ESP_INTR_FLAG_LOWMED;
|
|
|
+ flags |= ESP_INTR_FLAG_LOWMED;
|
|
|
}
|
|
|
}
|
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_alloc_intrstatus (cpu %u): Args okay. Resulting flags 0x%X", esp_cpu_get_core_id(), flags);
|
|
|
|
|
|
//Check 'special' interrupt sources. These are tied to one specific interrupt, so we
|
|
|
//have to force get_free_int to only look at that.
|
|
|
- if (source==ETS_INTERNAL_TIMER0_INTR_SOURCE) force=ETS_INTERNAL_TIMER0_INTR_NO;
|
|
|
- if (source==ETS_INTERNAL_TIMER1_INTR_SOURCE) force=ETS_INTERNAL_TIMER1_INTR_NO;
|
|
|
- if (source==ETS_INTERNAL_TIMER2_INTR_SOURCE) force=ETS_INTERNAL_TIMER2_INTR_NO;
|
|
|
- if (source==ETS_INTERNAL_SW0_INTR_SOURCE) force=ETS_INTERNAL_SW0_INTR_NO;
|
|
|
- if (source==ETS_INTERNAL_SW1_INTR_SOURCE) force=ETS_INTERNAL_SW1_INTR_NO;
|
|
|
- if (source==ETS_INTERNAL_PROFILING_INTR_SOURCE) force=ETS_INTERNAL_PROFILING_INTR_NO;
|
|
|
+ if (source == ETS_INTERNAL_TIMER0_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_TIMER0_INTR_NO;
|
|
|
+ }
|
|
|
+ if (source == ETS_INTERNAL_TIMER1_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_TIMER1_INTR_NO;
|
|
|
+ }
|
|
|
+ if (source == ETS_INTERNAL_TIMER2_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_TIMER2_INTR_NO;
|
|
|
+ }
|
|
|
+ if (source == ETS_INTERNAL_SW0_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_SW0_INTR_NO;
|
|
|
+ }
|
|
|
+ if (source == ETS_INTERNAL_SW1_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_SW1_INTR_NO;
|
|
|
+ }
|
|
|
+ if (source == ETS_INTERNAL_PROFILING_INTR_SOURCE) {
|
|
|
+ force = ETS_INTERNAL_PROFILING_INTR_NO;
|
|
|
+ }
|
|
|
|
|
|
//Allocate a return handle. If we end up not needing it, we'll free it later on.
|
|
|
- ret=heap_caps_malloc(sizeof(intr_handle_data_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
|
- if (ret==NULL) return ESP_ERR_NO_MEM;
|
|
|
+ ret = heap_caps_malloc(sizeof(intr_handle_data_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
|
|
+ if (ret == NULL) {
|
|
|
+ return ESP_ERR_NO_MEM;
|
|
|
+ }
|
|
|
|
|
|
portENTER_CRITICAL(&spinlock);
|
|
|
uint32_t cpu = esp_cpu_get_core_id();
|
|
|
//See if we can find an interrupt that matches the flags.
|
|
|
- int intr=get_available_int(flags, cpu, force, source);
|
|
|
- if (intr==-1) {
|
|
|
+ int intr = get_available_int(flags, cpu, force, source);
|
|
|
+ if (intr == -1) {
|
|
|
//None found. Bail out.
|
|
|
portEXIT_CRITICAL(&spinlock);
|
|
|
free(ret);
|
|
|
return ESP_ERR_NOT_FOUND;
|
|
|
}
|
|
|
//Get an int vector desc for int.
|
|
|
- vector_desc_t *vd=get_desc_for_int(intr, cpu);
|
|
|
- if (vd==NULL) {
|
|
|
+ vector_desc_t *vd = get_desc_for_int(intr, cpu);
|
|
|
+ if (vd == NULL) {
|
|
|
portEXIT_CRITICAL(&spinlock);
|
|
|
free(ret);
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
}
|
|
|
|
|
|
//Allocate that int!
|
|
|
- if (flags&ESP_INTR_FLAG_SHARED) {
|
|
|
+ if (flags & ESP_INTR_FLAG_SHARED) {
|
|
|
//Populate vector entry and add to linked list.
|
|
|
shared_vector_desc_t *sh_vec=malloc(sizeof(shared_vector_desc_t));
|
|
|
- if (sh_vec==NULL) {
|
|
|
+ if (sh_vec == NULL) {
|
|
|
portEXIT_CRITICAL(&spinlock);
|
|
|
free(ret);
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
}
|
|
|
memset(sh_vec, 0, sizeof(shared_vector_desc_t));
|
|
|
- sh_vec->statusreg=(uint32_t*)intrstatusreg;
|
|
|
- sh_vec->statusmask=intrstatusmask;
|
|
|
- sh_vec->isr=handler;
|
|
|
- sh_vec->arg=arg;
|
|
|
- sh_vec->next=vd->shared_vec_info;
|
|
|
- sh_vec->source=source;
|
|
|
- sh_vec->disabled=0;
|
|
|
- vd->shared_vec_info=sh_vec;
|
|
|
- vd->flags|=VECDESC_FL_SHARED;
|
|
|
+ sh_vec->statusreg = (uint32_t*)intrstatusreg;
|
|
|
+ sh_vec->statusmask = intrstatusmask;
|
|
|
+ sh_vec->isr = handler;
|
|
|
+ sh_vec->arg = arg;
|
|
|
+ sh_vec->next = vd->shared_vec_info;
|
|
|
+ sh_vec->source = source;
|
|
|
+ sh_vec->disabled = 0;
|
|
|
+ vd->shared_vec_info = sh_vec;
|
|
|
+ vd->flags |= VECDESC_FL_SHARED;
|
|
|
//(Re-)set shared isr handler to new value.
|
|
|
esp_cpu_intr_set_handler(intr, (esp_cpu_intr_handler_t)shared_intr_isr, vd);
|
|
|
} else {
|
|
|
//Mark as unusable for other interrupt sources. This is ours now!
|
|
|
- vd->flags=VECDESC_FL_NONSHARED;
|
|
|
+ vd->flags = VECDESC_FL_NONSHARED;
|
|
|
if (handler) {
|
|
|
#if CONFIG_APPTRACE_SV_ENABLE
|
|
|
non_shared_isr_arg_t *ns_isr_arg=malloc(sizeof(non_shared_isr_arg_t));
|
|
|
@@ -544,9 +588,9 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
|
|
|
free(ret);
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
}
|
|
|
- ns_isr_arg->isr=handler;
|
|
|
- ns_isr_arg->isr_arg=arg;
|
|
|
- ns_isr_arg->source=source;
|
|
|
+ ns_isr_arg->isr = handler;
|
|
|
+ ns_isr_arg->isr_arg = arg;
|
|
|
+ ns_isr_arg->source = source;
|
|
|
esp_cpu_intr_set_handler(intr, (esp_cpu_intr_handler_t)non_shared_intr_isr, ns_isr_arg);
|
|
|
#else
|
|
|
esp_cpu_intr_set_handler(intr, (esp_cpu_intr_handler_t)handler, arg);
|
|
|
@@ -557,29 +601,29 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
|
|
|
esp_cpu_intr_edge_ack(intr);
|
|
|
}
|
|
|
|
|
|
- vd->source=source;
|
|
|
+ vd->source = source;
|
|
|
}
|
|
|
- if (flags&ESP_INTR_FLAG_IRAM) {
|
|
|
- vd->flags|=VECDESC_FL_INIRAM;
|
|
|
- non_iram_int_mask[cpu]&=~(1<<intr);
|
|
|
+ if (flags & ESP_INTR_FLAG_IRAM) {
|
|
|
+ vd->flags |= VECDESC_FL_INIRAM;
|
|
|
+ non_iram_int_mask[cpu] &= ~(1<<intr);
|
|
|
} else {
|
|
|
- vd->flags&=~VECDESC_FL_INIRAM;
|
|
|
- non_iram_int_mask[cpu]|=(1<<intr);
|
|
|
+ vd->flags &= ~VECDESC_FL_INIRAM;
|
|
|
+ non_iram_int_mask[cpu] |= (1<<intr);
|
|
|
}
|
|
|
if (source>=0) {
|
|
|
esp_rom_route_intr_matrix(cpu, source, intr);
|
|
|
}
|
|
|
|
|
|
//Fill return handle data.
|
|
|
- ret->vector_desc=vd;
|
|
|
- ret->shared_vector_desc=vd->shared_vec_info;
|
|
|
+ ret->vector_desc = vd;
|
|
|
+ ret->shared_vector_desc = vd->shared_vec_info;
|
|
|
|
|
|
//Enable int at CPU-level;
|
|
|
ESP_INTR_ENABLE(intr);
|
|
|
|
|
|
//If interrupt has to be started disabled, do that now; ints won't be enabled for real until the end
|
|
|
//of the critical section.
|
|
|
- if (flags&ESP_INTR_FLAG_INTRDISABLED) {
|
|
|
+ if (flags & ESP_INTR_FLAG_INTRDISABLED) {
|
|
|
esp_intr_disable(ret);
|
|
|
}
|
|
|
|
|
|
@@ -598,8 +642,8 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
|
|
|
portEXIT_CRITICAL(&spinlock);
|
|
|
|
|
|
//Fill return handle if needed, otherwise free handle.
|
|
|
- if (ret_handle!=NULL) {
|
|
|
- *ret_handle=ret;
|
|
|
+ if (ret_handle != NULL) {
|
|
|
+ *ret_handle = ret;
|
|
|
} else {
|
|
|
free(ret);
|
|
|
}
|
|
|
@@ -620,7 +664,9 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
|
|
|
|
|
|
esp_err_t IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
|
|
|
{
|
|
|
- if (!handle) return ESP_ERR_INVALID_ARG;
|
|
|
+ if (!handle) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
vector_desc_t *vd = handle->vector_desc;
|
|
|
if (vd->flags & VECDESC_FL_SHARED) {
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
@@ -648,11 +694,13 @@ static void esp_intr_free_cb(void *arg)
|
|
|
esp_err_t esp_intr_free(intr_handle_t handle)
|
|
|
{
|
|
|
bool free_shared_vector=false;
|
|
|
- if (!handle) return ESP_ERR_INVALID_ARG;
|
|
|
+ if (!handle) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
|
//Assign this routine to the core where this interrupt is allocated on.
|
|
|
- if (handle->vector_desc->cpu!=esp_cpu_get_core_id()) {
|
|
|
+ if (handle->vector_desc->cpu != esp_cpu_get_core_id()) {
|
|
|
esp_err_t ret = esp_ipc_call_blocking(handle->vector_desc->cpu, &esp_intr_free_cb, (void *)handle);
|
|
|
return ret == ESP_OK ? ESP_OK : ESP_FAIL;
|
|
|
}
|
|
|
@@ -660,31 +708,36 @@ esp_err_t esp_intr_free(intr_handle_t handle)
|
|
|
|
|
|
portENTER_CRITICAL(&spinlock);
|
|
|
esp_intr_disable(handle);
|
|
|
- if (handle->vector_desc->flags&VECDESC_FL_SHARED) {
|
|
|
+ if (handle->vector_desc->flags & VECDESC_FL_SHARED) {
|
|
|
//Find and kill the shared int
|
|
|
- shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
|
|
|
- shared_vector_desc_t *prevsvd=NULL;
|
|
|
+ shared_vector_desc_t *svd = handle->vector_desc->shared_vec_info;
|
|
|
+ shared_vector_desc_t *prevsvd = NULL;
|
|
|
assert(svd); //should be something in there for a shared int
|
|
|
- while (svd!=NULL) {
|
|
|
- if (svd==handle->shared_vector_desc) {
|
|
|
+ while (svd != NULL) {
|
|
|
+ if (svd == handle->shared_vector_desc) {
|
|
|
//Found it. Now kill it.
|
|
|
if (prevsvd) {
|
|
|
- prevsvd->next=svd->next;
|
|
|
+ prevsvd->next = svd->next;
|
|
|
} else {
|
|
|
- handle->vector_desc->shared_vec_info=svd->next;
|
|
|
+ handle->vector_desc->shared_vec_info = svd->next;
|
|
|
}
|
|
|
free(svd);
|
|
|
break;
|
|
|
}
|
|
|
- prevsvd=svd;
|
|
|
- svd=svd->next;
|
|
|
+ prevsvd = svd;
|
|
|
+ svd = svd->next;
|
|
|
}
|
|
|
//If nothing left, disable interrupt.
|
|
|
- if (handle->vector_desc->shared_vec_info==NULL) free_shared_vector=true;
|
|
|
- ESP_EARLY_LOGV(TAG, "esp_intr_free: Deleting shared int: %s. Shared int is %s", svd?"not found or last one":"deleted", free_shared_vector?"empty now.":"still in use");
|
|
|
+ if (handle->vector_desc->shared_vec_info == NULL) {
|
|
|
+ free_shared_vector = true;
|
|
|
+ }
|
|
|
+ ESP_EARLY_LOGV(TAG,
|
|
|
+ "esp_intr_free: Deleting shared int: %s. Shared int is %s",
|
|
|
+ svd ? "not found or last one" : "deleted",
|
|
|
+ free_shared_vector ? "empty now." : "still in use");
|
|
|
}
|
|
|
|
|
|
- if ((handle->vector_desc->flags&VECDESC_FL_NONSHARED) || free_shared_vector) {
|
|
|
+ if ((handle->vector_desc->flags & VECDESC_FL_NONSHARED) || free_shared_vector) {
|
|
|
ESP_EARLY_LOGV(TAG, "esp_intr_free: Disabling int, killing handler");
|
|
|
#if CONFIG_APPTRACE_SV_ENABLE
|
|
|
if (!free_shared_vector) {
|
|
|
@@ -699,9 +752,9 @@ esp_err_t esp_intr_free(intr_handle_t handle)
|
|
|
//Theoretically, we could free the vector_desc... not sure if that's worth the few bytes of memory
|
|
|
//we save.(We can also not use the same exit path for empty shared ints anymore if we delete
|
|
|
//the desc.) For now, just mark it as free.
|
|
|
- handle->vector_desc->flags&=~(VECDESC_FL_NONSHARED|VECDESC_FL_RESERVED|VECDESC_FL_SHARED);
|
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+ handle->vector_desc->flags &= ~(VECDESC_FL_NONSHARED|VECDESC_FL_RESERVED|VECDESC_FL_SHARED);
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//Also kill non_iram mask bit.
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- non_iram_int_mask[handle->vector_desc->cpu]&=~(1<<(handle->vector_desc->intno));
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+ non_iram_int_mask[handle->vector_desc->cpu] &= ~(1<<(handle->vector_desc->intno));
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}
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portEXIT_CRITICAL(&spinlock);
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free(handle);
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@@ -731,11 +784,13 @@ int esp_intr_get_cpu(intr_handle_t handle)
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esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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{
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- if (!handle) return ESP_ERR_INVALID_ARG;
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+ if (!handle) {
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+ return ESP_ERR_INVALID_ARG;
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+ }
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portENTER_CRITICAL_SAFE(&spinlock);
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int source;
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if (handle->shared_vector_desc) {
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- handle->shared_vector_desc->disabled=0;
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+ handle->shared_vector_desc->disabled = 0;
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source=handle->shared_vector_desc->source;
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} else {
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source=handle->vector_desc->source;
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|
|
@@ -745,7 +800,9 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, handle->vector_desc->intno);
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|
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} else {
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//Re-enable using cpu int ena reg
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|
|
- if (handle->vector_desc->cpu!=esp_cpu_get_core_id()) return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
|
|
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+ if (handle->vector_desc->cpu != esp_cpu_get_core_id()) {
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|
|
+ return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
|
|
|
+ }
|
|
|
ESP_INTR_ENABLE(handle->vector_desc->intno);
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|
|
}
|
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
|
@@ -754,18 +811,20 @@ esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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|
|
|
|
esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
|
|
|
{
|
|
|
- if (!handle) return ESP_ERR_INVALID_ARG;
|
|
|
+ if (!handle) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
portENTER_CRITICAL_SAFE(&spinlock);
|
|
|
int source;
|
|
|
bool disabled = 1;
|
|
|
if (handle->shared_vector_desc) {
|
|
|
- handle->shared_vector_desc->disabled=1;
|
|
|
+ handle->shared_vector_desc->disabled = 1;
|
|
|
source=handle->shared_vector_desc->source;
|
|
|
|
|
|
- shared_vector_desc_t *svd=handle->vector_desc->shared_vec_info;
|
|
|
- assert( svd != NULL );
|
|
|
- while( svd ) {
|
|
|
- if ( svd->source == source && svd->disabled == 0 ) {
|
|
|
+ shared_vector_desc_t *svd = handle->vector_desc->shared_vec_info;
|
|
|
+ assert(svd != NULL);
|
|
|
+ while(svd) {
|
|
|
+ if (svd->source == source && svd->disabled == 0) {
|
|
|
disabled = 0;
|
|
|
break;
|
|
|
}
|
|
|
@@ -776,13 +835,13 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
|
|
|
}
|
|
|
|
|
|
if (source >= 0) {
|
|
|
- if ( disabled ) {
|
|
|
+ if (disabled) {
|
|
|
//Disable using int matrix
|
|
|
esp_rom_route_intr_matrix(handle->vector_desc->cpu, source, INT_MUX_DISABLED_INTNO);
|
|
|
}
|
|
|
} else {
|
|
|
//Disable using per-cpu regs
|
|
|
- if (handle->vector_desc->cpu!=esp_cpu_get_core_id()) {
|
|
|
+ if (handle->vector_desc->cpu != esp_cpu_get_core_id()) {
|
|
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
|
return ESP_ERR_INVALID_ARG; //Can only enable these ints on this cpu
|
|
|
}
|