Merge branch 'feature/efuse_support_for_esp32s3' into 'master'

efuse: Adds support for esp32-s3 chip

See merge request espressif/esp-idf!10491

components/bootloader_support/src/bootloader_efuse_esp32s3.c

@@ -16,6 +16,13 @@
 
 uint8_t bootloader_common_get_chip_revision(void)
 {
+    // should return the same value as esp_efuse_get_chip_ver()
     /* No other revisions for ESP32-S3 */
     return 0;
 }
+
+uint32_t bootloader_common_get_chip_ver_pkg(void)
+{
+    // should return the same value as esp_efuse_get_pkg_ver()
+    return 0;
+}

components/bootloader_support/src/esp32s3/flash_encrypt.c

@@ -210,7 +210,6 @@ static esp_err_t initialise_flash_encryption(void)
     ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
 #endif
 
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
 
     esp_err_t err = esp_efuse_batch_write_commit();

components/bootloader_support/src/esp32s3/secure_boot.c

@@ -284,7 +284,6 @@ esp_err_t esp_secure_boot_v2_permanently_enable(const esp_image_metadata_t *imag
 
     __attribute__((unused)) static const uint8_t enable = 1;
 
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
 
 #ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE

components/efuse/Kconfig

@@ -42,6 +42,6 @@ menu "eFuse Bit Manager"
         default 256 if EFUSE_CODE_SCHEME_COMPAT_NONE
         default 192 if EFUSE_CODE_SCHEME_COMPAT_3_4
         default 128 if EFUSE_CODE_SCHEME_COMPAT_REPEAT
-        default 256 if IDF_TARGET_ESP32S2
+        default 256 if !IDF_TARGET_ESP32
 
 endmenu

components/efuse/efuse_table_gen.py

@@ -353,8 +353,7 @@ class FuseDefinition(object):
         if idf_target == "esp32":
             if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3"]:
                 raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3")
-
-        if idf_target == "esp32s2":
+        else:
             if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3", "EFUSE_BLK4",
                               "EFUSE_BLK5", "EFUSE_BLK6", "EFUSE_BLK7", "EFUSE_BLK8", "EFUSE_BLK9",
                               "EFUSE_BLK10"]:
@@ -463,7 +462,7 @@ def main():
     global idf_target
 
     parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
-    parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32','esp32s2'], default='esp32')
+    parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3'], default='esp32')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--debug', help='Create header file with debug info', default=False, action="store_false")
     parser.add_argument('--info', help='Print info about range of used bits', default=False, action="store_true")

components/efuse/esp32s3/esp_efuse_table.c

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -11,3 +11,983 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License
+
+#include "sdkconfig.h"
+#include "esp_efuse.h"
+#include <assert.h>
+#include "esp_efuse_table.h"
+
+// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
+    {EFUSE_BLK0, 0, 1}, 	 // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
+};
+
+static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = {
+    {EFUSE_BLK0, 1, 1}, 	 // Write protection for DIS_RTC_RAM_BOOT,
+};
+
+static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
+    {EFUSE_BLK0, 2, 1}, 	 // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
+};
+
+static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
+    {EFUSE_BLK0, 3, 1}, 	 // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL,
+};
+
+static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 4, 1}, 	 // Write protection for SPI_BOOT_CRYPT_CNT,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 5, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE0,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 6, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE1,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 7, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // Write protection for key_purpose. KEY0,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // Write protection for key_purpose. KEY1,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // Write protection for key_purpose. KEY2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // Write protection for key_purpose. KEY3,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // Write protection for key_purpose. KEY4,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // Write protection for key_purpose. KEY5,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 15, 1}, 	 // Write protection for SECURE_BOOT_EN,
+};
+
+static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    {EFUSE_BLK0, 16, 1}, 	 // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
+};
+
+static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
+    {EFUSE_BLK0, 18, 1}, 	 // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
+};
+
+static const esp_efuse_desc_t WR_DIS_BLK1[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS,
+};
+
+static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // Write protection for EFUSE_BLK2.  SYS_DATA_PART1,
+};
+
+static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // Write protection for EFUSE_BLK3.  USER_DATA,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY0[] = {
+    {EFUSE_BLK0, 23, 1}, 	 // Write protection for EFUSE_BLK4.  KEY0,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY1[] = {
+    {EFUSE_BLK0, 24, 1}, 	 // Write protection for EFUSE_BLK5.  KEY1,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY2[] = {
+    {EFUSE_BLK0, 25, 1}, 	 // Write protection for EFUSE_BLK6.  KEY2,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY3[] = {
+    {EFUSE_BLK0, 26, 1}, 	 // Write protection for EFUSE_BLK7.  KEY3,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY4[] = {
+    {EFUSE_BLK0, 27, 1}, 	 // Write protection for EFUSE_BLK8.  KEY4,
+};
+
+static const esp_efuse_desc_t WR_DIS_KEY5[] = {
+    {EFUSE_BLK0, 28, 1}, 	 // Write protection for EFUSE_BLK9.  KEY5,
+};
+
+static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
+};
+
+static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 30, 1}, 	 // Write protection for USB_EXCHG_PINS,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY0[] = {
+    {EFUSE_BLK0, 32, 1}, 	 // Read protection for EFUSE_BLK4.  KEY0,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY1[] = {
+    {EFUSE_BLK0, 33, 1}, 	 // Read protection for EFUSE_BLK5.  KEY1,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY2[] = {
+    {EFUSE_BLK0, 34, 1}, 	 // Read protection for EFUSE_BLK6.  KEY2,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY3[] = {
+    {EFUSE_BLK0, 35, 1}, 	 // Read protection for EFUSE_BLK7.  KEY3,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY4[] = {
+    {EFUSE_BLK0, 36, 1}, 	 // Read protection for EFUSE_BLK8.  KEY4,
+};
+
+static const esp_efuse_desc_t RD_DIS_KEY5[] = {
+    {EFUSE_BLK0, 37, 1}, 	 // Read protection for EFUSE_BLK9.  KEY5,
+};
+
+static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
+};
+
+static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = {
+    {EFUSE_BLK0, 39, 1}, 	 // Disable boot from RTC RAM,
+};
+
+static const esp_efuse_desc_t DIS_ICACHE[] = {
+    {EFUSE_BLK0, 40, 1}, 	 // Disable Icache,
+};
+
+static const esp_efuse_desc_t DIS_DCACHE[] = {
+    {EFUSE_BLK0, 41, 1}, 	 // Disable Dcace,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
+    {EFUSE_BLK0, 42, 1}, 	 // Disable Icache in download mode include boot_mode 0 1 2 3 6 7,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = {
+    {EFUSE_BLK0, 43, 1}, 	 // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7,
+};
+
+static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
+    {EFUSE_BLK0, 44, 1}, 	 // Disable force chip go to download mode function,
+};
+
+static const esp_efuse_desc_t DIS_USB[] = {
+    {EFUSE_BLK0, 45, 1}, 	 // Disable USB function,
+};
+
+static const esp_efuse_desc_t DIS_CAN[] = {
+    {EFUSE_BLK0, 46, 1}, 	 // Disable CAN function,
+};
+
+static const esp_efuse_desc_t DIS_APP_CPU[] = {
+    {EFUSE_BLK0, 47, 1}, 	 // Disables APP CPU,
+};
+
+static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
+    {EFUSE_BLK0, 48, 3}, 	 // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral,
+};
+
+static const esp_efuse_desc_t HARD_DIS_JTAG[] = {
+    {EFUSE_BLK0, 51, 1}, 	 // Hardware disable jtag permanently disable jtag function,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    {EFUSE_BLK0, 52, 1}, 	 // Disable flash encrypt function,
+};
+
+static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
+    {EFUSE_BLK0, 57, 1}, 	 // Exchange D+ D- pins,
+};
+
+static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = {
+    {EFUSE_BLK0, 58, 1}, 	 // Enable external PHY,
+};
+
+static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = {
+    {EFUSE_BLK0, 59, 2}, 	 // Enables BTLC GPIO,
+};
+
+static const esp_efuse_desc_t VDD_SPI_XPD[] = {
+    {EFUSE_BLK0, 68, 1}, 	 // VDD_SPI regulator power up,
+};
+
+static const esp_efuse_desc_t VDD_SPI_TIEH[] = {
+    {EFUSE_BLK0, 69, 1}, 	 // VDD_SPI regulator tie high to vdda,
+};
+
+static const esp_efuse_desc_t VDD_SPI_FORCE[] = {
+    {EFUSE_BLK0, 70, 1}, 	 // Force using eFuse configuration of VDD_SPI,
+};
+
+static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
+    {EFUSE_BLK0, 80, 2}, 	 // Select RTC WDT time out threshold,
+};
+
+static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
+    {EFUSE_BLK0, 82, 3}, 	 // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
+    {EFUSE_BLK0, 85, 1}, 	 // Enable revoke first secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
+    {EFUSE_BLK0, 86, 1}, 	 // Enable revoke second secure boot key,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
+    {EFUSE_BLK0, 87, 1}, 	 // Enable revoke third secure boot key,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 88, 4}, 	 // Key0 purpose,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 92, 4}, 	 // Key1 purpose,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 96, 4}, 	 // Key2 purpose,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 100, 4}, 	 // Key3 purpose,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 104, 4}, 	 // Key4 purpose,
+};
+
+static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 108, 4}, 	 // Key5 purpose,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
+    {EFUSE_BLK0, 116, 1}, 	 // Secure boot enable,
+};
+
+static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    {EFUSE_BLK0, 117, 1}, 	 // Enable aggressive secure boot revoke,
+};
+
+static const esp_efuse_desc_t FLASH_TPUW[] = {
+    {EFUSE_BLK0, 124, 4}, 	 // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
+};
+
+static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 128, 1}, 	 // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
+};
+
+static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
+    {EFUSE_BLK0, 129, 1}, 	 // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
+};
+
+static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
+    {EFUSE_BLK0, 130, 1}, 	 // 0: UART0. 1: UART1,
+};
+
+static const esp_efuse_desc_t FLASH_ECC_MODE[] = {
+    {EFUSE_BLK0, 131, 1}, 	 // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode,
+};
+
+static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
+    {EFUSE_BLK0, 132, 1}, 	 // Disable download through USB,
+};
+
+static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
+    {EFUSE_BLK0, 133, 1}, 	 // Enable security download mode,
+};
+
+static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
+    {EFUSE_BLK0, 134, 2}, 	 // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.,
+};
+
+static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
+    {EFUSE_BLK0, 136, 1}, 	 // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
+};
+
+static const esp_efuse_desc_t FLASH_TYPE[] = {
+    {EFUSE_BLK0, 137, 1}, 	 // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
+};
+
+static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
+    {EFUSE_BLK0, 138, 2}, 	 // Sets the size of flash page,
+};
+
+static const esp_efuse_desc_t FLASH_ECC_EN[] = {
+    {EFUSE_BLK0, 140, 1}, 	 // Enables ECC in Flash boot mode,
+};
+
+static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
+    {EFUSE_BLK0, 141, 1}, 	 // Force ROM code to send a resume command during SPI boot,
+};
+
+static const esp_efuse_desc_t SECURE_VERSION[] = {
+    {EFUSE_BLK0, 142, 16}, 	 // Secure version for anti-rollback,
+};
+
+static const esp_efuse_desc_t MAC_FACTORY[] = {
+    {EFUSE_BLK1, 40, 8}, 	 // Factory MAC addr [0],
+    {EFUSE_BLK1, 32, 8}, 	 // Factory MAC addr [1],
+    {EFUSE_BLK1, 24, 8}, 	 // Factory MAC addr [2],
+    {EFUSE_BLK1, 16, 8}, 	 // Factory MAC addr [3],
+    {EFUSE_BLK1, 8, 8}, 	 // Factory MAC addr [4],
+    {EFUSE_BLK1, 0, 8}, 	 // Factory MAC addr [5],
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
+    {EFUSE_BLK1, 48, 6}, 	 // SPI_PAD_configure CLK,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
+    {EFUSE_BLK1, 54, 6}, 	 // SPI_PAD_configure Q(D1),
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
+    {EFUSE_BLK1, 60, 6}, 	 // SPI_PAD_configure D(D0),
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
+    {EFUSE_BLK1, 66, 6}, 	 // SPI_PAD_configure CS,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
+    {EFUSE_BLK1, 72, 6}, 	 // SPI_PAD_configure HD(D3),
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
+    {EFUSE_BLK1, 78, 6}, 	 // SPI_PAD_configure WP(D2),
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
+    {EFUSE_BLK1, 84, 6}, 	 // SPI_PAD_configure DQS,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
+    {EFUSE_BLK1, 90, 6}, 	 // SPI_PAD_configure D4,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
+    {EFUSE_BLK1, 96, 6}, 	 // SPI_PAD_configure D5,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
+    {EFUSE_BLK1, 102, 6}, 	 // SPI_PAD_configure D6,
+};
+
+static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
+    {EFUSE_BLK1, 108, 6}, 	 // SPI_PAD_configure D7,
+};
+
+static const esp_efuse_desc_t WAFER_VERSION[] = {
+    {EFUSE_BLK1, 114, 3}, 	 // WAFER version 0:A,
+};
+
+static const esp_efuse_desc_t PKG_VERSION[] = {
+    {EFUSE_BLK1, 117, 4}, 	 // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32,
+};
+
+static const esp_efuse_desc_t BLOCK1_VERSION[] = {
+    {EFUSE_BLK1, 121, 3}, 	 // BLOCK1 efuse version 0:No calibration 1:With calibration,
+};
+
+static const esp_efuse_desc_t SYS_DATA_PART0[] = {
+    {EFUSE_BLK1, 126, 66}, 	 // System configuration,
+};
+
+static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
+    {EFUSE_BLK2, 0, 128}, 	 // Optional unique 128-bit ID,
+};
+
+static const esp_efuse_desc_t BLOCK2_VERSION[] = {
+    {EFUSE_BLK2, 132, 3}, 	 // Version of BLOCK2,
+};
+
+static const esp_efuse_desc_t USER_DATA[] = {
+    {EFUSE_BLK3, 0, 256}, 	 // User data,
+};
+
+static const esp_efuse_desc_t KEY0[] = {
+    {EFUSE_BLK4, 0, 256}, 	 // Key0 or user data,
+};
+
+static const esp_efuse_desc_t KEY1[] = {
+    {EFUSE_BLK5, 0, 256}, 	 // Key1 or user data,
+};
+
+static const esp_efuse_desc_t KEY2[] = {
+    {EFUSE_BLK6, 0, 256}, 	 // Key2 or user data,
+};
+
+static const esp_efuse_desc_t KEY3[] = {
+    {EFUSE_BLK7, 0, 256}, 	 // Key3 or user data,
+};
+
+static const esp_efuse_desc_t KEY4[] = {
+    {EFUSE_BLK8, 0, 256}, 	 // Key4 or user data,
+};
+
+static const esp_efuse_desc_t KEY5[] = {
+    {EFUSE_BLK9, 0, 256}, 	 // Key5 or user data,
+};
+
+static const esp_efuse_desc_t SYS_DATA_PART2[] = {
+    {EFUSE_BLK10, 0, 256}, 	 // System configuration,
+};
+
+
+
+
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
+    &WR_DIS_RD_DIS[0],    		// Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = {
+    &WR_DIS_DIS_RTC_RAM_BOOT[0],    		// Write protection for DIS_RTC_RAM_BOOT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
+    &WR_DIS_GROUP_1[0],    		// Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
+    &WR_DIS_GROUP_2[0],    		// Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
+    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// Write protection for SPI_BOOT_CRYPT_CNT
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
+    &WR_DIS_KEY0_PURPOSE[0],    		// Write protection for key_purpose. KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
+    &WR_DIS_KEY1_PURPOSE[0],    		// Write protection for key_purpose. KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
+    &WR_DIS_KEY2_PURPOSE[0],    		// Write protection for key_purpose. KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
+    &WR_DIS_KEY3_PURPOSE[0],    		// Write protection for key_purpose. KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
+    &WR_DIS_KEY4_PURPOSE[0],    		// Write protection for key_purpose. KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
+    &WR_DIS_KEY5_PURPOSE[0],    		// Write protection for key_purpose. KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
+    &WR_DIS_SECURE_BOOT_EN[0],    		// Write protection for SECURE_BOOT_EN
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
+    &WR_DIS_GROUP_3[0],    		// Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
+    &WR_DIS_BLK1[0],    		// Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
+    &WR_DIS_SYS_DATA_PART1[0],    		// Write protection for EFUSE_BLK2.  SYS_DATA_PART1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
+    &WR_DIS_USER_DATA[0],    		// Write protection for EFUSE_BLK3.  USER_DATA
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
+    &WR_DIS_KEY0[0],    		// Write protection for EFUSE_BLK4.  KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
+    &WR_DIS_KEY1[0],    		// Write protection for EFUSE_BLK5.  KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
+    &WR_DIS_KEY2[0],    		// Write protection for EFUSE_BLK6.  KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
+    &WR_DIS_KEY3[0],    		// Write protection for EFUSE_BLK7.  KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
+    &WR_DIS_KEY4[0],    		// Write protection for EFUSE_BLK8.  KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
+    &WR_DIS_KEY5[0],    		// Write protection for EFUSE_BLK9.  KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
+    &WR_DIS_SYS_DATA_PART2[0],    		// Write protection for EFUSE_BLK10. SYS_DATA_PART2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
+    &WR_DIS_USB_EXCHG_PINS[0],    		// Write protection for USB_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
+    &RD_DIS_KEY0[0],    		// Read protection for EFUSE_BLK4.  KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
+    &RD_DIS_KEY1[0],    		// Read protection for EFUSE_BLK5.  KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
+    &RD_DIS_KEY2[0],    		// Read protection for EFUSE_BLK6.  KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
+    &RD_DIS_KEY3[0],    		// Read protection for EFUSE_BLK7.  KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
+    &RD_DIS_KEY4[0],    		// Read protection for EFUSE_BLK8.  KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
+    &RD_DIS_KEY5[0],    		// Read protection for EFUSE_BLK9.  KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
+    &RD_DIS_SYS_DATA_PART2[0],    		// Read protection for EFUSE_BLK10. SYS_DATA_PART2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = {
+    &DIS_RTC_RAM_BOOT[0],    		// Disable boot from RTC RAM
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
+    &DIS_ICACHE[0],    		// Disable Icache
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = {
+    &DIS_DCACHE[0],    		// Disable Dcace
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
+    &DIS_DOWNLOAD_ICACHE[0],    		// Disable Icache in download mode include boot_mode 0 1 2 3 6 7
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = {
+    &DIS_DOWNLOAD_DCACHE[0],    		// Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
+    &DIS_FORCE_DOWNLOAD[0],    		// Disable force chip go to download mode function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
+    &DIS_USB[0],    		// Disable USB function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
+    &DIS_CAN[0],    		// Disable CAN function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[] = {
+    &DIS_APP_CPU[0],    		// Disables APP CPU
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
+    &SOFT_DIS_JTAG[0],    		// Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = {
+    &HARD_DIS_JTAG[0],    		// Hardware disable jtag permanently disable jtag function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// Disable flash encrypt function
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
+    &USB_EXCHG_PINS[0],    		// Exchange D+ D- pins
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = {
+    &USB_EXT_PHY_ENABLE[0],    		// Enable external PHY
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = {
+    &BTLC_GPIO_ENABLE[0],    		// Enables BTLC GPIO
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = {
+    &VDD_SPI_XPD[0],    		// VDD_SPI regulator power up
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = {
+    &VDD_SPI_TIEH[0],    		// VDD_SPI regulator tie high to vdda
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = {
+    &VDD_SPI_FORCE[0],    		// Force using eFuse configuration of VDD_SPI
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
+    &WDT_DELAY_SEL[0],    		// Select RTC WDT time out threshold
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
+    &SPI_BOOT_CRYPT_CNT[0],    		// SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
+    &SECURE_BOOT_KEY_REVOKE0[0],    		// Enable revoke first secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
+    &SECURE_BOOT_KEY_REVOKE1[0],    		// Enable revoke second secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
+    &SECURE_BOOT_KEY_REVOKE2[0],    		// Enable revoke third secure boot key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
+    &KEY_PURPOSE_0[0],    		// Key0 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
+    &KEY_PURPOSE_1[0],    		// Key1 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
+    &KEY_PURPOSE_2[0],    		// Key2 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
+    &KEY_PURPOSE_3[0],    		// Key3 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
+    &KEY_PURPOSE_4[0],    		// Key4 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
+    &KEY_PURPOSE_5[0],    		// Key5 purpose
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
+    &SECURE_BOOT_EN[0],    		// Secure boot enable
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Enable aggressive secure boot revoke
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
+    &FLASH_TPUW[0],    		// Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
+    &DIS_DOWNLOAD_MODE[0],    		// Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
+    &DIS_LEGACY_SPI_BOOT[0],    		// Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
+    &UART_PRINT_CHANNEL[0],    		// 0: UART0. 1: UART1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = {
+    &FLASH_ECC_MODE[0],    		// Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
+    &DIS_USB_DOWNLOAD_MODE[0],    		// Disable download through USB
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// Enable security download mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
+    &UART_PRINT_CONTROL[0],    		// b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
+    &PIN_POWER_SELECTION[0],    		// GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
+    &FLASH_TYPE[0],    		// Connected Flash interface type. 0: 4 data line. 1: 8 data line
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
+    &FLASH_PAGE_SIZE[0],    		// Sets the size of flash page
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
+    &FLASH_ECC_EN[0],    		// Enables ECC in Flash boot mode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
+    &FORCE_SEND_RESUME[0],    		// Force ROM code to send a resume command during SPI boot
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
+    &SECURE_VERSION[0],    		// Secure version for anti-rollback
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
+    &MAC_FACTORY[0],    		// Factory MAC addr [0]
+    &MAC_FACTORY[1],    		// Factory MAC addr [1]
+    &MAC_FACTORY[2],    		// Factory MAC addr [2]
+    &MAC_FACTORY[3],    		// Factory MAC addr [3]
+    &MAC_FACTORY[4],    		// Factory MAC addr [4]
+    &MAC_FACTORY[5],    		// Factory MAC addr [5]
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
+    &SPI_PAD_CONFIG_CLK[0],    		// SPI_PAD_configure CLK
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
+    &SPI_PAD_CONFIG_Q_D1[0],    		// SPI_PAD_configure Q(D1)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
+    &SPI_PAD_CONFIG_D_D0[0],    		// SPI_PAD_configure D(D0)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
+    &SPI_PAD_CONFIG_CS[0],    		// SPI_PAD_configure CS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
+    &SPI_PAD_CONFIG_HD_D3[0],    		// SPI_PAD_configure HD(D3)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
+    &SPI_PAD_CONFIG_WP_D2[0],    		// SPI_PAD_configure WP(D2)
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
+    &SPI_PAD_CONFIG_DQS[0],    		// SPI_PAD_configure DQS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
+    &SPI_PAD_CONFIG_D4[0],    		// SPI_PAD_configure D4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
+    &SPI_PAD_CONFIG_D5[0],    		// SPI_PAD_configure D5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
+    &SPI_PAD_CONFIG_D6[0],    		// SPI_PAD_configure D6
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
+    &SPI_PAD_CONFIG_D7[0],    		// SPI_PAD_configure D7
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
+    &WAFER_VERSION[0],    		// WAFER version 0:A
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
+    &PKG_VERSION[0],    		// Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
+    &BLOCK1_VERSION[0],    		// BLOCK1 efuse version 0:No calibration 1:With calibration
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = {
+    &SYS_DATA_PART0[0],    		// System configuration
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
+    &OPTIONAL_UNIQUE_ID[0],    		// Optional unique 128-bit ID
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
+    &BLOCK2_VERSION[0],    		// Version of BLOCK2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
+    &USER_DATA[0],    		// User data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
+    &KEY0[0],    		// Key0 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
+    &KEY1[0],    		// Key1 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
+    &KEY2[0],    		// Key2 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
+    &KEY3[0],    		// Key3 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
+    &KEY4[0],    		// Key4 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
+    &KEY5[0],    		// Key5 or user data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
+    &SYS_DATA_PART2[0],    		// System configuration
+    NULL
+};
+

components/efuse/esp32s3/esp_efuse_table.csv

@@ -0,0 +1,146 @@
+# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1..256)   |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...      |            |            |        #
+#                   |     EFUSE_BLK10)|            |            |        #
+##########################################################################
+# !!!!!!!!!!! #
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" 
+# this will generate new source files, next rebuild all the sources.
+# !!!!!!!!!!! #
+
+# EFUSE_RD_REPEAT_DATA BLOCK #
+##############################
+    # EFUSE_RD_WR_DIS_REG #
+        # EFUSE_WR_DIS [WR_DIS 0 32] #
+            WR_DIS_RD_DIS,                EFUSE_BLK0,   0,    1,      Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
+            WR_DIS_DIS_RTC_RAM_BOOT,      EFUSE_BLK0,   1,    1,      Write protection for DIS_RTC_RAM_BOOT
+            WR_DIS_GROUP_1,               EFUSE_BLK0,   2,    1,      Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+            WR_DIS_GROUP_2,               EFUSE_BLK0,   3,    1,      Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
+            WR_DIS_SPI_BOOT_CRYPT_CNT,    EFUSE_BLK0,   4,    1,      Write protection for SPI_BOOT_CRYPT_CNT
+            WR_DIS_SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0,  5,    1,      Write protection for SECURE_BOOT_KEY_REVOKE0
+            WR_DIS_SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0,  6,    1,      Write protection for SECURE_BOOT_KEY_REVOKE1
+            WR_DIS_SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0,  7,    1,      Write protection for SECURE_BOOT_KEY_REVOKE2
+            WR_DIS_KEY0_PURPOSE,          EFUSE_BLK0,   8,    1,      Write protection for key_purpose. KEY0
+            WR_DIS_KEY1_PURPOSE,          EFUSE_BLK0,   9,    1,      Write protection for key_purpose. KEY1
+            WR_DIS_KEY2_PURPOSE,          EFUSE_BLK0,  10,    1,      Write protection for key_purpose. KEY2
+            WR_DIS_KEY3_PURPOSE,          EFUSE_BLK0,  11,    1,      Write protection for key_purpose. KEY3
+            WR_DIS_KEY4_PURPOSE,          EFUSE_BLK0,  12,    1,      Write protection for key_purpose. KEY4
+            WR_DIS_KEY5_PURPOSE,          EFUSE_BLK0,  13,    1,      Write protection for key_purpose. KEY5
+            WR_DIS_SECURE_BOOT_EN,        EFUSE_BLK0,  15,    1,      Write protection for SECURE_BOOT_EN
+            WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1,   Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
+            WR_DIS_GROUP_3,               EFUSE_BLK0,  18,    1,      Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
+            WR_DIS_BLK1,                  EFUSE_BLK0,  20,    1,      Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
+            WR_DIS_SYS_DATA_PART1,        EFUSE_BLK0,  21,    1,      Write protection for EFUSE_BLK2.  SYS_DATA_PART1
+            WR_DIS_USER_DATA,             EFUSE_BLK0,  22,    1,      Write protection for EFUSE_BLK3.  USER_DATA
+            WR_DIS_KEY0,                  EFUSE_BLK0,  23,    1,      Write protection for EFUSE_BLK4.  KEY0
+            WR_DIS_KEY1,                  EFUSE_BLK0,  24,    1,      Write protection for EFUSE_BLK5.  KEY1
+            WR_DIS_KEY2,                  EFUSE_BLK0,  25,    1,      Write protection for EFUSE_BLK6.  KEY2
+            WR_DIS_KEY3,                  EFUSE_BLK0,  26,    1,      Write protection for EFUSE_BLK7.  KEY3
+            WR_DIS_KEY4,                  EFUSE_BLK0,  27,    1,      Write protection for EFUSE_BLK8.  KEY4
+            WR_DIS_KEY5,                  EFUSE_BLK0,  28,    1,      Write protection for EFUSE_BLK9.  KEY5
+            WR_DIS_SYS_DATA_PART2,        EFUSE_BLK0,  29,    1,      Write protection for EFUSE_BLK10. SYS_DATA_PART2
+            WR_DIS_USB_EXCHG_PINS,        EFUSE_BLK0,  30,    1,      Write protection for USB_EXCHG_PINS
+
+    # EFUSE_RD_REPEAT_DATA0_REG #
+        # [RD_DIS 0 7] #
+            RD_DIS_KEY0,                  EFUSE_BLK0,   32,    1,     Read protection for EFUSE_BLK4.  KEY0
+            RD_DIS_KEY1,                  EFUSE_BLK0,   33,    1,     Read protection for EFUSE_BLK5.  KEY1
+            RD_DIS_KEY2,                  EFUSE_BLK0,   34,    1,     Read protection for EFUSE_BLK6.  KEY2
+            RD_DIS_KEY3,                  EFUSE_BLK0,   35,    1,     Read protection for EFUSE_BLK7.  KEY3
+            RD_DIS_KEY4,                  EFUSE_BLK0,   36,    1,     Read protection for EFUSE_BLK8.  KEY4
+            RD_DIS_KEY5,                  EFUSE_BLK0,   37,    1,     Read protection for EFUSE_BLK9.  KEY5
+            RD_DIS_SYS_DATA_PART2,        EFUSE_BLK0,   38,    1,     Read protection for EFUSE_BLK10. SYS_DATA_PART2
+        DIS_RTC_RAM_BOOT,                 EFUSE_BLK0,   39,    1,     Disable boot from RTC RAM
+        DIS_ICACHE,                       EFUSE_BLK0,   40,    1,     Disable Icache
+        DIS_DCACHE,                       EFUSE_BLK0,   41,    1,     Disable Dcace
+        DIS_DOWNLOAD_ICACHE,              EFUSE_BLK0,   42,    1,     Disable Icache in download mode include boot_mode 0 1 2 3 6 7
+        DIS_DOWNLOAD_DCACHE,              EFUSE_BLK0,   43,    1,     Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
+        DIS_FORCE_DOWNLOAD,               EFUSE_BLK0,   44,    1,     Disable force chip go to download mode function
+        DIS_USB,                          EFUSE_BLK0,   45,    1,     Disable USB function
+        DIS_CAN,                          EFUSE_BLK0,   46,    1,     Disable CAN function
+        DIS_APP_CPU,                      EFUSE_BLK0,   47,    1,     Disables APP CPU
+        SOFT_DIS_JTAG,                    EFUSE_BLK0,   48,    3,     Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
+        HARD_DIS_JTAG,                    EFUSE_BLK0,   51,    1,     Hardware disable jtag permanently disable jtag function
+        DIS_DOWNLOAD_MANUAL_ENCRYPT,      EFUSE_BLK0,   52,    1,     Disable flash encrypt function, other than SPI/Legacy SPI boot mode
+        USB_EXCHG_PINS,                   EFUSE_BLK0,   57,    1,     Exchange D+ D- pins
+        USB_EXT_PHY_ENABLE,               EFUSE_BLK0,   58,    1,     Enable external PHY
+        BTLC_GPIO_ENABLE,                 EFUSE_BLK0,   59,    2,     Enables BTLC GPIO
+
+    # EFUSE_RD_REPEAT_DATA1_REG #
+        VDD_SPI_XPD,                      EFUSE_BLK0,   68,    1,     VDD_SPI regulator power up
+        VDD_SPI_TIEH,                     EFUSE_BLK0,   69,    1,     VDD_SPI regulator tie high to vdda
+        VDD_SPI_FORCE,                    EFUSE_BLK0,   70,    1,     Force using eFuse configuration of VDD_SPI
+        WDT_DELAY_SEL,                    EFUSE_BLK0,   80,    2,     Select RTC WDT time out threshold
+        SPI_BOOT_CRYPT_CNT,               EFUSE_BLK0,   82,    3,     SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
+        SECURE_BOOT_KEY_REVOKE0,          EFUSE_BLK0,   85,    1,     Enable revoke first secure boot key
+        SECURE_BOOT_KEY_REVOKE1,          EFUSE_BLK0,   86,    1,     Enable revoke second secure boot key
+        SECURE_BOOT_KEY_REVOKE2,          EFUSE_BLK0,   87,    1,     Enable revoke third secure boot key
+        KEY_PURPOSE_0,                    EFUSE_BLK0,   88,    4,     Key0 purpose
+        KEY_PURPOSE_1,                    EFUSE_BLK0,   92,    4,     Key1 purpose
+
+    # EFUSE_RD_REPEAT_DATA2_REG #
+        KEY_PURPOSE_2,                    EFUSE_BLK0,   96,    4,     Key2 purpose
+        KEY_PURPOSE_3,                    EFUSE_BLK0,  100,    4,     Key3 purpose
+        KEY_PURPOSE_4,                    EFUSE_BLK0,  104,    4,     Key4 purpose
+        KEY_PURPOSE_5,                    EFUSE_BLK0,  108,    4,     Key5 purpose
+        SECURE_BOOT_EN,                   EFUSE_BLK0,  116,    1,     Secure boot enable
+        SECURE_BOOT_AGGRESSIVE_REVOKE,    EFUSE_BLK0,  117,    1,     Enable aggressive secure boot revoke
+        FLASH_TPUW,                       EFUSE_BLK0,  124,    4,     Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
+
+    # EFUSE_RD_REPEAT_DATA3_REG #
+        DIS_DOWNLOAD_MODE,                EFUSE_BLK0,  128,    1,     Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
+        DIS_LEGACY_SPI_BOOT,              EFUSE_BLK0,  129,    1,     Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
+        UART_PRINT_CHANNEL,               EFUSE_BLK0,  130,    1,     0: UART0. 1: UART1
+        FLASH_ECC_MODE,                   EFUSE_BLK0,  131,    1,     Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
+        DIS_USB_DOWNLOAD_MODE,            EFUSE_BLK0,  132,    1,     Disable download through USB
+        ENABLE_SECURITY_DOWNLOAD,         EFUSE_BLK0,  133,    1,     Enable security download mode
+        UART_PRINT_CONTROL,               EFUSE_BLK0,  134,    2,     b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
+        PIN_POWER_SELECTION,              EFUSE_BLK0,  136,    1,     GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
+        FLASH_TYPE,                       EFUSE_BLK0,  137,    1,     Connected Flash interface type. 0: 4 data line. 1: 8 data line
+        FLASH_PAGE_SIZE,                  EFUSE_BLK0,  138,    2,     Sets the size of flash page
+        FLASH_ECC_EN,                     EFUSE_BLK0,  140,    1,     Enables ECC in Flash boot mode
+        FORCE_SEND_RESUME,                EFUSE_BLK0,  141,    1,     Force ROM code to send a resume command during SPI boot
+        SECURE_VERSION,                   EFUSE_BLK0,  142,   16,     Secure version for anti-rollback
+
+    # EFUSE_RD_REPEAT_DATA4_REG #
+
+
+# MAC_SPI_8M_SYS BLOCK#
+#######################
+    MAC_FACTORY,                          EFUSE_BLK1,   40,    8,     Factory MAC addr [0]
+    ,                                     EFUSE_BLK1,   32,    8,     Factory MAC addr [1]
+    ,                                     EFUSE_BLK1,   24,    8,     Factory MAC addr [2]
+    ,                                     EFUSE_BLK1,   16,    8,     Factory MAC addr [3]
+    ,                                     EFUSE_BLK1,    8,    8,     Factory MAC addr [4]
+    ,                                     EFUSE_BLK1,    0,    8,     Factory MAC addr [5]
+    SPI_PAD_CONFIG_CLK,                   EFUSE_BLK1,   48,    6,     SPI_PAD_configure CLK
+    SPI_PAD_CONFIG_Q_D1,                  EFUSE_BLK1,   54,    6,     SPI_PAD_configure Q(D1)
+    SPI_PAD_CONFIG_D_D0,                  EFUSE_BLK1,   60,    6,     SPI_PAD_configure D(D0)
+    SPI_PAD_CONFIG_CS,                    EFUSE_BLK1,   66,    6,     SPI_PAD_configure CS
+    SPI_PAD_CONFIG_HD_D3,                 EFUSE_BLK1,   72,    6,     SPI_PAD_configure HD(D3)
+    SPI_PAD_CONFIG_WP_D2,                 EFUSE_BLK1,   78,    6,     SPI_PAD_configure WP(D2)
+    SPI_PAD_CONFIG_DQS,                   EFUSE_BLK1,   84,    6,     SPI_PAD_configure DQS
+    SPI_PAD_CONFIG_D4,                    EFUSE_BLK1,   90,    6,     SPI_PAD_configure D4
+    SPI_PAD_CONFIG_D5,                    EFUSE_BLK1,   96,    6,     SPI_PAD_configure D5
+    SPI_PAD_CONFIG_D6,                    EFUSE_BLK1,  102,    6,     SPI_PAD_configure D6
+    SPI_PAD_CONFIG_D7,                    EFUSE_BLK1,  108,    6,     SPI_PAD_configure D7
+    WAFER_VERSION,                        EFUSE_BLK1,  114,    3,     WAFER version 0:A
+    PKG_VERSION,                          EFUSE_BLK1,  117,    4,     Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
+    BLOCK1_VERSION,                       EFUSE_BLK1,  121,    3,     BLOCK1 efuse version 0:No calibration 1:With calibration
+    SYS_DATA_PART0,                       EFUSE_BLK1,  126,   66,     System configuration
+
+# SYS_DATA_PART1 BLOCK# - System configuration
+#######################
+    OPTIONAL_UNIQUE_ID,                   EFUSE_BLK2,    0,  128,     Optional unique 128-bit ID
+    BLOCK2_VERSION,                       EFUSE_BLK2,  132,    3,     Version of BLOCK2
+
+################
+USER_DATA,                                EFUSE_BLK3,    0,  256,     User data
+KEY0,                                     EFUSE_BLK4,    0,  256,     Key0 or user data
+KEY1,                                     EFUSE_BLK5,    0,  256,     Key1 or user data
+KEY2,                                     EFUSE_BLK6,    0,  256,     Key2 or user data
+KEY3,                                     EFUSE_BLK7,    0,  256,     Key3 or user data
+KEY4,                                     EFUSE_BLK8,    0,  256,     Key4 or user data
+KEY5,                                     EFUSE_BLK9,    0,  256,     Key5 or user data
+SYS_DATA_PART2,                           EFUSE_BLK10,   0,  256,     System configuration

components/efuse/esp32s3/include/esp_efuse_table.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -16,6 +16,14 @@
 extern "C" {
 #endif
 
+
+// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
@@ -59,12 +67,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
 extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
@@ -85,12 +94,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TINY_BASIC[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
@@ -105,9 +116,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];

components/efuse/include/esp32s3/esp_efuse.h

@@ -56,6 +56,14 @@ typedef enum {
     EFUSE_BLK_MAX
 } esp_efuse_block_t;
 
+struct esp_efuse_desc_s;
+
+/**
+ * @brief Given a key block in the range EFUSE_BLK_KEY0..EFUSE_BLK_KEY5, return
+ * efuse field for setting the key purpose
+ */
+const struct esp_efuse_desc_s **esp_efuse_get_purpose_field(esp_efuse_block_t block);
+
 /**
  * @brief Type of coding scheme
  */

components/efuse/src/esp32s3/esp_efuse_api.c

@@ -11,3 +11,95 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
+
+#include "esp_efuse.h"
+#include "esp_efuse_utility.h"
+#include "soc/efuse_periph.h"
+#include "assert.h"
+#include "sdkconfig.h"
+#include "esp_efuse_table.h"
+
+const static char *TAG = "efuse";
+
+// Sets a write protection for the whole block.
+esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk)
+{
+    if (blk == EFUSE_BLK1) {
+       return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK1, 1);
+    } else if (blk == EFUSE_BLK2) {
+       return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, 1);
+    } else if (blk == EFUSE_BLK3) {
+       return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, 1);
+    } else if (blk == EFUSE_BLK4) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY0, 1);
+    } else if (blk == EFUSE_BLK5) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY1, 1);
+    } else if (blk == EFUSE_BLK6) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY2, 1);
+    } else if (blk == EFUSE_BLK7) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY3, 1);
+    } else if (blk == EFUSE_BLK8) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY4, 1);
+    } else if (blk == EFUSE_BLK9) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY5, 1);
+    } else if (blk == EFUSE_BLK10) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART2, 1);
+    }
+    return ESP_ERR_NOT_SUPPORTED;
+}
+
+// read protect for blk.
+esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk)
+{
+    if (blk == EFUSE_BLK4) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY0, 1);
+    } else if (blk == EFUSE_BLK5) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY1, 1);
+    } else if (blk == EFUSE_BLK6) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY2, 1);
+    } else if (blk == EFUSE_BLK7) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY3, 1);
+    } else if (blk == EFUSE_BLK8) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY4, 1);
+    } else if (blk == EFUSE_BLK9) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY5, 1);
+    } else if (blk == EFUSE_BLK10) {
+        return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_SYS_DATA_PART2, 1);
+    }
+    return ESP_ERR_NOT_SUPPORTED;
+}
+
+// get efuse coding_scheme.
+esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk)
+{
+    esp_efuse_coding_scheme_t scheme;
+    if (blk == EFUSE_BLK0) {
+        scheme = EFUSE_CODING_SCHEME_NONE;
+    } else {
+        scheme = EFUSE_CODING_SCHEME_RS;
+    }
+    ESP_EARLY_LOGD(TAG, "coding scheme %d", scheme);
+    return scheme;
+}
+
+
+const esp_efuse_desc_t **esp_efuse_get_purpose_field(esp_efuse_block_t block)
+{
+    switch(block) {
+    case EFUSE_BLK_KEY0:
+        return ESP_EFUSE_KEY_PURPOSE_0;
+    case EFUSE_BLK_KEY1:
+        return ESP_EFUSE_KEY_PURPOSE_1;
+    case EFUSE_BLK_KEY2:
+        return ESP_EFUSE_KEY_PURPOSE_2;
+    case EFUSE_BLK_KEY3:
+        return ESP_EFUSE_KEY_PURPOSE_3;
+    case EFUSE_BLK_KEY4:
+        return ESP_EFUSE_KEY_PURPOSE_4;
+    case EFUSE_BLK_KEY5:
+        return ESP_EFUSE_KEY_PURPOSE_5;
+    default:
+        return NULL;
+    }
+}
+

components/efuse/src/esp32s3/esp_efuse_fields.c

@@ -11,3 +11,66 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
+
+#include "esp_efuse.h"
+#include "esp_efuse_utility.h"
+#include "esp_efuse_table.h"
+#include "stdlib.h"
+#include "esp_types.h"
+#include "assert.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "soc/efuse_periph.h"
+#include "bootloader_random.h"
+#include "sys/param.h"
+
+const static char *TAG = "efuse";
+
+// Contains functions that provide access to efuse fields which are often used in IDF.
+
+// Returns chip version from efuse
+uint8_t esp_efuse_get_chip_ver(void)
+{
+    // should return the same value as bootloader_common_get_chip_revision()
+    uint32_t chip_ver = 0;
+    // TODO: ESP32S2 does not have this field
+    return chip_ver;
+}
+
+// Returns chip package from efuse
+uint32_t esp_efuse_get_pkg_ver(void)
+{
+    uint32_t pkg_ver = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, 4);
+    return pkg_ver;
+}
+
+void esp_efuse_write_random_key(uint32_t blk_wdata0_reg)
+{
+    uint32_t buf[8];
+    uint8_t raw[24];
+
+    bootloader_fill_random(buf, sizeof(buf));
+
+    ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg);
+    for (int i = 0; i < 8; i++) {
+        ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]);
+        REG_WRITE(blk_wdata0_reg + 4*i, buf[i]);
+    }
+    bzero(buf, sizeof(buf));
+    bzero(raw, sizeof(raw));
+}
+
+esp_err_t esp_efuse_disable_rom_download_mode(void)
+{
+    return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
+}
+
+esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
+{
+    if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
+}
+

components/efuse/src/esp32s3/esp_efuse_utility.c

@@ -11,3 +11,128 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
+
+#include "esp_efuse_utility.h"
+#include "soc/efuse_periph.h"
+#include "esp32s3/clk.h"
+#include "esp_log.h"
+#include "assert.h"
+#include "sdkconfig.h"
+#include <sys/param.h>
+#include "esp32s3/rom/efuse.h"
+
+static const char *TAG = "efuse";
+
+#ifdef CONFIG_EFUSE_VIRTUAL
+extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
+#endif // CONFIG_EFUSE_VIRTUAL
+
+/*Range addresses to read blocks*/
+const esp_efuse_range_addr_t range_read_addr_blocks[] = {
+    {EFUSE_RD_WR_DIS_REG,       EFUSE_RD_REPEAT_DATA4_REG},      // range address of EFUSE_BLK0  REPEAT
+    {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG},      // range address of EFUSE_BLK1  MAC_SPI_8M
+    {EFUSE_RD_SYS_PART1_DATA0_REG,    EFUSE_RD_SYS_PART1_DATA7_REG},         // range address of EFUSE_BLK2  SYS_DATA
+    {EFUSE_RD_USR_DATA0_REG,    EFUSE_RD_USR_DATA7_REG},         // range address of EFUSE_BLK3  USR_DATA
+    {EFUSE_RD_KEY0_DATA0_REG,   EFUSE_RD_KEY0_DATA7_REG},        // range address of EFUSE_BLK4  KEY0
+    {EFUSE_RD_KEY1_DATA0_REG,   EFUSE_RD_KEY1_DATA7_REG},        // range address of EFUSE_BLK5  KEY1
+    {EFUSE_RD_KEY2_DATA0_REG,   EFUSE_RD_KEY2_DATA7_REG},        // range address of EFUSE_BLK6  KEY2
+    {EFUSE_RD_KEY3_DATA0_REG,   EFUSE_RD_KEY3_DATA7_REG},        // range address of EFUSE_BLK7  KEY3
+    {EFUSE_RD_KEY4_DATA0_REG,   EFUSE_RD_KEY4_DATA7_REG},        // range address of EFUSE_BLK8  KEY4
+    {EFUSE_RD_KEY5_DATA0_REG,   EFUSE_RD_KEY5_DATA7_REG},        // range address of EFUSE_BLK9  KEY5
+    {EFUSE_RD_SYS_PART2_DATA0_REG,   EFUSE_RD_SYS_PART2_DATA7_REG}         // range address of EFUSE_BLK10 KEY6
+};
+
+static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
+
+/*Range addresses to write blocks (it is not real regs, it is buffer) */
+const esp_efuse_range_addr_t range_write_addr_blocks[] = {
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
+};
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+// Update Efuse timing configuration
+static esp_err_t esp_efuse_set_timing(void)
+{
+    uint32_t clock_hz = esp_clk_apb_freq();
+    return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK;
+}
+#endif // ifndef CONFIG_EFUSE_VIRTUAL
+
+// Efuse read operation: copies data from physical efuses to efuse read registers.
+void esp_efuse_utility_clear_program_registers(void)
+{
+    ets_efuse_read();
+    ets_efuse_clear_program_registers();
+}
+
+// Burn values written to the efuse write registers
+void esp_efuse_utility_burn_efuses(void)
+{
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
+    for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
+        int subblock = 0;
+        for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+            virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
+        }
+    }
+#else
+    if (esp_efuse_set_timing() != ESP_OK) {
+        ESP_LOGE(TAG, "Efuse fields are not burnt");
+    } else {
+        // Permanently update values written to the efuse write registers
+        for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block) != 0) {
+                    if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+                        uint8_t block_rs[12];
+                        ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
+                        memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
+                    }
+                    int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
+                    memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
+                    ets_efuse_program(num_block);
+                    break;
+                }
+            }
+        }
+    }
+#endif // CONFIG_EFUSE_VIRTUAL
+    esp_efuse_utility_reset();
+}
+
+// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
+// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
+// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
+// They will be filled during the burn operation.
+esp_err_t esp_efuse_utility_apply_new_coding_scheme()
+{
+    // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
+    for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
+        if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block)) {
+                    int num_reg = 0;
+                    for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
+                        if (esp_efuse_utility_read_reg(num_block, num_reg)) {
+                            ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
+                            return ESP_ERR_CODING;
+                        }
+                    }
+                    break;
+                }
+            }
+        }
+    }
+    return ESP_OK;
+}

components/efuse/test/test_efuse.c

@@ -19,8 +19,6 @@
 #include "esp_rom_efuse.h"
 #include "bootloader_common.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 static const char* TAG = "efuse_test";
 
 static void test_read_blob(void)
@@ -538,7 +536,7 @@ TEST_CASE("Test esp_efuse_read_block esp_efuse_write_block functions", "[efuse]"
         printf("EFUSE_CODING_SCHEME_REPEAT\n");
         count_useful_reg = 4;
     }
-#elif CONFIG_IDF_TARGET_ESP32S2
+#else
     if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
         printf("EFUSE_CODING_SCHEME_RS\n");
         count_useful_reg = 8;
@@ -601,7 +599,7 @@ TEST_CASE("Test Bits are not empty. Write operation is forbidden", "[efuse]")
             printf("EFUSE_CODING_SCHEME_REPEAT\n");
             count_useful_reg = 4;
         }
-#elif CONFIG_IDF_TARGET_ESP32S2
+#else
         if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
             printf("EFUSE_CODING_SCHEME_RS\n");
             if (num_block == EFUSE_BLK1) {
@@ -769,7 +767,7 @@ TEST_CASE("Test a write/read protection", "[efuse]")
     test_rp(EFUSE_BLK1, ESP_EFUSE_RD_DIS_BLK1, true);
     test_rp(EFUSE_BLK2, ESP_EFUSE_RD_DIS_BLK2, false);
     test_rp(EFUSE_BLK3, ESP_EFUSE_RD_DIS_BLK3, false);
-#elif defined(CONFIG_IDF_TARGET_ESP32S2)
+#else
     test_wp(EFUSE_BLK2, ESP_EFUSE_WR_DIS_SYS_DATA_PART1);
     test_wp(EFUSE_BLK3, ESP_EFUSE_WR_DIS_USER_DATA);
 
@@ -778,8 +776,6 @@ TEST_CASE("Test a write/read protection", "[efuse]")
     test_rp(EFUSE_BLK4, ESP_EFUSE_RD_DIS_KEY0, true);
     test_rp(EFUSE_BLK5, ESP_EFUSE_RD_DIS_KEY1, false);
     test_rp(EFUSE_BLK6, ESP_EFUSE_RD_DIS_KEY2, false);
-#else
-#error New chip not supported!
 #endif
 
     esp_efuse_utility_debug_dump_blocks();
@@ -811,7 +807,7 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
         TEST_ASSERT_EQUAL_HEX8_ARRAY(new_mac, mac, sizeof(new_mac));
         esp_efuse_utility_debug_dump_blocks();
     }
-#ifdef CONFIG_IDF_TARGET_ESP32S2
+#ifndef CONFIG_IDF_TARGET_ESP32
     ESP_LOGI(TAG, "2. Write KEY3");
     uint8_t key[32] = {0};
     TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
@@ -834,7 +830,7 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
         TEST_ASSERT_EQUAL_INT(0, key[i]);
     }
     esp_efuse_utility_debug_dump_blocks();
-#endif // CONFIG_IDF_TARGET_ESP32S2
+#endif // not CONFIG_IDF_TARGET_ESP32
     ESP_LOGI(TAG, "4. Write SECURE_VERSION");
     int max_bits = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION);
     size_t read_sec_version;
@@ -860,5 +856,3 @@ TEST_CASE("Test chip_revision APIs return the same value", "[efuse]")
     esp_efuse_utility_update_virt_blocks();
     TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision());
 }
-
-#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)

components/soc/soc/esp32s3/include/soc/efuse_reg.h

@@ -19,402 +19,2233 @@ extern "C" {
 
 #include "soc.h"
 
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/* EFUSE_RD_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
+#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x000)
+/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Set this bit to disable eFuse programming.*/
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x004)
+/* EFUSE_VDD_SPI_DREFH : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: SPI regulator high voltage reference.*/
+#define EFUSE_VDD_SPI_DREFH  0x00000003
+#define EFUSE_VDD_SPI_DREFH_M  ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S))
+#define EFUSE_VDD_SPI_DREFH_V  0x3
+#define EFUSE_VDD_SPI_DREFH_S  30
+/* EFUSE_VDD_SPI_MODECURLIM : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: SPI regulator switches current limit mode.*/
+#define EFUSE_VDD_SPI_MODECURLIM  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_M  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_V  0x1
+#define EFUSE_VDD_SPI_MODECURLIM_S  29
+/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: Enable btlc gpio.*/
+#define EFUSE_BTLC_GPIO_ENABLE  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_M  ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S))
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/* EFUSE_USB_EXT_PHY_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable external PHY.*/
+#define EFUSE_USB_EXT_PHY_ENABLE  (BIT(26))
+#define EFUSE_USB_EXT_PHY_ENABLE_M  (BIT(26))
+#define EFUSE_USB_EXT_PHY_ENABLE_V  0x1
+#define EFUSE_USB_EXT_PHY_ENABLE_S  26
+/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to exchange D+ and D- pins.*/
+#define EFUSE_USB_EXCHG_PINS  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  25
+/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: Controls single-end input threshold vrefl  0.8 V to 1.04 V with
+ step of 80 mV  stored in eFuse.*/
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  23
+/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: Controls single-end input threshold vrefh  1.76 V to 2 V with
+ step of 80 mV  stored in eFuse.*/
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to disable flash encrypt function (except in SPI/HSPI/Legacy_SPI
+ boot mode).*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
+#define EFUSE_HARD_DIS_JTAG  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_M  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_V  0x1
+#define EFUSE_HARD_DIS_JTAG_S  19
+/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: Set these bits to disable JTAG in the soft way (odd number 1
+ means disable). JTAG can be enabled in HMAC module.*/
+#define EFUSE_SOFT_DIS_JTAG  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
+#define EFUSE_SOFT_DIS_JTAG_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/* EFUSE_DIS_APP_CPU : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to disable app cpu.*/
+#define EFUSE_DIS_APP_CPU  (BIT(15))
+#define EFUSE_DIS_APP_CPU_M  (BIT(15))
+#define EFUSE_DIS_APP_CPU_V  0x1
+#define EFUSE_DIS_APP_CPU_S  15
+/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to disable CAN function.*/
+#define EFUSE_DIS_CAN  (BIT(14))
+#define EFUSE_DIS_CAN_M  (BIT(14))
+#define EFUSE_DIS_CAN_V  0x1
+#define EFUSE_DIS_CAN_S  14
+/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to disable USB function.*/
+#define EFUSE_DIS_USB  (BIT(13))
+#define EFUSE_DIS_USB_M  (BIT(13))
+#define EFUSE_DIS_USB_V  0x1
+#define EFUSE_DIS_USB_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to disable the function that forces chip into download mode.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0]
+ is 0  1  2  3  6  7).*/
+#define EFUSE_DIS_DOWNLOAD_DCACHE  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to disable Icache in download mode (boot_mode[3:0]
+ is 0  1  2  3  6  7).*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to disable Dcache.*/
+#define EFUSE_DIS_DCACHE  (BIT(9))
+#define EFUSE_DIS_DCACHE_M  (BIT(9))
+#define EFUSE_DIS_DCACHE_V  0x1
+#define EFUSE_DIS_DCACHE_S  9
+/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to disable Icache.*/
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to disable boot from RTC RAM.*/
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: Set this bit to disable reading from BlOCK4-10.*/
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x008)
+/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Purpose of Key1. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: Purpose of Key0. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking third secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking second secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking first secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of
+ 1: enable. even number of 1: disable.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Selects RTC watchdog timeout threshold.*/
+#define EFUSE_WAT_DELAY_SEL  0x00000003
+#define EFUSE_WAT_DELAY_SEL_M  ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S))
+#define EFUSE_WAT_DELAY_SEL_V  0x3
+#define EFUSE_WAT_DELAY_SEL_S  16
+/* EFUSE_VDD_SPI_DCAP : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: Prevents SPI regulator from overshoot.*/
+#define EFUSE_VDD_SPI_DCAP  0x00000003
+#define EFUSE_VDD_SPI_DCAP_M  ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S))
+#define EFUSE_VDD_SPI_DCAP_V  0x3
+#define EFUSE_VDD_SPI_DCAP_S  14
+/* EFUSE_VDD_SPI_INIT : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/
+#define EFUSE_VDD_SPI_INIT  0x00000003
+#define EFUSE_VDD_SPI_INIT_M  ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S))
+#define EFUSE_VDD_SPI_INIT_V  0x3
+#define EFUSE_VDD_SPI_INIT_S  12
+/* EFUSE_VDD_SPI_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: Tunes the current limit threshold of SPI regulator when tieh=0
+  about 800 mA/(8+d).*/
+#define EFUSE_VDD_SPI_DCURLIM  0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_M  ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S))
+#define EFUSE_VDD_SPI_DCURLIM_V  0x7
+#define EFUSE_VDD_SPI_DCURLIM_S  9
+/* EFUSE_VDD_SPI_ENCURLIM : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set SPI regulator to 1 to enable output current limit.*/
+#define EFUSE_VDD_SPI_ENCURLIM  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_M  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_V  0x1
+#define EFUSE_VDD_SPI_ENCURLIM_S  8
+/* EFUSE_VDD_SPI_EN_INIT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set SPI regulator to 0 to configure init[1:0]=0.*/
+#define EFUSE_VDD_SPI_EN_INIT  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_M  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_V  0x1
+#define EFUSE_VDD_SPI_EN_INIT_S  7
+/* EFUSE_VDD_SPI_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/
+#define EFUSE_VDD_SPI_FORCE  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_M  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_V  0x1
+#define EFUSE_VDD_SPI_FORCE_S  6
+/* EFUSE_VDD_SPI_TIEH : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: SPI regulator output is short connected to VDD3P3_RTC_IO.*/
+#define EFUSE_VDD_SPI_TIEH  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_M  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_V  0x1
+#define EFUSE_VDD_SPI_TIEH_S  5
+/* EFUSE_VDD_SPI_XPD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: SPI regulator power up signal.*/
+#define EFUSE_VDD_SPI_XPD  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_M  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_V  0x1
+#define EFUSE_VDD_SPI_XPD_S  4
+/* EFUSE_VDD_SPI_DREFL : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: SPI regulator low voltage reference.*/
+#define EFUSE_VDD_SPI_DREFL  0x00000003
+#define EFUSE_VDD_SPI_DREFL_M  ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S))
+#define EFUSE_VDD_SPI_DREFL_V  0x3
+#define EFUSE_VDD_SPI_DREFL_S  2
+/* EFUSE_VDD_SPI_DREFM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI regulator medium voltage reference.*/
+#define EFUSE_VDD_SPI_DREFM  0x00000003
+#define EFUSE_VDD_SPI_DREFM_M  ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S))
+#define EFUSE_VDD_SPI_DREFM_V  0x3
+#define EFUSE_VDD_SPI_DREFM_S  0
+
+#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0x00C)
+/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Configures flash waiting time after power-up  in unit of ms.
+ When the value is 15  the waiting time is 30 ms.*/
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED0  0x0000003F
+#define EFUSE_RPT4_RESERVED0_M  ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S))
+#define EFUSE_RPT4_RESERVED0_V  0x3F
+#define EFUSE_RPT4_RESERVED0_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking aggressive secure boot.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to enable secure boot.*/
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: Purpose of Key6. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_6  0x0000000F
+#define EFUSE_KEY_PURPOSE_6_M  ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S))
+#define EFUSE_KEY_PURPOSE_6_V  0xF
+#define EFUSE_KEY_PURPOSE_6_S  16
+/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: Purpose of Key5. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: Purpose of Key4. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: Purpose of Key3. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Purpose of Key2. Refer to Table KEY_PURPOSE Values.*/
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x010)
+/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED1  0x00000003
+#define EFUSE_RPT4_RESERVED1_M  ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
+#define EFUSE_RPT4_RESERVED1_V  0x3
+#define EFUSE_RPT4_RESERVED1_S  30
+/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
+#define EFUSE_SECURE_VERSION  0x0000FFFF
+#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
+#define EFUSE_SECURE_VERSION_V  0xFFFF
+#define EFUSE_SECURE_VERSION_S  14
+/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/
+#define EFUSE_FORCE_SEND_RESUME  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/* EFUSE_FLASH_ECC_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set 1 to enable ECC for flash boot.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: Flash page size.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The type of the interfaced flash. 0: four data lines  1: eight data lines.*/
+#define EFUSE_FLASH_TYPE  (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_V  0x1
+#define EFUSE_FLASH_TYPE_S  9
+/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU 1: VDD_SPI.*/
+#define EFUSE_PIN_POWER_SELECTION  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: The type of UART print control.00: Forces to print.01: Controlled
+ by GPIO46  print at low level.10: Controlled by GPIO46  print at high level.11: Forces to disable print.*/
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable security download mode.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to disable download through USB.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_FLASH_ECC_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode.
+ 1:flash ecc 16to17 byte mode.*/
+#define EFUSE_FLASH_ECC_MODE  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_V  0x1
+#define EFUSE_FLASH_ECC_MODE_S  3
+/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Selectes UART print channel. 0: UART0 1: UART1.*/
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to disable download mode (boot_mode[3:0] = 0  1  2  3  6  7).*/
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x014)
+/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED4  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_M  ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S))
+#define EFUSE_RPT4_RESERVED4_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_S  0
+
+#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x018)
+/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the sixth 32-bit data to be programmed.*/
+#define EFUSE_PGM_DATA_6  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_M  ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_S  0
+
+#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x01C)
+/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the seventh 32-bit data to be programmed.*/
+#define EFUSE_PGM_DATA_7  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_M  ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_S  0
+
+#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x020)
+/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 0th 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_0  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_M  ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x024)
+/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the first 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_1  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_M  ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x028)
+/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the second 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_2  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_M  ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x02C)
+/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The value of WR_DIS.*/
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x030)
+/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: The value of VDD_SPI_DREFH.*/
+#define EFUSE_VDD_SPI_DREFH  0x00000003
+#define EFUSE_VDD_SPI_DREFH_M  ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S))
+#define EFUSE_VDD_SPI_DREFH_V  0x3
+#define EFUSE_VDD_SPI_DREFH_S  30
+/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_MODECURLIM.*/
+#define EFUSE_VDD_SPI_MODECURLIM  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_M  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_V  0x1
+#define EFUSE_VDD_SPI_MODECURLIM_S  29
+/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: The value of BTLC_GPIO_ENABLE.*/
+#define EFUSE_BTLC_GPIO_ENABLE  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_M  ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S))
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The value of EXT_PHY_ENABLE.*/
+#define EFUSE_USB_EXT_PHY_ENABLE  (BIT(26))
+#define EFUSE_USB_EXT_PHY_ENABLE_M  (BIT(26))
+#define EFUSE_USB_EXT_PHY_ENABLE_V  0x1
+#define EFUSE_USB_EXT_PHY_ENABLE_S  26
+/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The value of USB_EXCHG_PINS.*/
+#define EFUSE_USB_EXCHG_PINS  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  25
+/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: The value of USB_DREFL.*/
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  23
+/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: The value of USB_DREFH.*/
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The value of HARD_DIS_JTAG.*/
+#define EFUSE_HARD_DIS_JTAG  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_M  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_V  0x1
+#define EFUSE_HARD_DIS_JTAG_S  19
+/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: The value of SOFT_DIS_JTAG.*/
+#define EFUSE_SOFT_DIS_JTAG  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
+#define EFUSE_SOFT_DIS_JTAG_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/* EFUSE_DIS_APP_CPU : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The value of DIS_APP_CPU.*/
+#define EFUSE_DIS_APP_CPU  (BIT(15))
+#define EFUSE_DIS_APP_CPU_M  (BIT(15))
+#define EFUSE_DIS_APP_CPU_V  0x1
+#define EFUSE_DIS_APP_CPU_S  15
+/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The value of DIS_CAN.*/
+#define EFUSE_DIS_CAN  (BIT(14))
+#define EFUSE_DIS_CAN_M  (BIT(14))
+#define EFUSE_DIS_CAN_V  0x1
+#define EFUSE_DIS_CAN_S  14
+/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The value of DIS_USB.*/
+#define EFUSE_DIS_USB  (BIT(13))
+#define EFUSE_DIS_USB_M  (BIT(13))
+#define EFUSE_DIS_USB_V  0x1
+#define EFUSE_DIS_USB_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The value of DIS_FORCE_DOWNLOAD.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_DCACHE.*/
+#define EFUSE_DIS_DOWNLOAD_DCACHE  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_ICACHE.*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of DIS_DCACHE.*/
+#define EFUSE_DIS_DCACHE  (BIT(9))
+#define EFUSE_DIS_DCACHE_M  (BIT(9))
+#define EFUSE_DIS_DCACHE_V  0x1
+#define EFUSE_DIS_DCACHE_S  9
+/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of DIS_ICACHE.*/
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of DIS_RTC_RAM_BOOT.*/
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The value of RD_DIS.*/
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA1_REG          (DR_REG_EFUSE_BASE + 0x034)
+/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_1.*/
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_0.*/
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: The value of SPI_BOOT_CRYPT_CNT.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The value of WDT_DELAY_SEL.*/
+#define EFUSE_WDT_DELAY_SEL  0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  16
+/* EFUSE_EUFSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: The value of REG_VDD_SPI_DCAP.*/
+#define EFUSE_EUFSE_VDD_SPI_DCAP  0x00000003
+#define EFUSE_EUFSE_VDD_SPI_DCAP_M  ((EFUSE_EUFSE_VDD_SPI_DCAP_V)<<(EFUSE_EUFSE_VDD_SPI_DCAP_S))
+#define EFUSE_EUFSE_VDD_SPI_DCAP_V  0x3
+#define EFUSE_EUFSE_VDD_SPI_DCAP_S  14
+/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The value of VDD_SPI_INIT.*/
+#define EFUSE_VDD_SPI_INIT  0x00000003
+#define EFUSE_VDD_SPI_INIT_M  ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S))
+#define EFUSE_VDD_SPI_INIT_V  0x3
+#define EFUSE_VDD_SPI_INIT_S  12
+/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: The value of VDD_SPI_DCURLIM.*/
+#define EFUSE_VDD_SPI_DCURLIM  0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_M  ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S))
+#define EFUSE_VDD_SPI_DCURLIM_V  0x7
+#define EFUSE_VDD_SPI_DCURLIM_S  9
+/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_ENCURLIM.*/
+#define EFUSE_VDD_SPI_ENCURLIM  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_M  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_V  0x1
+#define EFUSE_VDD_SPI_ENCURLIM_S  8
+/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_EN_INIT.*/
+#define EFUSE_VDD_SPI_EN_INIT  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_M  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_V  0x1
+#define EFUSE_VDD_SPI_EN_INIT_S  7
+/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_FORCE.*/
+#define EFUSE_VDD_SPI_FORCE  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_M  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_V  0x1
+#define EFUSE_VDD_SPI_FORCE_S  6
+/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_TIEH.*/
+#define EFUSE_VDD_SPI_TIEH  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_M  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_V  0x1
+#define EFUSE_VDD_SPI_TIEH_S  5
+/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_XPD.*/
+#define EFUSE_VDD_SPI_XPD  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_M  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_V  0x1
+#define EFUSE_VDD_SPI_XPD_S  4
+/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: The value of VDD_SPI_DREFL.*/
+#define EFUSE_VDD_SPI_DREFL  0x00000003
+#define EFUSE_VDD_SPI_DREFL_M  ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S))
+#define EFUSE_VDD_SPI_DREFL_V  0x3
+#define EFUSE_VDD_SPI_DREFL_S  2
+/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The value of VDD_SPI_DREFM.*/
+#define EFUSE_VDD_SPI_DREFM  0x00000003
+#define EFUSE_VDD_SPI_DREFM_M  ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S))
+#define EFUSE_VDD_SPI_DREFM_V  0x3
+#define EFUSE_VDD_SPI_DREFM_S  0
+
+#define EFUSE_RD_REPEAT_DATA2_REG          (DR_REG_EFUSE_BASE + 0x038)
+/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: The value of FLASH_TPUW.*/
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED0  0x0000003F
+#define EFUSE_RPT4_RESERVED0_M  ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S))
+#define EFUSE_RPT4_RESERVED0_V  0x3F
+#define EFUSE_RPT4_RESERVED0_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_EN.*/
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_6.*/
+#define EFUSE_KEY_PURPOSE_6  0x0000000F
+#define EFUSE_KEY_PURPOSE_6_M  ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S))
+#define EFUSE_KEY_PURPOSE_6_V  0xF
+#define EFUSE_KEY_PURPOSE_6_S  16
+/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_5.*/
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_4.*/
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_3.*/
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_2.*/
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_RD_REPEAT_DATA3_REG          (DR_REG_EFUSE_BASE + 0x03C)
+/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED1  0x00000003
+#define EFUSE_RPT4_RESERVED1_M  ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
+#define EFUSE_RPT4_RESERVED1_V  0x3
+#define EFUSE_RPT4_RESERVED1_S  30
+/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: The value of SECURE_VERSION.*/
+#define EFUSE_SECURE_VERSION  0x0000FFFF
+#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
+#define EFUSE_SECURE_VERSION_V  0xFFFF
+#define EFUSE_SECURE_VERSION_S  14
+/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The value of FORCE_SEND_RESUME.*/
+#define EFUSE_FORCE_SEND_RESUME  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The value of FLASH_ECC_EN.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: The value of FLASH_PAGE_SIZE.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of FLASH_TYPE.*/
+#define EFUSE_FLASH_TYPE  (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_V  0x1
+#define EFUSE_FLASH_TYPE_S  9
+/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of PIN_POWER_SELECTION.*/
+#define EFUSE_PIN_POWER_SELECTION  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: The value of UART_PRINT_CONTROL.*/
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of DIS_USB_DOWNLOAD_MODE.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The value of FLASH_ECC_MODE.*/
+#define EFUSE_FLASH_ECC_MODE  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_V  0x1
+#define EFUSE_FLASH_ECC_MODE_S  3
+/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The value of UART_PRINT_CHANNEL.*/
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The value of DIS_LEGACY_SPI_BOOT.*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_MODE.*/
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_RD_REPEAT_DATA4_REG          (DR_REG_EFUSE_BASE + 0x040)
+/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED4  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_M  ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S))
+#define EFUSE_RPT4_RESERVED4_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_0_REG          (DR_REG_EFUSE_BASE + 0x044)
+/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the low 32 bits of MAC address.*/
+#define EFUSE_MAC_0  0xFFFFFFFF
+#define EFUSE_MAC_0_M  ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S))
+#define EFUSE_MAC_0_V  0xFFFFFFFF
+#define EFUSE_MAC_0_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_1_REG          (DR_REG_EFUSE_BASE + 0x048)
+/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: Stores the zeroth part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_0  0x0000FFFF
+#define EFUSE_SPI_PAD_CONF_0_M  ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S))
+#define EFUSE_SPI_PAD_CONF_0_V  0xFFFF
+#define EFUSE_SPI_PAD_CONF_0_S  16
+/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Stores the high 16 bits of MAC address.*/
+#define EFUSE_MAC_1  0x0000FFFF
+#define EFUSE_MAC_1_M  ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S))
+#define EFUSE_MAC_1_V  0xFFFF
+#define EFUSE_MAC_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_2_REG          (DR_REG_EFUSE_BASE + 0x04C)
+/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_1  0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
+#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_3_REG          (DR_REG_EFUSE_BASE + 0x050)
+/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
+/*description: Stores the fist 14 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_0  0x00003FFF
+#define EFUSE_SYS_DATA_PART0_0_M  ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
+#define EFUSE_SYS_DATA_PART0_0_V  0x3FFF
+#define EFUSE_SYS_DATA_PART0_0_S  18
+/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: Stores the second part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_2  0x0003FFFF
+#define EFUSE_SPI_PAD_CONF_2_M  ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
+#define EFUSE_SPI_PAD_CONF_2_V  0x3FFFF
+#define EFUSE_SPI_PAD_CONF_2_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_4_REG          (DR_REG_EFUSE_BASE + 0x054)
+/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fist 32 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_M  ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_5_REG          (DR_REG_EFUSE_BASE + 0x058)
+/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_M  ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S))
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x05C)
+/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_0  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_M  ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S))
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x060)
+/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_M  ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S))
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x064)
+/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_M  ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S))
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x068)
+/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_3  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_M  ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S))
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x06C)
+/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_4  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_M  ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S))
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x070)
+/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_5  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_M  ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S))
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x074)
+/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_6  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_M  ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S))
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x078)
+/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_7  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_M  ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S))
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_S  0
+
+#define EFUSE_RD_USR_DATA0_REG          (DR_REG_EFUSE_BASE + 0x07C)
+/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA0  0xFFFFFFFF
+#define EFUSE_USR_DATA0_M  ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S))
+#define EFUSE_USR_DATA0_V  0xFFFFFFFF
+#define EFUSE_USR_DATA0_S  0
+
+#define EFUSE_RD_USR_DATA1_REG          (DR_REG_EFUSE_BASE + 0x080)
+/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA1  0xFFFFFFFF
+#define EFUSE_USR_DATA1_M  ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S))
+#define EFUSE_USR_DATA1_V  0xFFFFFFFF
+#define EFUSE_USR_DATA1_S  0
+
+#define EFUSE_RD_USR_DATA2_REG          (DR_REG_EFUSE_BASE + 0x084)
+/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA2  0xFFFFFFFF
+#define EFUSE_USR_DATA2_M  ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S))
+#define EFUSE_USR_DATA2_V  0xFFFFFFFF
+#define EFUSE_USR_DATA2_S  0
+
+#define EFUSE_RD_USR_DATA3_REG          (DR_REG_EFUSE_BASE + 0x088)
+/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA3  0xFFFFFFFF
+#define EFUSE_USR_DATA3_M  ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S))
+#define EFUSE_USR_DATA3_V  0xFFFFFFFF
+#define EFUSE_USR_DATA3_S  0
+
+#define EFUSE_RD_USR_DATA4_REG          (DR_REG_EFUSE_BASE + 0x08C)
+/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA4  0xFFFFFFFF
+#define EFUSE_USR_DATA4_M  ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S))
+#define EFUSE_USR_DATA4_V  0xFFFFFFFF
+#define EFUSE_USR_DATA4_S  0
+
+#define EFUSE_RD_USR_DATA5_REG          (DR_REG_EFUSE_BASE + 0x090)
+/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA5  0xFFFFFFFF
+#define EFUSE_USR_DATA5_M  ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S))
+#define EFUSE_USR_DATA5_V  0xFFFFFFFF
+#define EFUSE_USR_DATA5_S  0
+
+#define EFUSE_RD_USR_DATA6_REG          (DR_REG_EFUSE_BASE + 0x094)
+/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA6  0xFFFFFFFF
+#define EFUSE_USR_DATA6_M  ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S))
+#define EFUSE_USR_DATA6_V  0xFFFFFFFF
+#define EFUSE_USR_DATA6_S  0
+
+#define EFUSE_RD_USR_DATA7_REG          (DR_REG_EFUSE_BASE + 0x098)
+/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA7  0xFFFFFFFF
+#define EFUSE_USR_DATA7_M  ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S))
+#define EFUSE_USR_DATA7_V  0xFFFFFFFF
+#define EFUSE_USR_DATA7_S  0
+
+#define EFUSE_RD_KEY0_DATA0_REG          (DR_REG_EFUSE_BASE + 0x09C)
+/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA0  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_M  ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S))
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_S  0
+
+#define EFUSE_RD_KEY0_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0A0)
+/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA1  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_M  ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S))
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_S  0
+
+#define EFUSE_RD_KEY0_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0A4)
+/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA2  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_M  ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S))
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_S  0
+
+#define EFUSE_RD_KEY0_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0A8)
+/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA3  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_M  ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S))
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_S  0
+
+#define EFUSE_RD_KEY0_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0AC)
+/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA4  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_M  ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S))
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_S  0
+
+#define EFUSE_RD_KEY0_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0B0)
+/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA5  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_M  ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S))
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_S  0
+
+#define EFUSE_RD_KEY0_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0B4)
+/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA6  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_M  ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S))
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_S  0
+
+#define EFUSE_RD_KEY0_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0B8)
+/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA7  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_M  ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S))
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_S  0
+
+#define EFUSE_RD_KEY1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0BC)
+/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA0  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_M  ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S))
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_S  0
+
+#define EFUSE_RD_KEY1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0C0)
+/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA1  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_M  ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S))
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_S  0
+
+#define EFUSE_RD_KEY1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0C4)
+/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA2  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_M  ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S))
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_S  0
+
+#define EFUSE_RD_KEY1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0C8)
+/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA3  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_M  ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S))
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_S  0
+
+#define EFUSE_RD_KEY1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0CC)
+/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA4  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_M  ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S))
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_S  0
+
+#define EFUSE_RD_KEY1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0D0)
+/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA5  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_M  ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S))
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_S  0
+
+#define EFUSE_RD_KEY1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0D4)
+/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA6  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_M  ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S))
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_S  0
+
+#define EFUSE_RD_KEY1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0D8)
+/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA7  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_M  ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S))
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_S  0
+
+#define EFUSE_RD_KEY2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0DC)
+/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA0  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_M  ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S))
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_S  0
+
+#define EFUSE_RD_KEY2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0E0)
+/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA1  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_M  ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S))
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_S  0
+
+#define EFUSE_RD_KEY2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0E4)
+/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA2  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_M  ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S))
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_S  0
+
+#define EFUSE_RD_KEY2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0E8)
+/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA3  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_M  ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S))
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_S  0
+
+#define EFUSE_RD_KEY2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0EC)
+/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA4  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_M  ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S))
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_S  0
+
+#define EFUSE_RD_KEY2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0F0)
+/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA5  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_M  ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S))
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_S  0
+
+#define EFUSE_RD_KEY2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0F4)
+/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA6  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_M  ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S))
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_S  0
+
+#define EFUSE_RD_KEY2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0F8)
+/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA7  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_M  ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S))
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_S  0
+
+#define EFUSE_RD_KEY3_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0FC)
+/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA0  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_M  ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S))
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_S  0
+
+#define EFUSE_RD_KEY3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA1  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_M  ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S))
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_S  0
+
+#define EFUSE_RD_KEY3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA2  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_M  ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S))
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_S  0
+
+#define EFUSE_RD_KEY3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA3  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_M  ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S))
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_S  0
+
+#define EFUSE_RD_KEY3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10C)
+/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA4  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_M  ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S))
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_S  0
+
+#define EFUSE_RD_KEY3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA5  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_M  ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S))
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_S  0
+
+#define EFUSE_RD_KEY3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA6  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_M  ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S))
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_S  0
+
+#define EFUSE_RD_KEY3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA7  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_M  ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S))
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_S  0
+
+#define EFUSE_RD_KEY4_DATA0_REG          (DR_REG_EFUSE_BASE + 0x11C)
+/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA0  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_M  ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S))
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_S  0
+
+#define EFUSE_RD_KEY4_DATA1_REG          (DR_REG_EFUSE_BASE + 0x120)
+/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA1  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_M  ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S))
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_S  0
+
+#define EFUSE_RD_KEY4_DATA2_REG          (DR_REG_EFUSE_BASE + 0x124)
+/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA2  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_M  ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S))
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_S  0
+
+#define EFUSE_RD_KEY4_DATA3_REG          (DR_REG_EFUSE_BASE + 0x128)
+/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA3  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_M  ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S))
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_S  0
+
+#define EFUSE_RD_KEY4_DATA4_REG          (DR_REG_EFUSE_BASE + 0x12C)
+/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA4  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_M  ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S))
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_S  0
+
+#define EFUSE_RD_KEY4_DATA5_REG          (DR_REG_EFUSE_BASE + 0x130)
+/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA5  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_M  ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S))
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_S  0
+
+#define EFUSE_RD_KEY4_DATA6_REG          (DR_REG_EFUSE_BASE + 0x134)
+/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA6  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_M  ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S))
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_S  0
+
+#define EFUSE_RD_KEY4_DATA7_REG          (DR_REG_EFUSE_BASE + 0x138)
+/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA7  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_M  ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S))
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_S  0
+
+#define EFUSE_RD_KEY5_DATA0_REG          (DR_REG_EFUSE_BASE + 0x13C)
+/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA0  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_M  ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S))
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_S  0
+
+#define EFUSE_RD_KEY5_DATA1_REG          (DR_REG_EFUSE_BASE + 0x140)
+/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA1  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_M  ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S))
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_S  0
+
+#define EFUSE_RD_KEY5_DATA2_REG          (DR_REG_EFUSE_BASE + 0x144)
+/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA2  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_M  ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S))
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_S  0
+
+#define EFUSE_RD_KEY5_DATA3_REG          (DR_REG_EFUSE_BASE + 0x148)
+/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA3  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_M  ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S))
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_S  0
+
+#define EFUSE_RD_KEY5_DATA4_REG          (DR_REG_EFUSE_BASE + 0x14C)
+/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA4  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_M  ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S))
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_S  0
+
+#define EFUSE_RD_KEY5_DATA5_REG          (DR_REG_EFUSE_BASE + 0x150)
+/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA5  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_M  ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S))
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_S  0
+
+#define EFUSE_RD_KEY5_DATA6_REG          (DR_REG_EFUSE_BASE + 0x154)
+/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA6  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_M  ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S))
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_S  0
+
+#define EFUSE_RD_KEY5_DATA7_REG          (DR_REG_EFUSE_BASE + 0x158)
+/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA7  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_M  ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S))
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x15C)
+/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_0  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_M  ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S))
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x160)
+/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_M  ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S))
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x164)
+/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_M  ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S))
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x168)
+/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_3  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_M  ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S))
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x16C)
+/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_4  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_M  ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S))
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x170)
+/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_5  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_M  ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S))
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x174)
+/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_6  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_M  ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S))
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x178)
+/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_7  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_M  ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S))
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+#define EFUSE_RD_REPEAT_ERR0_REG          (DR_REG_EFUSE_BASE + 0x17C)
+/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: If any bit in VDD_SPI_DREFH is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_DREFH_ERR  0x00000003
+#define EFUSE_VDD_SPI_DREFH_ERR_M  ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S))
+#define EFUSE_VDD_SPI_DREFH_ERR_V  0x3
+#define EFUSE_VDD_SPI_DREFH_ERR_S  30
+/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: If VDD_SPI_MODECURLIM is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_MODECURLIM_ERR  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_M  (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_V  0x1
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_S  29
+/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: If any bit in BTLC_GPIO_ENABLE is 1  then it indicates a programming error.*/
+#define EFUSE_BTLC_GPIO_ENABLE_ERR  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S))
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
+/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: If EXT_PHY_ENABLE is 1  then it indicates a programming error.*/
+#define EFUSE_EXT_PHY_ENABLE_ERR  (BIT(26))
+#define EFUSE_EXT_PHY_ENABLE_ERR_M  (BIT(26))
+#define EFUSE_EXT_PHY_ENABLE_ERR_V  0x1
+#define EFUSE_EXT_PHY_ENABLE_ERR_S  26
+/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: If USB_EXCHG_PINS is 1  then it indicates a programming error.*/
+#define EFUSE_USB_EXCHG_PINS_ERR  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x1
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: If any bit in USB_DREFL is 1  then it indicates a programming error.*/
+#define EFUSE_USB_DREFL_ERR  0x00000003
+#define EFUSE_USB_DREFL_ERR_M  ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S))
+#define EFUSE_USB_DREFL_ERR_V  0x3
+#define EFUSE_USB_DREFL_ERR_S  23
+/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: If any bit in USB_DREFH is 1  then it indicates a programming error.*/
+#define EFUSE_USB_DREFH_ERR  0x00000003
+#define EFUSE_USB_DREFH_ERR_M  ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S))
+#define EFUSE_USB_DREFH_ERR_V  0x3
+#define EFUSE_USB_DREFH_ERR_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/* EFUSE_HARD_DIS_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: If HARD_DIS_JTAG is 1  then it indicates a programming error.*/
+#define EFUSE_HARD_DIS_JTAG_ERR  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_ERR_M  (BIT(19))
+#define EFUSE_HARD_DIS_JTAG_ERR_V  0x1
+#define EFUSE_HARD_DIS_JTAG_ERR_S  19
+/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 1'b0 ; */
+/*description: If SOFT_DIS_JTAG is 1  then it indicates a programming error.*/
+#define EFUSE_SOFT_DIS_JTAG_ERR  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S))
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/* EFUSE_DIS_APP_CPU_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: If DIS_APP_CPU is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_APP_CPU_ERR  (BIT(15))
+#define EFUSE_DIS_APP_CPU_ERR_M  (BIT(15))
+#define EFUSE_DIS_APP_CPU_ERR_V  0x1
+#define EFUSE_DIS_APP_CPU_ERR_S  15
+/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: If DIS_CAN is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_CAN_ERR  (BIT(14))
+#define EFUSE_DIS_CAN_ERR_M  (BIT(14))
+#define EFUSE_DIS_CAN_ERR_V  0x1
+#define EFUSE_DIS_CAN_ERR_S  14
+/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If DIS_USB is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_USB_ERR  (BIT(13))
+#define EFUSE_DIS_USB_ERR_M  (BIT(13))
+#define EFUSE_DIS_USB_ERR_V  0x1
+#define EFUSE_DIS_USB_ERR_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If DIS_FORCE_DOWNLOAD is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_DCACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_ICACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: If DIS_DCACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DCACHE_ERR  (BIT(9))
+#define EFUSE_DIS_DCACHE_ERR_M  (BIT(9))
+#define EFUSE_DIS_DCACHE_ERR_V  0x1
+#define EFUSE_DIS_DCACHE_ERR_S  9
+/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If DIS_ICACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_ICACHE_ERR  (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_V  0x1
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: If DIS_RTC_RAM_BOOT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
+/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: If any bit in RD_DIS is 1  then it indicates a programming error.*/
+#define EFUSE_RD_DIS_ERR  0x0000007F
+#define EFUSE_RD_DIS_ERR_M  ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S))
+#define EFUSE_RD_DIS_ERR_V  0x7F
+#define EFUSE_RD_DIS_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR1_REG          (DR_REG_EFUSE_BASE + 0x180)
+/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_1 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_1_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_ERR_M  ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S))
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_0 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_0_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_ERR_M  ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S))
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE2 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE1 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE0 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1  then it indicates a programming error.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: If any bit in WDT_DELAY_SEL is 1  then it indicates a programming error.*/
+#define EFUSE_WDT_DELAY_SEL_ERR  0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_M  ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x3
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: If any bit in VDD_SPI_DCAP is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_DCAP_ERR  0x00000003
+#define EFUSE_VDD_SPI_DCAP_ERR_M  ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S))
+#define EFUSE_VDD_SPI_DCAP_ERR_V  0x3
+#define EFUSE_VDD_SPI_DCAP_ERR_S  14
+/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: If any bit in VDD_SPI_INIT is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_INIT_ERR  0x00000003
+#define EFUSE_VDD_SPI_INIT_ERR_M  ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S))
+#define EFUSE_VDD_SPI_INIT_ERR_V  0x3
+#define EFUSE_VDD_SPI_INIT_ERR_S  12
+/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: If any bit in VDD_SPI_DCURLIM is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_DCURLIM_ERR  0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_ERR_M  ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S))
+#define EFUSE_VDD_SPI_DCURLIM_ERR_V  0x7
+#define EFUSE_VDD_SPI_DCURLIM_ERR_S  9
+/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If VDD_SPI_ENCURLIM is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_ENCURLIM_ERR  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_M  (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_V  0x1
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_S  8
+/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: If VDD_SPI_EN_INIT is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_EN_INIT_ERR  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_ERR_M  (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_ERR_V  0x1
+#define EFUSE_VDD_SPI_EN_INIT_ERR_S  7
+/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: If VDD_SPI_FORCE is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_FORCE_ERR  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_ERR_M  (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_ERR_V  0x1
+#define EFUSE_VDD_SPI_FORCE_ERR_S  6
+/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: If VDD_SPI_TIEH is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_TIEH_ERR  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_ERR_M  (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_ERR_V  0x1
+#define EFUSE_VDD_SPI_TIEH_ERR_S  5
+/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: If VDD_SPI_XPD is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_XPD_ERR  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_ERR_M  (BIT(4))
+#define EFUSE_VDD_SPI_XPD_ERR_V  0x1
+#define EFUSE_VDD_SPI_XPD_ERR_S  4
+/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: If any bit in VDD_SPI_DREFL is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_DREFL_ERR  0x00000003
+#define EFUSE_VDD_SPI_DREFL_ERR_M  ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S))
+#define EFUSE_VDD_SPI_DREFL_ERR_V  0x3
+#define EFUSE_VDD_SPI_DREFL_ERR_S  2
+/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: If any bit in VDD_SPI_DREFM is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_DREFM_ERR  0x00000003
+#define EFUSE_VDD_SPI_DREFM_ERR_M  ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S))
+#define EFUSE_VDD_SPI_DREFM_ERR_V  0x3
+#define EFUSE_VDD_SPI_DREFM_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR2_REG          (DR_REG_EFUSE_BASE + 0x184)
+/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: If any bit in FLASH_TPUM is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_TPUW_ERR  0x0000000F
+#define EFUSE_FLASH_TPUW_ERR_M  ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
+#define EFUSE_FLASH_TPUW_ERR_V  0xF
+#define EFUSE_FLASH_TPUW_ERR_S  28
+/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED0_ERR  0x0000003F
+#define EFUSE_RPT4_RESERVED0_ERR_M  ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S))
+#define EFUSE_RPT4_RESERVED0_ERR_V  0x3F
+#define EFUSE_RPT4_RESERVED0_ERR_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_EN is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_EN_ERR  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/* EFUSE_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_6 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_6_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_6_ERR_M  ((EFUSE_KEY_PURPOSE_6_ERR_V)<<(EFUSE_KEY_PURPOSE_6_ERR_S))
+#define EFUSE_KEY_PURPOSE_6_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_6_ERR_S  16
+/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_5 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_5_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_ERR_M  ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S))
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_4 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_4_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_ERR_M  ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S))
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_3 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_3_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_ERR_M  ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S))
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_2 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_2_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_ERR_M  ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S))
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR3_REG          (DR_REG_EFUSE_BASE + 0x188)
+/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED1_ERR  0x00000003
+#define EFUSE_RPT4_RESERVED1_ERR_M  ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
+#define EFUSE_RPT4_RESERVED1_ERR_V  0x3
+#define EFUSE_RPT4_RESERVED1_ERR_S  30
+/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: If any bit in SECURE_VERSION is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_VERSION_ERR  0x0000FFFF
+#define EFUSE_SECURE_VERSION_ERR_M  ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S))
+#define EFUSE_SECURE_VERSION_ERR_V  0xFFFF
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If FORCE_SEND_RESUME is 1  then it indicates a programming error.*/
+#define EFUSE_FORCE_SEND_RESUME_ERR  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If FLASH_ECC_EN_ERR is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: If any bits in FLASH_PAGE_SIZE is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: If FLASH_TYPE is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_TYPE_ERR  (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_V  0x1
+#define EFUSE_FLASH_TYPE_ERR_S  9
+/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If PIN_POWER_SELECTION is 1  then it indicates a programming error.*/
+#define EFUSE_PIN_POWER_SELECTION_ERR  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
+/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: If any bit in UART_PRINT_CONTROL is 1  then it indicates a programming error.*/
+#define EFUSE_UART_PRINT_CONTROL_ERR  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: If ENABLE_SECURITY_DOWNLOAD is 1  then it indicates a programming error.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: If DIS_USB_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
+/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: If FLASH_ECC_MODE is 1*/
+#define EFUSE_FLASH_ECC_MODE_ERR  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_V  0x1
+#define EFUSE_FLASH_ECC_MODE_ERR_S  3
+/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: If UART_PRINT_CHANNEL is 1  then it indicates a programming error.*/
+#define EFUSE_UART_PRINT_CHANNEL_ERR  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: If DIS_LEGACY_SPI_BOOT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR4_REG          (DR_REG_EFUSE_BASE + 0x190)
+/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED4_ERR  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_ERR_M  ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S))
+#define EFUSE_RPT4_RESERVED4_ERR_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_ERR_S  0
+
+#define EFUSE_RD_RS_ERR0_REG          (DR_REG_EFUSE_BASE + 0x1C0)
+/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of key$n is reliable 1:
  Means that programming key$n failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY4_FAIL (BIT(31))
-#define EFUSE_RD_KEY4_FAIL_M (BIT(31))
-#define EFUSE_RD_KEY4_FAIL_V 0x1
-#define EFUSE_RD_KEY4_FAIL_S 31
-/* EFUSE_RD_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
+#define EFUSE_KEY4_FAIL  (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (BIT(31))
+#define EFUSE_KEY4_FAIL_V  0x1
+#define EFUSE_KEY4_FAIL_S  31
+/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY4_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY4_ERR_NUM_M ((EFUSE_RD_KEY4_ERR_NUM_V) << (EFUSE_RD_KEY4_ERR_NUM_S))
-#define EFUSE_RD_KEY4_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY4_ERR_NUM_S 28
-/* EFUSE_RD_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
+#define EFUSE_KEY4_ERR_NUM  0x00000007
+#define EFUSE_KEY4_ERR_NUM_M  ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S))
+#define EFUSE_KEY4_ERR_NUM_V  0x7
+#define EFUSE_KEY4_ERR_NUM_S  28
+/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of key$n is reliable 1:
  Means that programming key$n failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY3_FAIL (BIT(27))
-#define EFUSE_RD_KEY3_FAIL_M (BIT(27))
-#define EFUSE_RD_KEY3_FAIL_V 0x1
-#define EFUSE_RD_KEY3_FAIL_S 27
-/* EFUSE_RD_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+#define EFUSE_KEY3_FAIL  (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (BIT(27))
+#define EFUSE_KEY3_FAIL_V  0x1
+#define EFUSE_KEY3_FAIL_S  27
+/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY3_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY3_ERR_NUM_M ((EFUSE_RD_KEY3_ERR_NUM_V) << (EFUSE_RD_KEY3_ERR_NUM_S))
-#define EFUSE_RD_KEY3_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY3_ERR_NUM_S 24
-/* EFUSE_RD_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
+#define EFUSE_KEY3_ERR_NUM  0x00000007
+#define EFUSE_KEY3_ERR_NUM_M  ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S))
+#define EFUSE_KEY3_ERR_NUM_V  0x7
+#define EFUSE_KEY3_ERR_NUM_S  24
+/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of key$n is reliable 1:
  Means that programming key$n failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY2_FAIL (BIT(23))
-#define EFUSE_RD_KEY2_FAIL_M (BIT(23))
-#define EFUSE_RD_KEY2_FAIL_V 0x1
-#define EFUSE_RD_KEY2_FAIL_S 23
-/* EFUSE_RD_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+#define EFUSE_KEY2_FAIL  (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (BIT(23))
+#define EFUSE_KEY2_FAIL_V  0x1
+#define EFUSE_KEY2_FAIL_S  23
+/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY2_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY2_ERR_NUM_M ((EFUSE_RD_KEY2_ERR_NUM_V) << (EFUSE_RD_KEY2_ERR_NUM_S))
-#define EFUSE_RD_KEY2_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY2_ERR_NUM_S 20
-/* EFUSE_RD_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
+#define EFUSE_KEY2_ERR_NUM  0x00000007
+#define EFUSE_KEY2_ERR_NUM_M  ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S))
+#define EFUSE_KEY2_ERR_NUM_V  0x7
+#define EFUSE_KEY2_ERR_NUM_S  20
+/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of key$n is reliable 1:
  Means that programming key$n failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY1_FAIL (BIT(19))
-#define EFUSE_RD_KEY1_FAIL_M (BIT(19))
-#define EFUSE_RD_KEY1_FAIL_V 0x1
-#define EFUSE_RD_KEY1_FAIL_S 19
-/* EFUSE_RD_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+#define EFUSE_KEY1_FAIL  (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (BIT(19))
+#define EFUSE_KEY1_FAIL_V  0x1
+#define EFUSE_KEY1_FAIL_S  19
+/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY1_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY1_ERR_NUM_M ((EFUSE_RD_KEY1_ERR_NUM_V) << (EFUSE_RD_KEY1_ERR_NUM_S))
-#define EFUSE_RD_KEY1_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY1_ERR_NUM_S 16
-/* EFUSE_RD_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
+#define EFUSE_KEY1_ERR_NUM  0x00000007
+#define EFUSE_KEY1_ERR_NUM_M  ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S))
+#define EFUSE_KEY1_ERR_NUM_V  0x7
+#define EFUSE_KEY1_ERR_NUM_S  16
+/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of key$n is reliable 1:
  Means that programming key$n failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY0_FAIL (BIT(15))
-#define EFUSE_RD_KEY0_FAIL_M (BIT(15))
-#define EFUSE_RD_KEY0_FAIL_V 0x1
-#define EFUSE_RD_KEY0_FAIL_S 15
-/* EFUSE_RD_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
+#define EFUSE_KEY0_FAIL  (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (BIT(15))
+#define EFUSE_KEY0_FAIL_V  0x1
+#define EFUSE_KEY0_FAIL_S  15
+/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY0_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY0_ERR_NUM_M ((EFUSE_RD_KEY0_ERR_NUM_V) << (EFUSE_RD_KEY0_ERR_NUM_S))
-#define EFUSE_RD_KEY0_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY0_ERR_NUM_S 12
-/* EFUSE_RD_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
+#define EFUSE_KEY0_ERR_NUM  0x00000007
+#define EFUSE_KEY0_ERR_NUM_M  ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S))
+#define EFUSE_KEY0_ERR_NUM_V  0x7
+#define EFUSE_KEY0_ERR_NUM_S  12
+/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the user data is reliable 1: Means
  that programming user data failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_USR_DATA_FAIL (BIT(11))
-#define EFUSE_RD_USR_DATA_FAIL_M (BIT(11))
-#define EFUSE_RD_USR_DATA_FAIL_V 0x1
-#define EFUSE_RD_USR_DATA_FAIL_S 11
-/* EFUSE_RD_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
+#define EFUSE_USR_DATA_FAIL  (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (BIT(11))
+#define EFUSE_USR_DATA_FAIL_V  0x1
+#define EFUSE_USR_DATA_FAIL_S  11
+/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007
-#define EFUSE_RD_USR_DATA_ERR_NUM_M ((EFUSE_RD_USR_DATA_ERR_NUM_V) << (EFUSE_RD_USR_DATA_ERR_NUM_S))
-#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x7
-#define EFUSE_RD_USR_DATA_ERR_NUM_S 8
-/* EFUSE_RD_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+#define EFUSE_USR_DATA_ERR_NUM  0x00000007
+#define EFUSE_USR_DATA_ERR_NUM_M  ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S))
+#define EFUSE_USR_DATA_ERR_NUM_V  0x7
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of system part1 is reliable
  1: Means that programming user data failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_SYS_PART1_FAIL (BIT(7))
-#define EFUSE_RD_SYS_PART1_FAIL_M (BIT(7))
-#define EFUSE_RD_SYS_PART1_FAIL_V 0x1
-#define EFUSE_RD_SYS_PART1_FAIL_S 7
-/* EFUSE_RD_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+#define EFUSE_SYS_PART1_FAIL  (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_V  0x1
+#define EFUSE_SYS_PART1_FAIL_S  7
+/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_SYS_PART1_NUM 0x00000007
-#define EFUSE_RD_SYS_PART1_NUM_M ((EFUSE_RD_SYS_PART1_NUM_V) << (EFUSE_RD_SYS_PART1_NUM_S))
-#define EFUSE_RD_SYS_PART1_NUM_V 0x7
-#define EFUSE_RD_SYS_PART1_NUM_S 4
-/* EFUSE_RD_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+#define EFUSE_SYS_PART1_NUM  0x00000007
+#define EFUSE_SYS_PART1_NUM_M  ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S))
+#define EFUSE_SYS_PART1_NUM_V  0x7
+#define EFUSE_SYS_PART1_NUM_S  4
+/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable
  1: Means that programming user data failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_MAC_SPI_8M_FAIL (BIT(3))
-#define EFUSE_RD_MAC_SPI_8M_FAIL_M (BIT(3))
-#define EFUSE_RD_MAC_SPI_8M_FAIL_V 0x1
-#define EFUSE_RD_MAC_SPI_8M_FAIL_S 3
-/* EFUSE_RD_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+#define EFUSE_MAC_SPI_8M_FAIL  (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x1
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_MAC_SPI_8M_ERR_NUM 0x00000007
-#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_M ((EFUSE_RD_MAC_SPI_8M_ERR_NUM_V) << (EFUSE_RD_MAC_SPI_8M_ERR_NUM_S))
-#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_V 0x7
-#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_S 0
+#define EFUSE_MAC_SPI_8M_ERR_NUM  0x00000007
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S))
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x7
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
 
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/* EFUSE_RD_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+#define EFUSE_RD_RS_ERR1_REG          (DR_REG_EFUSE_BASE + 0x1C4)
+/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of system part2 is reliable
  1: Means that programming user data failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_SYS_PART2_FAIL (BIT(7))
-#define EFUSE_RD_SYS_PART2_FAIL_M (BIT(7))
-#define EFUSE_RD_SYS_PART2_FAIL_V 0x1
-#define EFUSE_RD_SYS_PART2_FAIL_S 7
-/* EFUSE_RD_SYS_PART2_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+#define EFUSE_SYS_PART2_FAIL  (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_V  0x1
+#define EFUSE_SYS_PART2_FAIL_S  7
+/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_SYS_PART2_NUM 0x00000007
-#define EFUSE_RD_SYS_PART2_NUM_M ((EFUSE_RD_SYS_PART2_NUM_V) << (EFUSE_RD_SYS_PART2_NUM_S))
-#define EFUSE_RD_SYS_PART2_NUM_V 0x7
-#define EFUSE_RD_SYS_PART2_NUM_S 4
-/* EFUSE_RD_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+#define EFUSE_SYS_PART2_ERR_NUM  0x00000007
+#define EFUSE_SYS_PART2_ERR_NUM_M  ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S))
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x7
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
 /*description: 0: Means no failure and that the data of KEY5 is reliable 1:
  Means that programming user data failed and the number of error bytes is over 6.*/
-#define EFUSE_RD_KEY5_FAIL (BIT(3))
-#define EFUSE_RD_KEY5_FAIL_M (BIT(3))
-#define EFUSE_RD_KEY5_FAIL_V 0x1
-#define EFUSE_RD_KEY5_FAIL_S 3
-/* EFUSE_RD_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+#define EFUSE_KEY5_FAIL  (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (BIT(3))
+#define EFUSE_KEY5_FAIL_V  0x1
+#define EFUSE_KEY5_FAIL_S  3
+/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
 /*description: The value of this signal means the number of error bytes.*/
-#define EFUSE_RD_KEY5_ERR_NUM 0x00000007
-#define EFUSE_RD_KEY5_ERR_NUM_M ((EFUSE_RD_KEY5_ERR_NUM_V) << (EFUSE_RD_KEY5_ERR_NUM_S))
-#define EFUSE_RD_KEY5_ERR_NUM_V 0x7
-#define EFUSE_RD_KEY5_ERR_NUM_S 0
+#define EFUSE_KEY5_ERR_NUM  0x00000007
+#define EFUSE_KEY5_ERR_NUM_M  ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S))
+#define EFUSE_KEY5_ERR_NUM_V  0x7
+#define EFUSE_KEY5_ERR_NUM_S  0
 
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x1C8)
 /* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
 /*description: Set this bit and force to enable clock signal of eFuse memory.*/
-#define EFUSE_CLK_EN (BIT(16))
-#define EFUSE_CLK_EN_M (BIT(16))
-#define EFUSE_CLK_EN_V 0x1
-#define EFUSE_CLK_EN_S 16
+#define EFUSE_CLK_EN  (BIT(16))
+#define EFUSE_CLK_EN_M  (BIT(16))
+#define EFUSE_CLK_EN_V  0x1
+#define EFUSE_CLK_EN_S  16
 /* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
 /*description: Set this bit to force eFuse SRAM into working mode.*/
-#define EFUSE_MEM_FORCE_PU (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M (BIT(2))
-#define EFUSE_MEM_FORCE_PU_V 0x1
-#define EFUSE_MEM_FORCE_PU_S 2
+#define EFUSE_MEM_FORCE_PU  (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (BIT(2))
+#define EFUSE_MEM_FORCE_PU_V  0x1
+#define EFUSE_MEM_FORCE_PU_S  2
 /* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
 /*description: Set this bit and force to activate clock signal of eFuse SRAM.*/
-#define EFUSE_MEM_CLK_FORCE_ON (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_V 0x1
-#define EFUSE_MEM_CLK_FORCE_ON_S 1
+#define EFUSE_MEM_CLK_FORCE_ON  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x1
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
 /* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to force eFuse SRAM into power-saving mode.*/
-#define EFUSE_MEM_FORCE_PD (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M (BIT(0))
-#define EFUSE_MEM_FORCE_PD_V 0x1
-#define EFUSE_MEM_FORCE_PD_S 0
+#define EFUSE_MEM_FORCE_PD  (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (BIT(0))
+#define EFUSE_MEM_FORCE_PD_V  0x1
+#define EFUSE_MEM_FORCE_PD_S  0
 
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x1CC)
 /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
 /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
-#define EFUSE_OP_CODE 0x0000FFFF
-#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << (EFUSE_OP_CODE_S))
-#define EFUSE_OP_CODE_V 0xFFFF
-#define EFUSE_OP_CODE_S 0
+#define EFUSE_OP_CODE  0x0000FFFF
+#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V  0xFFFF
+#define EFUSE_OP_CODE_S  0
 
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
 /* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
 /*description: Indicates the number of error bits during programming BLOCK0.*/
-#define EFUSE_REPEAT_ERR_CNT 0x000000FF
-#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V) << (EFUSE_REPEAT_ERR_CNT_S))
-#define EFUSE_REPEAT_ERR_CNT_V 0xFF
-#define EFUSE_REPEAT_ERR_CNT_S 10
+#define EFUSE_REPEAT_ERR_CNT  0x000000FF
+#define EFUSE_REPEAT_ERR_CNT_M  ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S))
+#define EFUSE_REPEAT_ERR_CNT_V  0xFF
+#define EFUSE_REPEAT_ERR_CNT_S  10
 /* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
 /*description: The value of OTP_VDDQ_IS_SW.*/
-#define EFUSE_OTP_VDDQ_IS_SW (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_V 0x1
-#define EFUSE_OTP_VDDQ_IS_SW_S 9
+#define EFUSE_OTP_VDDQ_IS_SW  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
 /* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
 /*description: The value of OTP_PGENB_SW.*/
-#define EFUSE_OTP_PGENB_SW (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M (BIT(8))
-#define EFUSE_OTP_PGENB_SW_V 0x1
-#define EFUSE_OTP_PGENB_SW_S 8
+#define EFUSE_OTP_PGENB_SW  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_V  0x1
+#define EFUSE_OTP_PGENB_SW_S  8
 /* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
 /*description: The value of OTP_CSB_SW.*/
-#define EFUSE_OTP_CSB_SW (BIT(7))
-#define EFUSE_OTP_CSB_SW_M (BIT(7))
-#define EFUSE_OTP_CSB_SW_V 0x1
-#define EFUSE_OTP_CSB_SW_S 7
+#define EFUSE_OTP_CSB_SW  (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (BIT(7))
+#define EFUSE_OTP_CSB_SW_V  0x1
+#define EFUSE_OTP_CSB_SW_S  7
 /* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
 /*description: The value of OTP_STROBE_SW.*/
-#define EFUSE_OTP_STROBE_SW (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M (BIT(6))
-#define EFUSE_OTP_STROBE_SW_V 0x1
-#define EFUSE_OTP_STROBE_SW_S 6
+#define EFUSE_OTP_STROBE_SW  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_V  0x1
+#define EFUSE_OTP_STROBE_SW_S  6
 /* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
 /*description: The value of OTP_VDDQ_C_SYNC2.*/
-#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1
-#define EFUSE_OTP_VDDQ_C_SYNC2_S 5
+#define EFUSE_OTP_VDDQ_C_SYNC2  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
 /* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
 /*description: The value of OTP_LOAD_SW.*/
-#define EFUSE_OTP_LOAD_SW (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M (BIT(4))
-#define EFUSE_OTP_LOAD_SW_V 0x1
-#define EFUSE_OTP_LOAD_SW_S 4
+#define EFUSE_OTP_LOAD_SW  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_V  0x1
+#define EFUSE_OTP_LOAD_SW_S  4
 /* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
 /*description: Indicates the state of the eFuse state machine.*/
-#define EFUSE_STATE 0x0000000F
-#define EFUSE_STATE_M ((EFUSE_STATE_V) << (EFUSE_STATE_S))
-#define EFUSE_STATE_V 0xF
-#define EFUSE_STATE_S 0
+#define EFUSE_STATE  0x0000000F
+#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
+#define EFUSE_STATE_V  0xF
+#define EFUSE_STATE_S  0
 
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x1D4)
 /* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */
 /*description: The serial number of the block to be programmed. Value 0-10 corresponds
  to block number 0-10  respectively.*/
-#define EFUSE_BLK_NUM 0x0000000F
-#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V) << (EFUSE_BLK_NUM_S))
-#define EFUSE_BLK_NUM_V 0xF
-#define EFUSE_BLK_NUM_S 2
+#define EFUSE_BLK_NUM  0x0000000F
+#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
+#define EFUSE_BLK_NUM_V  0xF
+#define EFUSE_BLK_NUM_S  2
 /* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
 /*description: Set this bit to send programming command.*/
-#define EFUSE_PGM_CMD (BIT(1))
-#define EFUSE_PGM_CMD_M (BIT(1))
-#define EFUSE_PGM_CMD_V 0x1
-#define EFUSE_PGM_CMD_S 1
+#define EFUSE_PGM_CMD  (BIT(1))
+#define EFUSE_PGM_CMD_M  (BIT(1))
+#define EFUSE_PGM_CMD_V  0x1
+#define EFUSE_PGM_CMD_S  1
 /* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to send read command.*/
-#define EFUSE_READ_CMD (BIT(0))
-#define EFUSE_READ_CMD_M (BIT(0))
-#define EFUSE_READ_CMD_V 0x1
-#define EFUSE_READ_CMD_S 0
+#define EFUSE_READ_CMD  (BIT(0))
+#define EFUSE_READ_CMD_M  (BIT(0))
+#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_S  0
 
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x1D8)
 /* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
 /*description: The raw bit signal for pgm_done interrupt.*/
-#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_V 0x1
-#define EFUSE_PGM_DONE_INT_RAW_S 1
+#define EFUSE_PGM_DONE_INT_RAW  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V  0x1
+#define EFUSE_PGM_DONE_INT_RAW_S  1
 /* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
 /*description: The raw bit signal for read_done interrupt.*/
-#define EFUSE_READ_DONE_INT_RAW (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_V 0x1
-#define EFUSE_READ_DONE_INT_RAW_S 0
+#define EFUSE_READ_DONE_INT_RAW  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_S  0
 
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x1DC)
 /* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
 /*description: The status signal for pgm_done interrupt.*/
-#define EFUSE_PGM_DONE_INT_ST (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_V 0x1
-#define EFUSE_PGM_DONE_INT_ST_S 1
+#define EFUSE_PGM_DONE_INT_ST  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V  0x1
+#define EFUSE_PGM_DONE_INT_ST_S  1
 /* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
 /*description: The status signal for read_done interrupt.*/
-#define EFUSE_READ_DONE_INT_ST (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_V 0x1
-#define EFUSE_READ_DONE_INT_ST_S 0
+#define EFUSE_READ_DONE_INT_ST  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_S  0
 
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x1E0)
 /* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
 /*description: The enable signal for pgm_done interrupt.*/
-#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_V 0x1
-#define EFUSE_PGM_DONE_INT_ENA_S 1
+#define EFUSE_PGM_DONE_INT_ENA  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V  0x1
+#define EFUSE_PGM_DONE_INT_ENA_S  1
 /* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: The enable signal for read_done interrupt.*/
-#define EFUSE_READ_DONE_INT_ENA (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_V 0x1
-#define EFUSE_READ_DONE_INT_ENA_S 0
+#define EFUSE_READ_DONE_INT_ENA  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_S  0
 
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x1E4)
 /* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
 /*description: The clear signal for pgm_done interrupt.*/
-#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_V 0x1
-#define EFUSE_PGM_DONE_INT_CLR_S 1
+#define EFUSE_PGM_DONE_INT_CLR  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V  0x1
+#define EFUSE_PGM_DONE_INT_CLR_S  1
 /* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
 /*description: The clear signal for read_done interrupt.*/
-#define EFUSE_READ_DONE_INT_CLR (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_V 0x1
-#define EFUSE_READ_DONE_INT_CLR_S 0
+#define EFUSE_READ_DONE_INT_CLR  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_S  0
 
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x1E8)
 /* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
 /*description: Reduces the power supply of the programming voltage.*/
-#define EFUSE_OE_CLR (BIT(17))
-#define EFUSE_OE_CLR_M (BIT(17))
-#define EFUSE_OE_CLR_V 0x1
-#define EFUSE_OE_CLR_S 17
+#define EFUSE_OE_CLR  (BIT(17))
+#define EFUSE_OE_CLR_M  (BIT(17))
+#define EFUSE_OE_CLR_V  0x1
+#define EFUSE_OE_CLR_S  17
 /* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
 /*description: Controls the rising period of the programming voltage.*/
-#define EFUSE_DAC_NUM 0x000000FF
-#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V) << (EFUSE_DAC_NUM_S))
-#define EFUSE_DAC_NUM_V 0xFF
-#define EFUSE_DAC_NUM_S 9
+#define EFUSE_DAC_NUM  0x000000FF
+#define EFUSE_DAC_NUM_M  ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
+#define EFUSE_DAC_NUM_V  0xFF
+#define EFUSE_DAC_NUM_S  9
 /* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
 /*description: Don't care.*/
-#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_V 0x1
-#define EFUSE_DAC_CLK_PAD_SEL_S 8
-/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'h28 ; */
+#define EFUSE_DAC_CLK_PAD_SEL  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */
 /*description: Controls the division factor of the rising clock of the programming voltage.*/
-#define EFUSE_DAC_CLK_DIV 0x000000FF
-#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << (EFUSE_DAC_CLK_DIV_S))
-#define EFUSE_DAC_CLK_DIV_V 0xFF
-#define EFUSE_DAC_CLK_DIV_S 0
+#define EFUSE_DAC_CLK_DIV  0x000000FF
+#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V  0xFF
+#define EFUSE_DAC_CLK_DIV_S  0
 
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x1EC)
 /* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
 /*description: Configures the initial read time of eFuse.*/
-#define EFUSE_READ_INIT_NUM 0x000000FF
-#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V) << (EFUSE_READ_INIT_NUM_S))
-#define EFUSE_READ_INIT_NUM_V 0xFF
-#define EFUSE_READ_INIT_NUM_S 24
+#define EFUSE_READ_INIT_NUM  0x000000FF
+#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
+#define EFUSE_READ_INIT_NUM_V  0xFF
+#define EFUSE_READ_INIT_NUM_S  24
 /* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
 /*description: Configures the setup time of read operation.*/
-#define EFUSE_TSUR_A 0x000000FF
-#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V) << (EFUSE_TSUR_A_S))
-#define EFUSE_TSUR_A_V 0xFF
-#define EFUSE_TSUR_A_S 16
+#define EFUSE_TSUR_A  0x000000FF
+#define EFUSE_TSUR_A_M  ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
+#define EFUSE_TSUR_A_V  0xFF
+#define EFUSE_TSUR_A_S  16
 /* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
 /*description: Configures the length of pulse of read operation.*/
-#define EFUSE_TRD 0x000000FF
-#define EFUSE_TRD_M ((EFUSE_TRD_V) << (EFUSE_TRD_S))
-#define EFUSE_TRD_V 0xFF
-#define EFUSE_TRD_S 8
+#define EFUSE_TRD  0x000000FF
+#define EFUSE_TRD_M  ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
+#define EFUSE_TRD_V  0xFF
+#define EFUSE_TRD_S  8
 /* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
 /*description: Configures the hold time of read operation.*/
-#define EFUSE_THR_A 0x000000FF
-#define EFUSE_THR_A_M ((EFUSE_THR_A_V) << (EFUSE_THR_A_S))
-#define EFUSE_THR_A_V 0xFF
-#define EFUSE_THR_A_S 0
+#define EFUSE_THR_A  0x000000FF
+#define EFUSE_THR_A_M  ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
+#define EFUSE_THR_A_V  0xFF
+#define EFUSE_THR_A_S  0
 
-#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0)
+#define EFUSE_WR_TIM_CONF0_REG          (DR_REG_EFUSE_BASE + 0x1F0)
 /* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */
 /*description: Configures the length of pulse during programming 1 to eFuse.*/
-#define EFUSE_TPGM 0x0000FFFF
-#define EFUSE_TPGM_M ((EFUSE_TPGM_V) << (EFUSE_TPGM_S))
-#define EFUSE_TPGM_V 0xFFFF
-#define EFUSE_TPGM_S 16
+#define EFUSE_TPGM  0x0000FFFF
+#define EFUSE_TPGM_M  ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
+#define EFUSE_TPGM_V  0xFFFF
+#define EFUSE_TPGM_S  16
 /* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
 /*description: Configures the length of pulse during programming 0 to eFuse.*/
-#define EFUSE_TPGM_INACTIVE 0x000000FF
-#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V) << (EFUSE_TPGM_INACTIVE_S))
-#define EFUSE_TPGM_INACTIVE_V 0xFF
-#define EFUSE_TPGM_INACTIVE_S 8
+#define EFUSE_TPGM_INACTIVE  0x000000FF
+#define EFUSE_TPGM_INACTIVE_M  ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
+#define EFUSE_TPGM_INACTIVE_V  0xFF
+#define EFUSE_TPGM_INACTIVE_S  8
 /* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
 /*description: Configures the hold time of programming operation.*/
-#define EFUSE_THP_A 0x000000FF
-#define EFUSE_THP_A_M ((EFUSE_THP_A_V) << (EFUSE_THP_A_S))
-#define EFUSE_THP_A_V 0xFF
-#define EFUSE_THP_A_S 0
+#define EFUSE_THP_A  0x000000FF
+#define EFUSE_THP_A_M  ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
+#define EFUSE_THP_A_V  0xFF
+#define EFUSE_THP_A_S  0
 
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4)
+#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x1F4)
 /* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */
 /*description: Configures the power up time for VDDQ.*/
-#define EFUSE_PWR_ON_NUM 0x0000FFFF
-#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V) << (EFUSE_PWR_ON_NUM_S))
-#define EFUSE_PWR_ON_NUM_V 0xFFFF
-#define EFUSE_PWR_ON_NUM_S 8
+#define EFUSE_PWR_ON_NUM  0x0000FFFF
+#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
+#define EFUSE_PWR_ON_NUM_V  0xFFFF
+#define EFUSE_PWR_ON_NUM_S  8
 /* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
 /*description: Configures the setup time of programming operation.*/
-#define EFUSE_TSUP_A 0x000000FF
-#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V) << (EFUSE_TSUP_A_S))
-#define EFUSE_TSUP_A_V 0xFF
-#define EFUSE_TSUP_A_S 0
+#define EFUSE_TSUP_A  0x000000FF
+#define EFUSE_TSUP_A_M  ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
+#define EFUSE_TSUP_A_V  0xFF
+#define EFUSE_TSUP_A_S  0
 
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8)
+#define EFUSE_WR_TIM_CONF2_REG          (DR_REG_EFUSE_BASE + 0x1F8)
 /* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */
 /*description: Configures the power outage time for VDDQ.*/
-#define EFUSE_PWR_OFF_NUM 0x0000FFFF
-#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V) << (EFUSE_PWR_OFF_NUM_S))
-#define EFUSE_PWR_OFF_NUM_V 0xFFFF
-#define EFUSE_PWR_OFF_NUM_S 0
+#define EFUSE_PWR_OFF_NUM  0x0000FFFF
+#define EFUSE_PWR_OFF_NUM_M  ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
+#define EFUSE_PWR_OFF_NUM_V  0xFFFF
+#define EFUSE_PWR_OFF_NUM_S  0
 
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC)
-/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003310 ; */
+#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28’h2004270 ; */
 /*description: Stores eFuse version.*/
-#define EFUSE_DATE 0x0FFFFFFF
-#define EFUSE_DATE_M ((EFUSE_DATE_V) << (EFUSE_DATE_S))
-#define EFUSE_DATE_V 0xFFFFFFF
-#define EFUSE_DATE_S 0
+#define EFUSE_DATE  0x0FFFFFFF
+#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V  0xFFFFFFF
+#define EFUSE_DATE_S  0
 
 #ifdef __cplusplus
 }