Merge branch 'bugfix/esp32s2beta_vfs_uart' into 'master'

Fix VFS UART unit tests for esp32s2beta

Closes IDF-1018

See merge request espressif/esp-idf!6301

components/driver/uart.c

@@ -166,6 +166,7 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
     UART_CHECK((stop_bit < UART_STOP_BITS_MAX), "stop bit error", ESP_FAIL);
 
     UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
+#if CONFIG_IDF_TARGET_ESP32
     //workaround for hardware bug, when uart stop bit set as 2-bit mode.
     if (stop_bit == UART_STOP_BITS_2) {
         stop_bit = UART_STOP_BITS_1;
@@ -173,6 +174,7 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
     } else {
         UART[uart_num]->rs485_conf.dl1_en = 0;
     }
+#endif
     UART[uart_num]->conf0.stop_bit_num = stop_bit;
     UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
     return ESP_OK;

components/esp32s2beta/cpu_start.c

@@ -262,7 +262,7 @@ void start_cpu0_default(void)
     esp_perip_clk_init();
     intr_matrix_clear();
 
-#ifndef CONFIG_CONSOLE_UART_NONE
+#ifndef CONFIG_ESP_CONSOLE_UART_NONE
 #ifdef CONFIG_PM_ENABLE
     const int uart_clk_freq = REF_CLK_FREQ;
     /* When DFS is enabled, use REFTICK as UART clock source */
@@ -270,8 +270,8 @@ void start_cpu0_default(void)
 #else
     const int uart_clk_freq = APB_CLK_FREQ;
 #endif // CONFIG_PM_DFS_ENABLE
-    uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
-#endif // CONFIG_CONSOLE_UART_NONE
+    uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
+#endif // CONFIG_ESP_CONSOLE_UART_NONE
 
 #if CONFIG_ESP32S2_BROWNOUT_DET
     esp_brownout_init();
@@ -282,7 +282,7 @@ void start_cpu0_default(void)
     rtc_gpio_force_hold_dis_all();
     esp_vfs_dev_uart_register();
     esp_reent_init(_GLOBAL_REENT);
-#ifndef CONFIG_CONSOLE_UART_NONE
+#ifndef CONFIG_ESP_CONSOLE_UART_NONE
     const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM);
     _GLOBAL_REENT->_stdin  = fopen(default_uart_dev, "r");
     _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");

components/vfs/test/CMakeLists.txt

@@ -1,7 +1,4 @@
 set(srcdirs ".")
-if(IDF_TARGET STREQUAL "esp32")
-    list(APPEND srcdirs "esp32")
-endif()
 
 idf_component_register(SRC_DIRS ${srcdirs}
                        INCLUDE_DIRS .

components/vfs/test/component.mk

@@ -1,4 +1,3 @@
 COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
-COMPONENT_SRCDIRS += esp32
 
 COMPONENT_ADD_LDFRAGMENTS += linker.lf

components/vfs/test/esp32/test_vfs_uart.c → components/vfs/test/test_vfs_uart.c

@@ -19,7 +19,11 @@
 #include <sys/termios.h>
 #include <sys/errno.h>
 #include "unity.h"
+#if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/uart.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/uart.h"
+#endif
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
@@ -42,8 +46,8 @@ static void fwrite_str_loopback(const char* str, size_t size)
 static void flush_stdin_stdout(void)
 {
     vTaskDelay(10 / portTICK_PERIOD_MS);
-    char *bitbucket = (char*) 0x3f000000;
-    while (fread(bitbucket, 1, 128, stdin) > 0) {
+    char bitbucket[UART_FIFO_LEN];
+    while (fread(bitbucket, 1, UART_FIFO_LEN, stdin) > 0) {
         ;
     }
     fflush(stdout);

components/vfs/vfs_uart.c

@@ -181,7 +181,7 @@ static int uart_rx_char(int fd)
 #if CONFIG_IDF_TARGET_ESP32
     return uart->fifo.rw_byte;
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
-    return uart->ahb_fifo.rw_byte;
+    return READ_PERI_REG(UART_FIFO_AHB_REG(fd));
 #endif
 }