pmu: sleep initialization and sleep start support for esp32c6

Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.

Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -0,0 +1,212 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_PMU_SUPPORTED
+#include "hal/pmu_hal.h"
+#include "pmu_param.h"
+
+#define RTC_SLEEP_PD_DIG                PMU_SLEEP_PD_TOP        //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         PMU_SLEEP_PD_LP_PERIPH  //!< Power down RTC peripherals
+// #define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)               //!< Power down RTC SLOW memory
+// #define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)               //!< Power down RTC FAST memory
+// #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)               //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+#define RTC_SLEEP_PD_VDDSDIO            PMU_SLEEP_PD_VDDSDIO    //!< Power down VDDSDIO regulator
+#define RTC_SLEEP_PD_CPU                PMU_SLEEP_PD_CPU        //!< Power down CPU when in lightsleep, but not restart
+#define RTC_SLEEP_PD_DIG_PERIPH         PMU_SLEEP_PD_HP_PERIPH  //!< Power down DIG peripherals
+#define RTC_SLEEP_PD_INT_8M             PMU_SLEEP_PD_RC_FAST    //!< Power down Internal 20M oscillator
+#define RTC_SLEEP_PD_XTAL               PMU_SLEEP_PD_XTAL       //!< Power down main XTAL
+
+//These flags are not power domains, but will affect some sleep parameters
+#define RTC_SLEEP_DIG_USE_8M            BIT(16)
+#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
+#define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
+
+#define RTC_GPIO_TRIG_EN            PMU_GPIO_WAKEUP_EN      //!< GPIO wakeup
+#define RTC_TIMER_TRIG_EN           PMU_LP_TIMER_WAKEUP_EN  //!< Timer wakeup
+#define RTC_WIFI_TRIG_EN            PMU_WIFI_SOC_WAKEUP_EN  //!< WIFI wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN           PMU_UART0_WAKEUP_EN     //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN           PMU_UART1_WAKEUP_EN     //!< UART1 wakeup (light sleep only)
+#define RTC_BT_TRIG_EN              PMU_BLE_SOC_WAKEUP_EN   //!< BT wakeup (light sleep only)
+#define RTC_USB_TRIG_EN             PMU_USB_WAKEUP_EN
+#define RTC_XTAL32K_DEAD_TRIG_EN    0 // TODO
+#define RTC_BROWNOUT_DET_TRIG_EN    0 // TODO
+
+/**
+ * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
+ */
+#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN         | \
+                               RTC_TIMER_TRIG_EN        | \
+                               RTC_WIFI_TRIG_EN         | \
+                               RTC_UART0_TRIG_EN        | \
+                               RTC_UART1_TRIG_EN        | \
+                               RTC_BT_TRIG_EN           | \
+                               RTC_XTAL32K_DEAD_TRIG_EN | \
+                               RTC_USB_TRIG_EN          | \
+                               RTC_BROWNOUT_DET_TRIG_EN)
+
+
+#define PMU_GPIO_WAKEUP_EN          BIT(2)
+#define PMU_WIFI_BEACON_WAKEUP_EN   BIT(3)
+#define PMU_LP_TIMER_WAKEUP_EN      BIT(4)
+#define PMU_WIFI_SOC_WAKEUP_EN      BIT(5)
+#define PMU_UART0_WAKEUP_EN         BIT(6)
+#define PMU_UART1_WAKEUP_EN         BIT(7)
+#define PMU_SDIO_WAKEUP_EN          BIT(8)
+#define PMU_BLE_SOC_WAKEUP_EN       BIT(10)
+#define PMU_USB_WAKEUP_EN           BIT(14)
+
+
+#define PMU_SLEEP_PD_TOP            BIT(0)
+#define PMU_SLEEP_PD_VDDSDIO        BIT(1)
+#define PMU_SLEEP_PD_MODEM          BIT(2)
+#define PMU_SLEEP_PD_HP_PERIPH      BIT(3)
+#define PMU_SLEEP_PD_CPU            BIT(4)
+#define PMU_SLEEP_PD_AON            BIT(5)
+#define PMU_SLEEP_PD_MEM_G0         BIT(6)
+#define PMU_SLEEP_PD_MEM_G1         BIT(7)
+#define PMU_SLEEP_PD_MEM_G2         BIT(8)
+#define PMU_SLEEP_PD_MEM_G3         BIT(9)
+#define PMU_SLEEP_PD_XTAL           BIT(10)
+#define PMU_SLEEP_PD_RC_FAST        BIT(11)
+#define PMU_SLEEP_PD_XTAL32K        BIT(12)
+#define PMU_SLEEP_PD_RC32K          BIT(13)
+#define PMU_SLEEP_PD_LP_PERIPH      BIT(14)
+
+typedef struct {
+    pmu_hal_context_t *hal;
+    void *mc;
+} pmu_context_t;
+
+pmu_context_t * PMU_instance(void);
+
+typedef enum pmu_hp_sysclk_src {
+    PMU_HP_SYSCLK_XTAL = 0,
+    PMU_HP_SYSCLK_PLL,
+    PMU_HP_SYSCLK_FOSC
+} pmu_hp_sysclk_src_t;
+
+typedef enum pmu_sleep_protect_mode {
+    PMU_SLEEP_PROTECT_HP_SLEEP = 0,
+    PMU_SLEEP_PROTECT_XTAL,
+    PMU_SLEEP_PROTECT_HP_LP_SLEEP,
+    PMU_SLEEP_PROTECT_DISABLE
+} pmu_sleep_protect_mode_t;
+
+typedef enum pmu_sleep_regdma_entry {
+    PMU_SLEEP_REGDMA_ENTRY_0 = 0,
+    PMU_SLEEP_REGDMA_ENTRY_1,
+    PMU_SLEEP_REGDMA_ENTRY_2,
+    PMU_SLEEP_REGDMA_ENTRY_3,
+    PMU_SLEEP_REGDMA_ENTRY_MAX
+} pmu_sleep_regdma_entry_t;
+
+
+
+/**
+  * @brief  Enable_regdma_backup.
+  */
+void pmu_sleep_enable_regdma_backup(void);
+
+/**
+  * @brief  Disable_regdma_backup.
+  */
+void pmu_sleep_disable_regdma_backup(void);
+
+/**
+ * @brief Calculate the hardware time overhead during sleep to compensate for sleep time
+ *
+ * @param pd_flags flags indicates the power domain that will be powered down
+ * @param slowclk_period re-calibrated slow clock period
+ * @param fastclk_period re-calibrated fast clock period
+ *
+ * @return hardware time overhead in us
+ */
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+
+/**
+ * @brief Get default sleep configuration
+ * @param config pmu_sleep_config instance
+ * @param pd_flags flags indicates the power domain that will be powered down
+ * @param adjustment total software and hardware time overhead
+ * @param slowclk_period re-calibrated slow clock period in microseconds,
+ *                       Q13.19 fixed point format
+ * @param fastclk_period re-calibrated fast clock period in microseconds,
+ *                       Q13.19 fixed point format
+ * @param dslp configuration for deep sleep mode
+
+ * @return hardware time overhead in us
+ */
+const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t pd_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power/analog parameters and lp/lp system configuration
+ * used in sleep state machines
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * pmu_sleep_start function. Software may do some other actions between
+ * pmu_sleep_init and pmu_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ *
+ * @param config sleep mode configuration
+ *
+ * @param dslp is initialize for deep sleep mode
+ */
+void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp);
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using pmu_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using pmu_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using pmu_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons, used to
+ *                    prevent wakeup source set before the sleep request)
+ * @param lslp_mem_inf_fpu If non-zero then the low power config is restored
+ *                         immediately on wake. Recommended for light sleep,
+ *                         has no effect if the system goes into deep sleep.
+ *
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp);
+
+/**
+ * @brief Initialize PMU related power/clock/digital parameters and functions
+ */
+void pmu_init(void);
+
+
+#endif //#if SOC_PMU_SUPPORTED
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/esp_sleep.h

@@ -48,10 +48,10 @@ typedef enum {
 #endif
     ESP_PD_DOMAIN_XTAL,            //!< XTAL oscillator
 #if SOC_PM_SUPPORT_XTAL32K_PD
-    ESP_PD_DOMAIN_XTAL32K,
+    ESP_PD_DOMAIN_XTAL32K,         //!< External 32 kHz XTAL oscillator
 #endif
 #if SOC_PM_SUPPORT_RC32K_PD
-    ESP_PD_DOMAIN_RC32K,
+    ESP_PD_DOMAIN_RC32K,           //!< Internal 32 kHz RC oscillator
 #endif
 #if SOC_PM_SUPPORT_RC_FAST_PD
     ESP_PD_DOMAIN_RC_FAST,         //!< Internal Fast oscillator
@@ -59,7 +59,9 @@ typedef enum {
 #if SOC_PM_SUPPORT_CPU_PD
     ESP_PD_DOMAIN_CPU,             //!< CPU core
 #endif
+#if SOC_PM_SUPPORT_VDDSDIO_PD
     ESP_PD_DOMAIN_VDDSDIO,         //!< VDD_SDIO
+#endif
     ESP_PD_DOMAIN_MAX              //!< Number of domains
 } esp_sleep_pd_domain_t;
 

components/esp_hw_support/linker.lf

@@ -18,6 +18,8 @@ entries:
         rtc_pm (noflash_text)
         rtc_sleep (noflash_text)
     rtc_time (noflash_text)
+    if SOC_PMU_SUPPORTED = y:
+        pmu_sleep (noflash)
     if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
         rtc_wdt (noflash_text)
     if PERIPH_CTRL_FUNC_IN_IRAM = y:

components/esp_hw_support/port/esp32c6/CMakeLists.txt

@@ -1,8 +1,8 @@
 set(srcs "rtc_clk_init.c"
          "rtc_clk.c"
-         "rtc_init.c"
-        #  "rtc_pm.c" // TODO: IDF-5645
-        #  "rtc_sleep.c" // TODO: IDF-5645
+         "pmu_param.c"
+         "pmu_init.c"
+         "pmu_sleep.c"
          "rtc_time.c"
          "chip_info.c")
 

components/esp_hw_support/port/esp32c6/pmu_init.c

@@ -0,0 +1,207 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/pmu_struct.h"
+#include "hal/pmu_hal.h"
+#include "pmu_param.h"
+#include "esp_private/esp_pmu.h"
+#include "soc/regi2c_dig_reg.h"
+#include "regi2c_ctrl.h"
+
+static __attribute__((unused)) const char *TAG = "pmu_init";
+
+typedef struct {
+    const pmu_hp_system_power_param_t     *power;
+    const pmu_hp_system_clock_param_t     *clock;
+    const pmu_hp_system_digital_param_t   *digital;
+    const pmu_hp_system_analog_param_t    *analog;
+    const pmu_hp_system_retention_param_t *retent;
+} pmu_hp_system_param_t;
+
+typedef struct {
+    const pmu_lp_system_power_param_t  *power;
+    const pmu_lp_system_analog_param_t *analog;
+} pmu_lp_system_param_t;
+
+pmu_context_t * __attribute__((weak)) IRAM_ATTR PMU_instance(void)
+{
+    /* It should be explicitly defined in the internal RAM, because this
+     * instance will be used in pmu_sleep.c */
+    static DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
+    static DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
+    static DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
+    return &pmu_context;
+}
+
+void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
+{
+    const pmu_hp_system_power_param_t *power = param->power;
+    const pmu_hp_system_clock_param_t *clock = param->clock;
+    const pmu_hp_system_digital_param_t *dig = param->digital;
+    const pmu_hp_system_analog_param_t *anlg = param->analog;
+    const pmu_hp_system_retention_param_t *ret = param->retent;
+
+    assert(ctx->hal);
+    /* Default configuration of hp-system power in active, modem and sleep modes */
+    pmu_ll_hp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
+    pmu_ll_hp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
+    pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtal);
+
+    /* Default configuration of hp-system clock in active, modem and sleep modes */
+    pmu_ll_hp_set_icg_func          (ctx->hal->dev, mode, clock->icg_func);
+    pmu_ll_hp_set_icg_apb           (ctx->hal->dev, mode, clock->icg_apb);
+    pmu_ll_hp_set_icg_modem         (ctx->hal->dev, mode, clock->icg_modem.code);
+    pmu_ll_hp_set_sysclk_nodiv      (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_nodiv);
+    pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, mode, clock->sysclk.icg_sysclk_en);
+    pmu_ll_hp_set_sysclk_slp_sel    (ctx->hal->dev, mode, clock->sysclk.sysclk_slp_sel);
+    pmu_ll_hp_set_icg_sysclk_slp_sel(ctx->hal->dev, mode, clock->sysclk.icg_slp_sel);
+    pmu_ll_hp_set_dig_sysclk        (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_sel);
+
+    /* Default configuration of hp-system digital sub-system in active, modem
+     * and sleep modes */
+    pmu_ll_hp_set_uart_wakeup_enable(ctx->hal->dev, mode, dig->syscntl.uart_wakeup_en);
+    pmu_ll_hp_set_hold_all_lp_pad   (ctx->hal->dev, mode, dig->syscntl.lp_pad_hold_all);
+    pmu_ll_hp_set_hold_all_hp_pad   (ctx->hal->dev, mode, dig->syscntl.hp_pad_hold_all);
+    pmu_ll_hp_set_dig_pad_slp_sel   (ctx->hal->dev, mode, dig->syscntl.dig_pad_slp_sel);
+    pmu_ll_hp_set_pause_watchdog    (ctx->hal->dev, mode, dig->syscntl.dig_pause_wdt);
+    pmu_ll_hp_set_cpu_stall         (ctx->hal->dev, mode, dig->syscntl.dig_cpu_stall);
+
+    /* Default configuration of hp-system analog sub-system in active, modem and
+     * sleep modes */
+    pmu_ll_hp_set_bias_xpd                    (ctx->hal->dev, mode, anlg->bias.xpd_bias);
+    pmu_ll_hp_set_dbg_atten                   (ctx->hal->dev, mode, anlg->bias.dbg_atten);
+    pmu_ll_hp_set_current_power_off           (ctx->hal->dev, mode, anlg->bias.pd_cur);
+    pmu_ll_hp_set_bias_sleep_enable           (ctx->hal->dev, mode, anlg->bias.bias_sleep);
+    pmu_ll_hp_set_regulator_sleep_memory_xpd  (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd);
+    pmu_ll_hp_set_regulator_sleep_logic_xpd   (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd);
+    pmu_ll_hp_set_regulator_xpd               (ctx->hal->dev, mode, anlg->regulator0.xpd);
+    pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias);
+    pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias);
+    pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, mode, anlg->regulator0.dbias);
+    pmu_ll_hp_set_regulator_driver_bar        (ctx->hal->dev, mode, anlg->regulator1.drv_b);
+
+    /* Default configuration of hp-system retention sub-system in active, modem
+     * and sleep modes */
+    pmu_ll_hp_set_retention_param(ctx->hal->dev, mode, ret->retention.val);
+    pmu_ll_hp_set_backup_icg_func(ctx->hal->dev, mode, ret->backup_clk);
+
+    /* Some PMU initial parameter configuration */
+    pmu_ll_imm_update_dig_icg_modem_code(ctx->hal->dev, true);
+    pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true);
+
+    pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP);
+}
+
+void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
+{
+    const pmu_lp_system_power_param_t *power = param->power;
+    const pmu_lp_system_analog_param_t *anlg = param->analog;
+
+    assert(ctx->hal);
+    /* Default configuration of lp-system power in active and sleep modes */
+    pmu_ll_lp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
+    pmu_ll_lp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
+    pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtal);
+
+    /* Default configuration of lp-system analog sub-system in active and
+     * sleep modes */
+    pmu_ll_lp_set_bias_xpd             (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.xpd_bias);
+    pmu_ll_lp_set_dbg_atten            (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.dbg_atten);
+    pmu_ll_lp_set_current_power_off    (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.pd_cur);
+    pmu_ll_lp_set_bias_sleep_enable    (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.bias_sleep);
+    pmu_ll_lp_set_regulator_slp_xpd    (ctx->hal->dev, mode, anlg->regulator0.slp_xpd);
+    pmu_ll_lp_set_regulator_xpd        (ctx->hal->dev, mode, anlg->regulator0.xpd);
+    pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_dbias);
+    pmu_ll_lp_set_regulator_dbias      (ctx->hal->dev, mode, anlg->regulator0.dbias);
+    pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b);
+}
+
+static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    // for bypass reserved power domain
+    const pmu_hp_power_domain_t pmu_hp_domains[] = {
+        PMU_HP_PD_TOP,
+        PMU_HP_PD_AON,
+        PMU_HP_PD_CPU,
+        PMU_HP_PD_WIFI
+    };
+
+    for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {
+        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_power_up  (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_no_reset  (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false);
+    }
+    /* Isolate all memory banks while sleeping, avoid memory leakage current */
+    pmu_ll_hp_set_memory_no_isolate     (ctx->hal->dev, 0);
+
+    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_power_up  (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_no_reset  (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
+}
+
+static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
+{
+    param->power = pmu_hp_system_power_param_default(mode);
+    param->clock = pmu_hp_system_clock_param_default(mode);
+    param->digital = pmu_hp_system_digital_param_default(mode);
+    param->analog = pmu_hp_system_analog_param_default(mode);
+    param->retent = pmu_hp_system_retention_param_default(mode);
+}
+
+static void pmu_hp_system_init_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    pmu_hp_system_param_t param = { 0 };
+    for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) {
+        pmu_hp_system_param_default(mode, &param);
+        pmu_hp_system_init(ctx, mode, &param);
+    }
+}
+
+static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
+{
+    param->power = pmu_lp_system_power_param_default(mode);
+    param->analog = pmu_lp_system_analog_param_default(mode);
+}
+
+static void pmu_lp_system_init_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    pmu_lp_system_param_t param;
+    for (pmu_lp_mode_t mode = PMU_MODE_LP_ACTIVE; mode < PMU_MODE_LP_MAX; mode++) {
+        pmu_lp_system_param_default(mode, &param);
+        pmu_lp_system_init(ctx, mode, &param);
+    }
+}
+
+void pmu_init(void)
+{
+    /* Peripheral reg i2c power up */
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
+    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+
+    pmu_hp_system_init_default(PMU_instance());
+    pmu_lp_system_init_default(PMU_instance());
+
+    pmu_power_domain_force_default(PMU_instance());
+}

components/esp_hw_support/port/esp32c6/pmu_param.c

@@ -0,0 +1,441 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "pmu_param.h"
+#include "soc/pmu_icg_mapping.h"
+#include "esp_private/esp_pmu.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a)   (sizeof(a) / sizeof((a)[0]))
+#endif
+
+#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 0, \
+        .mem_dslp      = 0, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 0, \
+        .cpu_pd_en     = 0, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 0  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 0, \
+        .i2c_retention = 0, \
+        .xpd_bb_i2c    = 1, \
+        .xpd_bbpll_i2c = 1, \
+        .xpd_bbpll     = 1  \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 1  \
+    } \
+}
+
+#define PMU_HP_MODEM_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 0, \
+        .mem_dslp      = 0, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 0, \
+        .cpu_pd_en     = 1, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 0  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 0, \
+        .i2c_retention = 0, \
+        .xpd_bb_i2c    = 1, \
+        .xpd_bbpll_i2c = 1, \
+        .xpd_bbpll     = 1  \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 1  \
+    } \
+}
+
+#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 1, \
+        .mem_dslp      = 0, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 1, \
+        .cpu_pd_en     = 0, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 0  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 1, \
+        .i2c_retention = 1, \
+        .xpd_bb_i2c    = 1, \
+        .xpd_bbpll_i2c = 0, \
+        .xpd_bbpll     = 0, \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 0  \
+    } \
+}
+
+const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_power_param_t hp_power[] = {
+        PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_POWER_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_POWER_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_power));
+    return &hp_power[mode];
+}
+
+#define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() {  \
+    .icg_func   = 0xffffffff,                   \
+    .icg_apb    = 0xffffffff,                   \
+    .icg_modem  = {                             \
+        .code = 2                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 1,                  \
+        .sysclk_slp_sel   = 0,                  \
+        .icg_slp_sel      = 0,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_XTAL  \
+    } \
+}
+
+#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() {   \
+    .icg_func   = 0,                            \
+    .icg_apb    = 0,                            \
+    .icg_modem  = {                             \
+        .code = 1                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 1,                  \
+        .sysclk_slp_sel   = 1,                  \
+        .icg_slp_sel      = 1,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_PLL   \
+    } \
+}
+
+#define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() {   \
+    .icg_func   = 0,                            \
+    .icg_apb    = 0,                            \
+    .icg_modem  = {                             \
+        .code = 0                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 0,                  \
+        .sysclk_slp_sel   = 1,                  \
+        .icg_slp_sel      = 1,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_XTAL  \
+    } \
+}
+
+const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_clock_param_t hp_clock[] = {
+        PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_clock));
+    return &hp_clock[mode];
+}
+
+#define PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 0,   \
+        .lp_pad_hold_all = 0,   \
+        .hp_pad_hold_all = 0,   \
+        .dig_pad_slp_sel = 0,   \
+        .dig_pause_wdt   = 0,   \
+        .dig_cpu_stall   = 0    \
+    } \
+}
+
+#define PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 1,   \
+        .lp_pad_hold_all = 0,   \
+        .hp_pad_hold_all = 0,   \
+        .dig_pad_slp_sel = 0,   \
+        .dig_pause_wdt   = 1,   \
+        .dig_cpu_stall   = 1    \
+    } \
+}
+
+#define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 1,   \
+        .lp_pad_hold_all = 0,   \
+        .hp_pad_hold_all = 0,   \
+        .dig_pad_slp_sel = 1,   \
+        .dig_pause_wdt   = 1,   \
+        .dig_cpu_stall   = 1    \
+    } \
+}
+
+const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_digital_param_t hp_digital[] = {
+        PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_digital));
+    return &hp_digital[mode];
+}
+
+#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_bias        = 1,   \
+        .dbg_atten       = 0x0, \
+        .pd_cur          = 0,   \
+        .bias_sleep      = 0    \
+    }, \
+    .regulator0 = {             \
+        .lp_dbias_vol    = 0xd, \
+        .hp_dbias_vol    = 0x1c,\
+        .dbias_sel       = 1,   \
+        .dbias_init      = 1,   \
+        .slp_mem_xpd     = 0,   \
+        .slp_logic_xpd   = 0,   \
+        .xpd             = 1,   \
+        .slp_mem_dbias   = 0xc, \
+        .slp_logic_dbias = 0xc, \
+        .dbias           = 0x19 \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x0 \
+    } \
+}
+
+#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_bias        = 0,   \
+        .dbg_atten       = 0x0, \
+        .pd_cur          = 0,   \
+        .bias_sleep      = 0    \
+    }, \
+    .regulator0 = {             \
+        .slp_mem_xpd     = 0,   \
+        .slp_logic_xpd   = 0,   \
+        .xpd             = 1,   \
+        .slp_mem_dbias   = 0xc, \
+        .slp_logic_dbias = 0xc, \
+        .dbias           = 0x1a \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x0 \
+    } \
+}
+
+#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_bias        = 0,   \
+        .dbg_atten       = 0x0, \
+        .pd_cur          = 0,   \
+        .bias_sleep      = 0    \
+    }, \
+    .regulator0 = {             \
+        .slp_mem_xpd     = 1,   \
+        .slp_logic_xpd   = 1,   \
+        .xpd             = 0,   \
+        .slp_mem_dbias   = 0x4, \
+        .slp_logic_dbias = 0x4, \
+        .dbias           = 0x1a \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x0 \
+    } \
+}
+
+const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_analog_param_t hp_analog[] = {
+        PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_analog));
+    return &hp_analog[mode];
+}
+
+#define PMU_HP_RETENTION_REGDMA_CONFIG(dir, entry)  ((((dir)<<2) | (entry & 0x3)) & 0x7)
+
+#define PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT() {  \
+    .retention = {                                  \
+        .hp_sleep2active_backup_modem_clk_code = 2, \
+        .hp_modem2active_backup_modem_clk_code = 2, \
+        .hp_active_retention_mode       = 0, \
+        .hp_sleep2active_retention_en   = 0, \
+        .hp_modem2active_retention_en   = 0, \
+        .hp_sleep2active_backup_clk_sel = 0, \
+        .hp_modem2active_backup_clk_sel = 0, \
+        .hp_sleep2active_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \
+        .hp_modem2active_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \
+        .hp_sleep2active_backup_en      = 0, \
+        .hp_modem2active_backup_en      = 0, \
+    }, \
+    .backup_clk = (                       \
+        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
+        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
+        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
+        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
+        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
+        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
+        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
+        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
+        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
+    ) \
+}
+
+#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
+    .retention = {                                  \
+        .hp_sleep2modem_backup_modem_clk_code  = 1, \
+        .hp_modem_retention_mode        = 0, \
+        .hp_sleep2modem_retention_en    = 0, \
+        .hp_sleep2modem_backup_clk_sel  = 0, \
+        .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
+        .hp_sleep2modem_backup_en       = 0, \
+    }, \
+    .backup_clk = (                       \
+        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
+        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
+        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
+        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
+        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
+        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
+        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
+        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
+        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
+    ) \
+}
+
+#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
+    .retention = {                                  \
+        .hp_modem2sleep_backup_modem_clk_code  = 0, \
+        .hp_active2sleep_backup_modem_clk_code = 2, \
+        .hp_sleep_retention_mode        = 0, \
+        .hp_modem2sleep_retention_en    = 0, \
+        .hp_active2sleep_retention_en   = 0, \
+        .hp_modem2sleep_backup_clk_sel  = 0, \
+        .hp_active2sleep_backup_clk_sel = 0, \
+        .hp_modem2sleep_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \
+        .hp_active2sleep_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \
+        .hp_modem2sleep_backup_en       = 0, \
+        .hp_active2sleep_backup_en      = 0, \
+    }, \
+    .backup_clk = (                       \
+        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
+        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
+        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
+        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
+        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
+        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
+        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
+        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
+        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
+    ) \
+}
+
+const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_retention_param_t hp_retention[] = {
+        PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_retention));
+    return &hp_retention[mode];
+}
+
+
+/** LP system default parameter */
+
+#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {              \
+        .mem_dslp       = 0,    \
+        .peri_pd_en     = 0,    \
+    }, \
+    .clk_power = {              \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 1,    \
+        .xpd_fosc       = 1,    \
+        .pd_osc         = 0     \
+    } \
+}
+
+#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {              \
+        .mem_dslp       = 1,    \
+        .peri_pd_en     = 0,    \
+    }, \
+    .clk_power = {              \
+        .xpd_xtal32k    = 0,    \
+        .xpd_rc32k      = 0,    \
+        .xpd_fosc       = 0,    \
+        .pd_osc         = 0     \
+    }, \
+    .xtal = {                   \
+        .xpd_xtal       = 0     \
+    } \
+}
+
+const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mode_t mode)
+{
+    static const pmu_lp_system_power_param_t lp_power[] = {
+        PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT(),
+        PMU_LP_SLEEP_POWER_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(lp_power));
+    return &lp_power[mode];
+}
+
+#define PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
+    .regulator0 = {         \
+        .slp_xpd    = 0,    \
+        .xpd        = 1,    \
+        .slp_dbias  = 0x0,  \
+        .dbias      = 0x1a  \
+    }, \
+    .regulator1 = {         \
+        .drv_b      = 0x0     \
+    } \
+}
+
+#define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {               \
+        .xpd_bias   = 0,    \
+        .dbg_atten  = 0x0,  \
+        .pd_cur     = 1,    \
+        .bias_sleep = 1,    \
+    }, \
+    .regulator0 = {         \
+        .slp_xpd    = 1,    \
+        .xpd        = 0,    \
+        .slp_dbias  = 0x0,  \
+        .dbias      = 0x12  \
+    }, \
+    .regulator1 = {         \
+        .drv_b      = 0x0     \
+    } \
+}
+
+const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode)
+{
+    static const pmu_lp_system_analog_param_t lp_analog[] = {
+        PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
+        PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(lp_analog));
+    return &lp_analog[mode];
+}

components/esp_hw_support/port/esp32c6/pmu_sleep.c

@@ -0,0 +1,256 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <sys/param.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/rtc.h"
+#include "soc/pmu_struct.h"
+#include "esp_private/esp_pmu.h"
+
+#define HP(state)   (PMU_MODE_HP_ ## state)
+#define LP(state)   (PMU_MODE_LP_ ## state)
+
+void pmu_sleep_enable_regdma_backup(void)
+{
+    assert(PMU_instance()->hal);
+    /* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
+     * and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
+     * respectively. entry 3 is reserved, not used yet! */
+    pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
+    pmu_hal_hp_set_sleep_modem_backup_enable(PMU_instance()->hal);
+    pmu_hal_hp_set_modem_active_backup_enable(PMU_instance()->hal);
+}
+
+void pmu_sleep_disable_regdma_backup(void)
+{
+    assert(PMU_instance()->hal);
+    pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
+    pmu_hal_hp_set_sleep_modem_backup_disable(PMU_instance()->hal);
+    pmu_hal_hp_set_modem_active_backup_disable(PMU_instance()->hal);
+}
+
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+{
+    const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
+
+    /* LP core hardware wait time, microsecond */
+    const int lp_wakeup_wait_time       = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
+    const int lp_clk_switch_time        = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
+    const int lp_clk_power_on_wait_time = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_ms \
+                            : rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
+
+    const int lp_hw_wait_time = mc->lp.min_slp_time_ms + mc->lp.analog_wait_time_ms + lp_clk_power_on_wait_time \
+                            + lp_wakeup_wait_time + lp_clk_switch_time + mc->lp.power_supply_wait_time_ms \
+                                + mc->lp.power_up_wait_time_ms;
+
+    /* HP core hardware wait time, microsecond */
+    const int hp_digital_power_up_wait_time_ms = mc->hp.power_supply_wait_time_ms + mc->hp.power_up_wait_time_ms;
+    const int hp_regdma_wait_time = MAX(mc->hp.regdma_s2m_work_time_ms + mc->hp.regdma_m2a_work_time_ms, mc->hp.regdma_s2a_work_time_ms);
+    const int hp_clock_wait_time = mc->hp.xtal_wait_stable_time_ms + mc->hp.pll_wait_stable_time_ms;
+
+    const int hp_hw_wait_time = mc->hp.analog_wait_time_ms + MAX(hp_digital_power_up_wait_time_ms + hp_regdma_wait_time, hp_clock_wait_time);
+
+    /* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc
+     * wakeup will be delayed until the RF is turned on in Modem state.
+     *
+     *                modem wakeup                      TBTT, RF on by HW
+     *                     |                                    |
+     *                    \|/                                  \|/
+     *   PMU_HP_ACTIVE                                                                         /------
+     *   PMU_HP_MODEM                                           /------------//////////////////
+     *   PMU_HP_SLEEP   ----------------------//////////////////
+     *                    /|\                /|\ /|\          /|\           /|\              /|\
+     *                     |<- some hw wait ->|   |            |             |<- M2A switch ->|
+     *                     |  slow cycles &   | soc wakeup     |                              |
+     *                     |   FOSC cycles    |<- S2M switch ->|                              |
+     *                     |                                                                  |
+     *                     |<--      PMU guard time, also the maximum time for the SOC     -->|
+     *                     |                           wake-up delay                          |
+     */
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_AUTO_BEACON_ENABLE
+    const int rf_on_protect_time = mc->hp.regdma_rf_on_work_time_ms;
+    const int total_hw_wait_time = lp_hw_wait_time + hp_hw_wait_time + mc->hp.clock_domain_sync_time_ms;
+#else
+    const int rf_on_protect_time = 0;
+    const int total_hw_wait_time = lp_hw_wait_time + hp_hw_wait_time;
+#endif
+    return total_hw_wait_time + rf_on_protect_time;
+}
+
+#define rtc_time_us_to_fastclk(time_us, period)     rtc_time_us_to_slowclk((time_us), (period))
+
+static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
+        pmu_sleep_param_config_t *param,
+        pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
+        const uint32_t pd_flags,
+        const uint32_t adjustment,
+        const uint32_t slowclk_period,
+        const uint32_t fastclk_period
+    )
+{
+    const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_ms, slowclk_period);
+    param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_ms, fastclk_period);
+    param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_ms, fastclk_period);
+    param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_ms, fastclk_period);
+    param->hp_sys.pll_stable_wait_cycle           = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_ms, fastclk_period);
+
+    const int hw_wait_time = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
+    const int modem_state_skip_time = mc->hp.regdma_m2a_work_time_ms + mc->hp.system_dfs_up_work_time_ms + mc->lp.min_slp_time_ms;
+    const int modem_wakeup_wait_time = adjustment - hw_wait_time + modem_state_skip_time + mc->hp.regdma_rf_on_work_time_ms;
+    param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time, fastclk_period);
+
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_ms, slowclk_period);
+    param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_ms, slowclk_period);
+    param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_ms, fastclk_period);
+    param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_ms, fastclk_period);
+
+    if (power->hp_sys.xtal.xpd_xtal) {
+        param->hp_lp.xtal_stable_wait_cycle       = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_ms, fastclk_period);
+    } else {
+        param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_ms, slowclk_period);
+    }
+    return param;
+}
+
+const pmu_sleep_config_t* pmu_sleep_config_default(
+        pmu_sleep_config_t *config,
+        uint32_t pd_flags,
+        uint32_t adjustment,
+        uint32_t slowclk_period,
+        uint32_t fastclk_period,
+        bool dslp
+    )
+{
+    pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
+
+    uint32_t iram_pd_flags = 0;
+    iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
+    iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
+    iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
+    iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
+    config->power = power_default;
+
+    pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
+
+    if (dslp) {
+        pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
+        config->analog = analog_default;
+    } else {
+        pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
+        if (!(pd_flags & PMU_SLEEP_PD_MODEM)){
+            analog_default.hp_sys.analog.slp_logic_dbias += 2;
+        }
+        if (!(pd_flags & PMU_SLEEP_PD_TOP)){
+            analog_default.hp_sys.analog.slp_logic_dbias += 2;
+        }
+        config->analog = analog_default;
+    }
+    return config;
+}
+
+static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp)
+{
+    pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val);
+    pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val);
+    pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal);
+
+    pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val);
+    pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val);
+
+    pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
+    pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
+    pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
+
+    if (dslp) {
+        // TODO: IDF-5349
+    } else {
+    }
+}
+
+static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
+{
+    assert(ctx->hal);
+    pmu_ll_hp_set_current_power_off           (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
+    pmu_ll_hp_set_bias_sleep_enable           (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
+    pmu_ll_hp_set_regulator_sleep_memory_xpd  (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd);
+    pmu_ll_hp_set_regulator_sleep_logic_xpd   (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd);
+    pmu_ll_hp_set_regulator_xpd               (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
+    pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_dbias);
+    pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias);
+    pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
+    pmu_ll_hp_set_regulator_driver_bar        (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
+
+    pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias);
+    pmu_ll_lp_set_regulator_dbias      (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.dbias);
+    pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.drv_b);
+
+    pmu_ll_lp_set_current_power_off    (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
+    pmu_ll_lp_set_bias_sleep_enable    (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep);
+    pmu_ll_lp_set_regulator_xpd        (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd);
+    pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias);
+    pmu_ll_lp_set_regulator_dbias      (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias);
+    pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b);
+
+    if (dslp) {
+        // TODO: IDF-5349
+    } else {
+    }
+}
+
+static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp)
+{
+    assert(ctx->hal);
+    pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle);
+    pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle);
+
+    pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle);
+    pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle);
+
+    pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle);
+    pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle);
+
+    pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle);
+    pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
+    pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
+}
+
+void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
+{
+    assert(PMU_instance());
+    pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
+    pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
+    pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
+}
+
+uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
+{
+    assert(PMU_instance()->hal);
+    pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
+    pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
+
+    pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev);
+    pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
+    pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
+
+    /* Start entry into sleep mode */
+    pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
+
+    while (!pmu_ll_hp_is_sleep_wakeup(PMU_instance()->hal->dev) &&
+        !pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
+        ;
+    }
+
+    return ESP_OK;
+}

components/esp_hw_support/port/esp32c6/private_include/pmu_param.h

@@ -0,0 +1,336 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "soc/pmu_struct.h"
+#include "hal/pmu_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    pmu_hp_dig_power_reg_t  dig_power;
+    pmu_hp_clk_power_reg_t  clk_power;
+    pmu_hp_xtal_reg_t       xtal;
+} pmu_hp_system_power_param_t;
+
+const pmu_hp_system_power_param_t* pmu_hp_system_power_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    uint32_t                icg_func;
+    uint32_t                icg_apb;
+    pmu_hp_icg_modem_reg_t  icg_modem;
+    pmu_hp_sysclk_reg_t     sysclk;
+} pmu_hp_system_clock_param_t;
+
+const pmu_hp_system_clock_param_t* pmu_hp_system_clock_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_sys_cntl_reg_t   syscntl;
+} pmu_hp_system_digital_param_t;
+
+const pmu_hp_system_digital_param_t* pmu_hp_system_digital_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_bias_reg_t       bias;
+    pmu_hp_regulator0_reg_t regulator0;
+    pmu_hp_regulator1_reg_t regulator1;
+} pmu_hp_system_analog_param_t;
+
+const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_backup_reg_t     retention;
+    uint32_t                backup_clk;
+} pmu_hp_system_retention_param_t;
+
+const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_lp_dig_power_reg_t  dig_power;
+    pmu_lp_clk_power_reg_t  clk_power;
+    pmu_lp_xtal_reg_t       xtal;
+} pmu_lp_system_power_param_t;
+
+const pmu_lp_system_power_param_t* pmu_lp_system_power_param_default(pmu_lp_mode_t mode);
+
+typedef struct {
+    pmu_lp_bias_reg_t       bias;
+    pmu_lp_regulator0_reg_t regulator0;
+    pmu_lp_regulator1_reg_t regulator1;
+} pmu_lp_system_analog_param_t;
+
+const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mode_t mode);
+
+#define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES        (10)
+#define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES        (10)
+
+#define PMU_HP_WAKEUP_DELAY_CYCLES              (0)
+#define PMU_HP_XTAL_STABLE_WAIT_CYCLES          (3155)  /* Not used, Fast OSC as PMU work clock source is about 201 us, corresponding to PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES */
+#define PMU_HP_PLL_STABLE_WAIT_CYCLES           (2)
+#define PMU_HP_ANALOG_WAIT_TARGET_CYCLES        (2419)  /* Fast OSC as PMU work clock source is about 154 us */
+#define PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)
+#define PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES     (32)
+#define PMU_HP_MODEM_WAKEUP_WAIT_CYCLES         (20700) /* Fast OSC as PMU work clock source is about 1318.6 us */
+
+#define PMU_LP_WAKEUP_DELAY_CYCLES              (0)
+#define PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES (30)    /* Slow OSC as PMU slow clock source is about 201 us */
+#define PMU_LP_ANALOG_WAIT_TARGET_CYCLES        (23)    /* Slow OSC as PMU slow clock source is about 154 us */
+#define PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)    /* Fast OSC as PMU work clock source is about 2 us */
+#define PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES     (32)    /* Fast OSC as PMU work clock source is about 2 us */
+
+
+typedef struct {
+    struct {
+        pmu_hp_power_t  dig_power;
+        pmu_hp_power_t  clk_power;
+        pmu_hp_power_t  xtal;
+    } hp_sys;
+    struct {
+        pmu_lp_power_t  dig_power;
+        pmu_lp_power_t  clk_power;
+        pmu_lp_power_t  xtal;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_power_config_t;
+
+#define PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags) {                          \
+    .hp_sys = {                                                             \
+        .dig_power = {                                                      \
+            .vdd_spi_pd_en = ((pd_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0,   \
+            .wifi_pd_en    = ((pd_flags) & PMU_SLEEP_PD_MODEM)   ? 1 : 0,   \
+            .cpu_pd_en     = ((pd_flags) & PMU_SLEEP_PD_CPU)     ? 1 : 0,   \
+            .aon_pd_en     = ((pd_flags) & PMU_SLEEP_PD_AON)     ? 1 : 0,   \
+            .top_pd_en     = ((pd_flags) & PMU_SLEEP_PD_TOP)     ? 1 : 0,   \
+            .mem_pd_en     = 0,                                             \
+            .mem_dslp      = 0                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .i2c_iso_en    = 1,                                             \
+            .i2c_retention = 1,                                             \
+            .xpd_bb_i2c    = 0,                                             \
+            .xpd_bbpll_i2c = 0,                                             \
+            .xpd_bbpll     = 0                                              \
+        },                                                                  \
+        .xtal = {                                                           \
+            .xpd_xtal      = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1,      \
+        }                                                                   \
+    },                                                                      \
+    .lp_sys[PMU_MODE_LP_ACTIVE] = {                                         \
+        .dig_power = {                                                      \
+            .peri_pd_en    = 0,                                             \
+            .mem_dslp      = 0                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .xpd_xtal32k   = 1,                                             \
+            .xpd_rc32k     = 1,                                             \
+            .xpd_fosc      = 1                                              \
+        }                                                                   \
+    },                                                                      \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                                          \
+        .dig_power = {                                                      \
+            .peri_pd_en    = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
+            .mem_dslp      = 1                                              \
+        },                                                                  \
+        .clk_power = {                                                      \
+            .xpd_xtal32k   = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,   \
+            .xpd_rc32k     = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1,     \
+            .xpd_fosc      = ((pd_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1    \
+        },                                                                  \
+        .xtal = {                                                           \
+            .xpd_xtal      = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1,      \
+        }                                                                   \
+    }                                                                       \
+}
+
+typedef struct {
+    struct {
+        pmu_hp_analog_t analog;
+    } hp_sys;
+    struct {
+        pmu_lp_analog_t analog;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_analog_config_t;
+
+#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) {    \
+    .hp_sys = {                                             \
+        .analog = {                                         \
+            .xpd_bias        = 0x0,                         \
+            .dbg_atten       = 0x0,                         \
+            .pd_cur          = 1,                           \
+            .bias_sleep      = 1,                           \
+            .slp_mem_xpd     = 1,                           \
+            .slp_logic_xpd   = 1,                           \
+            .slp_mem_dbias   = 0x4,                         \
+            .slp_logic_dbias = 0x4,                         \
+            .xpd             = 0,                           \
+            .dbias           = 0,                           \
+            .drv_b           = 0                            \
+        }                                                   \
+    },                                                      \
+    .lp_sys[PMU_MODE_LP_ACTIVE] = {                         \
+        .analog = {                                         \
+            .slp_xpd       = 0,                             \
+            .slp_dbias     = 0xc,                           \
+            .xpd           = 1,                             \
+            .dbias         = 0x1a,                          \
+            .drv_b         = 0x0                            \
+        }                                                   \
+    },                                                      \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                          \
+        .analog = {                                         \
+            .xpd_bias      = 0,                             \
+            .dbg_atten     = 0x0,                           \
+            .pd_cur        = 1,                             \
+            .bias_sleep    = 1,                             \
+            .xpd           = 0,                             \
+            .dbias         = 0x1c,                          \
+            .slp_xpd       = 1,                             \
+            .slp_dbias     = 0x3,                           \
+            .drv_b         = 0x0                            \
+        }                                                   \
+    }                                                       \
+}
+
+#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) {    \
+    .hp_sys = {                                             \
+        .analog = {                                         \
+            .xpd_bias        = 0,                           \
+            .dbg_atten       = 0x3,                         \
+            .pd_cur          = 1,                           \
+            .bias_sleep      = 1,                           \
+            .xpd             = 0,                           \
+            .dbias           = 0x15,                        \
+            .slp_mem_xpd     = 1,                           \
+            .slp_mem_dbias   = 0xc,                         \
+            .slp_logic_xpd   = 1,                           \
+            .slp_logic_dbias = 0x5,                         \
+            .drv_b           = 0x18c                        \
+        }                                                   \
+    },                                                      \
+    .lp_sys[PMU_MODE_LP_ACTIVE] = {                         \
+        .analog = {                                         \
+            .xpd           = 1,                             \
+            .dbias         = 0x1a,                          \
+            .slp_xpd       = 0,                             \
+            .slp_dbias     = 0,                             \
+            .drv_b         = 0x7                            \
+        }                                                   \
+    },                                                      \
+    .lp_sys[PMU_MODE_LP_SLEEP] = {                          \
+        .analog = {                                         \
+            .xpd_bias      = 0,                             \
+            .dbg_atten     = 0xe,                           \
+            .pd_cur        = 1,                             \
+            .bias_sleep    = 1,                             \
+            .xpd           = 0,                             \
+            .dbias         = 0,                             \
+            .slp_xpd       = 1,                             \
+            .slp_dbias     = 0xe,                           \
+            .drv_b         = 0                              \
+        }                                                   \
+    }                                                       \
+}
+
+typedef struct {
+    pmu_hp_param_t      hp_sys;
+    pmu_lp_param_t      lp_sys;
+    pmu_hp_lp_param_t   hp_lp;
+} pmu_sleep_param_config_t;
+
+#define PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags) {                                  \
+    .hp_sys = {                                                                     \
+        .min_slp_slow_clk_cycle          = PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES,        \
+        .analog_wait_target_cycle        = PMU_HP_ANALOG_WAIT_TARGET_CYCLES,        \
+        .digital_power_supply_wait_cycle = PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
+        .digital_power_up_wait_cycle     = PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES,     \
+        .modem_wakeup_wait_cycle         = PMU_HP_MODEM_WAKEUP_WAIT_CYCLES,         \
+        .pll_stable_wait_cycle           = PMU_HP_PLL_STABLE_WAIT_CYCLES            \
+    },                                                                              \
+    .lp_sys = {                                                                     \
+        .min_slp_slow_clk_cycle          = PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES,        \
+        .analog_wait_target_cycle        = PMU_LP_ANALOG_WAIT_TARGET_CYCLES,        \
+        .digital_power_supply_wait_cycle = PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
+        .digital_power_up_wait_cycle     = PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES      \
+    },                                                                              \
+    .hp_lp = {                                                                      \
+        .xtal_stable_wait_slow_clk_cycle = PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES  \
+    }                                                                               \
+}
+
+typedef struct {
+    pmu_sleep_power_config_t  power;
+    pmu_sleep_analog_config_t analog;
+    pmu_sleep_param_config_t  param;
+} pmu_sleep_config_t;
+
+typedef struct pmu_sleep_machine_constant {
+    struct {
+        uint16_t    min_slp_time_ms;            /* Mininum sleep protection time (unit: microsecond) */
+        uint8_t     wakeup_wait_cycle;          /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */
+        uint8_t     reserved0;
+        uint16_t    reserved1;
+        uint16_t    analog_wait_time_ms;        /* LP LDO power up wait time (unit: microsecond) */
+        uint16_t    xtal_wait_stable_time_ms;   /* Main XTAL stabilization wait time (unit: microsecond) */
+        uint8_t     clk_switch_cycle;           /* Clock switch to FOSC (unit: slow clock cycle) */
+        uint8_t     clk_power_on_wait_cycle;    /* Clock power on wait cycle (unit: slow clock cycle) */
+        uint16_t    power_supply_wait_time_ms;  /* (unit: microsecond) */
+        uint16_t    power_up_wait_time_ms;      /* (unit: microsecond) */
+    } lp;
+    struct {
+        uint16_t    min_slp_time_ms;            /* Mininum sleep protection time (unit: microsecond) */
+        uint16_t    clock_domain_sync_time_ms;  /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
+        uint16_t    system_dfs_up_work_time_ms; /* System DFS up scaling work time (unit: microsecond) */
+        uint16_t    analog_wait_time_ms;        /* HP LDO power up wait time (unit: microsecond) */
+        uint16_t    power_supply_wait_time_ms;  /* (unit: microsecond) */
+        uint16_t    power_up_wait_time_ms;      /* (unit: microsecond) */
+        uint16_t    regdma_s2m_work_time_ms;    /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */
+        uint16_t    regdma_s2a_work_time_ms;    /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (S2A switch) restore time (unit: microsecond) */
+        uint16_t    regdma_m2a_work_time_ms;    /* Digital Peripheral (M2A switch) REGDMA restore time (unit: microsecond) */
+        uint16_t    regdma_a2s_work_time_ms;    /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (A2S switch) backup time (unit: microsecond) */
+        uint16_t    regdma_rf_on_work_time_ms;  /* The REGDMA work time of RF enable (unit: microsecond) */
+        uint16_t    regdma_rf_off_work_time_ms; /* The REGDMA work time of RF disable (unit: microsecond) */
+        uint16_t    xtal_wait_stable_time_ms;   /* Main XTAL stabilization wait time (unit: microsecond) */
+        uint16_t    pll_wait_stable_time_ms;    /* PLL stabilization wait time (unit: microsecond) */
+    } hp;
+} pmu_sleep_machine_constant_t;
+
+#define PMU_SLEEP_MC_DEFAULT()      {           \
+    .lp = {                                     \
+        .min_slp_time_ms                = 450,  \
+        .wakeup_wait_cycle              = 4,    \
+        .analog_wait_time_ms            = 154,  \
+        .xtal_wait_stable_time_ms       = 250,  \
+        .clk_switch_cycle               = 1,    \
+        .clk_power_on_wait_cycle        = 1,    \
+        .power_supply_wait_time_ms      = 2,    \
+        .power_up_wait_time_ms          = 2     \
+    },                                          \
+    .hp = {                                     \
+        .min_slp_time_ms                = 450,  \
+        .clock_domain_sync_time_ms      = 150,  \
+        .system_dfs_up_work_time_ms     = 124,  \
+        .analog_wait_time_ms            = 154,  \
+        .power_supply_wait_time_ms      = 2,    \
+        .power_up_wait_time_ms          = 2,    \
+        .regdma_s2m_work_time_ms        = 172,  \
+        .regdma_s2a_work_time_ms        = 430,  \
+        .regdma_m2a_work_time_ms        = 265,  \
+        .regdma_a2s_work_time_ms        = 338,  \
+        .regdma_rf_on_work_time_ms      = 70,   \
+        .regdma_rf_off_work_time_ms     = 23,   \
+        .xtal_wait_stable_time_ms       = 250,  \
+        .pll_wait_stable_time_ms        = 1     \
+    }                                           \
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/port/esp32c6/rtc_init.c

@@ -1,26 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/rtc.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_dig_reg.h"
-#include "regi2c_ctrl.h"
-
-// TODO: IDF-5781
-
-void rtc_init(rtc_config_t cfg)
-{
-    /* Peripheral reg i2c power up */
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
-    REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, 25);
-    REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, 26);
-}

components/esp_hw_support/sleep_modes.c

@@ -24,7 +24,11 @@
 #include "soc/soc_caps.h"
 #include "driver/rtc_io.h"
 #include "hal/rtc_io_hal.h"
+
+#if !SOC_PMU_SUPPORTED
 #include "hal/rtc_cntl_ll.h"
+#include "hal/rtc_hal.h"
+#endif
 
 #include "driver/uart.h"
 
@@ -33,7 +37,6 @@
 #include "regi2c_ctrl.h"    //For `REGI2C_ANA_CALI_PD_WORKAROUND`, temp
 
 #include "hal/wdt_hal.h"
-#include "hal/rtc_hal.h"
 #include "hal/uart_hal.h"
 #if SOC_TOUCH_SENSOR_SUPPORTED
 #include "hal/touch_sensor_hal.h"
@@ -87,6 +90,7 @@
 
 // Cycles for RTC Timer clock source (internal oscillator) calibrate
 #define RTC_CLK_SRC_CAL_CYCLES      (10)
+#define FAST_CLK_SRC_CAL_CYCLES     (2000)  /* ~ 127.4 us */
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (212)
@@ -107,8 +111,8 @@
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
 #elif CONFIG_IDF_TARGET_ESP32C6
-#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)// TODO: IDF-5348
-#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
+#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)// TODO: IDF-6267
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
@@ -154,6 +158,7 @@ typedef struct {
     uint32_t ccount_ticks_record;
     uint32_t sleep_time_overhead_out;
     uint32_t rtc_clk_cal_period;
+    uint32_t fast_clk_cal_period;
     uint64_t rtc_ticks_at_sleep_start;
 } sleep_config_t;
 
@@ -161,7 +166,7 @@ typedef struct {
 _Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size");
 
 static sleep_config_t s_config = {
-    .pd_options = {[0 ... ESP_PD_DOMAIN_MAX - 1] = ESP_PD_OPTION_AUTO,},
+    .pd_options = { [0 ... ESP_PD_DOMAIN_MAX - 1] = ESP_PD_OPTION_AUTO },
     .ccount_ticks_record = 0,
     .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US,
     .wakeup_triggers = 0
@@ -492,6 +497,12 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     }
 
     // Enter sleep
+#if CONFIG_IDF_TARGET_ESP32C6
+    pmu_sleep_config_t config;
+    pmu_sleep_init(pmu_sleep_config_default(&config, pd_flags, s_config.sleep_time_adjustment,
+            s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
+            deep_sleep), deep_sleep);
+#else
     rtc_sleep_config_t config;
     rtc_sleep_get_default_config(sleep_flags, &config);
     rtc_sleep_init(config);
@@ -500,6 +511,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
     if (!deep_sleep) {
         rtc_sleep_low_init(s_config.rtc_clk_cal_period);
     }
+#endif
 
     // Configure timer wakeup
     if (s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) {
@@ -665,11 +677,11 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
  * x                        |  1                                   |  pd flash with relaxed conditions(force_pd)
  * 1                        |  0                                   |  pd flash with strict  conditions(safe_pd)
  */
-static inline bool can_power_down_vddsdio(const uint32_t vddsdio_pd_sleep_duration)
+static inline bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
 {
     bool force_pd = !(s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) || (s_config.sleep_duration > vddsdio_pd_sleep_duration);
     bool safe_pd  = (s_config.wakeup_triggers == RTC_TIMER_TRIG_EN) && (s_config.sleep_duration > vddsdio_pd_sleep_duration);
-    return (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] == ESP_PD_OPTION_OFF) ? force_pd : safe_pd;
+    return (pd_flags & RTC_SLEEP_PD_VDDSDIO) ? force_pd : safe_pd;
 }
 
 esp_err_t esp_light_sleep_start(void)
@@ -743,6 +755,10 @@ esp_err_t esp_light_sleep_start(void)
     esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32C6
+    s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
+#endif
+
     /*
      * Adjustment time consists of parts below:
      * 1. Hardware time waiting for internal 8M oscilate clock and XTAL;
@@ -751,9 +767,15 @@ esp_err_t esp_light_sleep_start(void)
      * 4. Code execution time which can be measured;
      */
 
+#if CONFIG_IDF_TARGET_ESP32C6
+    int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out;
+    int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
+    s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
+#else
     uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
     s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out
                                      + rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period);
+#endif
 
     // Decide if VDD_SDIO needs to be powered down;
     // If it needs to be powered down, adjust sleep time.
@@ -781,7 +803,7 @@ esp_err_t esp_light_sleep_start(void)
                         flash_enable_time_us + LIGHT_SLEEP_MIN_TIME_US + s_config.sleep_time_adjustment
                         + rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period));
 
-        if (can_power_down_vddsdio(vddsdio_pd_sleep_duration)) {
+        if (can_power_down_vddsdio(pd_flags, vddsdio_pd_sleep_duration)) {
             if (s_config.sleep_time_overhead_out < flash_enable_time_us) {
                 s_config.sleep_time_adjustment += flash_enable_time_us;
             }
@@ -1384,9 +1406,27 @@ static uint32_t get_power_down_flags(void)
         s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
     }
 #endif
+    /**
+     * VDD_SDIO power domain shall be kept on during the light sleep
+     * when CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set and off when it is set.
+     * The application can still force the power domain to remain on by calling
+     * `esp_sleep_pd_config` before getting into light sleep mode.
+     *
+     * In deep sleep mode, the power domain will be turned off, regardless the
+     * value of this field.
+     */
+#if SOC_PM_SUPPORT_VDDSDIO_PD
+    if (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] == ESP_PD_OPTION_AUTO) {
+#ifndef CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
+        s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] = ESP_PD_OPTION_ON;
+#endif
+    }
+#endif
 
+#if SOC_PM_SUPPORT_XTAL_PD
 #ifdef CONFIG_IDF_TARGET_ESP32
     s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
+#endif
 #endif
 
    const  __attribute__((unused)) char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
@@ -1424,31 +1464,39 @@ static uint32_t get_power_down_flags(void)
         pd_flags |= RTC_SLEEP_PD_CPU;
     }
 #endif
+#if SOC_PM_SUPPORT_XTAL32K_PD
+    if (s_config.pd_options[ESP_PD_DOMAIN_XTAL32K] != ESP_PD_OPTION_ON) {
+        pd_flags |= PMU_SLEEP_PD_XTAL32K;
+    }
+#endif
+#if SOC_PM_SUPPORT_RC32K_PD
+    if (s_config.pd_options[ESP_PD_DOMAIN_RC32K] != ESP_PD_OPTION_ON) {
+        pd_flags |= PMU_SLEEP_PD_RC32K;
+    }
+#endif
+#if SOC_PM_SUPPORT_RC_FAST_PD
     if (s_config.pd_options[ESP_PD_DOMAIN_RC_FAST] != ESP_PD_OPTION_ON) {
+#if CONFIG_IDF_TARGET_ESP32C6
+        pd_flags |= PMU_SLEEP_PD_FOSC;
+#else
         pd_flags |= RTC_SLEEP_PD_INT_8M;
+#endif
     }
+#endif
+#if SOC_PM_SUPPORT_XTAL_PD
     if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
         pd_flags |= RTC_SLEEP_PD_XTAL;
     }
-
-    /**
-     * VDD_SDIO power domain shall be kept on during the light sleep
-     * when CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set and off when it is set.
-     * The application can still force the power domain to remain on by calling
-     * `esp_sleep_pd_config` before getting into light sleep mode.
-     *
-     * In deep sleep mode, the power domain will be turned off, regardless the
-     * value of this field.
-     */
-    if (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] == ESP_PD_OPTION_AUTO) {
-#ifndef CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
-        s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] = ESP_PD_OPTION_ON;
 #endif
-    }
-
+#if SOC_PM_SUPPORT_VDDSDIO_PD
     if (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] != ESP_PD_OPTION_ON) {
+#if CONFIG_IDF_TARGET_ESP32C6
+        pd_flags |= PMU_SLEEP_PD_VDDSDIO;
+#else
         pd_flags |= RTC_SLEEP_PD_VDDSDIO;
+#endif
     }
+#endif
 
 #if ((defined CONFIG_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT) && (SOC_PM_SUPPORT_RTC_PERIPH_PD))
     if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {

components/esp_system/fpga_overrides.c

@@ -23,6 +23,7 @@
 #include "esp32c2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rtc.h"
+#include "esp_private/esp_pmu.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rtc.h"
 #endif
@@ -72,6 +73,9 @@ void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
 void esp_clk_init(void)
 {
     s_warn();
+#if SOC_PMU_SUPPORTED
+    pmu_init();
+#endif
 }
 
 void esp_perip_clk_init(void)

components/esp_system/port/soc/esp32c6/clk.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,7 @@
 #include "esp_private/esp_modem_clock.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/esp_pmu.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 
@@ -42,13 +43,7 @@ static const char *TAG = "clk";
  __attribute__((weak)) void esp_clk_init(void)
 {
 #if !CONFIG_IDF_ENV_FPGA
-    rtc_config_t cfg = RTC_CONFIG_DEFAULT();
-    soc_reset_reason_t rst_reas;
-    rst_reas = esp_rom_get_reset_reason(0);
-    if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
-        cfg.cali_ocode = 1;
-    }
-    rtc_init(cfg);
+    pmu_init();
 
     assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
 

components/hal/esp32c6/rtc_cntl_hal.c

@@ -1,53 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// The HAL layer for RTC CNTL (common part)
-
-#include "soc/soc_caps.h"
-#include "soc/lldesc.h"
-#include "hal/dma_types.h"
-#include "hal/rtc_hal.h"
-#include "hal/assert.h"
-#include "esp_attr.h"
-
-#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN  (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
-
-typedef struct rtc_cntl_link_buf_conf {
-    uint32_t cfg[4];    /* 4 word for dma link buffer configuration */
-} rtc_cntl_link_buf_conf_t;
-
-void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
-{
-    HAL_ASSERT(elem != NULL);
-    HAL_ASSERT(buff != NULL);
-    HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
-
-    lldesc_t *plink = (lldesc_t *)elem;
-
-    plink->eof    = next ? 0 : 1;
-    plink->owner  = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-    plink->size   = size >> 4;  /* in unit of 16 bytes */
-    plink->length = size >> 4;
-    plink->buf    = buff;
-    plink->offset = 0;
-    plink->sosf   = 0;
-    STAILQ_NEXT(plink, qe) = next;
-    return (void *)plink;
-}
-
-#if SOC_PM_SUPPORT_CPU_PD
-
-void rtc_cntl_hal_enable_cpu_retention(void *addr)
-{
-    // TODO: IDF-5718 has removed the retention feature
-}
-
-void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
-{
-    // TODO: IDF-5718 has removed the retention feature
-}
-
-#endif // SOC_PM_SUPPORT_CPU_PD

components/soc/esp32c6/include/soc/rtc.h

@@ -578,23 +578,6 @@ typedef struct {
     uint32_t light_slp_reject : 1;      //!< enable light sleep reject
 } rtc_sleep_config_t;
 
-#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
-#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
-#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
-#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
-#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
-#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
-#define RTC_SLEEP_PD_WIFI               BIT(6)  //!< Power down WIFI
-#define RTC_SLEEP_PD_BT                 BIT(7)  //!< Power down BT
-#define RTC_SLEEP_PD_CPU                BIT(8)  //!< Power down CPU when in lightsleep, but not restart
-#define RTC_SLEEP_PD_DIG_PERIPH         BIT(9)  //!< Power down DIG peripherals
-#define RTC_SLEEP_PD_INT_8M             BIT(10) //!< Power down Internal 8M oscillator
-#define RTC_SLEEP_PD_XTAL               BIT(11) //!< Power down main XTAL
-
-//These flags are not power domains, but will affect some sleep parameters
-#define RTC_SLEEP_DIG_USE_8M            BIT(16)
-#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
-#define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
 
 /**
  * Default initializer for rtc_sleep_config_t
@@ -640,29 +623,6 @@ void rtc_sleep_low_init(uint32_t slowclk_period);
  */
 void rtc_sleep_set_wakeup_time(uint64_t t);
 
-#define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
-#define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup
-#define RTC_WIFI_TRIG_EN            BIT(5)  //!< WIFI wakeup (light sleep only)
-#define RTC_UART0_TRIG_EN           BIT(6)  //!< UART0 wakeup (light sleep only)
-#define RTC_UART1_TRIG_EN           BIT(7)  //!< UART1 wakeup (light sleep only)
-#define RTC_BT_TRIG_EN              BIT(10) //!< BT wakeup (light sleep only)
-#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
-#define RTC_USB_TRIG_EN             BIT(14)
-#define RTC_BROWNOUT_DET_TRIG_EN    BIT(16)
-
-/**
- * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
- */
-#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN         | \
-                               RTC_TIMER_TRIG_EN        | \
-                               RTC_WIFI_TRIG_EN         | \
-                               RTC_UART0_TRIG_EN        | \
-                               RTC_UART1_TRIG_EN        | \
-                               RTC_BT_TRIG_EN           | \
-                               RTC_XTAL32K_DEAD_TRIG_EN | \
-                               RTC_USB_TRIG_EN          | \
-                               RTC_BROWNOUT_DET_TRIG_EN)
-
 /**
  * @brief Enter deep or light sleep mode
  *