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@@ -110,6 +110,18 @@ static const char *I2C_TAG = "i2c";
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#endif
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#define I2C_MEM_ALLOC_CAPS_DEFAULT MALLOC_CAP_DEFAULT
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+#if SOC_PERIPH_CLK_CTRL_SHARED
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+#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
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+#else
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+#define I2C_CLOCK_SRC_ATOMIC()
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+#endif
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+
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+#if !SOC_RCC_IS_INDEPENDENT
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+#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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+#else
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+#define I2C_RCC_ATOMIC()
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+#endif
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+
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/**
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* I2C bus are defined in the header files, let's check that the values are correct
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*/
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@@ -240,7 +252,9 @@ static void i2c_hw_disable(i2c_port_t i2c_num)
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{
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I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
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if (i2c_context[i2c_num].hw_enabled != false) {
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- periph_module_disable(i2c_periph_signal[i2c_num].module);
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+ I2C_RCC_ATOMIC() {
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+ i2c_ll_enable_bus_clock(i2c_num, false);
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+ }
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i2c_context[i2c_num].hw_enabled = false;
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}
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I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock));
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@@ -250,7 +264,10 @@ static void i2c_hw_enable(i2c_port_t i2c_num)
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{
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I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
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if (i2c_context[i2c_num].hw_enabled != true) {
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- periph_module_enable(i2c_periph_signal[i2c_num].module);
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+ I2C_RCC_ATOMIC() {
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+ i2c_ll_enable_bus_clock(i2c_num, true);
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+ i2c_ll_reset_register(i2c_num);
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+ }
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i2c_context[i2c_num].hw_enabled = true;
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}
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I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock));
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@@ -375,7 +392,9 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
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return ESP_FAIL;
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}
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i2c_hw_enable(i2c_num);
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- i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
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+ I2C_CLOCK_SRC_ATOMIC() {
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+ i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
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+ }
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//Disable I2C interrupt.
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i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK);
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i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK);
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@@ -478,7 +497,9 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
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}
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#endif
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- i2c_hal_deinit(&i2c_context[i2c_num].hal);
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+ I2C_CLOCK_SRC_ATOMIC() {
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+ i2c_hal_deinit(&i2c_context[i2c_num].hal);
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+ }
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free(p_i2c_obj[i2c_num]);
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p_i2c_obj[i2c_num] = NULL;
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@@ -746,7 +767,9 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
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return ret;
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}
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i2c_hw_enable(i2c_num);
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- i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
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+ I2C_CLOCK_SRC_ATOMIC() {
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+ i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
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+ }
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I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
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i2c_ll_disable_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK);
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i2c_ll_clear_intr_mask(i2c_context[i2c_num].hal.dev, I2C_LL_INTR_MASK);
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@@ -754,7 +777,9 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
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if (i2c_conf->mode == I2C_MODE_SLAVE) { //slave mode
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i2c_hal_slave_init(&(i2c_context[i2c_num].hal));
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i2c_ll_slave_tx_auto_start_en(i2c_context[i2c_num].hal.dev, true);
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- i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
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+ I2C_CLOCK_SRC_ATOMIC() {
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+ i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
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+ }
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i2c_ll_set_slave_addr(i2c_context[i2c_num].hal.dev, i2c_conf->slave.slave_addr, i2c_conf->slave.addr_10bit_en);
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i2c_ll_set_rxfifo_full_thr(i2c_context[i2c_num].hal.dev, I2C_FIFO_FULL_THRESH_VAL);
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i2c_ll_set_txfifo_empty_thr(i2c_context[i2c_num].hal.dev, I2C_FIFO_EMPTY_THRESH_VAL);
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@@ -768,7 +793,9 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
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i2c_hal_master_init(&(i2c_context[i2c_num].hal));
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//Default, we enable hardware filter
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i2c_ll_master_set_filter(i2c_context[i2c_num].hal.dev, I2C_FILTER_CYC_NUM_DEF);
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- i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, src_clk, s_get_src_clk_freq(src_clk));
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+ I2C_CLOCK_SRC_ATOMIC() {
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+ i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, src_clk, s_get_src_clk_freq(src_clk));
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+ }
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}
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i2c_ll_update(i2c_context[i2c_num].hal.dev);
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I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock));
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