Merge branch 'feat/esp32s3_support_gpio_deepsleep_wakeup' into 'master'

example/deep_sleep: add example of EXT0 and using internal pullups

Closes IDF-4657 and IDFGH-6711

See merge request espressif/esp-idf!17099

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -23,30 +23,6 @@ config SOC_CPU_HAS_FPU
     bool
     default y
 
-config SOC_GPIO_PORT
-    int
-    default 1
-
-config SOC_GPIO_PIN_COUNT
-    int
-    default 49
-
-config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-    bool
-    default y
-
-config SOC_GPIO_SUPPORT_FORCE_HOLD
-    bool
-    default y
-
-config SOC_GPIO_VALID_GPIO_MASK
-    hex
-    default 0x1FFFFFFFFFFFF
-
-config SOC_GPIO_SUPPORT_SLP_SWITCH
-    bool
-    default y
-
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
@@ -83,22 +59,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
     bool
     default n
 
-config SOC_RTCIO_PIN_COUNT
-    int
-    default 22
-
-config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
-    bool
-    default y
-
-config SOC_RTCIO_HOLD_SUPPORTED
-    bool
-    default y
-
-config SOC_RTCIO_WAKE_SUPPORTED
-    bool
-    default y
-
 config SOC_ADC_SUPPORTED
     bool
     default y
@@ -339,6 +299,30 @@ config SOC_GDMA_PSRAM_MIN_ALIGN
     int
     default 16
 
+config SOC_GPIO_PORT
+    int
+    default 1
+
+config SOC_GPIO_PIN_COUNT
+    int
+    default 49
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
+
+config SOC_GPIO_VALID_GPIO_MASK
+    hex
+    default 0x1FFFFFFFFFFFF
+
+config SOC_GPIO_SUPPORT_SLP_SWITCH
+    bool
+    default y
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
@@ -559,6 +543,22 @@ config SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH
     int
     default 128
 
+config SOC_RTCIO_PIN_COUNT
+    int
+    default 22
+
+config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_HOLD_SUPPORTED
+    bool
+    default y
+
+config SOC_RTCIO_WAKE_SUPPORTED
+    bool
+    default y
+
 config SOC_SIGMADELTA_NUM
     bool
     default y

components/soc/esp32s3/include/soc/gpio_caps.h

@@ -1,32 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S3 has 1 GPIO peripheral
-#define SOC_GPIO_PORT           (1U)
-#define SOC_GPIO_PIN_COUNT      (49)
-
-// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
-// Force hold is a new function of ESP32-S3
-#define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
-
-// 0~48 except from 22~25 are valid
-#define SOC_GPIO_VALID_GPIO_MASK         (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
-// No GPIO is input only
-#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK  (SOC_GPIO_VALID_GPIO_MASK)
-
-// Support to configure slept status
-#define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32s3/include/soc/rtc_io_caps.h

@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define SOC_RTCIO_PIN_COUNT   22
-#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
-#define SOC_RTCIO_HOLD_SUPPORTED 1
-#define SOC_RTCIO_WAKE_SUPPORTED 1

components/soc/esp32s3/include/soc/soc_caps.h

@@ -119,7 +119,23 @@
 #define SOC_GDMA_PSRAM_MIN_ALIGN   (16) // Minimal alignment for PSRAM transaction
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
-#include "gpio_caps.h"
+// ESP32-S3 has 1 GPIO peripheral
+#define SOC_GPIO_PORT           (1U)
+#define SOC_GPIO_PIN_COUNT      (49)
+
+// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
+// Force hold is a new function of ESP32-S3
+#define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
+
+// 0~48 except from 22~25 are valid
+#define SOC_GPIO_VALID_GPIO_MASK         (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
+// No GPIO is input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK  (SOC_GPIO_VALID_GPIO_MASK)
+
+// Support to configure slept status
+#define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
+
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
@@ -213,7 +229,10 @@
 #define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN   (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
-#include "rtc_io_caps.h"
+#define SOC_RTCIO_PIN_COUNT   22
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
+#define SOC_RTCIO_HOLD_SUPPORTED 1
+#define SOC_RTCIO_WAKE_SUPPORTED 1
 
 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/
 #define SOC_SIGMADELTA_NUM         (1) // 1 sigma-delta peripheral

examples/system/deep_sleep/main/Kconfig.projbuild

@@ -19,8 +19,17 @@ menu "Example Configuration"
             the window defined by the initial temperature and a threshold
             around it.
 
+    config EXAMPLE_EXT0_WAKEUP
+        bool "Enable wakeup from GPIO (ext0)"
+        default y
+        depends on !SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+        help
+            This option enables wake up from deep sleep from GPIO3. They should be connected to LOW to avoid
+            floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
+            pins may trigger a wake up.
+
     config EXAMPLE_EXT1_WAKEUP
-        bool "Enable wakeup from GPIO"
+        bool "Enable wakeup from GPIO (ext1)"
         default y
         depends on !SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
         help
@@ -28,6 +37,21 @@ menu "Example Configuration"
             floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
             pins may trigger a wake up.
 
+    config EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
+        bool "Use internal pull-up/downs for EXT1 wakeup source"
+        default n
+        depends on EXAMPLE_EXT1_WAKEUP
+        help
+            When using EXT1 wakeup source without external pull-up/downs, you may want to make use of the internal
+            ones.
+
+            However, the RTC IO reside in the RTC Periph power domain. Enable this option to force that power domain
+            ON during deep sleep. Note that this will increase some power comsumption, so it's still suggested to use
+            external ones instead.
+
+            EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal pull-up/downs are
+            always available. There's no need to explicitly force it on for EXT0.
+
     config EXAMPLE_GPIO_WAKEUP
         bool "Enable wakeup from GPIO"
         default y

examples/system/deep_sleep/main/deep_sleep_example_main.c

@@ -103,6 +103,12 @@ void app_main(void)
     int sleep_time_ms = (now.tv_sec - sleep_enter_time.tv_sec) * 1000 + (now.tv_usec - sleep_enter_time.tv_usec) / 1000;
 
     switch (esp_sleep_get_wakeup_cause()) {
+#if CONFIG_EXAMPLE_EXT0_WAKEUP
+        case ESP_SLEEP_WAKEUP_EXT0: {
+            printf("Wake up from ext0\n");
+            break;
+        }
+#endif // CONFIG_EXAMPLE_EXT0_WAKEUP
 #ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
         case ESP_SLEEP_WAKEUP_EXT1: {
             uint64_t wakeup_pin_mask = esp_sleep_get_ext1_wakeup_status();
@@ -174,6 +180,18 @@ void app_main(void)
     printf("Enabling timer wakeup, %ds\n", wakeup_time_sec);
     esp_sleep_enable_timer_wakeup(wakeup_time_sec * 1000000);
 
+#if CONFIG_EXAMPLE_EXT0_WAKEUP
+    const int ext_wakeup_pin_0 = 3;
+
+    printf("Enabling EXT0 wakeup on pin GPIO%d\n", ext_wakeup_pin_0);
+    esp_sleep_enable_ext0_wakeup(ext_wakeup_pin_0, 1);
+
+    // Configure pullup/downs via RTCIO to tie wakeup pins to inactive level during deepsleep.
+    // EXT0 resides in the same power domain (RTC_PERIPH) as the RTC IO pullup/downs.
+    // No need to keep that power domain explicitly, unlike EXT1.
+    rtc_gpio_pullup_dis(ext_wakeup_pin_0);
+    rtc_gpio_pulldown_en(ext_wakeup_pin_0);
+#endif // CONFIG_EXAMPLE_EXT0_WAKEUP
 #ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
     const int ext_wakeup_pin_1 = 2;
     const uint64_t ext_wakeup_pin_1_mask = 1ULL << ext_wakeup_pin_1;
@@ -182,6 +200,17 @@ void app_main(void)
 
     printf("Enabling EXT1 wakeup on pins GPIO%d, GPIO%d\n", ext_wakeup_pin_1, ext_wakeup_pin_2);
     esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ESP_EXT1_WAKEUP_ANY_HIGH);
+
+    /* If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO
+     * during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will
+     * increase some power comsumption. */
+#  if CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
+    esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+    rtc_gpio_pullup_dis(ext_wakeup_pin_1);
+    rtc_gpio_pulldown_en(ext_wakeup_pin_1);
+    rtc_gpio_pullup_dis(ext_wakeup_pin_2);
+    rtc_gpio_pulldown_en(ext_wakeup_pin_2);
+#  endif //CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
 #endif // CONFIG_EXAMPLE_EXT1_WAKEUP
 
 #ifdef CONFIG_EXAMPLE_GPIO_WAKEUP