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@@ -26,53 +26,45 @@
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#define PRO_CPUID (0xcdcd)
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#define APP_CPUID (0xabab)
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-#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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-
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-#define DR_REG_SYSTEM_BASE 0x600c0000
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-#define DR_REG_SENSITIVE_BASE 0x600c1000
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-#define DR_REG_INTERRUPT_BASE 0x600c2000
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-#define DR_REG_EXTMEM_BASE 0x600c4000
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-#define DR_REG_MMU_TABLE 0x600c5000
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-#define DR_REG_ITAG_TABLE 0x600c6000
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-#define DR_REG_DTAG_TABLE 0x600c8000
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-#define DR_REG_AES_BASE 0x6003a000
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-#define DR_REG_SHA_BASE 0x6003b000
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-#define DR_REG_RSA_BASE 0x6003c000
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-#define DR_REG_HMAC_BASE 0x6003e000
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-#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
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-#define DR_REG_GDMA_BASE 0x6003f000
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-#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
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-#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
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-#define DR_REG_WORLD_CNTL_BASE 0x600d0000
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-#define DR_REG_DPORT_END 0x600d3FFC
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#define DR_REG_UART_BASE 0x60000000
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#define DR_REG_SPI1_BASE 0x60002000
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#define DR_REG_SPI0_BASE 0x60003000
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#define DR_REG_GPIO_BASE 0x60004000
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#define DR_REG_GPIO_SD_BASE 0x60004f00
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+
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#define DR_REG_FE2_BASE 0x60005000
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#define DR_REG_FE_BASE 0x60006000
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-#define DR_REG_FRC_TIMER_BASE 0x60007000
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+
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+#define DR_REG_EFUSE_BASE 0x60007000
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#define DR_REG_RTCCNTL_BASE 0x60008000
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#define DR_REG_RTCIO_BASE 0x60008400
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#define DR_REG_SENS_BASE 0x60008800
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#define DR_REG_RTC_I2C_BASE 0x60008C00
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#define DR_REG_IO_MUX_BASE 0x60009000
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+
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#define DR_REG_HINF_BASE 0x6000B000
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#define DR_REG_UHCI1_BASE 0x6000C000
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+
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#define DR_REG_I2S_BASE 0x6000F000
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#define DR_REG_UART1_BASE 0x60010000
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+
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#define DR_REG_BT_BASE 0x60011000
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+
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#define DR_REG_I2C_EXT_BASE 0x60013000
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#define DR_REG_UHCI0_BASE 0x60014000
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+
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#define DR_REG_SLCHOST_BASE 0x60015000
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+
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#define DR_REG_RMT_BASE 0x60016000
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#define DR_REG_PCNT_BASE 0x60017000
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+
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#define DR_REG_SLC_BASE 0x60018000
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+
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#define DR_REG_LEDC_BASE 0x60019000
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-#define DR_REG_EFUSE_BASE 0x60007000
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+
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#define DR_REG_NRX_BASE 0x6001CC00
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#define DR_REG_BB_BASE 0x6001D000
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+
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#define DR_REG_PWM0_BASE 0x6001E000
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#define DR_REG_TIMERGROUP0_BASE 0x6001F000
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#define DR_REG_TIMERGROUP1_BASE 0x60020000
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@@ -81,20 +73,45 @@
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#define DR_REG_SPI2_BASE 0x60024000
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#define DR_REG_SPI3_BASE 0x60025000
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#define DR_REG_SYSCON_BASE 0x60026000
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-#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
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+#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
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#define DR_REG_I2C1_EXT_BASE 0x60027000
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#define DR_REG_SDMMC_BASE 0x60028000
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+
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#define DR_REG_PERI_BACKUP_BASE 0x6002A000
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+
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#define DR_REG_TWAI_BASE 0x6002B000
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#define DR_REG_PWM1_BASE 0x6002C000
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#define DR_REG_I2S1_BASE 0x6002D000
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#define DR_REG_UART2_BASE 0x6002E000
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-#define DR_REG_SPI4_BASE 0x60037000
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+
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#define DR_REG_USB_DEVICE_BASE 0x60038000
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#define DR_REG_USB_WRAP_BASE 0x60039000
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+#define DR_REG_AES_BASE 0x6003A000
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+#define DR_REG_SHA_BASE 0x6003B000
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+#define DR_REG_RSA_BASE 0x6003C000
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+#define DR_REG_HMAC_BASE 0x6003E000
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+#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000
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+#define DR_REG_GDMA_BASE 0x6003F000
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#define DR_REG_APB_SARADC_BASE 0x60040000
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#define DR_REG_LCD_CAM_BASE 0x60041000
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+#define DR_REG_SYSTEM_BASE 0x600C0000
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+#define DR_REG_SENSITIVE_BASE 0x600C1000
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+#define DR_REG_INTERRUPT_BASE 0x600C2000
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+
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+/* Cache configuration */
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+#define DR_REG_EXTMEM_BASE 0x600C4000
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+#define DR_REG_MMU_TABLE 0x600C5000
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+#define DR_REG_ITAG_TABLE 0x600C6000
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+#define DR_REG_DTAG_TABLE 0x600C8000
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+
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+#define DR_REG_EXT_MEM_ENC 0x600CC000
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+
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+#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
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+#define DR_REG_WORLD_CNTL_BASE 0x600D0000
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+#define DR_REG_DPORT_END 0x600D3FFC
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+
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+
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#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
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#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
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#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
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@@ -233,23 +250,28 @@
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#define SOC_DROM_LOW 0x3C000000
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#define SOC_DROM_HIGH 0x3D000000
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#define SOC_IROM_LOW 0x42000000
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-#define SOC_IROM_HIGH 0x42800000
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+#define SOC_IROM_HIGH 0x44000000
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#define SOC_IRAM_LOW 0x40370000
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#define SOC_IRAM_HIGH 0x403E0000
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#define SOC_DRAM_LOW 0x3FC88000
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#define SOC_DRAM_HIGH 0x3FD00000
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+
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#define SOC_RTC_IRAM_LOW 0x600FE000
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#define SOC_RTC_IRAM_HIGH 0x60100000
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#define SOC_RTC_DRAM_LOW 0x600FE000
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#define SOC_RTC_DRAM_HIGH 0x60100000
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+
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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+
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#define SOC_EXTRAM_DATA_LOW 0x3D000000
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#define SOC_EXTRAM_DATA_HIGH 0x3E000000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x4001A100
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#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
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+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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+
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x40378000
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Marius Vikhammer