lcd_cam: new csv header file

components/esp_lcd/src/esp_lcd_panel_io_i80.c

@@ -128,7 +128,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
     // interrupt is disabled by default
     int isr_flags = ESP_INTR_FLAG_INTRDISABLED;
     ret = esp_intr_alloc_intrstatus(lcd_periph_signals.buses[bus_id].irq_id, isr_flags,
-                                    lcd_ll_get_interrupt_status_reg(bus->hal.dev),
+                                    (uint32_t)lcd_ll_get_interrupt_status_reg(bus->hal.dev),
                                     LCD_LL_EVENT_TRANS_DONE, lcd_default_isr_handler, bus, &bus->intr);
     ESP_GOTO_ON_ERROR(ret, no_int, TAG, "install interrupt failed");
     lcd_ll_enable_interrupt(bus->hal.dev, LCD_LL_EVENT_TRANS_DONE, false); // disable all interrupts

components/esp_lcd/src/esp_lcd_rgb_panel.c

@@ -115,7 +115,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
     // install interrupt service, (LCD peripheral shares the interrupt source with Camera by different mask)
     int isr_flags = 0;
     ret = esp_intr_alloc_intrstatus(lcd_periph_signals.panels[panel_id].irq_id, isr_flags,
-                                    lcd_ll_get_interrupt_status_reg(rgb_panel->hal.dev),
+                                    (uint32_t)lcd_ll_get_interrupt_status_reg(rgb_panel->hal.dev),
                                     LCD_LL_EVENT_VSYNC_END, lcd_default_isr_handler, rgb_panel, &rgb_panel->intr);
     ESP_GOTO_ON_ERROR(ret, no_int, TAG, "install interrupt failed");
     lcd_ll_enable_interrupt(rgb_panel->hal.dev, LCD_LL_EVENT_VSYNC_END, false); // disable all interrupts

components/hal/esp32s3/include/hal/lcd_ll.h

@@ -165,12 +165,10 @@ static inline void lcd_ll_set_command(lcd_cam_dev_t *dev, uint32_t data_width, u
 {
     // if command phase has two cycles, in the first cycle, command[15:0] is sent out via lcd_data_out[15:0]
     // in the second cycle, command[31:16] is sent out via lcd_data_out[15:0]
-    // no matter the LCD is in 8bit mode or 16bit mode
-    // so this is a workaround especially for 8bit mode
     if (data_width == 8) {
         command = (command & 0xFF) | (command & 0xFF00) << 8;
     }
-    dev->lcd_cmd_val = command;
+    dev->lcd_cmd_val.lcd_cmd_value = command;
 }
 
 static inline void lcd_ll_enable_rgb_mode(lcd_cam_dev_t *dev, bool en)
@@ -252,9 +250,9 @@ static inline void lcd_ll_clear_interrupt_status(lcd_cam_dev_t *dev, uint32_t ma
     dev->lc_dma_int_clr.val = mask & 0x03;
 }
 
-static inline uint32_t lcd_ll_get_interrupt_status_reg(lcd_cam_dev_t *dev)
+static inline volatile void *lcd_ll_get_interrupt_status_reg(lcd_cam_dev_t *dev)
 {
-    return (uint32_t)(&dev->lc_dma_int_st);
+    return &dev->lc_dma_int_st;
 }
 
 #ifdef __cplusplus

components/soc/esp32s3/include/soc/lcd_cam_reg.h

@@ -1,846 +1,1057 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_LCD_CAM_REG_H_
-#define _SOC_LCD_CAM_REG_H_
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
-
-#include "soc.h"
+#include <stdint.h>
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LCD_CAM_LCD_CLOCK_REG          (DR_REG_LCD_CAM_BASE + 0x0)
-/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define LCD_CAM_CLK_EN    (BIT(31))
-#define LCD_CAM_CLK_EN_M  (BIT(31))
-#define LCD_CAM_CLK_EN_V  0x1
-#define LCD_CAM_CLK_EN_S  31
-/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
-#define LCD_CAM_LCD_CLK_SEL    0x00000003
-#define LCD_CAM_LCD_CLK_SEL_M  ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S))
-#define LCD_CAM_LCD_CLK_SEL_V  0x3
-#define LCD_CAM_LCD_CLK_SEL_S  29
-/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value.*/
-#define LCD_CAM_LCD_CLKM_DIV_A    0x0000003F
-#define LCD_CAM_LCD_CLKM_DIV_A_M  ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S))
-#define LCD_CAM_LCD_CLKM_DIV_A_V  0x3F
-#define LCD_CAM_LCD_CLKM_DIV_A_S  23
-/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value.*/
-#define LCD_CAM_LCD_CLKM_DIV_B    0x0000003F
-#define LCD_CAM_LCD_CLKM_DIV_B_M  ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S))
-#define LCD_CAM_LCD_CLKM_DIV_B_V  0x3F
-#define LCD_CAM_LCD_CLKM_DIV_B_S  17
-/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
-/*description: Integral LCD clock divider value.*/
-#define LCD_CAM_LCD_CLKM_DIV_NUM    0x000000FF
-#define LCD_CAM_LCD_CLKM_DIV_NUM_M  ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S))
-#define LCD_CAM_LCD_CLKM_DIV_NUM_V  0xFF
-#define LCD_CAM_LCD_CLKM_DIV_NUM_S  9
-/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: .*/
-#define LCD_CAM_LCD_CK_OUT_EDGE    (BIT(8))
-#define LCD_CAM_LCD_CK_OUT_EDGE_M  (BIT(8))
-#define LCD_CAM_LCD_CK_OUT_EDGE_V  0x1
-#define LCD_CAM_LCD_CK_OUT_EDGE_S  8
-/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle. .*/
-#define LCD_CAM_LCD_CK_IDLE_EDGE    (BIT(7))
-#define LCD_CAM_LCD_CK_IDLE_EDGE_M  (BIT(7))
-#define LCD_CAM_LCD_CK_IDLE_EDGE_V  0x1
-#define LCD_CAM_LCD_CK_IDLE_EDGE_S  7
-/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/
+/** LCD_CAM_LCD_CLOCK_REG register
+ *  LCD clock register
+ */
+#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0)
+/** LCD_CAM_LCD_CLKCNT_N : R/W; bitpos: [5:0]; default: 3;
+ *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+ */
+#define LCD_CAM_LCD_CLKCNT_N    0x0000003FU
+#define LCD_CAM_LCD_CLKCNT_N_M  (LCD_CAM_LCD_CLKCNT_N_V << LCD_CAM_LCD_CLKCNT_N_S)
+#define LCD_CAM_LCD_CLKCNT_N_V  0x0000003FU
+#define LCD_CAM_LCD_CLKCNT_N_S  0
+/** LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W; bitpos: [6]; default: 1;
+ *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+ */
 #define LCD_CAM_LCD_CLK_EQU_SYSCLK    (BIT(6))
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M  (BIT(6))
-#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V  0x1
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M  (LCD_CAM_LCD_CLK_EQU_SYSCLK_V << LCD_CAM_LCD_CLK_EQU_SYSCLK_S)
+#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V  0x00000001U
 #define LCD_CAM_LCD_CLK_EQU_SYSCLK_S  6
-/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/
-#define LCD_CAM_LCD_CLKCNT_N    0x0000003F
-#define LCD_CAM_LCD_CLKCNT_N_M  ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S))
-#define LCD_CAM_LCD_CLKCNT_N_V  0x3F
-#define LCD_CAM_LCD_CLKCNT_N_S  0
+/** LCD_CAM_LCD_CK_IDLE_EDGE : R/W; bitpos: [7]; default: 0;
+ *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+ */
+#define LCD_CAM_LCD_CK_IDLE_EDGE    (BIT(7))
+#define LCD_CAM_LCD_CK_IDLE_EDGE_M  (LCD_CAM_LCD_CK_IDLE_EDGE_V << LCD_CAM_LCD_CK_IDLE_EDGE_S)
+#define LCD_CAM_LCD_CK_IDLE_EDGE_V  0x00000001U
+#define LCD_CAM_LCD_CK_IDLE_EDGE_S  7
+/** LCD_CAM_LCD_CK_OUT_EDGE : R/W; bitpos: [8]; default: 0;
+ *  1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock
+ *  cycle.
+ */
+#define LCD_CAM_LCD_CK_OUT_EDGE    (BIT(8))
+#define LCD_CAM_LCD_CK_OUT_EDGE_M  (LCD_CAM_LCD_CK_OUT_EDGE_V << LCD_CAM_LCD_CK_OUT_EDGE_S)
+#define LCD_CAM_LCD_CK_OUT_EDGE_V  0x00000001U
+#define LCD_CAM_LCD_CK_OUT_EDGE_S  8
+/** LCD_CAM_LCD_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral LCD clock divider value
+ */
+#define LCD_CAM_LCD_CLKM_DIV_NUM    0x000000FFU
+#define LCD_CAM_LCD_CLKM_DIV_NUM_M  (LCD_CAM_LCD_CLKM_DIV_NUM_V << LCD_CAM_LCD_CLKM_DIV_NUM_S)
+#define LCD_CAM_LCD_CLKM_DIV_NUM_V  0x000000FFU
+#define LCD_CAM_LCD_CLKM_DIV_NUM_S  9
+/** LCD_CAM_LCD_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCD_CAM_LCD_CLKM_DIV_B    0x0000003FU
+#define LCD_CAM_LCD_CLKM_DIV_B_M  (LCD_CAM_LCD_CLKM_DIV_B_V << LCD_CAM_LCD_CLKM_DIV_B_S)
+#define LCD_CAM_LCD_CLKM_DIV_B_V  0x0000003FU
+#define LCD_CAM_LCD_CLKM_DIV_B_S  17
+/** LCD_CAM_LCD_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCD_CAM_LCD_CLKM_DIV_A    0x0000003FU
+#define LCD_CAM_LCD_CLKM_DIV_A_M  (LCD_CAM_LCD_CLKM_DIV_A_V << LCD_CAM_LCD_CLKM_DIV_A_S)
+#define LCD_CAM_LCD_CLKM_DIV_A_V  0x0000003FU
+#define LCD_CAM_LCD_CLKM_DIV_A_S  23
+/** LCD_CAM_LCD_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCD_CAM_LCD_CLK_SEL    0x00000003U
+#define LCD_CAM_LCD_CLK_SEL_M  (LCD_CAM_LCD_CLK_SEL_V << LCD_CAM_LCD_CLK_SEL_S)
+#define LCD_CAM_LCD_CLK_SEL_V  0x00000003U
+#define LCD_CAM_LCD_CLK_SEL_S  29
+/** LCD_CAM_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define LCD_CAM_CLK_EN    (BIT(31))
+#define LCD_CAM_CLK_EN_M  (LCD_CAM_CLK_EN_V << LCD_CAM_CLK_EN_S)
+#define LCD_CAM_CLK_EN_V  0x00000001U
+#define LCD_CAM_CLK_EN_S  31
 
-#define LCD_CAM_CAM_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x4)
-/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
-#define LCD_CAM_CAM_CLK_SEL    0x00000003
-#define LCD_CAM_CAM_CLK_SEL_M  ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S))
-#define LCD_CAM_CAM_CLK_SEL_V  0x3
-#define LCD_CAM_CAM_CLK_SEL_S  29
-/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value.*/
-#define LCD_CAM_CAM_CLKM_DIV_A    0x0000003F
-#define LCD_CAM_CAM_CLKM_DIV_A_M  ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S))
-#define LCD_CAM_CAM_CLKM_DIV_A_V  0x3F
-#define LCD_CAM_CAM_CLKM_DIV_A_S  23
-/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value.*/
-#define LCD_CAM_CAM_CLKM_DIV_B    0x0000003F
-#define LCD_CAM_CAM_CLKM_DIV_B_M  ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S))
-#define LCD_CAM_CAM_CLKM_DIV_B_V  0x3F
-#define LCD_CAM_CAM_CLKM_DIV_B_S  17
-/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
-/*description: Integral Camera clock divider value.*/
-#define LCD_CAM_CAM_CLKM_DIV_NUM    0x000000FF
-#define LCD_CAM_CAM_CLKM_DIV_NUM_M  ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S))
-#define LCD_CAM_CAM_CLKM_DIV_NUM_V  0xFF
-#define LCD_CAM_CAM_CLKM_DIV_NUM_S  9
-/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_
-data_cyclelen..*/
-#define LCD_CAM_CAM_VS_EOF_EN    (BIT(8))
-#define LCD_CAM_CAM_VS_EOF_EN_M  (BIT(8))
-#define LCD_CAM_CAM_VS_EOF_EN_V  0x1
-#define LCD_CAM_CAM_VS_EOF_EN_S  8
-/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/
-#define LCD_CAM_CAM_LINE_INT_EN    (BIT(7))
-#define LCD_CAM_CAM_LINE_INT_EN_M  (BIT(7))
-#define LCD_CAM_CAM_LINE_INT_EN_V  0x1
-#define LCD_CAM_CAM_LINE_INT_EN_S  7
-/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
-#define LCD_CAM_CAM_BIT_ORDER    (BIT(6))
-#define LCD_CAM_CAM_BIT_ORDER_M  (BIT(6))
-#define LCD_CAM_CAM_BIT_ORDER_V  0x1
-#define LCD_CAM_CAM_BIT_ORDER_S  6
-/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt
-e mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
-#define LCD_CAM_CAM_BYTE_ORDER    (BIT(5))
-#define LCD_CAM_CAM_BYTE_ORDER_M  (BIT(5))
-#define LCD_CAM_CAM_BYTE_ORDER_V  0x1
-#define LCD_CAM_CAM_BYTE_ORDER_S  5
-/* LCD_CAM_CAM_UPDATE_REG : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/
-#define LCD_CAM_CAM_UPDATE_REG    (BIT(4))
-#define LCD_CAM_CAM_UPDATE_REG_M  (BIT(4))
-#define LCD_CAM_CAM_UPDATE_REG_V  0x1
-#define LCD_CAM_CAM_UPDATE_REG_S  4
-/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */
-/*description: Filter threshold value for CAM_VSYNC signal..*/
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES    0x00000007
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M  ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S))
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V  0x7
-#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S  1
-/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop
-..*/
+/** LCD_CAM_CAM_CTRL_REG register
+ *  Camera configuration register
+ */
+#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4)
+/** LCD_CAM_CAM_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+ */
 #define LCD_CAM_CAM_STOP_EN    (BIT(0))
-#define LCD_CAM_CAM_STOP_EN_M  (BIT(0))
-#define LCD_CAM_CAM_STOP_EN_V  0x1
+#define LCD_CAM_CAM_STOP_EN_M  (LCD_CAM_CAM_STOP_EN_V << LCD_CAM_CAM_STOP_EN_S)
+#define LCD_CAM_CAM_STOP_EN_V  0x00000001U
 #define LCD_CAM_CAM_STOP_EN_S  0
+/** LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W; bitpos: [3:1]; default: 0;
+ *  Filter threshold value for CAM_VSYNC signal.
+ */
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES    0x00000007U
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M  (LCD_CAM_CAM_VSYNC_FILTER_THRES_V << LCD_CAM_CAM_VSYNC_FILTER_THRES_S)
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V  0x00000007U
+#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S  1
+/** LCD_CAM_CAM_UPDATE_REG : R/W; bitpos: [4]; default: 0;
+ *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCD_CAM_CAM_UPDATE_REG    (BIT(4))
+#define LCD_CAM_CAM_UPDATE_REG_M  (LCD_CAM_CAM_UPDATE_REG_V << LCD_CAM_CAM_UPDATE_REG_S)
+#define LCD_CAM_CAM_UPDATE_REG_V  0x00000001U
+#define LCD_CAM_CAM_UPDATE_REG_S  4
+/** LCD_CAM_CAM_BYTE_ORDER : R/W; bitpos: [5]; default: 0;
+ *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCD_CAM_CAM_BYTE_ORDER    (BIT(5))
+#define LCD_CAM_CAM_BYTE_ORDER_M  (LCD_CAM_CAM_BYTE_ORDER_V << LCD_CAM_CAM_BYTE_ORDER_S)
+#define LCD_CAM_CAM_BYTE_ORDER_V  0x00000001U
+#define LCD_CAM_CAM_BYTE_ORDER_S  5
+/** LCD_CAM_CAM_BIT_ORDER : R/W; bitpos: [6]; default: 0;
+ *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+ */
+#define LCD_CAM_CAM_BIT_ORDER    (BIT(6))
+#define LCD_CAM_CAM_BIT_ORDER_M  (LCD_CAM_CAM_BIT_ORDER_V << LCD_CAM_CAM_BIT_ORDER_S)
+#define LCD_CAM_CAM_BIT_ORDER_V  0x00000001U
+#define LCD_CAM_CAM_BIT_ORDER_S  6
+/** LCD_CAM_CAM_LINE_INT_EN : R/W; bitpos: [7]; default: 0;
+ *  1: Enable to generate CAM_HS_INT. 0: Disable.
+ */
+#define LCD_CAM_CAM_LINE_INT_EN    (BIT(7))
+#define LCD_CAM_CAM_LINE_INT_EN_M  (LCD_CAM_CAM_LINE_INT_EN_V << LCD_CAM_CAM_LINE_INT_EN_S)
+#define LCD_CAM_CAM_LINE_INT_EN_V  0x00000001U
+#define LCD_CAM_CAM_LINE_INT_EN_S  7
+/** LCD_CAM_CAM_VS_EOF_EN : R/W; bitpos: [8]; default: 0;
+ *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+ *  reg_cam_rec_data_cyclelen.
+ */
+#define LCD_CAM_CAM_VS_EOF_EN    (BIT(8))
+#define LCD_CAM_CAM_VS_EOF_EN_M  (LCD_CAM_CAM_VS_EOF_EN_V << LCD_CAM_CAM_VS_EOF_EN_S)
+#define LCD_CAM_CAM_VS_EOF_EN_V  0x00000001U
+#define LCD_CAM_CAM_VS_EOF_EN_S  8
+/** LCD_CAM_CAM_CLKM_DIV_NUM : R/W; bitpos: [16:9]; default: 4;
+ *  Integral Camera clock divider value
+ */
+#define LCD_CAM_CAM_CLKM_DIV_NUM    0x000000FFU
+#define LCD_CAM_CAM_CLKM_DIV_NUM_M  (LCD_CAM_CAM_CLKM_DIV_NUM_V << LCD_CAM_CAM_CLKM_DIV_NUM_S)
+#define LCD_CAM_CAM_CLKM_DIV_NUM_V  0x000000FFU
+#define LCD_CAM_CAM_CLKM_DIV_NUM_S  9
+/** LCD_CAM_CAM_CLKM_DIV_B : R/W; bitpos: [22:17]; default: 0;
+ *  Fractional clock divider numerator value
+ */
+#define LCD_CAM_CAM_CLKM_DIV_B    0x0000003FU
+#define LCD_CAM_CAM_CLKM_DIV_B_M  (LCD_CAM_CAM_CLKM_DIV_B_V << LCD_CAM_CAM_CLKM_DIV_B_S)
+#define LCD_CAM_CAM_CLKM_DIV_B_V  0x0000003FU
+#define LCD_CAM_CAM_CLKM_DIV_B_S  17
+/** LCD_CAM_CAM_CLKM_DIV_A : R/W; bitpos: [28:23]; default: 0;
+ *  Fractional clock divider denominator value
+ */
+#define LCD_CAM_CAM_CLKM_DIV_A    0x0000003FU
+#define LCD_CAM_CAM_CLKM_DIV_A_M  (LCD_CAM_CAM_CLKM_DIV_A_V << LCD_CAM_CAM_CLKM_DIV_A_S)
+#define LCD_CAM_CAM_CLKM_DIV_A_V  0x0000003FU
+#define LCD_CAM_CAM_CLKM_DIV_A_S  23
+/** LCD_CAM_CAM_CLK_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+ */
+#define LCD_CAM_CAM_CLK_SEL    0x00000003U
+#define LCD_CAM_CAM_CLK_SEL_M  (LCD_CAM_CAM_CLK_SEL_V << LCD_CAM_CAM_CLK_SEL_S)
+#define LCD_CAM_CAM_CLK_SEL_V  0x00000003U
+#define LCD_CAM_CAM_CLK_SEL_S  29
 
-#define LCD_CAM_CAM_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x8)
-/* LCD_CAM_CAM_AFIFO_RESET : WO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Camera AFIFO reset signal..*/
-#define LCD_CAM_CAM_AFIFO_RESET    (BIT(31))
-#define LCD_CAM_CAM_AFIFO_RESET_M  (BIT(31))
-#define LCD_CAM_CAM_AFIFO_RESET_V  0x1
-#define LCD_CAM_CAM_AFIFO_RESET_S  31
-/* LCD_CAM_CAM_RESET : WO ;bitpos:[30] ;default: 1'h0 ; */
-/*description: Camera module reset signal..*/
-#define LCD_CAM_CAM_RESET    (BIT(30))
-#define LCD_CAM_CAM_RESET_M  (BIT(30))
-#define LCD_CAM_CAM_RESET_V  0x1
-#define LCD_CAM_CAM_RESET_S  30
-/* LCD_CAM_CAM_START : R/W ;bitpos:[29] ;default: 1'h0 ; */
-/*description: Camera module start signal..*/
-#define LCD_CAM_CAM_START    (BIT(29))
-#define LCD_CAM_CAM_START_M  (BIT(29))
-#define LCD_CAM_CAM_START_V  0x1
-#define LCD_CAM_CAM_START_S  29
-/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
-/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input contr
-ol signals are CAM_DE and CAM_VSYNC.*/
-#define LCD_CAM_CAM_VH_DE_MODE_EN    (BIT(28))
-#define LCD_CAM_CAM_VH_DE_MODE_EN_M  (BIT(28))
-#define LCD_CAM_CAM_VH_DE_MODE_EN_V  0x1
-#define LCD_CAM_CAM_VH_DE_MODE_EN_S  28
-/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */
-/*description: CAM_VSYNC invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_VSYNC_INV    (BIT(27))
-#define LCD_CAM_CAM_VSYNC_INV_M  (BIT(27))
-#define LCD_CAM_CAM_VSYNC_INV_V  0x1
-#define LCD_CAM_CAM_VSYNC_INV_S  27
-/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: CAM_HSYNC invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_HSYNC_INV    (BIT(26))
-#define LCD_CAM_CAM_HSYNC_INV_M  (BIT(26))
-#define LCD_CAM_CAM_HSYNC_INV_V  0x1
-#define LCD_CAM_CAM_HSYNC_INV_S  26
-/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: CAM_DE invert enable signal, valid in high level..*/
-#define LCD_CAM_CAM_DE_INV    (BIT(25))
-#define LCD_CAM_CAM_DE_INV_M  (BIT(25))
-#define LCD_CAM_CAM_DE_INV_V  0x1
-#define LCD_CAM_CAM_DE_INV_S  25
-/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: 1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8
-. .*/
-#define LCD_CAM_CAM_2BYTE_EN    (BIT(24))
-#define LCD_CAM_CAM_2BYTE_EN_M  (BIT(24))
-#define LCD_CAM_CAM_2BYTE_EN_V  0x1
-#define LCD_CAM_CAM_2BYTE_EN_S  24
-/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/
-#define LCD_CAM_CAM_VSYNC_FILTER_EN    (BIT(23))
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_M  (BIT(23))
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_V  0x1
-#define LCD_CAM_CAM_VSYNC_FILTER_EN_S  23
-/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Invert  the input signal CAM_PCLK. 0: Not invert..*/
+/** LCD_CAM_CAM_CTRL1_REG register
+ *  Camera configuration register
+ */
+#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8)
+/** LCD_CAM_CAM_REC_DATA_BYTELEN : R/W; bitpos: [15:0]; default: 0;
+ *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+ */
+#define LCD_CAM_CAM_REC_DATA_BYTELEN    0x0000FFFFU
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_M  (LCD_CAM_CAM_REC_DATA_BYTELEN_V << LCD_CAM_CAM_REC_DATA_BYTELEN_S)
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_V  0x0000FFFFU
+#define LCD_CAM_CAM_REC_DATA_BYTELEN_S  0
+/** LCD_CAM_CAM_LINE_INT_NUM : R/W; bitpos: [21:16]; default: 0;
+ *  The line number minus 1 to generate cam_hs_int.
+ */
+#define LCD_CAM_CAM_LINE_INT_NUM    0x0000003FU
+#define LCD_CAM_CAM_LINE_INT_NUM_M  (LCD_CAM_CAM_LINE_INT_NUM_V << LCD_CAM_CAM_LINE_INT_NUM_S)
+#define LCD_CAM_CAM_LINE_INT_NUM_V  0x0000003FU
+#define LCD_CAM_CAM_LINE_INT_NUM_S  16
+/** LCD_CAM_CAM_CLK_INV : R/W; bitpos: [22]; default: 0;
+ *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+ */
 #define LCD_CAM_CAM_CLK_INV    (BIT(22))
-#define LCD_CAM_CAM_CLK_INV_M  (BIT(22))
-#define LCD_CAM_CAM_CLK_INV_V  0x1
+#define LCD_CAM_CAM_CLK_INV_M  (LCD_CAM_CAM_CLK_INV_V << LCD_CAM_CAM_CLK_INV_S)
+#define LCD_CAM_CAM_CLK_INV_V  0x00000001U
 #define LCD_CAM_CAM_CLK_INV_S  22
-/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */
-/*description: The line number minus 1 to generate cam_hs_int..*/
-#define LCD_CAM_CAM_LINE_INT_NUM    0x0000003F
-#define LCD_CAM_CAM_LINE_INT_NUM_M  ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S))
-#define LCD_CAM_CAM_LINE_INT_NUM_V  0x3F
-#define LCD_CAM_CAM_LINE_INT_NUM_S  16
-/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/
-#define LCD_CAM_CAM_REC_DATA_BYTELEN    0x0000FFFF
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_M  ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S))
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_V  0xFFFF
-#define LCD_CAM_CAM_REC_DATA_BYTELEN_S  0
+/** LCD_CAM_CAM_VSYNC_FILTER_EN : R/W; bitpos: [23]; default: 0;
+ *  1: Enable CAM_VSYNC filter function. 0: bypass.
+ */
+#define LCD_CAM_CAM_VSYNC_FILTER_EN    (BIT(23))
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_M  (LCD_CAM_CAM_VSYNC_FILTER_EN_V << LCD_CAM_CAM_VSYNC_FILTER_EN_S)
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_FILTER_EN_S  23
+/** LCD_CAM_CAM_2BYTE_EN : R/W; bitpos: [24]; default: 0;
+ *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+ */
+#define LCD_CAM_CAM_2BYTE_EN    (BIT(24))
+#define LCD_CAM_CAM_2BYTE_EN_M  (LCD_CAM_CAM_2BYTE_EN_V << LCD_CAM_CAM_2BYTE_EN_S)
+#define LCD_CAM_CAM_2BYTE_EN_V  0x00000001U
+#define LCD_CAM_CAM_2BYTE_EN_S  24
+/** LCD_CAM_CAM_DE_INV : R/W; bitpos: [25]; default: 0;
+ *  CAM_DE invert enable signal, valid in high level.
+ */
+#define LCD_CAM_CAM_DE_INV    (BIT(25))
+#define LCD_CAM_CAM_DE_INV_M  (LCD_CAM_CAM_DE_INV_V << LCD_CAM_CAM_DE_INV_S)
+#define LCD_CAM_CAM_DE_INV_V  0x00000001U
+#define LCD_CAM_CAM_DE_INV_S  25
+/** LCD_CAM_CAM_HSYNC_INV : R/W; bitpos: [26]; default: 0;
+ *  CAM_HSYNC invert enable signal, valid in high level.
+ */
+#define LCD_CAM_CAM_HSYNC_INV    (BIT(26))
+#define LCD_CAM_CAM_HSYNC_INV_M  (LCD_CAM_CAM_HSYNC_INV_V << LCD_CAM_CAM_HSYNC_INV_S)
+#define LCD_CAM_CAM_HSYNC_INV_V  0x00000001U
+#define LCD_CAM_CAM_HSYNC_INV_S  26
+/** LCD_CAM_CAM_VSYNC_INV : R/W; bitpos: [27]; default: 0;
+ *  CAM_VSYNC invert enable signal, valid in high level.
+ */
+#define LCD_CAM_CAM_VSYNC_INV    (BIT(27))
+#define LCD_CAM_CAM_VSYNC_INV_M  (LCD_CAM_CAM_VSYNC_INV_V << LCD_CAM_CAM_VSYNC_INV_S)
+#define LCD_CAM_CAM_VSYNC_INV_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_INV_S  27
+/** LCD_CAM_CAM_VH_DE_MODE_EN : R/W; bitpos: [28]; default: 0;
+ *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control
+ *  signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time.
+ */
+#define LCD_CAM_CAM_VH_DE_MODE_EN    (BIT(28))
+#define LCD_CAM_CAM_VH_DE_MODE_EN_M  (LCD_CAM_CAM_VH_DE_MODE_EN_V << LCD_CAM_CAM_VH_DE_MODE_EN_S)
+#define LCD_CAM_CAM_VH_DE_MODE_EN_V  0x00000001U
+#define LCD_CAM_CAM_VH_DE_MODE_EN_S  28
+/** LCD_CAM_CAM_START : R/W; bitpos: [29]; default: 0;
+ *  Camera module start signal.
+ */
+#define LCD_CAM_CAM_START    (BIT(29))
+#define LCD_CAM_CAM_START_M  (LCD_CAM_CAM_START_V << LCD_CAM_CAM_START_S)
+#define LCD_CAM_CAM_START_V  0x00000001U
+#define LCD_CAM_CAM_START_S  29
+/** LCD_CAM_CAM_RESET : WO; bitpos: [30]; default: 0;
+ *  Camera module reset signal.
+ */
+#define LCD_CAM_CAM_RESET    (BIT(30))
+#define LCD_CAM_CAM_RESET_M  (LCD_CAM_CAM_RESET_V << LCD_CAM_CAM_RESET_S)
+#define LCD_CAM_CAM_RESET_V  0x00000001U
+#define LCD_CAM_CAM_RESET_S  30
+/** LCD_CAM_CAM_AFIFO_RESET : WO; bitpos: [31]; default: 0;
+ *  Camera AFIFO reset signal.
+ */
+#define LCD_CAM_CAM_AFIFO_RESET    (BIT(31))
+#define LCD_CAM_CAM_AFIFO_RESET_M  (LCD_CAM_CAM_AFIFO_RESET_V << LCD_CAM_CAM_AFIFO_RESET_S)
+#define LCD_CAM_CAM_AFIFO_RESET_V  0x00000001U
+#define LCD_CAM_CAM_AFIFO_RESET_S  31
 
-#define LCD_CAM_CAM_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0xC)
-/* LCD_CAM_CAM_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: Bypass converter. 1: Enable converter..*/
-#define LCD_CAM_CAM_CONV_BYPASS    (BIT(31))
-#define LCD_CAM_CAM_CONV_BYPASS_M  (BIT(31))
-#define LCD_CAM_CAM_CONV_BYPASS_V  0x1
-#define LCD_CAM_CAM_CONV_BYPASS_S  31
-/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: YUV to RGB. 1: RGB to YUV..*/
-#define LCD_CAM_CAM_CONV_TRANS_MODE    (BIT(30))
-#define LCD_CAM_CAM_CONV_TRANS_MODE_M  (BIT(30))
-#define LCD_CAM_CAM_CONV_TRANS_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_TRANS_MODE_S  30
-/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 0: 16bits mode. 1: 8bits mode..*/
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M  (BIT(29))
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V  0x1
-#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S  29
-/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M  (BIT(28))
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S  28
-/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M  (BIT(27))
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S  27
-/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 0:BT601. 1:BT709..*/
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M  (BIT(26))
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V  0x1
-#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S  26
-/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-mode of Data_in.*/
-#define LCD_CAM_CAM_CONV_YUV_MODE    0x00000003
-#define LCD_CAM_CAM_CONV_YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S))
-#define LCD_CAM_CAM_CONV_YUV_MODE_V  0x3
-#define LCD_CAM_CAM_CONV_YUV_MODE_S  24
-/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
-/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-trans_mode must be set to 1. .*/
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE    0x00000003
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M  ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S))
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V  0x3
-#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S  22
-/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1:invert every two 8bits input data. 2. disabled..*/
+/** LCD_CAM_CAM_RGB_YUV_REG register
+ *  Camera configuration register
+ */
+#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xc)
+/** LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W; bitpos: [21]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV    (BIT(21))
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M  (BIT(21))
-#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V  0x1
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M  (LCD_CAM_CAM_CONV_8BITS_DATA_INV_V << LCD_CAM_CAM_CONV_8BITS_DATA_INV_S)
+#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V  0x00000001U
 #define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S  21
+/** LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+ *  trans_mode must be set to 1.
+ */
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE    0x00000003U
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M  (LCD_CAM_CAM_CONV_YUV2YUV_MODE_V << LCD_CAM_CAM_CONV_YUV2YUV_MODE_S)
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S  22
+/** LCD_CAM_CAM_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+ *  mode of Data_in
+ */
+#define LCD_CAM_CAM_CONV_YUV_MODE    0x00000003U
+#define LCD_CAM_CAM_CONV_YUV_MODE_M  (LCD_CAM_CAM_CONV_YUV_MODE_V << LCD_CAM_CAM_CONV_YUV_MODE_S)
+#define LCD_CAM_CAM_CONV_YUV_MODE_V  0x00000003U
+#define LCD_CAM_CAM_CONV_YUV_MODE_S  24
+/** LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M  (LCD_CAM_CAM_CONV_PROTOCOL_MODE_V << LCD_CAM_CAM_CONV_PROTOCOL_MODE_S)
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S  26
+/** LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M  (LCD_CAM_CAM_CONV_DATA_OUT_MODE_V << LCD_CAM_CAM_CONV_DATA_OUT_MODE_S)
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S  27
+/** LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE    (BIT(28))
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M  (LCD_CAM_CAM_CONV_DATA_IN_MODE_V << LCD_CAM_CAM_CONV_DATA_IN_MODE_S)
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S  28
+/** LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M  (LCD_CAM_CAM_CONV_MODE_8BITS_ON_V << LCD_CAM_CAM_CONV_MODE_8BITS_ON_S)
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S  29
+/** LCD_CAM_CAM_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCD_CAM_CAM_CONV_TRANS_MODE    (BIT(30))
+#define LCD_CAM_CAM_CONV_TRANS_MODE_M  (LCD_CAM_CAM_CONV_TRANS_MODE_V << LCD_CAM_CAM_CONV_TRANS_MODE_S)
+#define LCD_CAM_CAM_CONV_TRANS_MODE_V  0x00000001U
+#define LCD_CAM_CAM_CONV_TRANS_MODE_S  30
+/** LCD_CAM_CAM_CONV_BYPASS : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCD_CAM_CAM_CONV_BYPASS    (BIT(31))
+#define LCD_CAM_CAM_CONV_BYPASS_M  (LCD_CAM_CAM_CONV_BYPASS_V << LCD_CAM_CAM_CONV_BYPASS_S)
+#define LCD_CAM_CAM_CONV_BYPASS_V  0x00000001U
+#define LCD_CAM_CAM_CONV_BYPASS_S  31
 
-#define LCD_CAM_LCD_RGB_YUV_REG          (DR_REG_LCD_CAM_BASE + 0x10)
-/* LCD_CAM_LCD_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: Bypass converter. 1: Enable converter..*/
-#define LCD_CAM_LCD_CONV_BYPASS    (BIT(31))
-#define LCD_CAM_LCD_CONV_BYPASS_M  (BIT(31))
-#define LCD_CAM_LCD_CONV_BYPASS_V  0x1
-#define LCD_CAM_LCD_CONV_BYPASS_S  31
-/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: YUV to RGB. 1: RGB to YUV..*/
-#define LCD_CAM_LCD_CONV_TRANS_MODE    (BIT(30))
-#define LCD_CAM_LCD_CONV_TRANS_MODE_M  (BIT(30))
-#define LCD_CAM_LCD_CONV_TRANS_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_TRANS_MODE_S  30
-/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 0: 16bits mode. 1: 8bits mode..*/
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M  (BIT(29))
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V  0x1
-#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S  29
-/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M  (BIT(28))
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S  28
-/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M  (BIT(27))
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S  27
-/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 0:BT601. 1:BT709..*/
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M  (BIT(26))
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V  0x1
-#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S  26
-/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
-/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-mode of Data_in.*/
-#define LCD_CAM_LCD_CONV_YUV_MODE    0x00000003
-#define LCD_CAM_LCD_CONV_YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S))
-#define LCD_CAM_LCD_CONV_YUV_MODE_V  0x3
-#define LCD_CAM_LCD_CONV_YUV_MODE_S  24
-/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
-/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-trans_mode must be set to 1. .*/
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE    0x00000003
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M  ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S))
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V  0x3
-#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S  22
-/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 0: txtorx mode off. 1: txtorx mode on..*/
-#define LCD_CAM_LCD_CONV_TXTORX    (BIT(21))
-#define LCD_CAM_LCD_CONV_TXTORX_M  (BIT(21))
-#define LCD_CAM_LCD_CONV_TXTORX_V  0x1
-#define LCD_CAM_LCD_CONV_TXTORX_S  21
-/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: 1:invert every two 8bits input data. 2. disabled..*/
+/** LCD_CAM_LCD_RGB_YUV_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10)
+/** LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W; bitpos: [20]; default: 0;
+ *  1:invert every two 8bits input data. 2. disabled.
+ */
 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV    (BIT(20))
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M  (BIT(20))
-#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V  0x1
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M  (LCD_CAM_LCD_CONV_8BITS_DATA_INV_V << LCD_CAM_LCD_CONV_8BITS_DATA_INV_S)
+#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V  0x00000001U
 #define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S  20
+/** LCD_CAM_LCD_CONV_TXTORX : R/W; bitpos: [21]; default: 0;
+ *  0: txtorx mode off. 1: txtorx mode on.
+ */
+#define LCD_CAM_LCD_CONV_TXTORX    (BIT(21))
+#define LCD_CAM_LCD_CONV_TXTORX_M  (LCD_CAM_LCD_CONV_TXTORX_V << LCD_CAM_LCD_CONV_TXTORX_S)
+#define LCD_CAM_LCD_CONV_TXTORX_V  0x00000001U
+#define LCD_CAM_LCD_CONV_TXTORX_S  21
+/** LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W; bitpos: [23:22]; default: 3;
+ *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+ *  trans_mode must be set to 1.
+ */
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE    0x00000003U
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M  (LCD_CAM_LCD_CONV_YUV2YUV_MODE_V << LCD_CAM_LCD_CONV_YUV2YUV_MODE_S)
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V  0x00000003U
+#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S  22
+/** LCD_CAM_LCD_CONV_YUV_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+ *  mode of Data_in
+ */
+#define LCD_CAM_LCD_CONV_YUV_MODE    0x00000003U
+#define LCD_CAM_LCD_CONV_YUV_MODE_M  (LCD_CAM_LCD_CONV_YUV_MODE_V << LCD_CAM_LCD_CONV_YUV_MODE_S)
+#define LCD_CAM_LCD_CONV_YUV_MODE_V  0x00000003U
+#define LCD_CAM_LCD_CONV_YUV_MODE_S  24
+/** LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W; bitpos: [26]; default: 0;
+ *  0:BT601. 1:BT709.
+ */
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE    (BIT(26))
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M  (LCD_CAM_LCD_CONV_PROTOCOL_MODE_V << LCD_CAM_LCD_CONV_PROTOCOL_MODE_S)
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V  0x00000001U
+#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S  26
+/** LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W; bitpos: [27]; default: 0;
+ *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+ */
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE    (BIT(27))
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M  (LCD_CAM_LCD_CONV_DATA_OUT_MODE_V << LCD_CAM_LCD_CONV_DATA_OUT_MODE_S)
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V  0x00000001U
+#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S  27
+/** LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W; bitpos: [28]; default: 0;
+ *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+ */
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE    (BIT(28))
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M  (LCD_CAM_LCD_CONV_DATA_IN_MODE_V << LCD_CAM_LCD_CONV_DATA_IN_MODE_S)
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V  0x00000001U
+#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S  28
+/** LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W; bitpos: [29]; default: 0;
+ *  0: 16bits mode. 1: 8bits mode.
+ */
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON    (BIT(29))
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M  (LCD_CAM_LCD_CONV_MODE_8BITS_ON_V << LCD_CAM_LCD_CONV_MODE_8BITS_ON_S)
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V  0x00000001U
+#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S  29
+/** LCD_CAM_LCD_CONV_TRANS_MODE : R/W; bitpos: [30]; default: 0;
+ *  0: YUV to RGB. 1: RGB to YUV.
+ */
+#define LCD_CAM_LCD_CONV_TRANS_MODE    (BIT(30))
+#define LCD_CAM_LCD_CONV_TRANS_MODE_M  (LCD_CAM_LCD_CONV_TRANS_MODE_V << LCD_CAM_LCD_CONV_TRANS_MODE_S)
+#define LCD_CAM_LCD_CONV_TRANS_MODE_V  0x00000001U
+#define LCD_CAM_LCD_CONV_TRANS_MODE_S  30
+/** LCD_CAM_LCD_CONV_BYPASS : R/W; bitpos: [31]; default: 0;
+ *  0: Bypass converter. 1: Enable converter.
+ */
+#define LCD_CAM_LCD_CONV_BYPASS    (BIT(31))
+#define LCD_CAM_LCD_CONV_BYPASS_M  (LCD_CAM_LCD_CONV_BYPASS_V << LCD_CAM_LCD_CONV_BYPASS_S)
+#define LCD_CAM_LCD_CONV_BYPASS_V  0x00000001U
+#define LCD_CAM_LCD_CONV_BYPASS_S  31
 
-#define LCD_CAM_LCD_USER_REG          (DR_REG_LCD_CAM_BASE + 0x14)
-/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: The cycle length of command phase.*/
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M  (BIT(31))
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V  0x1
-#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S  31
-/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
-/*description: The dummy cycle length minus 1..*/
-#define LCD_CAM_LCD_DUMMY_CYCLELEN    0x00000003
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_M  ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S))
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_V  0x3
-#define LCD_CAM_LCD_DUMMY_CYCLELEN_S  29
-/* LCD_CAM_LCD_RESET : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The value of  command. .*/
-#define LCD_CAM_LCD_RESET    (BIT(28))
-#define LCD_CAM_LCD_RESET_M  (BIT(28))
-#define LCD_CAM_LCD_RESET_V  0x1
-#define LCD_CAM_LCD_RESET_S  28
-/* LCD_CAM_LCD_START : R/W ;bitpos:[27] ;default: 1'h0 ; */
-/*description: LCD start sending data enable signal, valid in high level..*/
-#define LCD_CAM_LCD_START    (BIT(27))
-#define LCD_CAM_LCD_START_M  (BIT(27))
-#define LCD_CAM_LCD_START_V  0x1
-#define LCD_CAM_LCD_START_S  27
-/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_CMD    (BIT(26))
-#define LCD_CAM_LCD_CMD_M  (BIT(26))
-#define LCD_CAM_LCD_CMD_V  0x1
-#define LCD_CAM_LCD_CMD_S  26
-/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_DUMMY    (BIT(25))
-#define LCD_CAM_LCD_DUMMY_M  (BIT(25))
-#define LCD_CAM_LCD_DUMMY_V  0x1
-#define LCD_CAM_LCD_DUMMY_S  25
-/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/
-#define LCD_CAM_LCD_DOUT    (BIT(24))
-#define LCD_CAM_LCD_DOUT_M  (BIT(24))
-#define LCD_CAM_LCD_DOUT_V  0x1
-#define LCD_CAM_LCD_DOUT_S  24
-/* LCD_CAM_LCD_2BYTE_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: 1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD d
-ata is 0~8. .*/
-#define LCD_CAM_LCD_2BYTE_EN    (BIT(23))
-#define LCD_CAM_LCD_2BYTE_EN_M  (BIT(23))
-#define LCD_CAM_LCD_2BYTE_EN_V  0x1
-#define LCD_CAM_LCD_2BYTE_EN_S  23
-/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
-#define LCD_CAM_LCD_BYTE_ORDER    (BIT(22))
-#define LCD_CAM_LCD_BYTE_ORDER_M  (BIT(22))
-#define LCD_CAM_LCD_BYTE_ORDER_V  0x1
-#define LCD_CAM_LCD_BYTE_ORDER_S  22
-/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b
-yte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change..*/
-#define LCD_CAM_LCD_BIT_ORDER    (BIT(21))
-#define LCD_CAM_LCD_BIT_ORDER_M  (BIT(21))
-#define LCD_CAM_LCD_BIT_ORDER_V  0x1
-#define LCD_CAM_LCD_BIT_ORDER_S  21
-/* LCD_CAM_LCD_UPDATE_REG : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/
-#define LCD_CAM_LCD_UPDATE_REG    (BIT(20))
-#define LCD_CAM_LCD_UPDATE_REG_M  (BIT(20))
-#define LCD_CAM_LCD_UPDATE_REG_V  0x1
-#define LCD_CAM_LCD_UPDATE_REG_S  20
-/* LCD_CAM_LCD_8BITS_ORDER : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: 1: invert every two data byte, valid in 1 byte mode. 0: Not change..*/
-#define LCD_CAM_LCD_8BITS_ORDER    (BIT(19))
-#define LCD_CAM_LCD_8BITS_ORDER_M  (BIT(19))
-#define LCD_CAM_LCD_8BITS_ORDER_V  0x1
-#define LCD_CAM_LCD_8BITS_ORDER_S  19
-/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared
- or reg_lcd_reset is set..*/
+/** LCD_CAM_LCD_USER_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14)
+/** LCD_CAM_LCD_DOUT_CYCLELEN : R/W; bitpos: [12:0]; default: 1;
+ *  The output data cycles minus 1 of LCD module.
+ */
+#define LCD_CAM_LCD_DOUT_CYCLELEN    0x00001FFFU
+#define LCD_CAM_LCD_DOUT_CYCLELEN_M  (LCD_CAM_LCD_DOUT_CYCLELEN_V << LCD_CAM_LCD_DOUT_CYCLELEN_S)
+#define LCD_CAM_LCD_DOUT_CYCLELEN_V  0x00001FFFU
+#define LCD_CAM_LCD_DOUT_CYCLELEN_S  0
+/** LCD_CAM_LCD_ALWAYS_OUT_EN : R/W; bitpos: [13]; default: 0;
+ *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+ *  reg_lcd_reset is set.
+ */
 #define LCD_CAM_LCD_ALWAYS_OUT_EN    (BIT(13))
-#define LCD_CAM_LCD_ALWAYS_OUT_EN_M  (BIT(13))
-#define LCD_CAM_LCD_ALWAYS_OUT_EN_V  0x1
+#define LCD_CAM_LCD_ALWAYS_OUT_EN_M  (LCD_CAM_LCD_ALWAYS_OUT_EN_V << LCD_CAM_LCD_ALWAYS_OUT_EN_S)
+#define LCD_CAM_LCD_ALWAYS_OUT_EN_V  0x00000001U
 #define LCD_CAM_LCD_ALWAYS_OUT_EN_S  13
-/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
-/*description: The output data cycles minus 1 of LCD module..*/
-#define LCD_CAM_LCD_DOUT_CYCLELEN    0x00001FFF
-#define LCD_CAM_LCD_DOUT_CYCLELEN_M  ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S))
-#define LCD_CAM_LCD_DOUT_CYCLELEN_V  0x1FFF
-#define LCD_CAM_LCD_DOUT_CYCLELEN_S  0
+/** LCD_CAM_LCD_8BITS_ORDER : R/W; bitpos: [19]; default: 0;
+ *  1: invert every two data byte, valid in 1 byte mode. 0: Not change.
+ */
+#define LCD_CAM_LCD_8BITS_ORDER    (BIT(19))
+#define LCD_CAM_LCD_8BITS_ORDER_M  (LCD_CAM_LCD_8BITS_ORDER_V << LCD_CAM_LCD_8BITS_ORDER_S)
+#define LCD_CAM_LCD_8BITS_ORDER_V  0x00000001U
+#define LCD_CAM_LCD_8BITS_ORDER_S  19
+/** LCD_CAM_LCD_UPDATE_REG : R/W; bitpos: [20]; default: 0;
+ *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+ */
+#define LCD_CAM_LCD_UPDATE_REG    (BIT(20))
+#define LCD_CAM_LCD_UPDATE_REG_M  (LCD_CAM_LCD_UPDATE_REG_V << LCD_CAM_LCD_UPDATE_REG_S)
+#define LCD_CAM_LCD_UPDATE_REG_V  0x00000001U
+#define LCD_CAM_LCD_UPDATE_REG_S  20
+/** LCD_CAM_LCD_BIT_ORDER : R/W; bitpos: [21]; default: 0;
+ *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+ *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+ */
+#define LCD_CAM_LCD_BIT_ORDER    (BIT(21))
+#define LCD_CAM_LCD_BIT_ORDER_M  (LCD_CAM_LCD_BIT_ORDER_V << LCD_CAM_LCD_BIT_ORDER_S)
+#define LCD_CAM_LCD_BIT_ORDER_V  0x00000001U
+#define LCD_CAM_LCD_BIT_ORDER_S  21
+/** LCD_CAM_LCD_BYTE_ORDER : R/W; bitpos: [22]; default: 0;
+ *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+ */
+#define LCD_CAM_LCD_BYTE_ORDER    (BIT(22))
+#define LCD_CAM_LCD_BYTE_ORDER_M  (LCD_CAM_LCD_BYTE_ORDER_V << LCD_CAM_LCD_BYTE_ORDER_S)
+#define LCD_CAM_LCD_BYTE_ORDER_V  0x00000001U
+#define LCD_CAM_LCD_BYTE_ORDER_S  22
+/** LCD_CAM_LCD_2BYTE_EN : R/W; bitpos: [23]; default: 0;
+ *  1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD data
+ *  is 0~8.
+ */
+#define LCD_CAM_LCD_2BYTE_EN    (BIT(23))
+#define LCD_CAM_LCD_2BYTE_EN_M  (LCD_CAM_LCD_2BYTE_EN_V << LCD_CAM_LCD_2BYTE_EN_S)
+#define LCD_CAM_LCD_2BYTE_EN_V  0x00000001U
+#define LCD_CAM_LCD_2BYTE_EN_S  23
+/** LCD_CAM_LCD_DOUT : R/W; bitpos: [24]; default: 0;
+ *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCD_CAM_LCD_DOUT    (BIT(24))
+#define LCD_CAM_LCD_DOUT_M  (LCD_CAM_LCD_DOUT_V << LCD_CAM_LCD_DOUT_S)
+#define LCD_CAM_LCD_DOUT_V  0x00000001U
+#define LCD_CAM_LCD_DOUT_S  24
+/** LCD_CAM_LCD_DUMMY : R/W; bitpos: [25]; default: 0;
+ *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCD_CAM_LCD_DUMMY    (BIT(25))
+#define LCD_CAM_LCD_DUMMY_M  (LCD_CAM_LCD_DUMMY_V << LCD_CAM_LCD_DUMMY_S)
+#define LCD_CAM_LCD_DUMMY_V  0x00000001U
+#define LCD_CAM_LCD_DUMMY_S  25
+/** LCD_CAM_LCD_CMD : R/W; bitpos: [26]; default: 0;
+ *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+ */
+#define LCD_CAM_LCD_CMD    (BIT(26))
+#define LCD_CAM_LCD_CMD_M  (LCD_CAM_LCD_CMD_V << LCD_CAM_LCD_CMD_S)
+#define LCD_CAM_LCD_CMD_V  0x00000001U
+#define LCD_CAM_LCD_CMD_S  26
+/** LCD_CAM_LCD_START : R/W; bitpos: [27]; default: 0;
+ *  LCD start sending data enable signal, valid in high level.
+ */
+#define LCD_CAM_LCD_START    (BIT(27))
+#define LCD_CAM_LCD_START_M  (LCD_CAM_LCD_START_V << LCD_CAM_LCD_START_S)
+#define LCD_CAM_LCD_START_V  0x00000001U
+#define LCD_CAM_LCD_START_S  27
+/** LCD_CAM_LCD_RESET : WO; bitpos: [28]; default: 0;
+ *  The value of  command.
+ */
+#define LCD_CAM_LCD_RESET    (BIT(28))
+#define LCD_CAM_LCD_RESET_M  (LCD_CAM_LCD_RESET_V << LCD_CAM_LCD_RESET_S)
+#define LCD_CAM_LCD_RESET_V  0x00000001U
+#define LCD_CAM_LCD_RESET_S  28
+/** LCD_CAM_LCD_DUMMY_CYCLELEN : R/W; bitpos: [30:29]; default: 0;
+ *  The dummy cycle length minus 1.
+ */
+#define LCD_CAM_LCD_DUMMY_CYCLELEN    0x00000003U
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_M  (LCD_CAM_LCD_DUMMY_CYCLELEN_V << LCD_CAM_LCD_DUMMY_CYCLELEN_S)
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_V  0x00000003U
+#define LCD_CAM_LCD_DUMMY_CYCLELEN_S  29
+/** LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W; bitpos: [31]; default: 0;
+ *  The cycle length of command phase.  1: 2 cycles. 0: 1 cycle.
+ */
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN    (BIT(31))
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M  (LCD_CAM_LCD_CMD_2_CYCLE_EN_V << LCD_CAM_LCD_CMD_2_CYCLE_EN_S)
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V  0x00000001U
+#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S  31
 
-#define LCD_CAM_LCD_MISC_REG          (DR_REG_LCD_CAM_BASE + 0x18)
-/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: The default value of LCD_CD. .*/
-#define LCD_CAM_LCD_CD_IDLE_EDGE    (BIT(31))
-#define LCD_CAM_LCD_CD_IDLE_EDGE_M  (BIT(31))
-#define LCD_CAM_LCD_CD_IDLE_EDGE_V  0x1
-#define LCD_CAM_LCD_CD_IDLE_EDGE_S  31
-/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
- reg_cd_idle_edge. .*/
-#define LCD_CAM_LCD_CD_CMD_SET    (BIT(30))
-#define LCD_CAM_LCD_CD_CMD_SET_M  (BIT(30))
-#define LCD_CAM_LCD_CD_CMD_SET_V  0x1
-#define LCD_CAM_LCD_CD_CMD_SET_S  30
-/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD
- = reg_cd_idle_edge. .*/
-#define LCD_CAM_LCD_CD_DUMMY_SET    (BIT(29))
-#define LCD_CAM_LCD_CD_DUMMY_SET_M  (BIT(29))
-#define LCD_CAM_LCD_CD_DUMMY_SET_V  0x1
-#define LCD_CAM_LCD_CD_DUMMY_SET_S  29
-/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD
-= reg_cd_idle_edge. .*/
-#define LCD_CAM_LCD_CD_DATA_SET    (BIT(28))
-#define LCD_CAM_LCD_CD_DATA_SET_M  (BIT(28))
-#define LCD_CAM_LCD_CD_DATA_SET_V  0x1
-#define LCD_CAM_LCD_CD_DATA_SET_S  28
-/* LCD_CAM_LCD_AFIFO_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: LCD AFIFO reset signal..*/
-#define LCD_CAM_LCD_AFIFO_RESET    (BIT(27))
-#define LCD_CAM_LCD_AFIFO_RESET_M  (BIT(27))
-#define LCD_CAM_LCD_AFIFO_RESET_V  0x1
-#define LCD_CAM_LCD_AFIFO_RESET_S  27
-/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/
-#define LCD_CAM_LCD_BK_EN    (BIT(26))
-#define LCD_CAM_LCD_BK_EN_M  (BIT(26))
-#define LCD_CAM_LCD_BK_EN_V  0x1
-#define LCD_CAM_LCD_BK_EN_S  26
-/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe
-n the current frame is sent out..*/
+/** LCD_CAM_LCD_MISC_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18)
+/** LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W; bitpos: [5:1]; default: 11;
+ *  The awfull threshold number of lcd_afifo.
+ */
+#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM    0x0000001FU
+#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M  (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V << LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S)
+#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V  0x0000001FU
+#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S  1
+/** LCD_CAM_LCD_VFK_CYCLELEN : R/W; bitpos: [11:6]; default: 3;
+ *  The setup cycle length minus 1 in LCD non-RGB mode.
+ */
+#define LCD_CAM_LCD_VFK_CYCLELEN    0x0000003FU
+#define LCD_CAM_LCD_VFK_CYCLELEN_M  (LCD_CAM_LCD_VFK_CYCLELEN_V << LCD_CAM_LCD_VFK_CYCLELEN_S)
+#define LCD_CAM_LCD_VFK_CYCLELEN_V  0x0000003FU
+#define LCD_CAM_LCD_VFK_CYCLELEN_S  6
+/** LCD_CAM_LCD_VBK_CYCLELEN : R/W; bitpos: [24:12]; default: 0;
+ *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+ *  time cycle length in LCD non-RGB mode.
+ */
+#define LCD_CAM_LCD_VBK_CYCLELEN    0x00001FFFU
+#define LCD_CAM_LCD_VBK_CYCLELEN_M  (LCD_CAM_LCD_VBK_CYCLELEN_V << LCD_CAM_LCD_VBK_CYCLELEN_S)
+#define LCD_CAM_LCD_VBK_CYCLELEN_V  0x00001FFFU
+#define LCD_CAM_LCD_VBK_CYCLELEN_S  12
+/** LCD_CAM_LCD_NEXT_FRAME_EN : R/W; bitpos: [25]; default: 0;
+ *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+ *  the current frame is sent out.
+ */
 #define LCD_CAM_LCD_NEXT_FRAME_EN    (BIT(25))
-#define LCD_CAM_LCD_NEXT_FRAME_EN_M  (BIT(25))
-#define LCD_CAM_LCD_NEXT_FRAME_EN_V  0x1
+#define LCD_CAM_LCD_NEXT_FRAME_EN_M  (LCD_CAM_LCD_NEXT_FRAME_EN_V << LCD_CAM_LCD_NEXT_FRAME_EN_S)
+#define LCD_CAM_LCD_NEXT_FRAME_EN_V  0x00000001U
 #define LCD_CAM_LCD_NEXT_FRAME_EN_S  25
-/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */
-/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
- time cycle length in LCD non-RGB mode..*/
-#define LCD_CAM_LCD_VBK_CYCLELEN    0x00001FFF
-#define LCD_CAM_LCD_VBK_CYCLELEN_M  ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S))
-#define LCD_CAM_LCD_VBK_CYCLELEN_V  0x1FFF
-#define LCD_CAM_LCD_VBK_CYCLELEN_S  12
-/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */
-/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/
-#define LCD_CAM_LCD_VFK_CYCLELEN    0x0000003F
-#define LCD_CAM_LCD_VFK_CYCLELEN_M  ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S))
-#define LCD_CAM_LCD_VFK_CYCLELEN_V  0x3F
-#define LCD_CAM_LCD_VFK_CYCLELEN_S  6
-/* LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W ;bitpos:[5:1] ;default: 5'd11 ; */
-/*description: The awfull threshold number of lcd_afifo..*/
-#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM    0x0000001F
-#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M  ((LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V)<<(LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S))
-#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V  0x1F
-#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S  1
+/** LCD_CAM_LCD_BK_EN : R/W; bitpos: [26]; default: 0;
+ *  1: Enable blank region when LCD sends data out. 0: No blank region.
+ */
+#define LCD_CAM_LCD_BK_EN    (BIT(26))
+#define LCD_CAM_LCD_BK_EN_M  (LCD_CAM_LCD_BK_EN_V << LCD_CAM_LCD_BK_EN_S)
+#define LCD_CAM_LCD_BK_EN_V  0x00000001U
+#define LCD_CAM_LCD_BK_EN_S  26
+/** LCD_CAM_LCD_AFIFO_RESET : WO; bitpos: [27]; default: 0;
+ *  LCD AFIFO reset signal.
+ */
+#define LCD_CAM_LCD_AFIFO_RESET    (BIT(27))
+#define LCD_CAM_LCD_AFIFO_RESET_M  (LCD_CAM_LCD_AFIFO_RESET_V << LCD_CAM_LCD_AFIFO_RESET_S)
+#define LCD_CAM_LCD_AFIFO_RESET_V  0x00000001U
+#define LCD_CAM_LCD_AFIFO_RESET_S  27
+/** LCD_CAM_LCD_CD_DATA_SET : R/W; bitpos: [28]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCD_CAM_LCD_CD_DATA_SET    (BIT(28))
+#define LCD_CAM_LCD_CD_DATA_SET_M  (LCD_CAM_LCD_CD_DATA_SET_V << LCD_CAM_LCD_CD_DATA_SET_S)
+#define LCD_CAM_LCD_CD_DATA_SET_V  0x00000001U
+#define LCD_CAM_LCD_CD_DATA_SET_S  28
+/** LCD_CAM_LCD_CD_DUMMY_SET : R/W; bitpos: [29]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCD_CAM_LCD_CD_DUMMY_SET    (BIT(29))
+#define LCD_CAM_LCD_CD_DUMMY_SET_M  (LCD_CAM_LCD_CD_DUMMY_SET_V << LCD_CAM_LCD_CD_DUMMY_SET_S)
+#define LCD_CAM_LCD_CD_DUMMY_SET_V  0x00000001U
+#define LCD_CAM_LCD_CD_DUMMY_SET_S  29
+/** LCD_CAM_LCD_CD_CMD_SET : R/W; bitpos: [30]; default: 0;
+ *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+ *  reg_cd_idle_edge.
+ */
+#define LCD_CAM_LCD_CD_CMD_SET    (BIT(30))
+#define LCD_CAM_LCD_CD_CMD_SET_M  (LCD_CAM_LCD_CD_CMD_SET_V << LCD_CAM_LCD_CD_CMD_SET_S)
+#define LCD_CAM_LCD_CD_CMD_SET_V  0x00000001U
+#define LCD_CAM_LCD_CD_CMD_SET_S  30
+/** LCD_CAM_LCD_CD_IDLE_EDGE : R/W; bitpos: [31]; default: 0;
+ *  The default value of LCD_CD.
+ */
+#define LCD_CAM_LCD_CD_IDLE_EDGE    (BIT(31))
+#define LCD_CAM_LCD_CD_IDLE_EDGE_M  (LCD_CAM_LCD_CD_IDLE_EDGE_V << LCD_CAM_LCD_CD_IDLE_EDGE_S)
+#define LCD_CAM_LCD_CD_IDLE_EDGE_V  0x00000001U
+#define LCD_CAM_LCD_CD_IDLE_EDGE_S  31
 
-#define LCD_CAM_LCD_CTRL_REG          (DR_REG_LCD_CAM_BASE + 0x1C)
-/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: Enable reg mode input vsync.*/
+/** LCD_CAM_LCD_CTRL_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1c)
+/** LCD_CAM_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0;
+ *  It is the horizontal blank front porch of a frame.
+ */
+#define LCD_CAM_LCD_HB_FRONT    0x000007FFU
+#define LCD_CAM_LCD_HB_FRONT_M  (LCD_CAM_LCD_HB_FRONT_V << LCD_CAM_LCD_HB_FRONT_S)
+#define LCD_CAM_LCD_HB_FRONT_V  0x000007FFU
+#define LCD_CAM_LCD_HB_FRONT_S  0
+/** LCD_CAM_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0;
+ *  It is the vertical active height of a frame.
+ */
+#define LCD_CAM_LCD_VA_HEIGHT    0x000003FFU
+#define LCD_CAM_LCD_VA_HEIGHT_M  (LCD_CAM_LCD_VA_HEIGHT_V << LCD_CAM_LCD_VA_HEIGHT_S)
+#define LCD_CAM_LCD_VA_HEIGHT_V  0x000003FFU
+#define LCD_CAM_LCD_VA_HEIGHT_S  11
+/** LCD_CAM_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0;
+ *  It is the vertical total height of a frame.
+ */
+#define LCD_CAM_LCD_VT_HEIGHT    0x000003FFU
+#define LCD_CAM_LCD_VT_HEIGHT_M  (LCD_CAM_LCD_VT_HEIGHT_V << LCD_CAM_LCD_VT_HEIGHT_S)
+#define LCD_CAM_LCD_VT_HEIGHT_V  0x000003FFU
+#define LCD_CAM_LCD_VT_HEIGHT_S  21
+/** LCD_CAM_LCD_RGB_MODE_EN : R/W; bitpos: [31]; default: 0;
+ *  1: Enable reg mode input vsync, hsync, de. 0: Disable.
+ */
 #define LCD_CAM_LCD_RGB_MODE_EN    (BIT(31))
-#define LCD_CAM_LCD_RGB_MODE_EN_M  (BIT(31))
-#define LCD_CAM_LCD_RGB_MODE_EN_V  0x1
+#define LCD_CAM_LCD_RGB_MODE_EN_M  (LCD_CAM_LCD_RGB_MODE_EN_V << LCD_CAM_LCD_RGB_MODE_EN_S)
+#define LCD_CAM_LCD_RGB_MODE_EN_V  0x00000001U
 #define LCD_CAM_LCD_RGB_MODE_EN_S  31
-/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
-/*description: It is the vertical total height of a frame. .*/
-#define LCD_CAM_LCD_VT_HEIGHT    0x000003FF
-#define LCD_CAM_LCD_VT_HEIGHT_M  ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S))
-#define LCD_CAM_LCD_VT_HEIGHT_V  0x3FF
-#define LCD_CAM_LCD_VT_HEIGHT_S  21
-/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */
-/*description: It is the vertical active height of a frame. .*/
-#define LCD_CAM_LCD_VA_HEIGHT    0x000003FF
-#define LCD_CAM_LCD_VA_HEIGHT_M  ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S))
-#define LCD_CAM_LCD_VA_HEIGHT_V  0x3FF
-#define LCD_CAM_LCD_VA_HEIGHT_S  11
-/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */
-/*description: It is the horizontal blank front porch of a frame. .*/
-#define LCD_CAM_LCD_HB_FRONT    0x000007FF
-#define LCD_CAM_LCD_HB_FRONT_M  ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S))
-#define LCD_CAM_LCD_HB_FRONT_V  0x7FF
-#define LCD_CAM_LCD_HB_FRONT_S  0
 
-#define LCD_CAM_LCD_CTRL1_REG          (DR_REG_LCD_CAM_BASE + 0x20)
-/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
-/*description: It is the horizontal total width of a frame. .*/
-#define LCD_CAM_LCD_HT_WIDTH    0x00000FFF
-#define LCD_CAM_LCD_HT_WIDTH_M  ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S))
-#define LCD_CAM_LCD_HT_WIDTH_V  0xFFF
-#define LCD_CAM_LCD_HT_WIDTH_S  20
-/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */
-/*description: It is the horizontal active width of a frame. .*/
-#define LCD_CAM_LCD_HA_WIDTH    0x00000FFF
-#define LCD_CAM_LCD_HA_WIDTH_M  ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S))
-#define LCD_CAM_LCD_HA_WIDTH_V  0xFFF
-#define LCD_CAM_LCD_HA_WIDTH_S  8
-/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
-/*description: It is the vertical blank front porch of a frame. .*/
-#define LCD_CAM_LCD_VB_FRONT    0x000000FF
-#define LCD_CAM_LCD_VB_FRONT_M  ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S))
-#define LCD_CAM_LCD_VB_FRONT_V  0xFF
+/** LCD_CAM_LCD_CTRL1_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20)
+/** LCD_CAM_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0;
+ *  It is the vertical blank front porch of a frame.
+ */
+#define LCD_CAM_LCD_VB_FRONT    0x000000FFU
+#define LCD_CAM_LCD_VB_FRONT_M  (LCD_CAM_LCD_VB_FRONT_V << LCD_CAM_LCD_VB_FRONT_S)
+#define LCD_CAM_LCD_VB_FRONT_V  0x000000FFU
 #define LCD_CAM_LCD_VB_FRONT_S  0
+/** LCD_CAM_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0;
+ *  It is the horizontal active width of a frame.
+ */
+#define LCD_CAM_LCD_HA_WIDTH    0x00000FFFU
+#define LCD_CAM_LCD_HA_WIDTH_M  (LCD_CAM_LCD_HA_WIDTH_V << LCD_CAM_LCD_HA_WIDTH_S)
+#define LCD_CAM_LCD_HA_WIDTH_V  0x00000FFFU
+#define LCD_CAM_LCD_HA_WIDTH_S  8
+/** LCD_CAM_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0;
+ *  It is the horizontal total width of a frame.
+ */
+#define LCD_CAM_LCD_HT_WIDTH    0x00000FFFU
+#define LCD_CAM_LCD_HT_WIDTH_M  (LCD_CAM_LCD_HT_WIDTH_V << LCD_CAM_LCD_HT_WIDTH_S)
+#define LCD_CAM_LCD_HT_WIDTH_V  0x00000FFFU
+#define LCD_CAM_LCD_HT_WIDTH_S  20
 
-#define LCD_CAM_LCD_CTRL2_REG          (DR_REG_LCD_CAM_BASE + 0x24)
-/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
-/*description: It is the position of LCD_HSYNC active pulse in a line. .*/
-#define LCD_CAM_LCD_HSYNC_POSITION    0x000000FF
-#define LCD_CAM_LCD_HSYNC_POSITION_M  ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S))
-#define LCD_CAM_LCD_HSYNC_POSITION_V  0xFF
-#define LCD_CAM_LCD_HSYNC_POSITION_S  24
-/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: It is the idle value of LCD_HSYNC. .*/
-#define LCD_CAM_LCD_HSYNC_IDLE_POL    (BIT(23))
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_M  (BIT(23))
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_V  0x1
-#define LCD_CAM_LCD_HSYNC_IDLE_POL_S  23
-/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
-/*description: It is the position of LCD_HSYNC active pulse in a line. .*/
-#define LCD_CAM_LCD_HSYNC_WIDTH    0x0000007F
-#define LCD_CAM_LCD_HSYNC_WIDTH_M  ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S))
-#define LCD_CAM_LCD_HSYNC_WIDTH_V  0x7F
-#define LCD_CAM_LCD_HSYNC_WIDTH_S  16
-/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY
-NC pulse is valid only in active region lines in RGB mode. .*/
-#define LCD_CAM_LCD_HS_BLANK_EN    (BIT(9))
-#define LCD_CAM_LCD_HS_BLANK_EN_M  (BIT(9))
-#define LCD_CAM_LCD_HS_BLANK_EN_V  0x1
-#define LCD_CAM_LCD_HS_BLANK_EN_S  9
-/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: It is the idle value of LCD_DE. .*/
-#define LCD_CAM_LCD_DE_IDLE_POL    (BIT(8))
-#define LCD_CAM_LCD_DE_IDLE_POL_M  (BIT(8))
-#define LCD_CAM_LCD_DE_IDLE_POL_V  0x1
-#define LCD_CAM_LCD_DE_IDLE_POL_S  8
-/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: It is the idle value of LCD_VSYNC. .*/
+/** LCD_CAM_LCD_CTRL2_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24)
+/** LCD_CAM_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 1;
+ *  It is the position of LCD_VSYNC active pulse in a line.
+ */
+#define LCD_CAM_LCD_VSYNC_WIDTH    0x0000007FU
+#define LCD_CAM_LCD_VSYNC_WIDTH_M  (LCD_CAM_LCD_VSYNC_WIDTH_V << LCD_CAM_LCD_VSYNC_WIDTH_S)
+#define LCD_CAM_LCD_VSYNC_WIDTH_V  0x0000007FU
+#define LCD_CAM_LCD_VSYNC_WIDTH_S  0
+/** LCD_CAM_LCD_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0;
+ *  It is the idle value of LCD_VSYNC.
+ */
 #define LCD_CAM_LCD_VSYNC_IDLE_POL    (BIT(7))
-#define LCD_CAM_LCD_VSYNC_IDLE_POL_M  (BIT(7))
-#define LCD_CAM_LCD_VSYNC_IDLE_POL_V  0x1
+#define LCD_CAM_LCD_VSYNC_IDLE_POL_M  (LCD_CAM_LCD_VSYNC_IDLE_POL_V << LCD_CAM_LCD_VSYNC_IDLE_POL_S)
+#define LCD_CAM_LCD_VSYNC_IDLE_POL_V  0x00000001U
 #define LCD_CAM_LCD_VSYNC_IDLE_POL_S  7
-/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
-/*description: It is the position of LCD_VSYNC active pulse in a line. .*/
-#define LCD_CAM_LCD_VSYNC_WIDTH    0x0000007F
-#define LCD_CAM_LCD_VSYNC_WIDTH_M  ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S))
-#define LCD_CAM_LCD_VSYNC_WIDTH_V  0x7F
-#define LCD_CAM_LCD_VSYNC_WIDTH_S  0
+/** LCD_CAM_LCD_DE_IDLE_POL : R/W; bitpos: [8]; default: 0;
+ *  It is the idle value of LCD_DE.
+ */
+#define LCD_CAM_LCD_DE_IDLE_POL    (BIT(8))
+#define LCD_CAM_LCD_DE_IDLE_POL_M  (LCD_CAM_LCD_DE_IDLE_POL_V << LCD_CAM_LCD_DE_IDLE_POL_S)
+#define LCD_CAM_LCD_DE_IDLE_POL_V  0x00000001U
+#define LCD_CAM_LCD_DE_IDLE_POL_S  8
+/** LCD_CAM_LCD_HS_BLANK_EN : R/W; bitpos: [9]; default: 0;
+ *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+ *  pulse is valid only in active region lines in RGB mode.
+ */
+#define LCD_CAM_LCD_HS_BLANK_EN    (BIT(9))
+#define LCD_CAM_LCD_HS_BLANK_EN_M  (LCD_CAM_LCD_HS_BLANK_EN_V << LCD_CAM_LCD_HS_BLANK_EN_S)
+#define LCD_CAM_LCD_HS_BLANK_EN_V  0x00000001U
+#define LCD_CAM_LCD_HS_BLANK_EN_S  9
+/** LCD_CAM_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 1;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCD_CAM_LCD_HSYNC_WIDTH    0x0000007FU
+#define LCD_CAM_LCD_HSYNC_WIDTH_M  (LCD_CAM_LCD_HSYNC_WIDTH_V << LCD_CAM_LCD_HSYNC_WIDTH_S)
+#define LCD_CAM_LCD_HSYNC_WIDTH_V  0x0000007FU
+#define LCD_CAM_LCD_HSYNC_WIDTH_S  16
+/** LCD_CAM_LCD_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0;
+ *  It is the idle value of LCD_HSYNC.
+ */
+#define LCD_CAM_LCD_HSYNC_IDLE_POL    (BIT(23))
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_M  (LCD_CAM_LCD_HSYNC_IDLE_POL_V << LCD_CAM_LCD_HSYNC_IDLE_POL_S)
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_V  0x00000001U
+#define LCD_CAM_LCD_HSYNC_IDLE_POL_S  23
+/** LCD_CAM_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0;
+ *  It is the position of LCD_HSYNC active pulse in a line.
+ */
+#define LCD_CAM_LCD_HSYNC_POSITION    0x000000FFU
+#define LCD_CAM_LCD_HSYNC_POSITION_M  (LCD_CAM_LCD_HSYNC_POSITION_V << LCD_CAM_LCD_HSYNC_POSITION_S)
+#define LCD_CAM_LCD_HSYNC_POSITION_V  0x000000FFU
+#define LCD_CAM_LCD_HSYNC_POSITION_S  24
 
-#define LCD_CAM_LCD_CMD_VAL_REG          (DR_REG_LCD_CAM_BASE + 0x28)
-/* LCD_CAM_LCD_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The LCD write command value..*/
-#define LCD_CAM_LCD_CMD_VALUE    0xFFFFFFFF
-#define LCD_CAM_LCD_CMD_VALUE_M  ((LCD_CAM_LCD_CMD_VALUE_V)<<(LCD_CAM_LCD_CMD_VALUE_S))
-#define LCD_CAM_LCD_CMD_VALUE_V  0xFFFFFFFF
+/** LCD_CAM_LCD_CMD_VAL_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28)
+/** LCD_CAM_LCD_CMD_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  The LCD write command value.
+ */
+#define LCD_CAM_LCD_CMD_VALUE    0xFFFFFFFFU
+#define LCD_CAM_LCD_CMD_VALUE_M  (LCD_CAM_LCD_CMD_VALUE_V << LCD_CAM_LCD_CMD_VALUE_S)
+#define LCD_CAM_LCD_CMD_VALUE_V  0xFFFFFFFFU
 #define LCD_CAM_LCD_CMD_VALUE_S  0
 
-#define LCD_CAM_LCD_DLY_MODE_REG          (DR_REG_LCD_CAM_BASE + 0x30)
-/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_LCD_VSYNC_MODE    0x00000003
-#define LCD_CAM_LCD_VSYNC_MODE_M  ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S))
-#define LCD_CAM_LCD_VSYNC_MODE_V  0x3
-#define LCD_CAM_LCD_VSYNC_MODE_S  6
-/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_LCD_HSYNC_MODE    0x00000003
-#define LCD_CAM_LCD_HSYNC_MODE_M  ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S))
-#define LCD_CAM_LCD_HSYNC_MODE_V  0x3
-#define LCD_CAM_LCD_HSYNC_MODE_S  4
-/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: The output LCD_DE is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_LCD_DE_MODE    0x00000003
-#define LCD_CAM_LCD_DE_MODE_M  ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S))
-#define LCD_CAM_LCD_DE_MODE_V  0x3
-#define LCD_CAM_LCD_DE_MODE_S  2
-/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The output LCD_CD is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_LCD_CD_MODE    0x00000003
-#define LCD_CAM_LCD_CD_MODE_M  ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S))
-#define LCD_CAM_LCD_CD_MODE_V  0x3
+/** LCD_CAM_LCD_DLY_MODE_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x30)
+/** LCD_CAM_LCD_CD_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCD_CAM_LCD_CD_MODE    0x00000003U
+#define LCD_CAM_LCD_CD_MODE_M  (LCD_CAM_LCD_CD_MODE_V << LCD_CAM_LCD_CD_MODE_S)
+#define LCD_CAM_LCD_CD_MODE_V  0x00000003U
 #define LCD_CAM_LCD_CD_MODE_S  0
+/** LCD_CAM_LCD_DE_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+ *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCD_CAM_LCD_DE_MODE    0x00000003U
+#define LCD_CAM_LCD_DE_MODE_M  (LCD_CAM_LCD_DE_MODE_V << LCD_CAM_LCD_DE_MODE_S)
+#define LCD_CAM_LCD_DE_MODE_V  0x00000003U
+#define LCD_CAM_LCD_DE_MODE_S  2
+/** LCD_CAM_LCD_HSYNC_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCD_CAM_LCD_HSYNC_MODE    0x00000003U
+#define LCD_CAM_LCD_HSYNC_MODE_M  (LCD_CAM_LCD_HSYNC_MODE_V << LCD_CAM_LCD_HSYNC_MODE_S)
+#define LCD_CAM_LCD_HSYNC_MODE_V  0x00000003U
+#define LCD_CAM_LCD_HSYNC_MODE_S  4
+/** LCD_CAM_LCD_VSYNC_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+ *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+ */
+#define LCD_CAM_LCD_VSYNC_MODE    0x00000003U
+#define LCD_CAM_LCD_VSYNC_MODE_M  (LCD_CAM_LCD_VSYNC_MODE_V << LCD_CAM_LCD_VSYNC_MODE_S)
+#define LCD_CAM_LCD_VSYNC_MODE_V  0x00000003U
+#define LCD_CAM_LCD_VSYNC_MODE_S  6
 
-#define LCD_CAM_LCD_DATA_DOUT_MODE_REG          (DR_REG_LCD_CAM_BASE + 0x38)
-/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT15_MODE    0x00000003
-#define LCD_CAM_DOUT15_MODE_M  ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S))
-#define LCD_CAM_DOUT15_MODE_V  0x3
-#define LCD_CAM_DOUT15_MODE_S  30
-/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT14_MODE    0x00000003
-#define LCD_CAM_DOUT14_MODE_M  ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S))
-#define LCD_CAM_DOUT14_MODE_V  0x3
-#define LCD_CAM_DOUT14_MODE_S  28
-/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT13_MODE    0x00000003
-#define LCD_CAM_DOUT13_MODE_M  ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S))
-#define LCD_CAM_DOUT13_MODE_V  0x3
-#define LCD_CAM_DOUT13_MODE_S  26
-/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT12_MODE    0x00000003
-#define LCD_CAM_DOUT12_MODE_M  ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S))
-#define LCD_CAM_DOUT12_MODE_V  0x3
-#define LCD_CAM_DOUT12_MODE_S  24
-/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT11_MODE    0x00000003
-#define LCD_CAM_DOUT11_MODE_M  ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S))
-#define LCD_CAM_DOUT11_MODE_V  0x3
-#define LCD_CAM_DOUT11_MODE_S  22
-/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT10_MODE    0x00000003
-#define LCD_CAM_DOUT10_MODE_M  ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S))
-#define LCD_CAM_DOUT10_MODE_V  0x3
-#define LCD_CAM_DOUT10_MODE_S  20
-/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT9_MODE    0x00000003
-#define LCD_CAM_DOUT9_MODE_M  ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S))
-#define LCD_CAM_DOUT9_MODE_V  0x3
-#define LCD_CAM_DOUT9_MODE_S  18
-/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT8_MODE    0x00000003
-#define LCD_CAM_DOUT8_MODE_M  ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S))
-#define LCD_CAM_DOUT8_MODE_V  0x3
-#define LCD_CAM_DOUT8_MODE_S  16
-/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT7_MODE    0x00000003
-#define LCD_CAM_DOUT7_MODE_M  ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S))
-#define LCD_CAM_DOUT7_MODE_V  0x3
-#define LCD_CAM_DOUT7_MODE_S  14
-/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT6_MODE    0x00000003
-#define LCD_CAM_DOUT6_MODE_M  ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S))
-#define LCD_CAM_DOUT6_MODE_V  0x3
-#define LCD_CAM_DOUT6_MODE_S  12
-/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT5_MODE    0x00000003
-#define LCD_CAM_DOUT5_MODE_M  ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S))
-#define LCD_CAM_DOUT5_MODE_V  0x3
-#define LCD_CAM_DOUT5_MODE_S  10
-/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT4_MODE    0x00000003
-#define LCD_CAM_DOUT4_MODE_M  ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S))
-#define LCD_CAM_DOUT4_MODE_V  0x3
-#define LCD_CAM_DOUT4_MODE_S  8
-/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT3_MODE    0x00000003
-#define LCD_CAM_DOUT3_MODE_M  ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S))
-#define LCD_CAM_DOUT3_MODE_V  0x3
-#define LCD_CAM_DOUT3_MODE_S  6
-/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT2_MODE    0x00000003
-#define LCD_CAM_DOUT2_MODE_M  ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S))
-#define LCD_CAM_DOUT2_MODE_V  0x3
-#define LCD_CAM_DOUT2_MODE_S  4
-/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT1_MODE    0x00000003
-#define LCD_CAM_DOUT1_MODE_M  ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S))
-#define LCD_CAM_DOUT1_MODE_V  0x3
-#define LCD_CAM_DOUT1_MODE_S  2
-/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The output data bit $n is delayed by module clock LCD_CLK.*/
-#define LCD_CAM_DOUT0_MODE    0x00000003
-#define LCD_CAM_DOUT0_MODE_M  ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S))
-#define LCD_CAM_DOUT0_MODE_V  0x3
+/** LCD_CAM_LCD_DATA_DOUT_MODE_REG register
+ *  LCD configuration register
+ */
+#define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x38)
+/** LCD_CAM_DOUT0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT0_MODE    0x00000003U
+#define LCD_CAM_DOUT0_MODE_M  (LCD_CAM_DOUT0_MODE_V << LCD_CAM_DOUT0_MODE_S)
+#define LCD_CAM_DOUT0_MODE_V  0x00000003U
 #define LCD_CAM_DOUT0_MODE_S  0
+/** LCD_CAM_DOUT1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT1_MODE    0x00000003U
+#define LCD_CAM_DOUT1_MODE_M  (LCD_CAM_DOUT1_MODE_V << LCD_CAM_DOUT1_MODE_S)
+#define LCD_CAM_DOUT1_MODE_V  0x00000003U
+#define LCD_CAM_DOUT1_MODE_S  2
+/** LCD_CAM_DOUT2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT2_MODE    0x00000003U
+#define LCD_CAM_DOUT2_MODE_M  (LCD_CAM_DOUT2_MODE_V << LCD_CAM_DOUT2_MODE_S)
+#define LCD_CAM_DOUT2_MODE_V  0x00000003U
+#define LCD_CAM_DOUT2_MODE_S  4
+/** LCD_CAM_DOUT3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT3_MODE    0x00000003U
+#define LCD_CAM_DOUT3_MODE_M  (LCD_CAM_DOUT3_MODE_V << LCD_CAM_DOUT3_MODE_S)
+#define LCD_CAM_DOUT3_MODE_V  0x00000003U
+#define LCD_CAM_DOUT3_MODE_S  6
+/** LCD_CAM_DOUT4_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT4_MODE    0x00000003U
+#define LCD_CAM_DOUT4_MODE_M  (LCD_CAM_DOUT4_MODE_V << LCD_CAM_DOUT4_MODE_S)
+#define LCD_CAM_DOUT4_MODE_V  0x00000003U
+#define LCD_CAM_DOUT4_MODE_S  8
+/** LCD_CAM_DOUT5_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT5_MODE    0x00000003U
+#define LCD_CAM_DOUT5_MODE_M  (LCD_CAM_DOUT5_MODE_V << LCD_CAM_DOUT5_MODE_S)
+#define LCD_CAM_DOUT5_MODE_V  0x00000003U
+#define LCD_CAM_DOUT5_MODE_S  10
+/** LCD_CAM_DOUT6_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT6_MODE    0x00000003U
+#define LCD_CAM_DOUT6_MODE_M  (LCD_CAM_DOUT6_MODE_V << LCD_CAM_DOUT6_MODE_S)
+#define LCD_CAM_DOUT6_MODE_V  0x00000003U
+#define LCD_CAM_DOUT6_MODE_S  12
+/** LCD_CAM_DOUT7_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT7_MODE    0x00000003U
+#define LCD_CAM_DOUT7_MODE_M  (LCD_CAM_DOUT7_MODE_V << LCD_CAM_DOUT7_MODE_S)
+#define LCD_CAM_DOUT7_MODE_V  0x00000003U
+#define LCD_CAM_DOUT7_MODE_S  14
+/** LCD_CAM_DOUT8_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT8_MODE    0x00000003U
+#define LCD_CAM_DOUT8_MODE_M  (LCD_CAM_DOUT8_MODE_V << LCD_CAM_DOUT8_MODE_S)
+#define LCD_CAM_DOUT8_MODE_V  0x00000003U
+#define LCD_CAM_DOUT8_MODE_S  16
+/** LCD_CAM_DOUT9_MODE : R/W; bitpos: [19:18]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT9_MODE    0x00000003U
+#define LCD_CAM_DOUT9_MODE_M  (LCD_CAM_DOUT9_MODE_V << LCD_CAM_DOUT9_MODE_S)
+#define LCD_CAM_DOUT9_MODE_V  0x00000003U
+#define LCD_CAM_DOUT9_MODE_S  18
+/** LCD_CAM_DOUT10_MODE : R/W; bitpos: [21:20]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT10_MODE    0x00000003U
+#define LCD_CAM_DOUT10_MODE_M  (LCD_CAM_DOUT10_MODE_V << LCD_CAM_DOUT10_MODE_S)
+#define LCD_CAM_DOUT10_MODE_V  0x00000003U
+#define LCD_CAM_DOUT10_MODE_S  20
+/** LCD_CAM_DOUT11_MODE : R/W; bitpos: [23:22]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT11_MODE    0x00000003U
+#define LCD_CAM_DOUT11_MODE_M  (LCD_CAM_DOUT11_MODE_V << LCD_CAM_DOUT11_MODE_S)
+#define LCD_CAM_DOUT11_MODE_V  0x00000003U
+#define LCD_CAM_DOUT11_MODE_S  22
+/** LCD_CAM_DOUT12_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT12_MODE    0x00000003U
+#define LCD_CAM_DOUT12_MODE_M  (LCD_CAM_DOUT12_MODE_V << LCD_CAM_DOUT12_MODE_S)
+#define LCD_CAM_DOUT12_MODE_V  0x00000003U
+#define LCD_CAM_DOUT12_MODE_S  24
+/** LCD_CAM_DOUT13_MODE : R/W; bitpos: [27:26]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT13_MODE    0x00000003U
+#define LCD_CAM_DOUT13_MODE_M  (LCD_CAM_DOUT13_MODE_V << LCD_CAM_DOUT13_MODE_S)
+#define LCD_CAM_DOUT13_MODE_V  0x00000003U
+#define LCD_CAM_DOUT13_MODE_S  26
+/** LCD_CAM_DOUT14_MODE : R/W; bitpos: [29:28]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT14_MODE    0x00000003U
+#define LCD_CAM_DOUT14_MODE_M  (LCD_CAM_DOUT14_MODE_V << LCD_CAM_DOUT14_MODE_S)
+#define LCD_CAM_DOUT14_MODE_V  0x00000003U
+#define LCD_CAM_DOUT14_MODE_S  28
+/** LCD_CAM_DOUT15_MODE : R/W; bitpos: [31:30]; default: 0;
+ *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+ *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+ *  LCD_CLK.
+ */
+#define LCD_CAM_DOUT15_MODE    0x00000003U
+#define LCD_CAM_DOUT15_MODE_M  (LCD_CAM_DOUT15_MODE_V << LCD_CAM_DOUT15_MODE_S)
+#define LCD_CAM_DOUT15_MODE_V  0x00000003U
+#define LCD_CAM_DOUT15_MODE_S  30
 
-#define LCD_CAM_LC_DMA_INT_ENA_REG          (DR_REG_LCD_CAM_BASE + 0x64)
-/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_ENA    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ENA_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ENA_V  0x1
-#define LCD_CAM_CAM_HS_INT_ENA_S  3
-/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_ENA    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ENA_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ENA_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_ENA_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S  1
-/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for LCD frame end interrupt..*/
+/** LCD_CAM_LC_DMA_INT_ENA_REG register
+ *  LCD_camera DMA inturrupt enable register
+ */
+#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64)
+/** LCD_CAM_LCD_VSYNC_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for LCD frame end interrupt.
+ */
 #define LCD_CAM_LCD_VSYNC_INT_ENA    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ENA_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ENA_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_ENA_M  (LCD_CAM_LCD_VSYNC_INT_ENA_V << LCD_CAM_LCD_VSYNC_INT_ENA_S)
+#define LCD_CAM_LCD_VSYNC_INT_ENA_V  0x00000001U
 #define LCD_CAM_LCD_VSYNC_INT_ENA_S  0
+/** LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for lcd transfer end interrupt.
+ */
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M  (LCD_CAM_LCD_TRANS_DONE_INT_ENA_V << LCD_CAM_LCD_TRANS_DONE_INT_ENA_S)
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V  0x00000001U
+#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S  1
+/** LCD_CAM_CAM_VSYNC_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for Camera frame end interrupt.
+ */
+#define LCD_CAM_CAM_VSYNC_INT_ENA    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ENA_M  (LCD_CAM_CAM_VSYNC_INT_ENA_V << LCD_CAM_CAM_VSYNC_INT_ENA_S)
+#define LCD_CAM_CAM_VSYNC_INT_ENA_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_INT_ENA_S  2
+/** LCD_CAM_CAM_HS_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for Camera line interrupt.
+ */
+#define LCD_CAM_CAM_HS_INT_ENA    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ENA_M  (LCD_CAM_CAM_HS_INT_ENA_V << LCD_CAM_CAM_HS_INT_ENA_S)
+#define LCD_CAM_CAM_HS_INT_ENA_V  0x00000001U
+#define LCD_CAM_CAM_HS_INT_ENA_S  3
 
-#define LCD_CAM_LC_DMA_INT_RAW_REG          (DR_REG_LCD_CAM_BASE + 0x68)
-/* LCD_CAM_CAM_HS_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_RAW    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_RAW_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_RAW_V  0x1
-#define LCD_CAM_CAM_HS_INT_RAW_S  3
-/* LCD_CAM_CAM_VSYNC_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_RAW    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_RAW_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_RAW_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_RAW_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S  1
-/* LCD_CAM_LCD_VSYNC_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for LCD frame end interrupt..*/
+/** LCD_CAM_LC_DMA_INT_RAW_REG register
+ *  LCD_camera DMA raw inturrupt status register
+ */
+#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68)
+/** LCD_CAM_LCD_VSYNC_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw bit for LCD frame end interrupt.
+ */
 #define LCD_CAM_LCD_VSYNC_INT_RAW    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_RAW_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_RAW_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_RAW_M  (LCD_CAM_LCD_VSYNC_INT_RAW_V << LCD_CAM_LCD_VSYNC_INT_RAW_S)
+#define LCD_CAM_LCD_VSYNC_INT_RAW_V  0x00000001U
 #define LCD_CAM_LCD_VSYNC_INT_RAW_S  0
+/** LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw bit for lcd transfer end interrupt.
+ */
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M  (LCD_CAM_LCD_TRANS_DONE_INT_RAW_V << LCD_CAM_LCD_TRANS_DONE_INT_RAW_S)
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V  0x00000001U
+#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S  1
+/** LCD_CAM_CAM_VSYNC_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw bit for Camera frame end interrupt.
+ */
+#define LCD_CAM_CAM_VSYNC_INT_RAW    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_RAW_M  (LCD_CAM_CAM_VSYNC_INT_RAW_V << LCD_CAM_CAM_VSYNC_INT_RAW_S)
+#define LCD_CAM_CAM_VSYNC_INT_RAW_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_INT_RAW_S  2
+/** LCD_CAM_CAM_HS_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw bit for Camera line interrupt.
+ */
+#define LCD_CAM_CAM_HS_INT_RAW    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_RAW_M  (LCD_CAM_CAM_HS_INT_RAW_V << LCD_CAM_CAM_HS_INT_RAW_S)
+#define LCD_CAM_CAM_HS_INT_RAW_V  0x00000001U
+#define LCD_CAM_CAM_HS_INT_RAW_S  3
 
-#define LCD_CAM_LC_DMA_INT_ST_REG          (DR_REG_LCD_CAM_BASE + 0x6C)
-/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for Camera transfer end interrupt..*/
-#define LCD_CAM_CAM_HS_INT_ST    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ST_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_ST_V  0x1
-#define LCD_CAM_CAM_HS_INT_ST_S  3
-/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_ST    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ST_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_ST_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_ST_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S  1
-/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for LCD frame end interrupt..*/
+/** LCD_CAM_LC_DMA_INT_ST_REG register
+ *  LCD_camera DMA masked inturrupt status register
+ */
+#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6c)
+/** LCD_CAM_LCD_VSYNC_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for LCD frame end interrupt.
+ */
 #define LCD_CAM_LCD_VSYNC_INT_ST    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ST_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_ST_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_ST_M  (LCD_CAM_LCD_VSYNC_INT_ST_V << LCD_CAM_LCD_VSYNC_INT_ST_S)
+#define LCD_CAM_LCD_VSYNC_INT_ST_V  0x00000001U
 #define LCD_CAM_LCD_VSYNC_INT_ST_S  0
+/** LCD_CAM_LCD_TRANS_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for lcd transfer end interrupt.
+ */
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M  (LCD_CAM_LCD_TRANS_DONE_INT_ST_V << LCD_CAM_LCD_TRANS_DONE_INT_ST_S)
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V  0x00000001U
+#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S  1
+/** LCD_CAM_CAM_VSYNC_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for Camera frame end interrupt.
+ */
+#define LCD_CAM_CAM_VSYNC_INT_ST    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_ST_M  (LCD_CAM_CAM_VSYNC_INT_ST_V << LCD_CAM_CAM_VSYNC_INT_ST_S)
+#define LCD_CAM_CAM_VSYNC_INT_ST_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_INT_ST_S  2
+/** LCD_CAM_CAM_HS_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for Camera transfer end interrupt.
+ */
+#define LCD_CAM_CAM_HS_INT_ST    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_ST_M  (LCD_CAM_CAM_HS_INT_ST_V << LCD_CAM_CAM_HS_INT_ST_S)
+#define LCD_CAM_CAM_HS_INT_ST_V  0x00000001U
+#define LCD_CAM_CAM_HS_INT_ST_S  3
 
-#define LCD_CAM_LC_DMA_INT_CLR_REG          (DR_REG_LCD_CAM_BASE + 0x70)
-/* LCD_CAM_CAM_HS_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for Camera line interrupt..*/
-#define LCD_CAM_CAM_HS_INT_CLR    (BIT(3))
-#define LCD_CAM_CAM_HS_INT_CLR_M  (BIT(3))
-#define LCD_CAM_CAM_HS_INT_CLR_V  0x1
-#define LCD_CAM_CAM_HS_INT_CLR_S  3
-/* LCD_CAM_CAM_VSYNC_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for Camera frame end interrupt..*/
-#define LCD_CAM_CAM_VSYNC_INT_CLR    (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_CLR_M  (BIT(2))
-#define LCD_CAM_CAM_VSYNC_INT_CLR_V  0x1
-#define LCD_CAM_CAM_VSYNC_INT_CLR_S  2
-/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for lcd transfer end interrupt..*/
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M  (BIT(1))
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V  0x1
-#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S  1
-/* LCD_CAM_LCD_VSYNC_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for LCD frame end interrupt..*/
+/** LCD_CAM_LC_DMA_INT_CLR_REG register
+ *  LCD_camera DMA inturrupt clear register
+ */
+#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70)
+/** LCD_CAM_LCD_VSYNC_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  The clear bit for LCD frame end interrupt.
+ */
 #define LCD_CAM_LCD_VSYNC_INT_CLR    (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_CLR_M  (BIT(0))
-#define LCD_CAM_LCD_VSYNC_INT_CLR_V  0x1
+#define LCD_CAM_LCD_VSYNC_INT_CLR_M  (LCD_CAM_LCD_VSYNC_INT_CLR_V << LCD_CAM_LCD_VSYNC_INT_CLR_S)
+#define LCD_CAM_LCD_VSYNC_INT_CLR_V  0x00000001U
 #define LCD_CAM_LCD_VSYNC_INT_CLR_S  0
+/** LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  The clear bit for lcd transfer end interrupt.
+ */
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR    (BIT(1))
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M  (LCD_CAM_LCD_TRANS_DONE_INT_CLR_V << LCD_CAM_LCD_TRANS_DONE_INT_CLR_S)
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V  0x00000001U
+#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S  1
+/** LCD_CAM_CAM_VSYNC_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  The clear bit for Camera frame end interrupt.
+ */
+#define LCD_CAM_CAM_VSYNC_INT_CLR    (BIT(2))
+#define LCD_CAM_CAM_VSYNC_INT_CLR_M  (LCD_CAM_CAM_VSYNC_INT_CLR_V << LCD_CAM_CAM_VSYNC_INT_CLR_S)
+#define LCD_CAM_CAM_VSYNC_INT_CLR_V  0x00000001U
+#define LCD_CAM_CAM_VSYNC_INT_CLR_S  2
+/** LCD_CAM_CAM_HS_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  The clear bit for Camera line interrupt.
+ */
+#define LCD_CAM_CAM_HS_INT_CLR    (BIT(3))
+#define LCD_CAM_CAM_HS_INT_CLR_M  (LCD_CAM_CAM_HS_INT_CLR_V << LCD_CAM_CAM_HS_INT_CLR_S)
+#define LCD_CAM_CAM_HS_INT_CLR_V  0x00000001U
+#define LCD_CAM_CAM_HS_INT_CLR_S  3
 
-#define LCD_CAM_LC_REG_DATE_REG          (DR_REG_LCD_CAM_BASE + 0xFC)
-/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
-/*description: LCD_CAM version control register.*/
-#define LCD_CAM_LC_DATE    0x0FFFFFFF
-#define LCD_CAM_LC_DATE_M  ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S))
-#define LCD_CAM_LC_DATE_V  0xFFFFFFF
+/** LCD_CAM_LC_REG_DATE_REG register
+ *  Version register
+ */
+#define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xfc)
+/** LCD_CAM_LC_DATE : R/W; bitpos: [27:0]; default: 33566752;
+ *  LCD_CAM version control register
+ */
+#define LCD_CAM_LC_DATE    0x0FFFFFFFU
+#define LCD_CAM_LC_DATE_M  (LCD_CAM_LC_DATE_V << LCD_CAM_LC_DATE_S)
+#define LCD_CAM_LC_DATE_V  0x0FFFFFFFU
 #define LCD_CAM_LC_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LCD_CAM_REG_H_ */

components/soc/esp32s3/include/soc/lcd_cam_struct.h

@@ -1,302 +1,798 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_LCD_CAM_STRUCT_H_
-#define _SOC_LCD_CAM_STRUCT_H_
-
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t lcd_clkcnt_n                  :    6;  /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
-            uint32_t lcd_clk_equ_sysclk            :    1;  /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
-            uint32_t lcd_ck_idle_edge              :    1;  /*1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle. */
-            uint32_t lcd_ck_out_edge               :    1;
-            uint32_t lcd_clkm_div_num              :    8;  /*Integral LCD clock divider value*/
-            uint32_t lcd_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
-            uint32_t lcd_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
-            uint32_t lcd_clk_sel                   :    2;  /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-        };
-        uint32_t val;
-    } lcd_clock;
-    union {
-        struct {
-            uint32_t cam_stop_en                   :    1;  /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
-            uint32_t cam_vsync_filter_thres        :    3;  /*Filter threshold value for CAM_VSYNC signal.*/
-            uint32_t cam_update                    :    1;  /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/
-            uint32_t cam_byte_order                :    1;  /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t cam_bit_order                 :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
-            uint32_t cam_line_int_en               :    1;  /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
-            uint32_t cam_vs_eof_en                 :    1;  /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
-            uint32_t cam_clkm_div_num              :    8;  /*Integral Camera clock divider value*/
-            uint32_t cam_clkm_div_b                :    6;  /*Fractional clock divider numerator value*/
-            uint32_t cam_clkm_div_a                :    6;  /*Fractional clock divider denominator value*/
-            uint32_t cam_clk_sel                   :    2;  /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } cam_ctrl;
-    union {
-        struct {
-            uint32_t cam_rec_data_bytelen          :    16;  /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
-            uint32_t cam_line_int_num              :    6;  /*The line number minus 1 to generate cam_hs_int.*/
-            uint32_t cam_clk_inv                   :    1;  /*1: Invert  the input signal CAM_PCLK. 0: Not invert.*/
-            uint32_t cam_vsync_filter_en           :    1;  /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
-            uint32_t cam_2byte_en                  :    1;  /*1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8. */
-            uint32_t cam_de_inv                    :    1;  /*CAM_DE invert enable signal, valid in high level.*/
-            uint32_t cam_hsync_inv                 :    1;  /*CAM_HSYNC invert enable signal, valid in high level.*/
-            uint32_t cam_vsync_inv                 :    1;  /*CAM_VSYNC invert enable signal, valid in high level.*/
-            uint32_t cam_vh_de_mode_en             :    1;  /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/
-            uint32_t cam_start                     :    1;  /*Camera module start signal.*/
-            uint32_t cam_reset                     :    1;  /*Camera module reset signal.*/
-            uint32_t cam_afifo_reset               :    1;  /*Camera AFIFO reset signal.*/
-        };
-        uint32_t val;
-    } cam_ctrl1;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;  /*reserved*/
-            uint32_t cam_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t cam_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
-            uint32_t cam_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
-            uint32_t cam_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
-            uint32_t cam_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t cam_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t cam_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t cam_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t cam_conv_bypass               :    1;  /*0: Bypass converter. 1: Enable converter.*/
-        };
-        uint32_t val;
-    } cam_rgb_yuv;
-    union {
-        struct {
-            uint32_t reserved0                     :    20;  /*reserved*/
-            uint32_t lcd_conv_8bits_data_inv       :    1;  /*1:invert every two 8bits input data. 2. disabled.*/
-            uint32_t lcd_conv_txtorx               :    1;  /*0: txtorx mode off. 1: txtorx mode on.*/
-            uint32_t lcd_conv_yuv2yuv_mode         :    2;  /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1. */
-            uint32_t lcd_conv_yuv_mode             :    2;  /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
-            uint32_t lcd_conv_protocol_mode        :    1;  /*0:BT601. 1:BT709.*/
-            uint32_t lcd_conv_data_out_mode        :    1;  /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
-            uint32_t lcd_conv_data_in_mode         :    1;  /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
-            uint32_t lcd_conv_mode_8bits_on        :    1;  /*0: 16bits mode. 1: 8bits mode.*/
-            uint32_t lcd_conv_trans_mode           :    1;  /*0: YUV to RGB. 1: RGB to YUV.*/
-            uint32_t lcd_conv_bypass               :    1;  /*0: Bypass converter. 1: Enable converter.*/
-        };
-        uint32_t val;
-    } lcd_rgb_yuv;
-    union {
-        struct {
-            uint32_t lcd_dout_cyclelen             :    13;  /*The output data cycles minus 1 of LCD module.*/
-            uint32_t lcd_always_out_en             :    1;  /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
-            uint32_t reserved14                    :    5;  /*reserved*/
-            uint32_t lcd_8bits_order               :    1;  /*1: invert every two data byte, valid in 1 byte mode. 0: Not change.*/
-            uint32_t lcd_update                    :    1;  /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/
-            uint32_t lcd_bit_order                 :    1;  /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.*/
-            uint32_t lcd_byte_order                :    1;  /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
-            uint32_t lcd_2byte_en                  :    1;  /*1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD data is 0~8. */
-            uint32_t lcd_dout                      :    1;  /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_dummy                     :    1;  /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_cmd                       :    1;  /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
-            uint32_t lcd_start                     :    1;  /*LCD start sending data enable signal, valid in high level.*/
-            uint32_t lcd_reset                     :    1;  /*The value of  command. */
-            uint32_t lcd_dummy_cyclelen            :    2;  /*The dummy cycle length minus 1.*/
-            uint32_t lcd_cmd_2_cycle_en            :    1;  /*The cycle length of command phase*/
-        };
-        uint32_t val;
-    } lcd_user;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*reserved*/
-            uint32_t lcd_afifo_threshold_num       :    5;  /*The awfull threshold number of lcd_afifo.*/
-            uint32_t lcd_vfk_cyclelen              :    6;  /*The setup cycle length minus 1 in LCD non-RGB mode.*/
-            uint32_t lcd_vbk_cyclelen              :    13;  /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/
-            uint32_t lcd_next_frame_en             :    1;  /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
-            uint32_t lcd_bk_en                     :    1;  /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
-            uint32_t lcd_afifo_reset               :    1;  /*LCD AFIFO reset signal.*/
-            uint32_t lcd_cd_data_set               :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_dummy_set              :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_cmd_set                :    1;  /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge. */
-            uint32_t lcd_cd_idle_edge              :    1;  /*The default value of LCD_CD. */
-        };
-        uint32_t val;
-    } lcd_misc;
-    union {
-        struct {
-            uint32_t lcd_hb_front                  :    11;  /*It is the horizontal blank front porch of a frame. */
-            uint32_t lcd_va_height                 :    10;  /*It is the vertical active height of a frame. */
-            uint32_t lcd_vt_height                 :    10;  /*It is the vertical total height of a frame. */
-            uint32_t lcd_rgb_mode_en               :    1;  /*1: Enable reg mode input vsync*/
-        };
-        uint32_t val;
-    } lcd_ctrl;
-    union {
-        struct {
-            uint32_t lcd_vb_front                  :    8;  /*It is the vertical blank front porch of a frame. */
-            uint32_t lcd_ha_width                  :    12;  /*It is the horizontal active width of a frame. */
-            uint32_t lcd_ht_width                  :    12;  /*It is the horizontal total width of a frame. */
-        };
-        uint32_t val;
-    } lcd_ctrl1;
-    union {
-        struct {
-            uint32_t lcd_vsync_width               :    7;  /*It is the position of LCD_VSYNC active pulse in a line. */
-            uint32_t lcd_vsync_idle_pol            :    1;  /*It is the idle value of LCD_VSYNC. */
-            uint32_t lcd_de_idle_pol               :    1;  /*It is the idle value of LCD_DE. */
-            uint32_t lcd_hs_blank_en               :    1;  /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */
-            uint32_t reserved10                    :    6;  /*reserved*/
-            uint32_t lcd_hsync_width               :    7;  /*It is the position of LCD_HSYNC active pulse in a line. */
-            uint32_t lcd_hsync_idle_pol            :    1;  /*It is the idle value of LCD_HSYNC. */
-            uint32_t lcd_hsync_position            :    8;  /*It is the position of LCD_HSYNC active pulse in a line. */
-        };
-        uint32_t val;
-    } lcd_ctrl2;
-    uint32_t lcd_cmd_val;
-    uint32_t reserved_2c;
-    union {
-        struct {
-            uint32_t lcd_cd_mode                   :    2;  /*The output LCD_CD is delayed by module clock LCD_CLK*/
-            uint32_t lcd_de_mode                   :    2;  /*The output LCD_DE is delayed by module clock LCD_CLK*/
-            uint32_t lcd_hsync_mode                :    2;  /*The output LCD_HSYNC is delayed by module clock LCD_CLK*/
-            uint32_t lcd_vsync_mode                :    2;  /*The output LCD_VSYNC is delayed by module clock LCD_CLK*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } lcd_dly_mode;
-    uint32_t reserved_34;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout1_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout2_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout3_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout4_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout5_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout6_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout7_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout8_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout9_mode                    :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout10_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout11_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout12_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout13_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout14_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-            uint32_t dout15_mode                   :    2;  /*The output data bit $n is delayed by module clock LCD_CLK*/
-        };
-        uint32_t val;
-    } lcd_data_dout_mode;
-    uint32_t reserved_3c;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The enable bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The enable bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The enable bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The enable bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } lc_dma_int_ena;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The raw bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The raw bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The raw bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The raw bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } lc_dma_int_raw;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The status bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The status bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The status bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The status bit for Camera transfer end interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } lc_dma_int_st;
-    union {
-        struct {
-            uint32_t lcd_vsync                     :    1;  /*The clear bit for LCD frame end interrupt.*/
-            uint32_t lcd_trans_done                :    1;  /*The clear bit for lcd transfer end interrupt.*/
-            uint32_t cam_vsync                     :    1;  /*The clear bit for Camera frame end interrupt.*/
-            uint32_t cam_hs                        :    1;  /*The clear bit for Camera line interrupt.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } lc_dma_int_clr;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    union {
-        struct {
-            uint32_t lc_date                       :    28;  /*LCD_CAM version control register*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } lc_date;
+/** Group: LCD Configuration Register */
+/** Type of lcd_clock register
+ *  LCD clock register
+ */
+typedef union {
+    struct {
+        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
+         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
+         */
+        uint32_t lcd_clkcnt_n: 6;
+        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
+         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
+         */
+        uint32_t lcd_clk_equ_sysclk: 1;
+        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
+         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
+         */
+        uint32_t lcd_ck_idle_edge: 1;
+        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
+         *  1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock
+         *  cycle.
+         */
+        uint32_t lcd_ck_out_edge: 1;
+        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral LCD clock divider value
+         */
+        uint32_t lcd_clkm_div_num: 8;
+        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t lcd_clkm_div_b: 6;
+        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t lcd_clkm_div_a: 6;
+        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t lcd_clk_sel: 2;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} lcd_cam_lcd_clock_reg_t;
+
+/** Type of lcd_rgb_yuv register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 20;
+        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t lcd_conv_8bits_data_inv: 1;
+        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
+         *  0: txtorx mode off. 1: txtorx mode on.
+         */
+        uint32_t lcd_conv_txtorx: 1;
+        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t lcd_conv_yuv2yuv_mode: 2;
+        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t lcd_conv_yuv_mode: 2;
+        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t lcd_conv_protocol_mode: 1;
+        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_out_mode: 1;
+        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t lcd_conv_data_in_mode: 1;
+        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t lcd_conv_mode_8bits_on: 1;
+        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t lcd_conv_trans_mode: 1;
+        /** lcd_conv_bypass : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t lcd_conv_bypass: 1;
+    };
+    uint32_t val;
+} lcd_cam_lcd_rgb_yuv_reg_t;
+
+/** Type of lcd_user register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
+         *  The output data cycles minus 1 of LCD module.
+         */
+        uint32_t lcd_dout_cyclelen: 13;
+        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
+         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
+         *  reg_lcd_reset is set.
+         */
+        uint32_t lcd_always_out_en: 1;
+        uint32_t reserved_14: 5;
+        /** lcd_8bits_order : R/W; bitpos: [19]; default: 0;
+         *  1: invert every two data byte, valid in 1 byte mode. 0: Not change.
+         */
+        uint32_t lcd_8bits_order: 1;
+        /** lcd_update_reg : R/W; bitpos: [20]; default: 0;
+         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t lcd_update: 1;
+        /** lcd_bit_order : R/W; bitpos: [21]; default: 0;
+         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t lcd_bit_order: 1;
+        /** lcd_byte_order : R/W; bitpos: [22]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t lcd_byte_order: 1;
+        /** lcd_2byte_en : R/W; bitpos: [23]; default: 0;
+         *  1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD data
+         *  is 0~8.
+         */
+        uint32_t lcd_2byte_en: 1;
+        /** lcd_dout : R/W; bitpos: [24]; default: 0;
+         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dout: 1;
+        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
+         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_dummy: 1;
+        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
+         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
+         */
+        uint32_t lcd_cmd: 1;
+        /** lcd_start : R/W; bitpos: [27]; default: 0;
+         *  LCD start sending data enable signal, valid in high level.
+         */
+        uint32_t lcd_start: 1;
+        /** lcd_reset : WO; bitpos: [28]; default: 0;
+         *  The value of  command.
+         */
+        uint32_t lcd_reset: 1;
+        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
+         *  The dummy cycle length minus 1.
+         */
+        uint32_t lcd_dummy_cyclelen: 2;
+        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
+         *  The cycle length of command phase.  1: 2 cycles. 0: 1 cycle.
+         */
+        uint32_t lcd_cmd_2_cycle_en: 1;
+    };
+    uint32_t val;
+} lcd_cam_lcd_user_reg_t;
+
+/** Type of lcd_misc register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 1;
+        /** lcd_afifo_threshold_num : R/W; bitpos: [5:1]; default: 11;
+         *  The awfull threshold number of lcd_afifo.
+         */
+        uint32_t lcd_afifo_threshold_num: 5;
+        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
+         *  The setup cycle length minus 1 in LCD non-RGB mode.
+         */
+        uint32_t lcd_vfk_cyclelen: 6;
+        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
+         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
+         *  time cycle length in LCD non-RGB mode.
+         */
+        uint32_t lcd_vbk_cyclelen: 13;
+        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
+         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
+         *  the current frame is sent out.
+         */
+        uint32_t lcd_next_frame_en: 1;
+        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
+         *  1: Enable blank region when LCD sends data out. 0: No blank region.
+         */
+        uint32_t lcd_bk_en: 1;
+        /** lcd_afifo_reset : WO; bitpos: [27]; default: 0;
+         *  LCD AFIFO reset signal.
+         */
+        uint32_t lcd_afifo_reset: 1;
+        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_data_set: 1;
+        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_dummy_set: 1;
+        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
+         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
+         *  reg_cd_idle_edge.
+         */
+        uint32_t lcd_cd_cmd_set: 1;
+        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
+         *  The default value of LCD_CD.
+         */
+        uint32_t lcd_cd_idle_edge: 1;
+    };
+    uint32_t val;
+} lcd_cam_lcd_misc_reg_t;
+
+/** Type of lcd_ctrl register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
+         *  It is the horizontal blank front porch of a frame.
+         */
+        uint32_t lcd_hb_front: 11;
+        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
+         *  It is the vertical active height of a frame.
+         */
+        uint32_t lcd_va_height: 10;
+        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
+         *  It is the vertical total height of a frame.
+         */
+        uint32_t lcd_vt_height: 10;
+        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
+         *  1: Enable reg mode input vsync, hsync, de. 0: Disable.
+         */
+        uint32_t lcd_rgb_mode_en: 1;
+    };
+    uint32_t val;
+} lcd_cam_lcd_ctrl_reg_t;
+
+/** Type of lcd_ctrl1 register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
+         *  It is the vertical blank front porch of a frame.
+         */
+        uint32_t lcd_vb_front: 8;
+        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
+         *  It is the horizontal active width of a frame.
+         */
+        uint32_t lcd_ha_width: 12;
+        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
+         *  It is the horizontal total width of a frame.
+         */
+        uint32_t lcd_ht_width: 12;
+    };
+    uint32_t val;
+} lcd_cam_lcd_ctrl1_reg_t;
+
+/** Type of lcd_ctrl2 register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
+         *  It is the position of LCD_VSYNC active pulse in a line.
+         */
+        uint32_t lcd_vsync_width: 7;
+        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
+         *  It is the idle value of LCD_VSYNC.
+         */
+        uint32_t lcd_vsync_idle_pol: 1;
+        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
+         *  It is the idle value of LCD_DE.
+         */
+        uint32_t lcd_de_idle_pol: 1;
+        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
+         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
+         *  pulse is valid only in active region lines in RGB mode.
+         */
+        uint32_t lcd_hs_blank_en: 1;
+        uint32_t reserved_10: 6;
+        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_width: 7;
+        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
+         *  It is the idle value of LCD_HSYNC.
+         */
+        uint32_t lcd_hsync_idle_pol: 1;
+        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
+         *  It is the position of LCD_HSYNC active pulse in a line.
+         */
+        uint32_t lcd_hsync_position: 8;
+    };
+    uint32_t val;
+} lcd_cam_lcd_ctrl2_reg_t;
+
+/** Type of lcd_cmd_val register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_cmd_value : R/W; bitpos: [31:0]; default: 0;
+         *  The LCD write command value.
+         */
+        uint32_t lcd_cmd_value: 32;
+    };
+    uint32_t val;
+} lcd_cam_lcd_cmd_val_reg_t;
+
+/** Type of lcd_dly_mode register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** lcd_cd_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_cd_mode: 2;
+        /** lcd_de_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
+         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_de_mode: 2;
+        /** lcd_hsync_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_hsync_mode: 2;
+        /** lcd_vsync_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
+         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
+         */
+        uint32_t lcd_vsync_mode: 2;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} lcd_cam_lcd_dly_mode_reg_t;
+
+/** Type of lcd_data_dout_mode register
+ *  LCD configuration register
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout0_mode: 2;
+        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout1_mode: 2;
+        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout2_mode: 2;
+        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout3_mode: 2;
+        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout4_mode: 2;
+        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout5_mode: 2;
+        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout6_mode: 2;
+        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout7_mode: 2;
+        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout8_mode: 2;
+        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout9_mode: 2;
+        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout10_mode: 2;
+        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout11_mode: 2;
+        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout12_mode: 2;
+        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout13_mode: 2;
+        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout14_mode: 2;
+        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
+         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
+         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
+         *  LCD_CLK.
+         */
+        uint32_t dout15_mode: 2;
+    };
+    uint32_t val;
+} lcd_cam_lcd_data_dout_mode_reg_t;
+
+
+/** Group: Camera Configuration Register */
+/** Type of cam_ctrl register
+ *  Camera configuration register
+ */
+typedef union {
+    struct {
+        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
+         */
+        uint32_t cam_stop_en: 1;
+        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
+         *  Filter threshold value for CAM_VSYNC signal.
+         */
+        uint32_t cam_vsync_filter_thres: 3;
+        /** cam_update_reg : R/W; bitpos: [4]; default: 0;
+         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
+         */
+        uint32_t cam_update: 1;
+        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         */
+        uint32_t cam_byte_order: 1;
+        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
+         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         */
+        uint32_t cam_bit_order: 1;
+        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
+         *  1: Enable to generate CAM_HS_INT. 0: Disable.
+         */
+        uint32_t cam_line_int_en: 1;
+        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
+         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
+         *  reg_cam_rec_data_cyclelen.
+         */
+        uint32_t cam_vs_eof_en: 1;
+        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
+         *  Integral Camera clock divider value
+         */
+        uint32_t cam_clkm_div_num: 8;
+        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
+         *  Fractional clock divider numerator value
+         */
+        uint32_t cam_clkm_div_b: 6;
+        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
+         *  Fractional clock divider denominator value
+         */
+        uint32_t cam_clkm_div_a: 6;
+        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
+         */
+        uint32_t cam_clk_sel: 2;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} lcd_cam_cam_ctrl_reg_t;
+
+/** Type of cam_ctrl1 register
+ *  Camera configuration register
+ */
+typedef union {
+    struct {
+        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
+         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
+         */
+        uint32_t cam_rec_data_bytelen: 16;
+        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
+         *  The line number minus 1 to generate cam_hs_int.
+         */
+        uint32_t cam_line_int_num: 6;
+        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
+         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
+         */
+        uint32_t cam_clk_inv: 1;
+        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
+         *  1: Enable CAM_VSYNC filter function. 0: bypass.
+         */
+        uint32_t cam_vsync_filter_en: 1;
+        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
+         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
+         */
+        uint32_t cam_2byte_en: 1;
+        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
+         *  CAM_DE invert enable signal, valid in high level.
+         */
+        uint32_t cam_de_inv: 1;
+        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
+         *  CAM_HSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_hsync_inv: 1;
+        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
+         *  CAM_VSYNC invert enable signal, valid in high level.
+         */
+        uint32_t cam_vsync_inv: 1;
+        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
+         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control
+         *  signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time.
+         */
+        uint32_t cam_vh_de_mode_en: 1;
+        /** cam_start : R/W; bitpos: [29]; default: 0;
+         *  Camera module start signal.
+         */
+        uint32_t cam_start: 1;
+        /** cam_reset : WO; bitpos: [30]; default: 0;
+         *  Camera module reset signal.
+         */
+        uint32_t cam_reset: 1;
+        /** cam_afifo_reset : WO; bitpos: [31]; default: 0;
+         *  Camera AFIFO reset signal.
+         */
+        uint32_t cam_afifo_reset: 1;
+    };
+    uint32_t val;
+} lcd_cam_cam_ctrl1_reg_t;
+
+/** Type of cam_rgb_yuv register
+ *  Camera configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 21;
+        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
+         *  1:invert every two 8bits input data. 2. disabled.
+         */
+        uint32_t cam_conv_8bits_data_inv: 1;
+        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
+         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
+         *  trans_mode must be set to 1.
+         */
+        uint32_t cam_conv_yuv2yuv_mode: 2;
+        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
+         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
+         *  mode of Data_in
+         */
+        uint32_t cam_conv_yuv_mode: 2;
+        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
+         *  0:BT601. 1:BT709.
+         */
+        uint32_t cam_conv_protocol_mode: 1;
+        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
+         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_out_mode: 1;
+        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
+         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
+         */
+        uint32_t cam_conv_data_in_mode: 1;
+        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
+         *  0: 16bits mode. 1: 8bits mode.
+         */
+        uint32_t cam_conv_mode_8bits_on: 1;
+        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
+         *  0: YUV to RGB. 1: RGB to YUV.
+         */
+        uint32_t cam_conv_trans_mode: 1;
+        /** cam_conv_bypass : R/W; bitpos: [31]; default: 0;
+         *  0: Bypass converter. 1: Enable converter.
+         */
+        uint32_t cam_conv_bypass: 1;
+    };
+    uint32_t val;
+} lcd_cam_cam_rgb_yuv_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of lc_dma_int_ena register
+ *  LCD_camera DMA inturrupt enable register
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_ena: 1;
+        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_ena: 1;
+        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_ena: 1;
+        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_ena: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} lcd_cam_lc_dma_int_ena_reg_t;
+
+/** Type of lc_dma_int_raw register
+ *  LCD_camera DMA raw inturrupt status register
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_raw : RO; bitpos: [0]; default: 0;
+         *  The raw bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_raw: 1;
+        /** lcd_trans_done_int_raw : RO; bitpos: [1]; default: 0;
+         *  The raw bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_raw: 1;
+        /** cam_vsync_int_raw : RO; bitpos: [2]; default: 0;
+         *  The raw bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_raw: 1;
+        /** cam_hs_int_raw : RO; bitpos: [3]; default: 0;
+         *  The raw bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_raw: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} lcd_cam_lc_dma_int_raw_reg_t;
+
+/** Type of lc_dma_int_st register
+ *  LCD_camera DMA masked inturrupt status register
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_st: 1;
+        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_st: 1;
+        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_st: 1;
+        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for Camera transfer end interrupt.
+         */
+        uint32_t cam_hs_int_st: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} lcd_cam_lc_dma_int_st_reg_t;
+
+/** Type of lc_dma_int_clr register
+ *  LCD_camera DMA inturrupt clear register
+ */
+typedef union {
+    struct {
+        /** lcd_vsync_int_clr : WO; bitpos: [0]; default: 0;
+         *  The clear bit for LCD frame end interrupt.
+         */
+        uint32_t lcd_vsync_int_clr: 1;
+        /** lcd_trans_done_int_clr : WO; bitpos: [1]; default: 0;
+         *  The clear bit for lcd transfer end interrupt.
+         */
+        uint32_t lcd_trans_done_int_clr: 1;
+        /** cam_vsync_int_clr : WO; bitpos: [2]; default: 0;
+         *  The clear bit for Camera frame end interrupt.
+         */
+        uint32_t cam_vsync_int_clr: 1;
+        /** cam_hs_int_clr : WO; bitpos: [3]; default: 0;
+         *  The clear bit for Camera line interrupt.
+         */
+        uint32_t cam_hs_int_clr: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} lcd_cam_lc_dma_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of lc_reg_date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** lc_date : R/W; bitpos: [27:0]; default: 33566752;
+         *  LCD_CAM version control register
+         */
+        uint32_t lc_date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} lcd_cam_lc_reg_date_reg_t;
+
+
+typedef struct {
+    volatile lcd_cam_lcd_clock_reg_t lcd_clock;
+    volatile lcd_cam_cam_ctrl_reg_t cam_ctrl;
+    volatile lcd_cam_cam_ctrl1_reg_t cam_ctrl1;
+    volatile lcd_cam_cam_rgb_yuv_reg_t cam_rgb_yuv;
+    volatile lcd_cam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
+    volatile lcd_cam_lcd_user_reg_t lcd_user;
+    volatile lcd_cam_lcd_misc_reg_t lcd_misc;
+    volatile lcd_cam_lcd_ctrl_reg_t lcd_ctrl;
+    volatile lcd_cam_lcd_ctrl1_reg_t lcd_ctrl1;
+    volatile lcd_cam_lcd_ctrl2_reg_t lcd_ctrl2;
+    volatile lcd_cam_lcd_cmd_val_reg_t lcd_cmd_val;
+    uint32_t reserved_02c;
+    volatile lcd_cam_lcd_dly_mode_reg_t lcd_dly_mode;
+    uint32_t reserved_034;
+    volatile lcd_cam_lcd_data_dout_mode_reg_t lcd_data_dout_mode;
+    uint32_t reserved_03c[10];
+    volatile lcd_cam_lc_dma_int_ena_reg_t lc_dma_int_ena;
+    volatile lcd_cam_lc_dma_int_raw_reg_t lc_dma_int_raw;
+    volatile lcd_cam_lc_dma_int_st_reg_t lc_dma_int_st;
+    volatile lcd_cam_lc_dma_int_clr_reg_t lc_dma_int_clr;
+    uint32_t reserved_074[34];
+    volatile lcd_cam_lc_reg_date_reg_t lc_reg_date;
 } lcd_cam_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcd_cam_dev_t structure");
+#endif
+
 extern lcd_cam_dev_t LCD_CAM;
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LCD_CAM_STRUCT_H_ */