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@@ -0,0 +1,692 @@
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+/*
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+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+
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+// #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
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+
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+/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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+// Although we're manipulating I2S peripheral (on esp32/s2 target), it has nothing to do with the AUDIO BUS.
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+// In fact, we're simulating the Intel 8080 bus with I2S peripheral, in a special parallel mode.
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+/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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+
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+#include <stdlib.h>
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+#include <string.h>
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+#include <sys/cdefs.h>
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+#include <sys/param.h>
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+#include <sys/queue.h>
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+#include "freertos/FreeRTOS.h"
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+#include "freertos/task.h"
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+#include "freertos/queue.h"
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+#include "esp_attr.h"
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+#include "esp_check.h"
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+#include "esp_intr_alloc.h"
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+#include "esp_heap_caps.h"
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+#include "esp_lcd_panel_io_interface.h"
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+#include "esp_lcd_panel_io.h"
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+#include "esp_lcd_common.h"
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+#include "esp_rom_gpio.h"
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+#include "soc/soc_caps.h"
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+#include "hal/dma_types.h"
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+#include "hal/gpio_hal.h"
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+#include "driver/gpio.h"
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+#include "driver/periph_ctrl.h"
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+#if SOC_I2S_LCD_I80_VARIANT
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+#include "esp_private/i2s_platform.h"
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+#include "soc/lcd_periph.h"
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+#include "hal/i2s_hal.h"
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+#include "hal/i2s_ll.h"
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+#include "hal/i2s_types.h"
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+
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+static const char *TAG = "lcd_panel.io.i80";
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+
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+typedef struct esp_lcd_i80_bus_t esp_lcd_i80_bus_t;
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+typedef struct lcd_panel_io_i80_t lcd_panel_io_i80_t;
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+typedef struct lcd_i80_trans_descriptor_t lcd_i80_trans_descriptor_t;
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+
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+static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, const void *param, size_t param_size);
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+static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, const void *color, size_t color_size);
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+static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io);
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+static unsigned long i2s_lcd_select_periph_clock(i2s_hal_context_t *hal);
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+static esp_err_t i2s_lcd_init_dma_link(esp_lcd_i80_bus_handle_t bus);
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+static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config);
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+static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus);
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+static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device);
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+static IRAM_ATTR void lcd_default_isr_handler(void *args);
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+
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+struct esp_lcd_i80_bus_t {
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+ int bus_id; // Bus ID, index from 0
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+ portMUX_TYPE spinlock; // spinlock used to protect i80 bus members(hal, device_list, cur_trans)
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+ i2s_hal_context_t hal; // Hal object
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+ size_t bus_width; // Number of data lines
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+ int dc_gpio_num; // GPIO used for DC line
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+ int wr_gpio_num; // GPIO used for WR line
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+ intr_handle_t intr; // LCD peripheral interrupt handle
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+ size_t num_dma_nodes; // Number of DMA descriptors
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+ uint8_t *format_buffer;// The driver allocates an internal buffer for DMA to do data format transformer
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+ size_t resolution_hz; // LCD_CLK resolution, determined by selected clock source
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+ lcd_i80_trans_descriptor_t *cur_trans; // Current transaction
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+ lcd_panel_io_i80_t *cur_device; // Current working device
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+ LIST_HEAD(i80_device_list, lcd_panel_io_i80_t) device_list; // Head of i80 device list
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+ dma_descriptor_t dma_nodes[]; // DMA descriptor pool, the descriptors are shared by all i80 devices
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+};
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+
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+struct lcd_i80_trans_descriptor_t {
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+ lcd_panel_io_i80_t *i80_device; // i80 device issuing this transaction
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+ const void *data; // Data buffer
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+ uint32_t data_length; // Data buffer size
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+ void *cb_user_data; // private data used by trans_done_cb
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+ bool (*trans_done_cb)(esp_lcd_panel_io_handle_t panel_io, void *user_data, void *event_data); // transaction done callback
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+ struct {
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+ unsigned int dc_level: 1; // Level of DC line for this transaction
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+ } flags;
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+};
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+
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+struct lcd_panel_io_i80_t {
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+ esp_lcd_panel_io_t base; // Base class of generic lcd panel io
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+ esp_lcd_i80_bus_t *bus; // Which bus the device is attached to
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+ int cs_gpio_num; // GPIO used for CS line
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+ unsigned int pclk_hz; // PCLK clock frequency
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+ size_t clock_prescale; // Prescaler coefficient, determined by user's configured PCLK frequency
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+ QueueHandle_t trans_queue; // Transaction queue, transactions in this queue are pending for scheduler to dispatch
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+ QueueHandle_t done_queue; // Transaction done queue, transactions in this queue are finished but not recycled by the caller
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+ size_t queue_size; // Size of transaction queue
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+ size_t num_trans_inflight; // Number of transactions that are undergoing (the descriptor not recycled yet)
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+ int lcd_cmd_bits; // Bit width of LCD command
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+ int lcd_param_bits; // Bit width of LCD parameter
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+ void *cb_user_data; // private data used when transfer color data
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+ bool (*on_color_trans_done)(esp_lcd_panel_io_handle_t panel_io, void *user_data, void *event_data); // color data trans done callback
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+ LIST_ENTRY(lcd_panel_io_i80_t) device_list_entry; // Entry of i80 device list
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+ struct {
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+ unsigned int dc_cmd_level: 1; // Level of DC line in CMD phase
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+ unsigned int dc_data_level: 1; // Level of DC line in DATA phase
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+ } dc_levels;
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+ struct {
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+ unsigned int cs_active_high: 1; // Whether the CS line is active on high level
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+ unsigned int swap_color_bytes: 1; // Swap adjacent two data bytes before sending out
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+ unsigned int pclk_idle_low: 1; // The WR line keeps at low level in IDLE phase
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+ } flags;
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+ lcd_i80_trans_descriptor_t trans_pool[]; // Transaction pool
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+};
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+
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+esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lcd_i80_bus_handle_t *ret_bus)
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+{
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+ esp_err_t ret = ESP_OK;
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+ esp_lcd_i80_bus_t *bus = NULL;
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+ ESP_GOTO_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, err_arg, TAG, "invalid argument");
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+ // although I2S bus supports up to 24 parallel data lines, we restrict users to only use 8 or 16 bit width, due to limited GPIO numbers
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+ ESP_GOTO_ON_FALSE(bus_config->bus_width == 8 || bus_config->bus_width == 16, ESP_ERR_INVALID_ARG, err_arg,
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+ TAG, "invalid bus width:%d", bus_config->bus_width);
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+ size_t max_transfer_bytes = (bus_config->max_transfer_bytes + 3) & ~0x03; // align up to 4 bytes
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+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
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+ // double the size of the internal DMA buffer if bus_width is 8,
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+ // because one I2S FIFO (4 bytes) will only contain two bytes of valid data
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+ max_transfer_bytes = max_transfer_bytes * 16 / bus_config->bus_width + 4;
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+#endif
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+ size_t num_dma_nodes = max_transfer_bytes / DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1;
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+ // DMA descriptors must be placed in internal SRAM
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+ bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t) + num_dma_nodes * sizeof(dma_descriptor_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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+ ESP_GOTO_ON_FALSE(bus, ESP_ERR_NO_MEM, no_mem_bus, TAG, "no mem for i80 bus");
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+ bus->num_dma_nodes = num_dma_nodes;
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+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
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+ // transform format for LCD commands, parameters and color data, so we need a big buffer
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+ bus->format_buffer = heap_caps_calloc(1, max_transfer_bytes, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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+#else
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+ // only transform format for LCD parameters, buffer size depends on specific LCD, set at compile time
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+ bus->format_buffer = heap_caps_calloc(1, CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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+#endif
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+ ESP_GOTO_ON_FALSE(bus->format_buffer, ESP_ERR_NO_MEM, no_mem_format, TAG, "no mem for format buffer");
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+ // I2S0 has the LCD mode, but the LCD mode can't work with other modes at the same time, we need to register the driver object to the I2S platform
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+ ESP_GOTO_ON_ERROR(i2s_priv_register_object(bus, 0), no_slot, TAG, "register to I2S platform failed");
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+ bus->bus_id = 0;
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+ // initialize HAL layer
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+ i2s_hal_init(&bus->hal, bus->bus_id);
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+ // set peripheral clock resolution
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+ bus->resolution_hz = i2s_lcd_select_periph_clock(&bus->hal);
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+ // reset peripheral, DMA channel and FIFO
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+ i2s_ll_tx_reset(bus->hal.dev);
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+ i2s_ll_tx_reset_dma(bus->hal.dev);
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+ i2s_ll_tx_reset_fifo(bus->hal.dev);
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+ // install interrupt service, (I2S LCD mode only uses the "TX Unit", which leaves "RX Unit" for other purpose)
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+ // So the interrupt should also be able to share with other functionality
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+ int isr_flags = ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED;
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+ ret = esp_intr_alloc_intrstatus(lcd_periph_signals.buses[bus->bus_id].irq_id, isr_flags,
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+ (uint32_t)i2s_ll_get_intr_status_reg(bus->hal.dev),
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+ I2S_LL_EVENT_TX_EOF, lcd_default_isr_handler, bus, &bus->intr);
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+ ESP_GOTO_ON_ERROR(ret, no_int, TAG, "install interrupt failed");
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+ i2s_ll_enable_intr(bus->hal.dev, I2S_LL_EVENT_TX_EOF, false); // disable interrupt temporarily
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+ i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF); // clear pending interrupt
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+ // initialize DMA link
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+ i2s_lcd_init_dma_link(bus);
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+ // enable I2S LCD master mode (refer to I2S TRM)
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+ i2s_ll_enable_lcd(bus->hal.dev, true);
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+ i2s_ll_tx_stop_on_fifo_empty(bus->hal.dev, true);
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+ i2s_ll_tx_bypass_pcm(bus->hal.dev, true);
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+ i2s_ll_tx_set_slave_mod(bus->hal.dev, false);
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+ i2s_ll_tx_set_bits_mod(bus->hal.dev, bus_config->bus_width);
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+ i2s_ll_tx_set_chan_mod(bus->hal.dev, 1); // mono
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+ bus->bus_width = bus_config->bus_width;
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+ i2s_ll_tx_enable_right_first(bus->hal.dev, true);
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+#if SOC_I2S_SUPPORTS_DMA_EQUAL
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+ i2s_ll_tx_enable_dma_equal(bus->hal.dev, true);
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+#endif
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+ // enable trans done interrupt
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+ i2s_ll_enable_intr(bus->hal.dev, I2S_LL_EVENT_TX_EOF, true);
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+ // trigger a quick "trans done" event, and wait for the interrupt line goes active
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+ // this could ensure we go into ISR handler next time we call `esp_intr_enable`
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+ i2s_lcd_trigger_quick_trans_done_event(bus);
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+ // configure GPIO
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+ ret = i2s_lcd_configure_gpio(bus, bus_config);
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+ ESP_GOTO_ON_ERROR(ret, invalid_gpio, TAG, "configure GPIO failed");
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+ // fill other i80 bus runtime parameters
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+ LIST_INIT(&bus->device_list); // initialize device list head
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+ bus->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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+ bus->dc_gpio_num = bus_config->dc_gpio_num;
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+ bus->wr_gpio_num = bus_config->wr_gpio_num;
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+ *ret_bus = bus;
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+ ESP_LOGD(TAG, "new i80 bus(%d) @%p, %zu dma nodes, resolution %zuHz", bus->bus_id, bus, bus->num_dma_nodes, bus->resolution_hz);
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+ return ESP_OK;
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+
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+invalid_gpio:
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+ esp_intr_free(bus->intr);
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+no_int:
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+ i2s_priv_deregister_object(bus->bus_id);
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+no_slot:
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+ free(bus->format_buffer);
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+no_mem_format:
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+ free(bus);
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+no_mem_bus:
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+err_arg:
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+ return ret;
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+}
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+
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+esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus)
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+{
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+ esp_err_t ret = ESP_OK;
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+ ESP_GOTO_ON_FALSE(bus, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
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+ ESP_GOTO_ON_FALSE(LIST_EMPTY(&bus->device_list), ESP_ERR_INVALID_STATE, err, TAG, "device list not empty");
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+ int bus_id = bus->bus_id;
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+ esp_intr_free(bus->intr);
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+ i2s_priv_deregister_object(bus_id);
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+ free(bus->format_buffer);
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+ free(bus);
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+ ESP_LOGD(TAG, "del i80 bus(%d)", bus_id);
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+err:
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+ return ret;
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+}
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+
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+esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_panel_io_i80_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io)
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+{
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+ esp_err_t ret = ESP_OK;
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+ lcd_panel_io_i80_t *i80_device = NULL;
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+ ESP_GOTO_ON_FALSE(bus && io_config && ret_io, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
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+ // because we set the I2S's left channel data same to right channel, so f_pclk = f_i2s/pclk_div/2
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+ uint32_t pclk_prescale = bus->resolution_hz / 2 / io_config->pclk_hz;
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+ ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= I2S_LL_BCK_MAX_PRESCALE, ESP_ERR_NOT_SUPPORTED, err, TAG,
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+ "prescaler can't satisfy PCLK clock %u", io_config->pclk_hz);
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+ i80_device = calloc(1, sizeof(lcd_panel_io_i80_t) + io_config->trans_queue_depth * sizeof(lcd_i80_trans_descriptor_t));
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+ ESP_GOTO_ON_FALSE(i80_device, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 panel io");
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+ // create two queues for i80 device
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+ i80_device->trans_queue = xQueueCreate(io_config->trans_queue_depth, sizeof(lcd_i80_trans_descriptor_t *));
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+ ESP_GOTO_ON_FALSE(i80_device->trans_queue, ESP_ERR_NO_MEM, err, TAG, "create trans queue failed");
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+ i80_device->done_queue = xQueueCreate(io_config->trans_queue_depth, sizeof(lcd_i80_trans_descriptor_t *));
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+ ESP_GOTO_ON_FALSE(i80_device->done_queue, ESP_ERR_NO_MEM, err, TAG, "create done queue failed");
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+ // adding device to list
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+ portENTER_CRITICAL(&bus->spinlock);
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+ LIST_INSERT_HEAD(&bus->device_list, i80_device, device_list_entry);
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+ portEXIT_CRITICAL(&bus->spinlock);
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+ // we don't initialize the i80 bus at the memont, but initialize the bus when start a transaction for a new device
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+ // so save these as i80 device runtime parameters
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+ i80_device->bus = bus;
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+ i80_device->queue_size = io_config->trans_queue_depth;
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+ i80_device->clock_prescale = pclk_prescale;
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+ i80_device->lcd_cmd_bits = io_config->lcd_cmd_bits;
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+ i80_device->lcd_param_bits = io_config->lcd_param_bits;
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+ i80_device->pclk_hz = bus->resolution_hz / pclk_prescale / 2;
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+ i80_device->dc_levels.dc_cmd_level = io_config->dc_levels.dc_cmd_level;
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+ i80_device->dc_levels.dc_data_level = io_config->dc_levels.dc_data_level;
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+ i80_device->cs_gpio_num = io_config->cs_gpio_num;
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+ i80_device->on_color_trans_done = io_config->on_color_trans_done;
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+ i80_device->cb_user_data = io_config->user_data;
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+ i80_device->flags.cs_active_high = io_config->flags.cs_active_high;
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+ i80_device->flags.swap_color_bytes = io_config->flags.swap_color_bytes;
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+ i80_device->flags.pclk_idle_low = io_config->flags.pclk_idle_low;
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+ // fill panel io function table
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+ i80_device->base.del = panel_io_i80_del;
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+ i80_device->base.tx_param = panel_io_i80_tx_param;
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+ i80_device->base.tx_color = panel_io_i80_tx_color;
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+ // CS signal is controlled by software
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+ gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default
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+ gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT);
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+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO);
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+ *ret_io = &(i80_device->base);
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+ ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%uHz", i80_device, bus->bus_id, i80_device->pclk_hz);
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+ return ESP_OK;
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+
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+err:
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+ if (i80_device) {
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+ if (i80_device->trans_queue) {
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+ vQueueDelete(i80_device->trans_queue);
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+ }
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+ if (i80_device->done_queue) {
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+ vQueueDelete(i80_device->done_queue);
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+ }
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+ free(i80_device);
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+ }
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+ return ret;
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+}
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+
|
|
|
+static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io)
|
|
|
+{
|
|
|
+ lcd_panel_io_i80_t *i80_device = __containerof(io, lcd_panel_io_i80_t, base);
|
|
|
+ esp_lcd_i80_bus_t *bus = i80_device->bus;
|
|
|
+ lcd_i80_trans_descriptor_t *trans_desc = NULL;
|
|
|
+ // wait all pending transaction to finish
|
|
|
+ for (size_t i = 0; i < i80_device->num_trans_inflight; i++) {
|
|
|
+ xQueueReceive(i80_device->done_queue, &trans_desc, portMAX_DELAY);
|
|
|
+ }
|
|
|
+ // remove from device list
|
|
|
+ portENTER_CRITICAL(&bus->spinlock);
|
|
|
+ LIST_REMOVE(i80_device, device_list_entry);
|
|
|
+ portEXIT_CRITICAL(&bus->spinlock);
|
|
|
+
|
|
|
+ ESP_LOGD(TAG, "del i80 lcd panel io @%p", i80_device);
|
|
|
+ vQueueDelete(i80_device->trans_queue);
|
|
|
+ vQueueDelete(i80_device->done_queue);
|
|
|
+ free(i80_device);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static void i2s_lcd_prepare_cmd_buffer(lcd_i80_trans_descriptor_t *trans_desc, const void *cmd)
|
|
|
+{
|
|
|
+ lcd_panel_io_i80_t *i80_device = trans_desc->i80_device;
|
|
|
+ esp_lcd_i80_bus_t *bus = i80_device->bus;
|
|
|
+ uint8_t *from = (uint8_t *)cmd;
|
|
|
+ // LCD is big-endian, e.g. to send command 0x1234, byte 0x12 should appear on the data bus first
|
|
|
+ // However, the I2S peripheral will send 0x34 first, so we reversed the order below
|
|
|
+ if (bus->bus_width < i80_device->lcd_cmd_bits) {
|
|
|
+ int start = 0;
|
|
|
+ int end = i80_device->lcd_cmd_bits / 8 - 1;
|
|
|
+ lcd_com_reverse_buffer_bytes(from, start, end);
|
|
|
+ }
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ uint8_t *to = bus->format_buffer;
|
|
|
+ int cmd_cycle = i80_device->lcd_cmd_bits / bus->bus_width;
|
|
|
+ if (cmd_cycle * bus->bus_width < i80_device->lcd_cmd_bits) {
|
|
|
+ cmd_cycle++;
|
|
|
+ }
|
|
|
+ int bytes_to_copy = MIN(bus->bus_width, i80_device->lcd_cmd_bits) / 8;
|
|
|
+ int cnt_from = 0;
|
|
|
+ // format command buffer
|
|
|
+ for (int i = 0; i < cmd_cycle; i++) {
|
|
|
+ for (int j = 0; j < bytes_to_copy; j++) {
|
|
|
+ to[2 + j] = from[cnt_from++];
|
|
|
+ }
|
|
|
+ to += 4;
|
|
|
+ }
|
|
|
+ trans_desc->data = bus->format_buffer;
|
|
|
+ trans_desc->data_length = cmd_cycle * 4;
|
|
|
+#else
|
|
|
+ trans_desc->data = cmd;
|
|
|
+ trans_desc->data_length = MAX(i80_device->lcd_cmd_bits, bus->bus_width) / 8;
|
|
|
+#endif
|
|
|
+}
|
|
|
+
|
|
|
+static void i2s_lcd_prepare_param_buffer(lcd_i80_trans_descriptor_t *trans_desc, const void *param, size_t param_num)
|
|
|
+{
|
|
|
+ lcd_panel_io_i80_t *i80_device = trans_desc->i80_device;
|
|
|
+ esp_lcd_i80_bus_t *bus = i80_device->bus;
|
|
|
+ uint8_t *from = (uint8_t *)param;
|
|
|
+ int param_size = i80_device->lcd_param_bits / 8;
|
|
|
+ // LCD is big-endian, e.g. to send param 0x1234, byte 0x12 should appear on the data bus first
|
|
|
+ // However, the I2S peripheral will send 0x34 first, so we reversed the order below
|
|
|
+ if (bus->bus_width < i80_device->lcd_param_bits) {
|
|
|
+ for (size_t i = 0; i < param_num; i++) {
|
|
|
+ int start = i * param_size;
|
|
|
+ int end = start + param_size - 1;
|
|
|
+ lcd_com_reverse_buffer_bytes(from, start, end);
|
|
|
+ }
|
|
|
+ }
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ uint8_t *to = bus->format_buffer;
|
|
|
+ int param_cycle = i80_device->lcd_param_bits / bus->bus_width;
|
|
|
+ if (param_cycle * bus->bus_width < i80_device->lcd_param_bits) {
|
|
|
+ param_cycle++;
|
|
|
+ }
|
|
|
+ int ele_cycles = param_cycle * param_num;
|
|
|
+ int bytes_to_copy = MIN(bus->bus_width, i80_device->lcd_param_bits) / 8;
|
|
|
+ int cnt_from = 0;
|
|
|
+ // format parameter buffer
|
|
|
+ for (int i = 0; i < ele_cycles; i++) {
|
|
|
+ for (int j = 0; j < bytes_to_copy; j++) {
|
|
|
+ to[2 + j] = from[cnt_from++];
|
|
|
+ }
|
|
|
+ to += 4;
|
|
|
+ }
|
|
|
+ trans_desc->data = bus->format_buffer;
|
|
|
+ trans_desc->data_length = ele_cycles * 4;
|
|
|
+#else
|
|
|
+ uint8_t *to = bus->format_buffer;
|
|
|
+ uint8_t step = bus->bus_width / 8;
|
|
|
+ int param_cycle = i80_device->lcd_param_bits / bus->bus_width;
|
|
|
+ if (param_cycle * bus->bus_width < i80_device->lcd_param_bits) {
|
|
|
+ param_cycle++;
|
|
|
+ }
|
|
|
+ int ele_cycles = param_cycle * param_num;
|
|
|
+ int bytes_to_copy = MIN(bus->bus_width, i80_device->lcd_param_bits) / 8;
|
|
|
+ int cnt_from = 0;
|
|
|
+ // format parameter buffer
|
|
|
+ for (int i = 0; i < ele_cycles; i++) {
|
|
|
+ for (int j = 0; j < bytes_to_copy; j++) {
|
|
|
+ to[j] = from[cnt_from++];
|
|
|
+ }
|
|
|
+ to += step;
|
|
|
+ }
|
|
|
+ trans_desc->data = bus->format_buffer;
|
|
|
+ trans_desc->data_length = to - bus->format_buffer;
|
|
|
+#endif
|
|
|
+}
|
|
|
+
|
|
|
+static void i2s_lcd_prepare_color_buffer(lcd_i80_trans_descriptor_t *trans_desc, const void *color, size_t color_size)
|
|
|
+{
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ lcd_panel_io_i80_t *i80_device = trans_desc->i80_device;
|
|
|
+ esp_lcd_i80_bus_t *bus = i80_device->bus;
|
|
|
+ uint8_t *from = (uint8_t *)color;
|
|
|
+ uint8_t *to = bus->format_buffer;
|
|
|
+ int bytes_to_copy = bus->bus_width / 8;
|
|
|
+ int cnt_from = 0;
|
|
|
+ int first_half = i80_device->flags.swap_color_bytes ? 0 : 2;
|
|
|
+ int second_half = i80_device->flags.swap_color_bytes ? 2 : 0;
|
|
|
+ // format color buffer
|
|
|
+ while (cnt_from < color_size) {
|
|
|
+ for (int i = 0; i < bytes_to_copy; i++) {
|
|
|
+ to[first_half + i] = from[cnt_from++];
|
|
|
+ }
|
|
|
+ for (int i = 0; i < bytes_to_copy; i++) {
|
|
|
+ to[second_half + i] = from[cnt_from++];
|
|
|
+ }
|
|
|
+ to += 4;
|
|
|
+ }
|
|
|
+ trans_desc->data = bus->format_buffer;
|
|
|
+ trans_desc->data_length = to - bus->format_buffer;
|
|
|
+#else
|
|
|
+ trans_desc->data = color;
|
|
|
+ trans_desc->data_length = color_size;
|
|
|
+#endif
|
|
|
+}
|
|
|
+
|
|
|
+static esp_err_t panel_io_i80_tx_param(esp_lcd_panel_io_t *io, int lcd_cmd, const void *param, size_t param_size)
|
|
|
+{
|
|
|
+ lcd_panel_io_i80_t *next_device = __containerof(io, lcd_panel_io_i80_t, base);
|
|
|
+ esp_lcd_i80_bus_t *bus = next_device->bus;
|
|
|
+ lcd_panel_io_i80_t *cur_device = bus->cur_device;
|
|
|
+ lcd_i80_trans_descriptor_t *trans_desc = NULL;
|
|
|
+ assert(param_size <= (bus->num_dma_nodes * DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "parameter bytes too long, enlarge max_transfer_bytes");
|
|
|
+ assert(param_size <= CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE && "format buffer too small, increase CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE");
|
|
|
+
|
|
|
+ // before issue a polling transaction, need to wait queued transactions finished
|
|
|
+ for (size_t i = 0; i < next_device->num_trans_inflight; i++) {
|
|
|
+ xQueueReceive(next_device->done_queue, &trans_desc, portMAX_DELAY);
|
|
|
+ }
|
|
|
+ next_device->num_trans_inflight = 0;
|
|
|
+
|
|
|
+ i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF);
|
|
|
+ // switch devices if necessary
|
|
|
+ lcd_i80_switch_devices(cur_device, next_device);
|
|
|
+ trans_desc = &next_device->trans_pool[0];
|
|
|
+ trans_desc->i80_device = next_device;
|
|
|
+ trans_desc->trans_done_cb = NULL; // no callback for command transfer
|
|
|
+ bus->cur_trans = trans_desc;
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ // switch to I2S 32bits mode, one WS cycle <=> one I2S FIFO
|
|
|
+ i2s_ll_tx_set_bits_mod(bus->hal.dev, 32);
|
|
|
+#endif
|
|
|
+ i2s_lcd_prepare_cmd_buffer(trans_desc, &lcd_cmd);
|
|
|
+ lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length);
|
|
|
+ gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_cmd_level);
|
|
|
+ i2s_ll_tx_stop(bus->hal.dev);
|
|
|
+ i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first
|
|
|
+ i2s_ll_start_out_link(bus->hal.dev);
|
|
|
+ // delay a while, wait for DMA data beeing feed to I2S FIFO
|
|
|
+ // in fact, this is only needed when LCD pixel clock is set too high
|
|
|
+ esp_rom_delay_us(1);
|
|
|
+ i2s_ll_tx_start(bus->hal.dev);
|
|
|
+ // polling the trans done event
|
|
|
+ while (!(i2s_ll_get_intr_status(bus->hal.dev) & I2S_LL_EVENT_TX_EOF)) {}
|
|
|
+
|
|
|
+ // parameter is usually short, using polling mode
|
|
|
+ if (param && param_size) {
|
|
|
+ i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF);
|
|
|
+ i2s_lcd_prepare_param_buffer(trans_desc, param, param_size * 8 / next_device->lcd_param_bits);
|
|
|
+ lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length);
|
|
|
+ gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_data_level);
|
|
|
+ i2s_ll_tx_stop(bus->hal.dev);
|
|
|
+ i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first
|
|
|
+ i2s_ll_start_out_link(bus->hal.dev);
|
|
|
+ esp_rom_delay_us(1);
|
|
|
+ i2s_ll_tx_start(bus->hal.dev);
|
|
|
+ // polling the trans done event, but don't clear the event status
|
|
|
+ while (!(i2s_ll_get_intr_status(bus->hal.dev) & I2S_LL_EVENT_TX_EOF)) {}
|
|
|
+ }
|
|
|
+ bus->cur_trans = NULL;
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, const void *color, size_t color_size)
|
|
|
+{
|
|
|
+ lcd_panel_io_i80_t *next_device = __containerof(io, lcd_panel_io_i80_t, base);
|
|
|
+ esp_lcd_i80_bus_t *bus = next_device->bus;
|
|
|
+ lcd_panel_io_i80_t *cur_device = bus->cur_device;
|
|
|
+ lcd_i80_trans_descriptor_t *trans_desc = NULL;
|
|
|
+ assert(color_size <= (bus->num_dma_nodes * DMA_DESCRIPTOR_BUFFER_MAX_SIZE) && "color bytes too long, enlarge max_transfer_bytes");
|
|
|
+
|
|
|
+ // before issue a polling transaction, need to wait queued transactions finished
|
|
|
+ for (size_t i = 0; i < next_device->num_trans_inflight; i++) {
|
|
|
+ xQueueReceive(next_device->done_queue, &trans_desc, portMAX_DELAY);
|
|
|
+ }
|
|
|
+ next_device->num_trans_inflight = 0;
|
|
|
+
|
|
|
+ i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF);
|
|
|
+ // switch devices if necessary
|
|
|
+ lcd_i80_switch_devices(cur_device, next_device);
|
|
|
+ trans_desc = &next_device->trans_pool[0];
|
|
|
+ trans_desc->i80_device = next_device;
|
|
|
+ trans_desc->trans_done_cb = NULL; // no callback for command transfer
|
|
|
+ bus->cur_trans = trans_desc;
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ // switch to I2S 32bits mode, one WS cycle <=> one I2S FIFO
|
|
|
+ i2s_ll_tx_set_bits_mod(bus->hal.dev, 32);
|
|
|
+#endif
|
|
|
+ i2s_lcd_prepare_cmd_buffer(trans_desc, &lcd_cmd);
|
|
|
+ lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length);
|
|
|
+ gpio_set_level(bus->dc_gpio_num, next_device->dc_levels.dc_cmd_level);
|
|
|
+ i2s_ll_tx_stop(bus->hal.dev);
|
|
|
+ i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first
|
|
|
+ i2s_ll_start_out_link(bus->hal.dev);
|
|
|
+ esp_rom_delay_us(1);
|
|
|
+ i2s_ll_tx_start(bus->hal.dev);
|
|
|
+ // polling the trans done event
|
|
|
+ while (!(i2s_ll_get_intr_status(bus->hal.dev) & I2S_LL_EVENT_TX_EOF)) {}
|
|
|
+ bus->cur_trans = NULL;
|
|
|
+
|
|
|
+ // sending LCD color data to queue
|
|
|
+ trans_desc->trans_done_cb = next_device->on_color_trans_done;
|
|
|
+ trans_desc->cb_user_data = next_device->cb_user_data;
|
|
|
+ trans_desc->flags.dc_level = next_device->dc_levels.dc_data_level; // DC level for data transaction
|
|
|
+ i2s_lcd_prepare_color_buffer(trans_desc, color, color_size);
|
|
|
+ // send transaction to trans_queue
|
|
|
+ xQueueSend(next_device->trans_queue, &trans_desc, portMAX_DELAY);
|
|
|
+ next_device->num_trans_inflight++;
|
|
|
+ // enable interrupt and go into isr handler, where we fetch the transactions from trans_queue and start it
|
|
|
+ // we will go into `lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment
|
|
|
+ esp_intr_enable(bus->intr);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static unsigned long i2s_lcd_select_periph_clock(i2s_hal_context_t *hal)
|
|
|
+{
|
|
|
+ unsigned long resolution_hz = 0;
|
|
|
+ i2s_clock_src_t clock_source;
|
|
|
+#if CONFIG_LCD_PERIPH_CLK_SRC_PLL160M
|
|
|
+ resolution_hz = 160000000 / LCD_PERIPH_CLOCK_PRE_SCALE;
|
|
|
+ clock_source = I2S_CLK_D2CLK;
|
|
|
+#else
|
|
|
+#error "invalid LCD peripheral clock source"
|
|
|
+#endif
|
|
|
+ i2s_ll_tx_clk_set_src(hal->dev, clock_source);
|
|
|
+ i2s_ll_clk_cal_t clk_cal_config = {
|
|
|
+ .mclk_div = LCD_PERIPH_CLOCK_PRE_SCALE,
|
|
|
+ .a = 1,
|
|
|
+ .b = 0,
|
|
|
+ };
|
|
|
+ i2s_ll_tx_set_clk(hal->dev, &clk_cal_config);
|
|
|
+ return resolution_hz;
|
|
|
+}
|
|
|
+
|
|
|
+static esp_err_t i2s_lcd_init_dma_link(esp_lcd_i80_bus_handle_t bus)
|
|
|
+{
|
|
|
+ for (int i = 0; i < bus->num_dma_nodes; i++) {
|
|
|
+ bus->dma_nodes[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
|
|
|
+ bus->dma_nodes[i].next = &bus->dma_nodes[i + 1];
|
|
|
+ }
|
|
|
+ bus->dma_nodes[bus->num_dma_nodes - 1].next = NULL; // one-off DMA chain
|
|
|
+ i2s_ll_dma_enable_eof_on_fifo_empty(bus->hal.dev, true);
|
|
|
+ i2s_ll_dma_enable_owner_check(bus->hal.dev, true);
|
|
|
+ i2s_ll_dma_enable_auto_write_back(bus->hal.dev, true);
|
|
|
+ i2s_ll_set_out_link_addr(bus->hal.dev, (uint32_t)bus->dma_nodes);
|
|
|
+ i2s_ll_enable_dma(bus->hal.dev, true);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config)
|
|
|
+{
|
|
|
+ int bus_id = bus->bus_id;
|
|
|
+ // check validation of GPIO number
|
|
|
+ bool valid_gpio = (bus_config->wr_gpio_num >= 0) && (bus_config->dc_gpio_num >= 0);
|
|
|
+ for (size_t i = 0; i < bus_config->bus_width; i++) {
|
|
|
+ valid_gpio = valid_gpio && (bus_config->data_gpio_nums[i] >= 0);
|
|
|
+ }
|
|
|
+ if (!valid_gpio) {
|
|
|
+ return ESP_ERR_INVALID_ARG;
|
|
|
+ }
|
|
|
+ // connect peripheral signals via GPIO matrix
|
|
|
+ // data line
|
|
|
+ for (size_t i = 0; i < bus_config->bus_width; i++) {
|
|
|
+ gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT);
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_signals.buses[bus_id].data_sigs[i + 8], false, false);
|
|
|
+#else
|
|
|
+ esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_signals.buses[bus_id].data_sigs[i + SOC_LCD_I80_BUS_WIDTH - bus_config->bus_width], false, false);
|
|
|
+#endif
|
|
|
+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->data_gpio_nums[i]], PIN_FUNC_GPIO);
|
|
|
+ }
|
|
|
+ // WR signal (pclk)
|
|
|
+ gpio_set_direction(bus_config->wr_gpio_num, GPIO_MODE_OUTPUT);
|
|
|
+ esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_signals.buses[bus_id].wr_sig, true, false);
|
|
|
+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->wr_gpio_num], PIN_FUNC_GPIO);
|
|
|
+ // DC signal is controlled by software, set as general purpose IO
|
|
|
+ gpio_set_direction(bus_config->dc_gpio_num, GPIO_MODE_OUTPUT);
|
|
|
+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->dc_gpio_num], PIN_FUNC_GPIO);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus)
|
|
|
+{
|
|
|
+ // trigger a quick interrupt event by a dummy transaction, wait the LCD interrupt line goes active
|
|
|
+ // next time when esp_intr_enable is invoked, we can go into interrupt handler immediately
|
|
|
+ // where we dispatch transactions for i80 devices
|
|
|
+ static uint32_t fake_trigger = 0;
|
|
|
+ lcd_com_mount_dma_data(bus->dma_nodes, &fake_trigger, 4);
|
|
|
+ i2s_ll_start_out_link(bus->hal.dev);
|
|
|
+ i2s_ll_tx_start(bus->hal.dev);
|
|
|
+ while (!(i2s_ll_get_intr_status(bus->hal.dev) & I2S_LL_EVENT_TX_EOF)) {}
|
|
|
+}
|
|
|
+
|
|
|
+static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device)
|
|
|
+{
|
|
|
+ // the caller should make sure the next_device and cur_device are attached to the same bus
|
|
|
+ esp_lcd_i80_bus_t *bus = next_device->bus;
|
|
|
+ if (next_device != cur_device) {
|
|
|
+ // reconfigure PCLK for the new device
|
|
|
+ i2s_ll_tx_set_bck_div_num(bus->hal.dev, next_device->clock_prescale);
|
|
|
+ if (cur_device) { // de-assert current device
|
|
|
+ gpio_set_level(cur_device->cs_gpio_num, !cur_device->flags.cs_active_high);
|
|
|
+ }
|
|
|
+ gpio_set_level(next_device->cs_gpio_num, next_device->flags.cs_active_high); // select the next device
|
|
|
+ // the WR signal (a.k.a the PCLK) generated by I2S is low level in idle stage
|
|
|
+ // but most of 8080 LCDs require the WR line to be in high level during idle stage
|
|
|
+ esp_rom_gpio_connect_out_signal(bus->wr_gpio_num, lcd_periph_signals.buses[bus->bus_id].wr_sig, !next_device->flags.pclk_idle_low, false);
|
|
|
+ }
|
|
|
+ bus->cur_device = next_device;
|
|
|
+}
|
|
|
+
|
|
|
+static IRAM_ATTR void lcd_default_isr_handler(void *args)
|
|
|
+{
|
|
|
+ esp_lcd_i80_bus_t *bus = (esp_lcd_i80_bus_t *)args;
|
|
|
+ lcd_i80_trans_descriptor_t *trans_desc = NULL;
|
|
|
+ lcd_panel_io_i80_t *cur_device = NULL;
|
|
|
+ lcd_panel_io_i80_t *next_device = NULL;
|
|
|
+ BaseType_t high_task_woken = pdFALSE;
|
|
|
+ bool need_yield = false;
|
|
|
+ uint32_t intr_status = i2s_ll_get_intr_status(bus->hal.dev);
|
|
|
+ if (intr_status & I2S_LL_EVENT_TX_EOF) { // trans done event
|
|
|
+ // disable interrupt temporarily, only re-enable when there be remained transaction in the queue
|
|
|
+ esp_intr_disable(bus->intr);
|
|
|
+ trans_desc = bus->cur_trans; // the finished transaction
|
|
|
+ cur_device = bus->cur_device;// the working device
|
|
|
+ // process finished transaction
|
|
|
+ if (trans_desc) {
|
|
|
+ assert(trans_desc->i80_device == cur_device && "transaction device mismatch");
|
|
|
+ // device callback
|
|
|
+ if (trans_desc->trans_done_cb) {
|
|
|
+ if (trans_desc->trans_done_cb(&cur_device->base, trans_desc->cb_user_data, NULL)) {
|
|
|
+ need_yield = true;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ // move transaction to done_queue
|
|
|
+ high_task_woken = pdFALSE;
|
|
|
+ xQueueSendFromISR(cur_device->done_queue, &trans_desc, &high_task_woken);
|
|
|
+ if (high_task_woken == pdTRUE) {
|
|
|
+ need_yield = true;
|
|
|
+ }
|
|
|
+ bus->cur_trans = NULL;
|
|
|
+ }
|
|
|
+ // fetch transactions from devices' trans_queue
|
|
|
+ // Note: the first registered device will have the highest priority to be scheduled
|
|
|
+ LIST_FOREACH(next_device, &bus->device_list, device_list_entry) {
|
|
|
+ high_task_woken = pdFALSE;
|
|
|
+ if (xQueueReceiveFromISR(next_device->trans_queue, &trans_desc, &high_task_woken) == pdTRUE) {
|
|
|
+ if (high_task_woken == pdTRUE) {
|
|
|
+ need_yield = true;
|
|
|
+ }
|
|
|
+ // only clear the interrupt status when we're sure there still remains transaction to handle
|
|
|
+ i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF);
|
|
|
+ // switch devices if necessary
|
|
|
+ lcd_i80_switch_devices(cur_device, next_device);
|
|
|
+ bus->cur_trans = trans_desc;
|
|
|
+ gpio_set_level(bus->dc_gpio_num, trans_desc->flags.dc_level);
|
|
|
+ // mount data to DMA links
|
|
|
+ lcd_com_mount_dma_data(bus->dma_nodes, trans_desc->data, trans_desc->data_length);
|
|
|
+#if SOC_I2S_TRANS_SIZE_ALIGN_WORD
|
|
|
+ // switch to I2S 16bits mode, two WS cycle <=> one I2S FIFO
|
|
|
+ i2s_ll_tx_set_bits_mod(bus->hal.dev, 16);
|
|
|
+#endif
|
|
|
+ // enable interrupt again, because the new transaction can trigger new trans done event
|
|
|
+ esp_intr_enable(bus->intr);
|
|
|
+ i2s_ll_tx_stop(bus->hal.dev);
|
|
|
+ i2s_ll_tx_reset(bus->hal.dev); // reset TX engine first
|
|
|
+ i2s_ll_start_out_link(bus->hal.dev);
|
|
|
+ esp_rom_delay_us(1);
|
|
|
+ i2s_ll_tx_start(bus->hal.dev);
|
|
|
+ break; // exit for-each loop
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+ if (need_yield) {
|
|
|
+ portYIELD_FROM_ISR();
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#endif // SOC_I2S_LCD_I80_VARIANT
|
morris