interrupt: removed descriptor table from esp32c3 interrupt hal.

components/esp_common/src/int_wdt.c

@@ -126,11 +126,11 @@ void esp_int_wdt_cpu_init(void)
 
     /* Set the type and priority to cache error interrupts, if supported. */
 #if SOC_INTERRUPT_TYPE_CAN_SET
-    interrupt_controller_hal_set_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
+    interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
 #endif
 
 #if SOC_INTERRUPT_LEVEL_CAN_SET
-    interrupt_controller_hal_set_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
+    interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 #endif
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX

components/hal/CMakeLists.txt

@@ -28,8 +28,7 @@ if(NOT BOOTLOADER_BUILD)
                 "soc_hal.c"
                 "interrupt_controller_hal.c"
                 "sha_hal.c"
-                "aes_hal.c"
-                "${target}/interrupt_descriptor_table.c")
+                "aes_hal.c")
 
     if(${target} STREQUAL "esp32")
         list(APPEND srcs
@@ -43,6 +42,7 @@ if(NOT BOOTLOADER_BUILD)
                     "twai_hal_iram.c"
                     "esp32/adc_hal.c"
                     "esp32/brownout_hal.c"
+                    "esp32/interrupt_descriptor_table.c"
                     "esp32/touch_sensor_hal.c")
         if(NOT BOOTLOADER_BUILD AND CONFIG_ETH_USE_ESP32_EMAC)
             list(APPEND srcs "esp32/emac_hal.c")
@@ -65,6 +65,7 @@ if(NOT BOOTLOADER_BUILD)
                     "esp32s2/systimer_hal.c"
                     "esp32s2/touch_sensor_hal.c"
                     "esp32s2/dac_hal.c"
+                    "esp32s2/interrupt_descriptor_table.c"
                     "esp32s2/usb_hal.c")
     endif()
 
@@ -79,6 +80,7 @@ if(NOT BOOTLOADER_BUILD)
             "twai_hal.c"
             "twai_hal_iram.c"
             "esp32s3/brownout_hal.c"
+            "esp32s3/interrupt_descriptor_table.c"
             "esp32s3/systimer_hal.c"
             "esp32s3/touch_sensor_hal.c")
     endif()

components/hal/esp32c3/include/hal/interrupt_controller_ll.h

@@ -117,17 +117,17 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
 
 /**
  * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
- * 
+ *
  * @param intr interrupt number ranged from 0 to 31
  */
 static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
 {
-    esprv_intc_set_interrupt_clear(intr);
+     REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
 }
 
 /**
  * @brief Sets the interrupt level int the interrupt controller.
- * 
+ *
  * @param interrupt_number Interrupt number 0 to 31
  * @param level priority between 1 (lowest) to 7 (highest)
  */
@@ -138,7 +138,7 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level)
 
 /**
  * @brief Set the type of an interrupt in the controller.
- * 
+ *
  * @param interrupt_number Interrupt number 0 to 31
  * @param type interrupt type as edge or level triggered
  */

components/hal/esp32c3/interrupt_descriptor_table.c

@@ -1,58 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include "sdkconfig.h"
-#include "hal/interrupt_controller_hal.h"
-#include "soc/soc_caps.h"
-#include "soc/soc.h"
-
-//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
-const int_desc_t interrupt_descriptor_table[32] = {
-    { 1, INTTP_NA, {INTDESC_RESVD } }, //0
-    { 1, INTTP_NA, {INTDESC_SPECIAL } }, //1
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //2
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //3
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //4
-    { 1, INTTP_NA, {INTDESC_SPECIAL } }, //5
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //6
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //7
-    { 1, INTTP_NA, {INTDESC_SPECIAL } }, //8
-    { 1, INTTP_NA, {INTDESC_SPECIAL } }, //9
-    { 1, INTTP_NA, {INTDESC_NORMAL } },  //10
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //11
-    { 1, INTTP_NA, {INTDESC_SPECIAL } }, //12
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //13
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //14
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //15
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //16
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //17
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //18
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //19
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //20
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //21
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //22
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //23
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //24
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //25
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //26
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //27
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //28
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //29
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //30
-    { 1, INTTP_NA, {INTDESC_NORMAL } }, //31
-};
-
-const int_desc_t *interrupt_controller_hal_desc_table(void)
-{
-    return interrupt_descriptor_table;
-}

components/hal/include/hal/interrupt_controller_hal.h

@@ -23,12 +23,14 @@
 extern "C" {
 #endif
 
+#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
 /**
  * @brief Gets target platform interrupt descriptor table
  *
  * @return Address of interrupt descriptor table
  */
 __attribute__((pure))  const int_desc_t *interrupt_controller_hal_desc_table(void);
+#endif
 
 /**
  * @brief Gets the interrupt type given an interrupt number.
@@ -55,24 +57,6 @@ __attribute__((pure))  int interrupt_controller_hal_desc_level(int interrupt_num
  */
 __attribute__((pure))  int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number);
 
-#if SOC_INTERRUPT_LEVEL_CAN_SET
-/**
- * @brief Set the interrupt level given an interrupt number.
- *
- * @param interrupt_number number of the interrupt
- * @param level new level for this interrupt
- */
-void interrupt_controller_hal_set_level(int interrupt_number, int level);
-
-/**
- * @brief Set the interrupt type given an interrupt number.
- *
- * @param interrupt_number number of the interrupt
- * @param type new type for this interrupt
- */
-void interrupt_controller_hal_set_type(int interrupt_number, int_type_t type);
-#endif
-
 /**
  * @brief Gets the interrupt type given an interrupt number.
  *
@@ -98,7 +82,7 @@ static inline int interrupt_controller_hal_get_level(int interrupt_number)
 #ifdef SOC_CPU_HAS_FLEXIBLE_INTC
 /**
  * @brief Set the type of an interrupt in the controller.
- * 
+ *
  * @param interrupt_number Interrupt number 0 to 31
  * @param type interrupt type as edge or level triggered
  */
@@ -109,7 +93,7 @@ static inline void interrupt_controller_hal_set_int_type(int intr, int_type_t ty
 
 /**
  * @brief Sets the interrupt level int the interrupt controller.
- * 
+ *
  * @param interrupt_number Interrupt number 0 to 31
  * @param level priority between 1 (lowest) to 7 (highest)
  */
@@ -210,10 +194,10 @@ static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask)
 
 /**
  * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
- * 
+ *
  * @param intr interrupt number ranged from 0 to 31
  */
-static inline void interrupt_controller_hal_edge_int_acknowledge(int intr) 
+static inline void interrupt_controller_hal_edge_int_acknowledge(int intr)
 {
     intr_cntrl_ll_edge_int_acknowledge(intr);
 }

components/hal/interrupt_controller_hal.c

@@ -16,34 +16,30 @@
 
 int_type_t interrupt_controller_hal_desc_type(int interrupt_number)
 {
+#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
     const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
     return(int_desc[interrupt_number].type);
+#else
+    return (INTTP_NA);
+#endif
 }
 
 int interrupt_controller_hal_desc_level(int interrupt_number)
 {
+#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
     const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
     return(int_desc[interrupt_number].level);
+#else
+    return 1;
+#endif
 }
 
 int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number)
 {
+#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
     const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
     return(int_desc[interrupt_number].cpuflags[cpu_number]);
-}
-
-#if SOC_INTERRUPT_LEVEL_CAN_SET
-
-void interrupt_controller_hal_set_level(int interrupt_number, int level) {
-   intr_cntrl_ll_set_level(interrupt_number, level);
-}
-
+#else
+    return INTDESC_NORMAL;
 #endif
-
-#if SOC_INTERRUPT_TYPE_CAN_SET
-
-void interrupt_controller_hal_set_type(int interrupt_number, int_type_t type) {
-   intr_cntrl_ll_set_type(interrupt_number, type);
 }
-
-#endif

components/riscv/include/riscv/interrupt.h

@@ -110,13 +110,6 @@ void esprv_intc_set_threshold(int priority_threshold);
  */
 uint32_t esprv_intc_get_interrupt_unmask(void);
 
-/**
- * @brief Set a bit in int clear register
- * @param intr bit to set from 0 to 31
- * @return none
- */
-void esprv_intc_set_interrupt_clear(int intr); 
-
 #ifdef __cplusplus
 }
 #endif

components/riscv/interrupt.c

@@ -89,12 +89,6 @@ uint32_t esprv_intc_get_interrupt_unmask(void)
     return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
 }
 
-void esprv_intc_set_interrupt_clear(int intr)
-{
-    REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
-}
-
-
 /*************************** Exception names. Used in .gdbinit file. ***************************/
 
 const char *riscv_excp_names[16] __attribute__((used)) = {