Merge branch 'bugfix/fix_esp32_mmu_init_issue' into 'master'

mmu: add ll functions for mmu unmap

Closes OCD-526 and IDF-4962

See merge request espressif/esp-idf!17868

components/hal/esp32/include/hal/cache_ll.h

@@ -49,10 +49,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
         mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
         mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
     } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        HAL_ASSERT(vaddr_end <= DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS1;
     } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        HAL_ASSERT(vaddr_end <= DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(false);

components/hal/esp32/include/hal/mmu_ll.h

@@ -9,10 +9,11 @@
 #pragma once
 
 #include "soc/ext_mem_defs.h"
+#include "soc/dport_reg.h"
+#include "soc/dport_access.h"
 #include "hal/assert.h"
 #include "hal/mmu_types.h"
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -68,6 +69,44 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
            (ADDRESS_IN_DROM0_CACHE(vaddr_start) && ADDRESS_IN_DROM0_CACHE(vaddr_end));
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    DPORT_INTERRUPT_DISABLE();
+    switch (mmu_id) {
+        case 0:
+            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], DPORT_FLASH_MMU_TABLE_INVALID_VAL);
+            break;
+        case 1:
+            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], DPORT_FLASH_MMU_TABLE_INVALID_VAL);
+            break;
+        default:
+            HAL_ASSERT(false && "invalid mmu_id");
+    }
+    DPORT_INTERRUPT_RESTORE();
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c2/include/hal/mmu_ll.h

@@ -142,11 +142,38 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
 {
     (void)mmu_id;
     HAL_ASSERT(target == MMU_TARGET_FLASH0);
-    HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
 
     *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
 
 #ifdef __cplusplus
 }

components/hal/esp32c3/include/hal/mmu_ll.h

@@ -109,11 +109,38 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
 {
     (void)mmu_id;
     HAL_ASSERT(target == MMU_TARGET_FLASH0);
-    HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
 
     *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
 
 #ifdef __cplusplus
 }

components/hal/esp32h2/include/hal/mmu_ll.h

@@ -109,11 +109,38 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
 {
     (void)mmu_id;
     HAL_ASSERT(target == MMU_TARGET_FLASH0);
-    HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
 
     *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
 
 #ifdef __cplusplus
 }

components/hal/esp32s2/include/hal/mmu_ll.h

@@ -132,12 +132,40 @@ __attribute__((always_inline))
 static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
 
     uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
     *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/cache_ll.h

@@ -42,9 +42,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
 
     cache_bus_mask_t mask = 0;
     uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;    //Both cores have their own IBUS0
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;    //Both cores have their own DBUS0
     } else {
         HAL_ASSERT(0);      //Out of region

components/hal/esp32s3/include/hal/mmu_ll.h

@@ -108,12 +108,40 @@ __attribute__((always_inline))
 static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
 
     uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
     *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
 }
 
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+}
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/mmu_hal.c

@@ -30,20 +30,9 @@
 
 void mmu_hal_init(void)
 {
-#if CONFIG_IDF_TARGET_ESP32
-    mmu_init(0);
+    mmu_ll_unmap_all(0);
 #if !CONFIG_FREERTOS_UNICORE
-    /**
-     * The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are necessary to work around a hardware bug.
-     * See ESP32 Errata 3.1
-     */
-    DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-    mmu_init(1);
-    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-#endif
-
-#else //!esp32
-    Cache_MMU_Init();
+    mmu_ll_unmap_all(1);
 #endif
 }
 
@@ -94,7 +83,7 @@ void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr,
     uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
     HAL_ASSERT(vaddr % page_size_in_bytes == 0);
     HAL_ASSERT(paddr % page_size_in_bytes == 0);
-    HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_ENTRY_NUM));
+    HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_PADDR_PAGE_NUM));
     HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr, len));
 
     uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;

components/soc/esp32/include/soc/ext_mem_defs.h

@@ -30,13 +30,15 @@ extern "C" {
 #define DROM0_CACHE_ADDRESS_HIGH    0x3F800000
 
 
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
 #define ADDRESS_IN_IRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
 #define ADDRESS_IN_IROM0_CACHE(vaddr)      ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
 #define ADDRESS_IN_DRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
 #define ADDRESS_IN_DROM0_CACHE(vaddr)      ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
 
+//MMU entry num
+#define MMU_ENTRY_NUM    256
 
 #ifdef __cplusplus
 }

components/soc/esp32/include/soc/mmu.h

@@ -1,16 +1,9 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #pragma once
 
 #include <stdint.h>
@@ -31,7 +24,8 @@ extern "C" {
 #define SOC_MMU_INVALID_ENTRY_VAL               DPORT_FLASH_MMU_TABLE_INVALID_VAL
 #define SOC_MMU_ADDR_MASK                       DPORT_MMU_ADDRESS_MASK
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page)
-#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       ((volatile uint32_t*) 0x3FF10000)
+#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       DPORT_PRO_FLASH_MMU_TABLE
+#define SOC_MMU_DPORT_APP_FLASH_MMU_TABLE       DPORT_APP_FLASH_MMU_TABLE
 #define SOC_MMU_VADDR1_START_ADDR               SOC_IROM_MASK_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
 #define SOC_MMU_VADDR0_START_ADDR               SOC_DROM_LOW

components/soc/esp32c2/include/soc/ext_mem_defs.h

@@ -32,7 +32,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
@@ -42,9 +42,6 @@ extern "C" {
 #define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
 #define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
 
-//IDF-3821
-// #define MMU_SIZE                        0x100
-
 #define CACHE_IBUS                      0
 #define CACHE_IBUS_MMU_START            0
 #define CACHE_IBUS_MMU_END              0x100
@@ -95,16 +92,18 @@ extern "C" {
  */
 #define INVALID_PHY_PAGE                0x7f
 /**
- * Max MMU entry num.
- * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
- * 64 * 64KB, means MMU can map 4MB at most
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 64 * 64KB, means MMU can support 4MB paddr at most
  */
-#define MMU_MAX_ENTRY_NUM    64
+#define MMU_MAX_PADDR_PAGE_NUM    64
 /**
  * This is the mask used for mapping. e.g.:
  * 0x4200_0000 & MMU_VADDR_MASK
  */
 #define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1)
+//MMU entry num
+#define MMU_ENTRY_NUM  64
 
 #define BUS_PMS_MASK  0xffffff
 

components/soc/esp32c3/include/soc/ext_mem_defs.h

@@ -27,7 +27,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
@@ -86,17 +86,18 @@ extern "C" {
  */
 #define INVALID_PHY_PAGE 0xffff
 /**
- * Max MMU entry num.
- * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
- * 256 * 64KB, means MMU can map 16MB at most
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_ENTRY_NUM    256
+#define MMU_MAX_PADDR_PAGE_NUM    256
 /**
  * This is the mask used for mapping. e.g.:
  * 0x4200_0000 & MMU_VADDR_MASK
  */
 #define MMU_VADDR_MASK  0x7FFFFF
-
+//MMU entry num
+#define MMU_ENTRY_NUM   128
 
 #define CACHE_ICACHE_LOW_SHIFT         0
 #define CACHE_ICACHE_HIGH_SHIFT        2

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -27,7 +27,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C000000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
@@ -86,16 +86,18 @@ extern "C" {
  */
 #define INVALID_PHY_PAGE 0xffff
 /**
- * Max MMU entry num.
- * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
- * 256 * 64KB, means MMU can map 16MB at most
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_ENTRY_NUM    256
+#define MMU_MAX_PADDR_PAGE_NUM    256
 /**
  * This is the mask used for mapping. e.g.:
  * 0x4200_0000 & MMU_VADDR_MASK
  */
 #define MMU_VADDR_MASK    0x7fffff
+//MMU entry num
+#define MMU_ENTRY_NUM     128
 
 #define CACHE_ICACHE_LOW_SHIFT         0
 #define CACHE_ICACHE_HIGH_SHIFT        2

components/soc/esp32s2/include/soc/ext_mem_defs.h

@@ -43,7 +43,7 @@ extern "C" {
 #define DPORT_CACHE_ADDRESS_HIGH      	0x3f800000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
@@ -111,16 +111,19 @@ extern "C" {
  */
 #define MMU_VALID_VAL_MASK 0x3fff
 /**
- * Max MMU entry num.
- * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
- * 16384 * 64KB, means MMU can map 1GB at most
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 16384 * 64KB, means MMU can support 1GB paddr at most
  */
-#define MMU_MAX_ENTRY_NUM    16384
+#define MMU_MAX_PADDR_PAGE_NUM    16384
 /**
  * This is the mask used for mapping. e.g.:
  * 0x4200_0000 & MMU_VADDR_MASK
  */
 #define MMU_VADDR_MASK  0x3FFFFF
+//MMU entry num
+#define MMU_ENTRY_NUM   384
+
 #define BUS_NUM_MASK  0x3
 
 #define CACHE_MEMORY_BANK_SIZE         8192

components/soc/esp32s3/include/soc/ext_mem_defs.h

@@ -26,7 +26,7 @@ extern "C" {
 #define ESP_CACHE_TEMP_ADDR             0x3C800000
 
 #define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
 
 #define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
 #define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
@@ -86,16 +86,18 @@ extern "C" {
  */
 #define INVALID_PHY_PAGE 0xffff
 /**
- * Max MMU entry num.
- * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
- * 16384 * 64KB, means MMU can map 1GB at most
+ * Max MMU available paddr page num.
+ * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * 16384 * 64KB, means MMU can support 1GB paddr at most
  */
-#define MMU_MAX_ENTRY_NUM    16384
+#define MMU_MAX_PADDR_PAGE_NUM    16384
 /**
  * This is the mask used for mapping. e.g.:
  * 0x4200_0000 & MMU_VADDR_MASK
  */
 #define MMU_VADDR_MASK  0x1FFFFFF
+//MMU entry num
+#define MMU_ENTRY_NUM   512
 
 #define CACHE_ICACHE_LOW_SHIFT         0
 #define CACHE_ICACHE_HIGH_SHIFT        2

tools/ci/check_copyright_ignore.txt

@@ -1229,7 +1229,6 @@ components/soc/esp32/include/soc/i2c_struct.h
 components/soc/esp32/include/soc/io_mux_reg.h
 components/soc/esp32/include/soc/ledc_reg.h
 components/soc/esp32/include/soc/ledc_struct.h
-components/soc/esp32/include/soc/mmu.h
 components/soc/esp32/include/soc/nrx_reg.h
 components/soc/esp32/include/soc/pid.h
 components/soc/esp32/include/soc/reset_reasons.h