Merge branch 'feature/check_mcpwm_sync_direction' into 'master'

mcpwm: check sync direction is valid

See merge request espressif/esp-idf!20134

components/driver/deprecated/driver/mcpwm.h

@@ -344,8 +344,8 @@ esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time
  * @param mcpwm_num set MCPWM unit(0-1)
  * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
  * @param dt_mode set deadtime mode
- * @param red set rising edge delay = red*100ns
- * @param fed set rising edge delay = fed*100ns
+ * @param red set rising edge delay = (red + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`)
+ * @param fed set rising edge delay = (fed + 1) * MCPWM Group Resolution (default to 100ns, can be changed by `mcpwm_group_set_resolution`)
  *
  * @return
  *     - ESP_OK Success

components/driver/mcpwm/mcpwm_timer.c

@@ -273,6 +273,18 @@ esp_err_t mcpwm_timer_set_phase_on_sync(mcpwm_timer_handle_t timer, const mcpwm_
     int group_id = group->group_id;
     int timer_id = timer->timer_id;
     mcpwm_sync_handle_t sync_source = config->sync_src;
+    // check if the sync direction is valid
+    bool valid_direction = true;
+    if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_UP) {
+        valid_direction = config->direction == MCPWM_TIMER_DIRECTION_UP;
+    } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_DOWN) {
+        valid_direction = config->direction == MCPWM_TIMER_DIRECTION_DOWN;
+    } else if (timer->count_mode == MCPWM_TIMER_COUNT_MODE_PAUSE) {
+        valid_direction = false;
+    } else {
+        valid_direction = true;
+    }
+    ESP_RETURN_ON_FALSE(valid_direction, ESP_ERR_INVALID_ARG, TAG, "invalid sync direction");
 
     // enable sync feature and set sync phase
     if (sync_source) {

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -224,7 +224,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of MCPWM Timer
  */
-#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_D2}
+#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M}
 
 /**
  * @brief Type of MCPWM timer clock source