Merge branch 'feature/bringup_spiflash_esp32c6' into 'master'

spi_flash: bringup driver for esp32c6

Closes IDF-5333, IDF-4066, IDF-5631, and IDF-5659

See merge request espressif/esp-idf!20692

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c

@@ -55,15 +55,3 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
     }
     esp_rom_spiflash_config_clk(spi_clk_div, 0);
 }
-
-void IRAM_ATTR bootloader_flash_set_dummy_out(void)
-{
-    REG_SET_BIT(SPI_MEM_CTRL_REG(0), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: IDF-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
-    REG_SET_BIT(SPI_MEM_CTRL_REG(1), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: idf-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
-}
-
-void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
-{
-    bootloader_configure_spi_pins(1);
-    bootloader_flash_set_dummy_out();
-}

components/bootloader_support/bootloader_flash/src/flash_qio_mode.c

@@ -102,18 +102,20 @@ void bootloader_enable_qio_mode(void)
 
 static void s_flash_set_qio_pins(void)
 {
+#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
+
 #if CONFIG_IDF_TARGET_ESP32
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-    int wp_pin = bootloader_flash_get_wp_pin();
-    esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
-#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5649 Add a soc_caps
+    esp_rom_spiflash_select_qio_pins(bootloader_flash_get_wp_pin(), esp_rom_efuse_get_flash_gpio_info());
+#else
+    esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), esp_rom_efuse_get_flash_gpio_info());
+#endif // CONFIG_IDF_TARGET_ESP32
+
+#else
     // ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second
     // parameter is set to 0, means that chip uses default SPI pins
     // and wp_gpio_num parameter(the first parameter) is ignored.
     esp_rom_spiflash_select_qio_pins(0, 0);
-#else
-    esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), esp_rom_efuse_get_flash_gpio_info());
-#endif
+#endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
 }
 
 

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -46,27 +46,18 @@ static const char *TAG = "boot.esp32c6";
 
 void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 {
-    // TODO: IDF-5649
-    const uint32_t spiconfig = 0;
     uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
     uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
     uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
     uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
     uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
     uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
-    if (spiconfig == 0) {
-
-    }
     esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
     esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
     esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
     esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
-    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
-    }
-    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
-    }
+    esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
 }
 
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
@@ -168,7 +159,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
 
 static void IRAM_ATTR bootloader_init_flash_configure(void)
 {
-    bootloader_flash_dummy_config(&bootloader_image_hdr);
+    bootloader_configure_spi_pins(1);
     bootloader_flash_cs_timing_config();
 }
 
@@ -181,15 +172,6 @@ static void bootloader_spi_flash_resume(void)
 static esp_err_t bootloader_init_spi_flash(void)
 {
     bootloader_init_flash_configure();
-// TODO: IDF-5649
-// #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
-//     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-//     if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
-//         ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
-//         return ESP_FAIL;
-//     }
-// #endif
-
     bootloader_spi_flash_resume();
     bootloader_flash_unlock();
 

components/esp_system/port/soc/esp32c6/system_internal.c

@@ -63,16 +63,6 @@ void IRAM_ATTR esp_restart_noos(void)
     // Disable cache
     Cache_Disable_ICache();
 
-    // 2nd stage bootloader reconfigures SPI flash signals.
-    // Reset them to the defaults expected by ROM.
-    WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
-    // TODO: IDF-5659
-    // WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
-    // WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
-    // WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
-    // WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
-    // WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
-
     // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
     // Moved to module internal
     // SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,

components/hal/esp32/include/hal/spi_flash_ll.h

@@ -45,6 +45,9 @@ extern "C" {
 /// Empty function to be compatible with new version chips.
 #define spi_flash_ll_set_dummy_out(dev, out_en, out_lev)
 
+// On ESP32, we extent 4 bits to occupy `Continuous Read Mode` bits. (same to origin code.)
+#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (4)
+
 /// type to store pre-calculated register value in above layers
 typedef typeof(SPI1.clock.val) spi_flash_ll_clock_reg_t;
 
@@ -431,6 +434,17 @@ static inline uint32_t spi_flash_ll_calculate_clock_reg(uint8_t host_id, uint8_t
     return div_parameter;
 }
 
+/**
+ * Set extra address for bits M0-M7 in DIO/QIO mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param extra_addr extra address(M0-M7) to send.
+ */
+static inline void spi_flash_ll_set_extra_address(spi_dev_t *dev, uint32_t extra_addr)
+{
+    // Not supported on ESP32.
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c6/include/hal/gpspi_flash_ll.h

@@ -353,20 +353,6 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
     HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
 }
 
-/**
- * Set D/Q output level during dummy phase
- *
- * @param dev Beginning address of the peripheral registers.
- * @param out_en whether to enable IO output for dummy phase
- * @param out_level dummy output level
- */
-static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev)
-{
-    dev->ctrl.dummy_out = out_en;
-    dev->ctrl.q_pol = out_lev;
-    dev->ctrl.d_pol = out_lev;
-}
-
 /**
  * Set extra hold time of CS after the clocks.
  *

components/hal/esp32c6/include/hal/spi_flash_ll.h

@@ -35,7 +35,8 @@ extern "C" {
                                      }\
                                      dev_id; \
                                     })
-
+// Since ESP32-C6, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
+#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS  (8)
 
 typedef union  {
     gpspi_flash_ll_clock_reg_t gpspi;
@@ -61,9 +62,9 @@ typedef union  {
 #define spi_flash_ll_set_address(dev, addr)                  gpspi_flash_ll_set_address((spi_dev_t*)dev, addr)
 #define spi_flash_ll_set_usr_address(dev, addr, bitlen)      gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen)
 #define spi_flash_ll_set_dummy(dev, dummy)                   gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy)
-#define spi_flash_ll_set_dummy_out(dev, en, lev)             gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_set_extra_address(dev, extra_addr)      { /* Not supported on gpspi on ESP32-C6*/ }
 #else
 #define spi_flash_ll_reset(dev)                              spimem_flash_ll_reset((spi_mem_dev_t*)dev)
 #define spi_flash_ll_cmd_is_done(dev)                        spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
@@ -88,9 +89,9 @@ typedef union  {
 #define spi_flash_ll_set_address(dev, addr)                  spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr)
 #define spi_flash_ll_set_usr_address(dev, addr, bitlen)      spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen)
 #define spi_flash_ll_set_dummy(dev, dummy)                   spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy)
-#define spi_flash_ll_set_dummy_out(dev, en, lev)             spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
 #define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
 
 #endif
 

components/hal/esp32c6/include/hal/spimem_flash_ll.h

@@ -24,6 +24,7 @@
 #include "hal/assert.h"
 #include "hal/spi_types.h"
 #include "hal/spi_flash_types.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -474,6 +475,18 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
     dev->user.usr_addr = bitlen ? 1 : 0;
 }
 
+/**
+ * Set extra address for bits M0-M7 in DIO/QIO mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param extra_addr extra address(M0-M7) to send.
+ */
+static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
+{
+    dev->cache_fctrl.usr_addr_4byte = 0;
+    dev->rd_status.wb_mode = extra_addr;
+}
+
 /**
  * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
  *
@@ -509,20 +522,6 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
     dev->user1.usr_dummy_cyclelen = dummy_n - 1;
 }
 
-/**
- * Set D/Q output level during dummy phase
- *
- * @param dev Beginning address of the peripheral registers.
- * @param out_en whether to enable IO output for dummy phase
- * @param out_level dummy output level
- */
-static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev)
-{
-    // dev->ctrl.fdummy_out = out_en; // TODO: IDF-5333 removed
-    dev->ctrl.q_pol = out_lev;
-    dev->ctrl.d_pol = out_lev;
-}
-
 /**
  * Set CS hold time.
  *
@@ -551,25 +550,44 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_
  */
 static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
 {
-    // TODO: IDF-5333
-    // // TODO: Default is PLL480M, this is hard-coded.
-    // // In the future, we can get the CPU clock source by calling interface.
-    // uint8_t clock_val = 0;
-    // switch (SPIMEM0.core_clk_sel.spi01_clk_sel) {
-    // case 0:
-    //     clock_val = 80;
-    //     break;
-    // case 1:
-    //     clock_val = 120;
-    //     break;
-    // case 2:
-    //     clock_val = 160;
-    //     break;
-    // default:
-    //     abort();
-    // }
-    // return clock_val;
-    return 80;
+    // TODO: Default is PLL480M, this is hard-coded.
+    // In the future, we can get the CPU clock source by calling interface.
+    uint8_t clock_val = 0;
+
+    if (PCR.sysclk_conf.soc_clk_sel == 1) {
+        switch (PCR.mspi_clk_conf.mspi_fast_hs_div_num) {
+        case 3:
+            clock_val = 120;
+            break;
+        case 4:
+            clock_val = 96;
+            break;
+        case 5:
+            clock_val = 80;
+            break;
+        default:
+            HAL_ASSERT(false);
+        }
+    } else {
+        // If the system clock source is XTAL/FOSC
+        switch (PCR.mspi_clk_conf.mspi_fast_ls_div_num) {
+        case 0:
+            clock_val = 40;
+            break;
+        case 1:
+            clock_val = 20;
+            break;
+        case 2:
+            clock_val = 10;
+            break;
+        default:
+            HAL_ASSERT(false);
+        }
+    }
+    // Hard-coded line, will be removed when pll is enabled.
+    clock_val = 80;
+
+    return clock_val;
 }
 
 /**

components/hal/spi_flash_hal.c

@@ -23,7 +23,7 @@ static const char *TAG = "flash_hal";
 static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
 {
     int clk_source = cfg->clock_src_freq;
-    // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz, // TODO: IDF-5333 (check this)
+    // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz
     // If user passes freq_mhz like 26 or 27, it's allowed to use integer divider 3.
     // However on other chips or on other frequency, we only allow user pass frequency which
     // can be integer divided. If no, the following strategy is round up the division and

components/hal/spi_flash_hal_common.inc

@@ -105,12 +105,28 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
     // The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
     spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
 #else
-    // On ESP32, dummy output is not supported. These dummy bits will be moved into the address
-    // phase (and appended as ones).
+    /**
+     * - On current chips, addr phase can support 32 bits at most.
+     * - Flash chip requires continuous mode bits
+     *
+     * We send continuous mode bits via the dummy output feature, so as to support
+     * 32-bit address.
+     *
+     * On chips without dummy output feature (ESP32, ESP32C6), we fallback to use
+     * addr phase to send the continuous mode bits:
+     * - On ESP32 (QIO), qio_dummy: 6 - 4 / 4 = 5, addr_bitlen: 24 + 4 = 28. (This
+     *   setting exists for long time, we keep this on ESP32)
+     * - On ESP32C6 (QIO), qio_dummy: 6 - 8 / 4 = 4, addr_bitlen: 24 + 8 = 32
+     * - On future chips without dummy output feature, we follow the ESP32C6 (QIO)
+     *   way.
+     * - Above two ways, the timings are same.
+     * - DIO is similar.
+     */
     if (conf_required) {
         int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
-        dummy_cyclelen_base -= 4 / line_width;
-        addr_bitlen += 4;   //extra 4 bits indicate the conf bits is included
+        dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
+        addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
+        spi_flash_ll_set_extra_address(dev, 0);
     }
 #endif
 

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -635,10 +635,6 @@ config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
     bool
     default y
 
-config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
-    bool
-    default y
-
 config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -317,7 +317,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT 1
 #define SOC_SPI_MAX_PRE_DIVIDER 16
 
-// TODO: IDF-5333 (Copy from esp32c3, need check)
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
@@ -328,7 +327,6 @@
 
 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED         1
 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
 
 // TODO: IDF-5323 (Copy from esp32c3, need check)

components/soc/esp32c6/spi_periph.c

@@ -11,7 +11,7 @@
  Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
-    { // TODO: IDF-5333 Need check
+    {
         .spiclk_in = 0,/* SPI clock is not an input signal*/
         .spics_in = 0,/* SPI cs is not an input signal*/
         .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,

components/spi_flash/.build-test-rules.yml

@@ -4,7 +4,7 @@ components/spi_flash/test_apps/esp_flash:
   disable:
     - if: IDF_TARGET == "esp32c6"
       temporary: true
-      reason: target esp32c6 is not supported yet
+      reason: target esp32c6 cannot pass atomic build
 
 components/spi_flash/test_apps/flash_encryption:
   disable_test:

components/spi_flash/esp32c6/flash_ops_esp32c6.c

@@ -29,7 +29,6 @@ esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
     SPIFLASH.user.fwrite_dual = 0;
     SPIFLASH.user.fwrite_qio = 1;
     SPIFLASH.user.fwrite_quad = 0;
-    // SPIFLASH.ctrl.fcmd_dual = 0; // TODO: IDF-5333
     SPIFLASH.ctrl.fcmd_quad = 0;
     SPIFLASH.user.usr_dummy = 0;
     SPIFLASH.user.usr_addr = 1;
@@ -53,7 +52,8 @@ esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
 
 esp_err_t spi_flash_enable_wrap(uint32_t wrap_size)
 {
-    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL2_REG(0), SPI_MEM_SPLIT_TRANS_EN_M); // TODO: IDF-5333 Newly added
+    // IDF-6198 TODO: support wrap on esp32-c6
+    CLEAR_PERI_REG_MASK(SPI_MEM_CTRL2_REG(0), SPI_MEM_SPLIT_TRANS_EN_M);
     switch (wrap_size) {
     case 8:
         return spi_flash_wrap_set(FLASH_WRAP_MODE_8B);

components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h

@@ -80,6 +80,23 @@
 #define FSPI_PIN_NUM_WP     5
 #define FSPI_PIN_NUM_CS     10
 
+// Just use the same pins for HSPI
+#define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
+#define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
+#define HSPI_PIN_NUM_CLK    FSPI_PIN_NUM_CLK
+#define HSPI_PIN_NUM_HD     FSPI_PIN_NUM_HD
+#define HSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
+#define HSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
+
+#elif CONFIG_IDF_TARGET_ESP32C6
+
+#define FSPI_PIN_NUM_MOSI   7
+#define FSPI_PIN_NUM_MISO   2
+#define FSPI_PIN_NUM_CLK    6
+#define FSPI_PIN_NUM_HD     4
+#define FSPI_PIN_NUM_WP     5
+#define FSPI_PIN_NUM_CS     17
+
 // Just use the same pins for HSPI
 #define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
 #define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
@@ -115,7 +132,7 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part);
 #define BYPASS_MULTIPLE_CHIP    1
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
 //chips without PSRAM
 #define TEST_CHIP_NUM   2
 #elif CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
@@ -223,7 +240,7 @@ flashtest_config_t config_list[] = {
         .input_delay_ns = 0,
     },
 };
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
 flashtest_config_t config_list[] = {
     /* No SPI1 CS1 flash on esp32c3 test */
     {

components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c

@@ -40,6 +40,8 @@
 #include "esp32h2/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c2/rom/cache.h"
 #endif
 
 #define FUNC_SPI    1

components/spi_flash/test_apps/flash_mmap/main/test_mmap.c

@@ -165,7 +165,7 @@ TEST_CASE("Can mmap into data address space", "[spi_flash][mmap]")
     TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
 }
 
-#if !(CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2)
+#if !(CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6)
 /* On S3/C3/C2 the cache is programmatically split between Icache and dcache and with the default setup we dont leave a lot pages
    available for additional mmaps into instruction space. Disabling this test for now since any hypothetical use case for this
    is no longer supported "out of the box"