Merge branch 'feature/support_esp8684_esp32h2_ledc' into 'master'

ledc: Provide support for esp32c2 and esp32h2

Closes IDF-4347, IDF-3900, IDF-4157, and IDF-4648

See merge request espressif/esp-idf!17071

components/driver/include/driver/ledc.h

@@ -15,8 +15,21 @@
 extern "C" {
 #endif
 
-#define LEDC_APB_CLK_HZ         (APB_CLK_FREQ)
-#define LEDC_REF_CLK_HZ         (REF_CLK_FREQ)
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+/**
+ * @brief Frequency of one of the LEDC peripheral clock sources, APB_CLK
+ * @note  This macro should have no use in your application, we keep it here only for backward compatible
+ */
+#define LEDC_APB_CLK_HZ _Pragma ("GCC warning \"'LEDC_APB_CLK_HZ' macro is deprecated\"") (APB_CLK_FREQ)
+#endif
+#if SOC_LEDC_SUPPORT_REF_TICK
+/**
+ * @brief Frequency of one of the LEDC peripheral clock sources, REF_TICK
+ * @note  This macro should have no use in your application, we keep it here only for backward compatible
+ */
+#define LEDC_REF_CLK_HZ _Pragma ("GCC warning \"'LEDC_REF_CLK_HZ' macro is deprecated\"") (REF_CLK_FREQ)
+#endif
+
 #define LEDC_ERR_DUTY           (0xFFFFFFFF)
 #define LEDC_ERR_VAL            (-1)
 
@@ -48,9 +61,13 @@ typedef struct {
     };
     ledc_timer_t  timer_num;               /*!< The timer source of channel (0 - 3) */
     uint32_t freq_hz;                      /*!< LEDC timer frequency (Hz) */
-    ledc_clk_cfg_t clk_cfg;                /*!< Configure LEDC source clock.
-                                                For low speed channels and high speed channels, you can specify the source clock using LEDC_USE_REF_TICK, LEDC_USE_APB_CLK or LEDC_AUTO_CLK.
-                                                For low speed channels, you can also specify the source clock using LEDC_USE_RTC8M_CLK, in this case, all low speed channel's source clock must be RTC8M_CLK*/
+    ledc_clk_cfg_t clk_cfg;                /*!< Configure LEDC source clock from ledc_clk_cfg_t.
+                                                Note that LEDC_USE_RTC8M_CLK and LEDC_USE_XTAL_CLK are
+                                                non-timer-specific clock sources. You can not have one LEDC timer uses
+                                                RTC8M_CLK as the clock source and have another LEDC timer uses XTAL_CLK
+                                                as its clock source. All chips except esp32 and esp32s2 do not have
+                                                timer-specific clock sources, which means clock source for all timers
+                                                must be the same one. */
 } ledc_timer_config_t;
 
 typedef intr_handle_t ledc_isr_handle_t;

components/driver/ledc.c

@@ -26,6 +26,8 @@ static __attribute__((unused)) const char *LEDC_TAG = "ledc";
 #define LEDC_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, LEDC_TAG, "%s", str)
 #define LEDC_ARG_CHECK(a, param) ESP_RETURN_ON_FALSE(a, ESP_ERR_INVALID_ARG, LEDC_TAG, param " argument is invalid")
 
+#define LEDC_CLK_NOT_FOUND  0
+
 typedef enum {
     LEDC_FSM_IDLE,
     LEDC_FSM_HW_FADE,
@@ -60,15 +62,9 @@ static ledc_isr_handle_t s_ledc_fade_isr_handle = NULL;
 static portMUX_TYPE ledc_spinlock = portMUX_INITIALIZER_UNLOCKED;
 
 #define LEDC_VAL_NO_CHANGE        (-1)
-#define LEDC_STEP_NUM_MAX         (1023)
+#define LEDC_DUTY_NUM_MAX         LEDC_LL_DUTY_NUM_MAX            // Maximum steps per hardware fade
 #define LEDC_DUTY_DECIMAL_BIT_NUM (4)
 #define LEDC_TIMER_DIV_NUM_MAX    (0x3FFFF)
-#define LEDC_DUTY_NUM_MAX         (LEDC_DUTY_NUM_LSCH0_V)
-#define LEDC_DUTY_CYCLE_MAX       (LEDC_DUTY_CYCLE_LSCH0_V)
-#define LEDC_DUTY_SCALE_MAX       (LEDC_DUTY_SCALE_LSCH0_V)
-#define LEDC_HPOINT_VAL_MAX       (LEDC_HPOINT_LSCH1_V)
-#define DELAY_CLK8M_CLK_SWITCH    (5)
-#define SLOW_CLK_CYC_CALIBRATE    (13)
 #define LEDC_FADE_TOO_SLOW_STR    "LEDC FADE TOO SLOW"
 #define LEDC_FADE_TOO_FAST_STR    "LEDC FADE TOO FAST"
 #define DIM(array)                (sizeof(array)/sizeof(*array))
@@ -81,6 +77,11 @@ static __attribute__((unused)) const char *LEDC_FADE_INIT_ERROR_STR = "LEDC fade
 //This value will be calibrated when in use.
 static uint32_t s_ledc_slow_clk_8M = 0;
 
+static const ledc_slow_clk_sel_t s_glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
+#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+static const struct { ledc_clk_src_t clk; uint32_t freq; } s_timer_specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
+#endif
+
 static void ledc_ls_timer_update(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
 {
     if (speed_mode == LEDC_LOW_SPEED_MODE) {
@@ -100,7 +101,12 @@ static bool ledc_slow_clk_calibrate(void)
 {
     if (periph_rtc_dig_clk8m_enable()) {
         s_ledc_slow_clk_8M = periph_rtc_dig_clk8m_get_freq();
+#if CONFIG_IDF_TARGET_ESP32H2
+        /* Workaround: Calibration cannot be done for CLK8M on H2, we just use its theoretic frequency */
+        ESP_LOGD(LEDC_TAG, "Calibration cannot be performed, approximate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M);
+#else
         ESP_LOGD(LEDC_TAG, "Calibrate CLK8M_CLK : %d Hz", s_ledc_slow_clk_8M);
+#endif
         return true;
     }
     ESP_LOGE(LEDC_TAG, "Calibrate CLK8M_CLK failed");
@@ -110,13 +116,19 @@ static bool ledc_slow_clk_calibrate(void)
 static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg)
 {
     uint32_t src_clk_freq = 0;
-    if (clk_cfg == LEDC_USE_APB_CLK) {
-        src_clk_freq = LEDC_APB_CLK_HZ;
-    } else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
+    if (clk_cfg == LEDC_USE_RTC8M_CLK) {
         src_clk_freq = s_ledc_slow_clk_8M;
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+    } else if (clk_cfg == LEDC_USE_APB_CLK) {
+        src_clk_freq = esp_clk_apb_freq();
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    } else if (clk_cfg == LEDC_USE_PLL_DIV_CLK) {
+        src_clk_freq = LEDC_LL_PLL_DIV_CLK_FREQ;
+#endif
 #if SOC_LEDC_SUPPORT_REF_TICK
     } else if (clk_cfg == LEDC_USE_REF_TICK) {
-        src_clk_freq = LEDC_REF_CLK_HZ;
+        src_clk_freq = REF_CLK_FREQ;
 #endif
 #if SOC_LEDC_SUPPORT_XTAL_CLOCK
     } else if (clk_cfg == LEDC_USE_XTAL_CLK) {
@@ -132,9 +144,16 @@ static uint32_t ledc_get_glb_clk_freq(ledc_slow_clk_sel_t clk_cfg)
     uint32_t src_clk_freq = 0;
 
     switch (clk_cfg) {
+#if SOC_LEDC_SUPPORT_APB_CLOCK
         case LEDC_SLOW_CLK_APB:
-            src_clk_freq = LEDC_APB_CLK_HZ;
+            src_clk_freq = esp_clk_apb_freq();
             break;
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+        case LEDC_SLOW_CLK_PLL_DIV:
+            src_clk_freq = LEDC_LL_PLL_DIV_CLK_FREQ;
+            break;
+#endif
         case LEDC_SLOW_CLK_RTC8M:
             src_clk_freq = s_ledc_slow_clk_8M;
             break;
@@ -329,52 +348,46 @@ static inline uint32_t ledc_calculate_divisor(uint32_t src_clk_freq, int freq_hz
 
 static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precision, ledc_slow_clk_sel_t* clk_target)
 {
-    uint32_t div_param = 0;
-    uint32_t i = 0;
+    uint32_t ret = LEDC_CLK_NOT_FOUND;
     uint32_t clk_freq = 0;
+
     /* This function will go through all the following clock sources to look
      * for a valid divisor which generates the requested frequency. */
-    const ledc_slow_clk_sel_t glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
-
-    for (i = 0; i < DIM(glb_clks); i++) {
+    for (int i = 0; i < DIM(s_glb_clks); i++) {
         /* Before calculating the divisor, we need to have the RTC frequency.
-         * If it hasn't been mesured yet, try calibrating it now. */
-        if (glb_clks[i] == LEDC_SLOW_CLK_RTC8M && s_ledc_slow_clk_8M == 0 && !ledc_slow_clk_calibrate()) {
+         * If it hasn't been measured yet, try calibrating it now. */
+        if (s_glb_clks[i] == LEDC_SLOW_CLK_RTC8M && s_ledc_slow_clk_8M == 0 && !ledc_slow_clk_calibrate()) {
             ESP_LOGD(LEDC_TAG, "Unable to retrieve RTC clock frequency, skipping it\n");
             continue;
         }
 
-        clk_freq = ledc_get_glb_clk_freq(glb_clks[i]);
-        div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
+        clk_freq = ledc_get_glb_clk_freq(s_glb_clks[i]);
+        uint32_t div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
 
         /* If the divisor is valid, we can return this value. */
         if (!LEDC_IS_DIV_INVALID(div_param)) {
-            *clk_target = glb_clks[i];
+            *clk_target = s_glb_clks[i];
+            ret = div_param;
             break;
         }
     }
 
-    return div_param;
-
+    return ret;
 }
 
 #if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
 static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
                                                             ledc_clk_src_t* clk_source)
 {
-    uint32_t div_param = 0;
-    uint32_t i = 0;
+    uint32_t ret = LEDC_CLK_NOT_FOUND;
 
-    /* Use an anonymous structure, only this function requires it.
-     * Get the list of the timer-specific clocks, try to find one for the reuested frequency.  */
-    const struct { ledc_clk_src_t clk; uint32_t freq; } specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
-
-    for (i = 0; i < DIM(specific_clks); i++) {
-        div_param = ledc_calculate_divisor(specific_clks[i].freq, freq_hz, precision);
+    for (int i = 0; i < DIM(s_timer_specific_clks); i++) {
+        uint32_t div_param = ledc_calculate_divisor(s_timer_specific_clks[i].freq, freq_hz, precision);
 
         /* If the divisor is valid, we can return this value. */
         if (!LEDC_IS_DIV_INVALID(div_param)) {
-            *clk_source = specific_clks[i].clk;
+            *clk_source = s_timer_specific_clks[i].clk;
+            ret = div_param;
             break;
         }
     }
@@ -383,17 +396,18 @@ static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mo
     /* On board that support LEDC high-speed mode, APB clock becomes a timer-
      * specific clock when in high speed mode. Check if it is necessary here
      * to test APB. */
-    if (speed_mode == LEDC_HIGH_SPEED_MODE && i == DIM(specific_clks)) {
+    if (speed_mode == LEDC_HIGH_SPEED_MODE && ret == LEDC_CLK_NOT_FOUND) {
         /* No divider was found yet, try with APB! */
-        div_param = ledc_calculate_divisor(LEDC_APB_CLK_HZ, freq_hz, precision);
+        uint32_t div_param = ledc_calculate_divisor(esp_clk_apb_freq(), freq_hz, precision);
 
         if (!LEDC_IS_DIV_INVALID(div_param)) {
             *clk_source = LEDC_APB_CLK;
+            ret = div_param;
         }
     }
 #endif
 
-    return div_param;
+    return ret;
 }
 #endif
 
@@ -404,38 +418,48 @@ static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mo
 static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
                                       ledc_clk_src_t* clk_source, ledc_slow_clk_sel_t* clk_target)
 {
-    uint32_t div_param = 0;
+    uint32_t ret = LEDC_CLK_NOT_FOUND;
 
 #if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
     /* If the SoC presents timer-specific clock(s), try to achieve the given frequency
      * thanks to it/them.
      * clk_source parameter will returned by this function. */
-    div_param = ledc_auto_timer_specific_clk_divisor(speed_mode, freq_hz, precision, clk_source);
+    uint32_t div_param_timer = ledc_auto_timer_specific_clk_divisor(speed_mode, freq_hz, precision, clk_source);
 
-    if (!LEDC_IS_DIV_INVALID(div_param)) {
+    if (div_param_timer != LEDC_CLK_NOT_FOUND) {
         /* The dividor is valid, no need try any other clock, return directly. */
-        return div_param;
+        ret = div_param_timer;
     }
 #endif
 
     /* On ESP32, only low speed channel can use the global clocks. For other
      * chips, there are no high speed channels. */
-    if (speed_mode == LEDC_LOW_SPEED_MODE) {
-        div_param = ledc_auto_global_clk_divisor(freq_hz, precision, clk_target);
+    if (ret == LEDC_CLK_NOT_FOUND && speed_mode == LEDC_LOW_SPEED_MODE) {
+        uint32_t div_param_global = ledc_auto_global_clk_divisor(freq_hz, precision, clk_target);
+        if (div_param_global != LEDC_CLK_NOT_FOUND) {
+            *clk_source = LEDC_SCLK;
+            ret = div_param_global;
+        }
     }
 
-    return div_param;
+    return ret;
 }
 
 static ledc_slow_clk_sel_t ledc_clk_cfg_to_global_clk(const ledc_clk_cfg_t clk_cfg)
 {
-    /* Initialization required for preventing a compiler warning */
-    ledc_slow_clk_sel_t glb_clk = LEDC_SLOW_CLK_APB;
+    ledc_slow_clk_sel_t glb_clk;
 
     switch (clk_cfg) {
+#if SOC_LEDC_SUPPORT_APB_CLOCK
         case LEDC_USE_APB_CLK:
             glb_clk = LEDC_SLOW_CLK_APB;
             break;
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+        case LEDC_USE_PLL_DIV_CLK:
+            glb_clk = LEDC_SLOW_CLK_PLL_DIV;
+            break;
+#endif
         case LEDC_USE_RTC8M_CLK:
             glb_clk = LEDC_SLOW_CLK_RTC8M;
             break;
@@ -450,7 +474,7 @@ static ledc_slow_clk_sel_t ledc_clk_cfg_to_global_clk(const ledc_clk_cfg_t clk_c
         default:
             /* We should not get here, REF_TICK is NOT a global clock,
              * it is a timer-specific clock. */
-            assert(false);
+            abort();
     }
 
     return glb_clk;
@@ -465,36 +489,37 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
 {
     uint32_t div_param = 0;
     const uint32_t precision = ( 0x1 << duty_resolution );
-    /* This variable represents the timer's mux value. It will be overwritten
-     * if a timer-specific clock is used. */
-    ledc_clk_src_t timer_clk_src = LEDC_SCLK;
-    /* Store the global clock. */
-    ledc_slow_clk_sel_t glb_clk = LEDC_SLOW_CLK_APB;
-    uint32_t src_clk_freq = 0;
+    /* The clock sources are not initialized on purpose. To produce compiler warning if used but the selector functions
+     * don't set them properly. */
+    /* Timer-specific mux. Set to timer-specific clock or LEDC_SCLK if a global clock is used. */
+    ledc_clk_src_t timer_clk_src;
+    /* Global clock mux. Should be set when LEDC_SCLK is used in LOW_SPEED_MODE. Otherwise left uninitialized. */
+    ledc_slow_clk_sel_t glb_clk;
 
     if (clk_cfg == LEDC_AUTO_CLK) {
         /* User hasn't specified the speed, we should try to guess it. */
         div_param = ledc_auto_clk_divisor(speed_mode, freq_hz, precision, &timer_clk_src, &glb_clk);
-
     } else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
         /* User specified source clock(RTC8M_CLK) for low speed channel.
          * Make sure the speed mode is correct. */
         ESP_RETURN_ON_FALSE((speed_mode == LEDC_LOW_SPEED_MODE), ESP_ERR_INVALID_ARG, LEDC_TAG, "RTC clock can only be used in low speed mode");
 
         /* Before calculating the divisor, we need to have the RTC frequency.
-         * If it hasn't been mesured yet, try calibrating it now. */
+         * If it hasn't been measured yet, try calibrating it now. */
         if(s_ledc_slow_clk_8M == 0 && ledc_slow_clk_calibrate() == false) {
             goto error;
         }
 
-        /* We have the RTC clock frequency now. */
-        div_param = ledc_calculate_divisor(s_ledc_slow_clk_8M, freq_hz, precision);
-
         /* Set the global clock source */
+        timer_clk_src = LEDC_SCLK;
         glb_clk =  LEDC_SLOW_CLK_RTC8M;
 
+        /* We have the RTC clock frequency now. */
+        div_param = ledc_calculate_divisor(s_ledc_slow_clk_8M, freq_hz, precision);
+        if (LEDC_IS_DIV_INVALID(div_param)) {
+            div_param = LEDC_CLK_NOT_FOUND;
+        }
     } else {
-
 #if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
         if (LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(speed_mode, clk_cfg)) {
             /* Currently we can convert a timer-specific clock to a source clock that
@@ -505,14 +530,18 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
         } else
 #endif
         {
+            timer_clk_src = LEDC_SCLK;
             glb_clk = ledc_clk_cfg_to_global_clk(clk_cfg);
         }
 
-        src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
+        uint32_t src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
         div_param = ledc_calculate_divisor(src_clk_freq, freq_hz, precision);
+        if (LEDC_IS_DIV_INVALID(div_param)) {
+            div_param = LEDC_CLK_NOT_FOUND;
+        }
     }
 
-    if (LEDC_IS_DIV_INVALID(div_param)) {
+    if (div_param == LEDC_CLK_NOT_FOUND) {
         goto error;
     }
 
@@ -521,20 +550,25 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
              timer_clk_src, (speed_mode == LEDC_LOW_SPEED_MODE ? "slow" : "fast"), div_param);
 
     /* The following block configures the global clock.
-     * Thus, in theory, this only makes sense when the source clock is LEDC_SCLK
-     * and in LOW_SPEED_MODE (as FAST_SPEED_MODE doesn't present any global clock)
-     *
-     * However, in practice, on modules that support high-speed mode, no matter
-     * whether the source clock is a timer-specific one (e.g. REF_TICK) or not,
-     * the global clock MUST be configured when in low speed mode.
-     * When using high-speed mode, this is not necessary.
+     * Thus, in theory, this only makes sense when configuring the LOW_SPEED timer and the source clock is LEDC_SCLK (as
+     * HIGH_SPEED timers won't be clocked by the global clock). However, there are some limitations due to HW design.
      */
-#if SOC_LEDC_SUPPORT_HS_MODE
     if (speed_mode == LEDC_LOW_SPEED_MODE) {
+#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+        /* On ESP32 and ESP32-S2, when the source clock of LOW_SPEED timer is a timer-specific one (i.e. REF_TICK), the
+         * global clock MUST be set to APB_CLK. For HIGH_SPEED timers, this is not necessary.
+         */
+        if (timer_clk_src != LEDC_SCLK) {
+            glb_clk = LEDC_SLOW_CLK_APB;
+        }
 #else
-    if (timer_clk_src == LEDC_SCLK) {
+        /* On later chips, there is only one type of timer/channel (referred as LOW_SPEED in the code), which can only be
+         * clocked by the global clock. So there's no limitation on the global clock, except that it must be set.
+         */
+        assert(timer_clk_src == LEDC_SCLK);
 #endif
-        ESP_LOGD(LEDC_TAG, "In slow speed mode, using clock %d", glb_clk);
+        ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
+
         portENTER_CRITICAL(&ledc_spinlock);
         ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);
         portEXIT_CRITICAL(&ledc_spinlock);
@@ -546,6 +580,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
     /* Reset the timer. */
     ledc_timer_rst(speed_mode, timer_num);
     return ESP_OK;
+
 error:
     ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=%d",
              (uint32_t ) div_param);
@@ -683,9 +718,9 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
     LEDC_ARG_CHECK(fade_direction < LEDC_DUTY_DIR_MAX, "fade_direction");
-    LEDC_ARG_CHECK(step_num <= LEDC_DUTY_NUM_MAX, "step_num");
-    LEDC_ARG_CHECK(duty_cyle_num <= LEDC_DUTY_CYCLE_MAX, "duty_cycle_num");
-    LEDC_ARG_CHECK(duty_scale <= LEDC_DUTY_SCALE_MAX, "duty_scale");
+    LEDC_ARG_CHECK(step_num <= LEDC_LL_DUTY_NUM_MAX, "step_num");
+    LEDC_ARG_CHECK(duty_cyle_num <= LEDC_LL_DUTY_CYCLE_MAX, "duty_cycle_num");
+    LEDC_ARG_CHECK(duty_scale <= LEDC_LL_DUTY_SCALE_MAX, "duty_scale");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
     _ledc_fade_hw_acquire(speed_mode, channel);
     portENTER_CRITICAL(&ledc_spinlock);
@@ -707,7 +742,7 @@ esp_err_t ledc_set_duty_with_hpoint(ledc_mode_t speed_mode, ledc_channel_t chann
 {
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
-    LEDC_ARG_CHECK(hpoint <= LEDC_HPOINT_VAL_MAX, "hpoint");
+    LEDC_ARG_CHECK(hpoint <= LEDC_LL_HPOINT_VAL_MAX, "hpoint");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
     /* The channel configuration should not be changed before the fade operation is done. */
     _ledc_fade_hw_acquire(speed_mode, channel);
@@ -773,7 +808,7 @@ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(timer_num < LEDC_TIMER_MAX, "timer_num");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
-    ledc_clk_cfg_t clk_cfg = LEDC_USE_APB_CLK;
+    ledc_clk_cfg_t clk_cfg = LEDC_AUTO_CLK;
     uint32_t duty_resolution = 0;
     ledc_hal_get_clk_cfg(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clk_cfg);
     ledc_hal_get_duty_resolution(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &duty_resolution);
@@ -788,13 +823,17 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num)
     portENTER_CRITICAL(&ledc_spinlock);
     uint32_t clock_divider = 0;
     uint32_t duty_resolution = 0;
-    ledc_clk_cfg_t clk_cfg = LEDC_USE_APB_CLK;
+    ledc_clk_cfg_t clk_cfg = LEDC_AUTO_CLK;
     ledc_hal_get_clock_divider(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clock_divider);
     ledc_hal_get_duty_resolution(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &duty_resolution);
     ledc_hal_get_clk_cfg(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clk_cfg);
     uint32_t precision = (0x1 << duty_resolution);
     uint32_t src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
     portEXIT_CRITICAL(&ledc_spinlock);
+    if (clock_divider == 0) {
+        ESP_LOGW(LEDC_TAG, "LEDC timer not configured, call ledc_timer_config to set timer frequency");
+        return 0;
+    }
     return ((uint64_t) src_clk_freq << 8) / precision / clock_divider;
 }
 
@@ -864,7 +903,7 @@ void IRAM_ATTR ledc_fade_isr(void *arg)
                             (duty_cur - duty_tar) : (duty_tar - duty_cur);
                 if (delta > scale) {
                     next_duty = duty_cur;
-                    step = (delta / scale > LEDC_STEP_NUM_MAX) ? LEDC_STEP_NUM_MAX : (delta / scale);
+                    step = (delta / scale > LEDC_DUTY_NUM_MAX) ? LEDC_DUTY_NUM_MAX : (delta / scale);
                     cycle = s_ledc_fade_rec[speed_mode][channel]->cycle_num;
                 } else {
                     next_duty = duty_tar;
@@ -990,12 +1029,12 @@ static esp_err_t _ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t
         if (duty_cur > target_duty) {
             s_ledc_fade_rec[speed_mode][channel]->direction = LEDC_DUTY_DIR_DECREASE;
             step_num = (duty_cur - target_duty) / scale;
-            step_num = step_num > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : step_num;
+            step_num = step_num > LEDC_DUTY_NUM_MAX ? LEDC_DUTY_NUM_MAX : step_num;
         } else {
             s_ledc_fade_rec[speed_mode][channel]->direction = LEDC_DUTY_DIR_INCREASE;
             dir = LEDC_DUTY_DIR_INCREASE;
             step_num = (target_duty - duty_cur) / scale;
-            step_num = step_num > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : step_num;
+            step_num = step_num > LEDC_DUTY_NUM_MAX ? LEDC_DUTY_NUM_MAX : step_num;
         }
     }
 
@@ -1036,16 +1075,16 @@ static esp_err_t _ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t
     if (total_cycles > duty_delta) {
         scale = 1;
         cycle_num = total_cycles / duty_delta;
-        if (cycle_num > LEDC_DUTY_NUM_MAX) {
+        if (cycle_num > LEDC_LL_DUTY_NUM_MAX) {
             ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_SLOW_STR);
-            cycle_num = LEDC_DUTY_NUM_MAX;
+            cycle_num = LEDC_LL_DUTY_NUM_MAX;
         }
     } else {
         cycle_num = 1;
         scale = duty_delta / total_cycles;
-        if (scale > LEDC_DUTY_SCALE_MAX) {
+        if (scale > LEDC_LL_DUTY_SCALE_MAX) {
             ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_FAST_STR);
-            scale = LEDC_DUTY_SCALE_MAX;
+            scale = LEDC_LL_DUTY_SCALE_MAX;
         }
     }
     return _ledc_set_fade_with_step(speed_mode, channel, target_duty, scale, cycle_num);
@@ -1092,8 +1131,8 @@ esp_err_t ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t channel
 {
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
-    LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale");
-    LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num");
+    LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_LL_DUTY_SCALE_MAX), "fade scale");
+    LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_LL_DUTY_CYCLE_MAX), "cycle_num");
     LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
     LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK, LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
@@ -1207,7 +1246,7 @@ esp_err_t ledc_set_duty_and_update(ledc_mode_t speed_mode, ledc_channel_t channe
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
     LEDC_ARG_CHECK(duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
-    LEDC_ARG_CHECK(hpoint <= LEDC_HPOINT_VAL_MAX, "hpoint");
+    LEDC_ARG_CHECK(hpoint <= LEDC_LL_HPOINT_VAL_MAX, "hpoint");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
     LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK, LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
     _ledc_fade_hw_acquire(speed_mode, channel);
@@ -1242,8 +1281,8 @@ esp_err_t ledc_set_fade_step_and_start(ledc_mode_t speed_mode, ledc_channel_t ch
     LEDC_ARG_CHECK(fade_mode < LEDC_FADE_MAX, "fade_mode");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
     LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK, LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
-    LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale");
-    LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num");
+    LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_LL_DUTY_SCALE_MAX), "fade scale");
+    LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_LL_DUTY_CYCLE_MAX), "cycle_num");
     LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
     _ledc_op_lock_acquire(speed_mode, channel);
     _ledc_fade_hw_acquire(speed_mode, channel);

components/driver/test/test_ledc.c

@@ -24,6 +24,7 @@
 #include "soc/io_mux_reg.h"
 #include "esp_system.h"
 #include "driver/ledc.h"
+#include "hal/ledc_ll.h"
 #include "driver/gpio.h"
 
 #define PULSE_IO      18
@@ -38,6 +39,12 @@
 #define SPEED_MODE_LIST {LEDC_LOW_SPEED_MODE}
 #endif
 
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+#define TEST_DEFAULT_CLK_CFG LEDC_USE_APB_CLK
+#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+#define TEST_DEFAULT_CLK_CFG LEDC_USE_PLL_DIV_CLK
+#endif
+
 static ledc_channel_config_t initialize_channel_config(void)
 {
     ledc_channel_config_t config;
@@ -60,7 +67,7 @@ static ledc_timer_config_t create_default_timer_config(void)
     ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT;
     ledc_time_config.timer_num = LEDC_TIMER_0;
     ledc_time_config.freq_hz = TEST_PWM_FREQ;
-    ledc_time_config.clk_cfg = LEDC_USE_APB_CLK;
+    ledc_time_config.clk_cfg = TEST_DEFAULT_CLK_CFG;
     return ledc_time_config;
 }
 
@@ -178,7 +185,7 @@ TEST_CASE("LEDC timer config basic parameter test", "[ledc]")
     TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
 }
 
-TEST_CASE("LEDC error log channel and timer config", "[ledc]")
+TEST_CASE("LEDC output idle level test", "[ledc]")
 {
     const ledc_mode_t test_speed_mode = TEST_SPEED_MODE;
     ledc_channel_config_t ledc_ch_config = initialize_channel_config();
@@ -390,7 +397,7 @@ TEST_CASE("LEDC fade stop test", "[ledc]")
 }
 #endif // SOC_LEDC_SUPPORT_FADE_STOP
 
-#if SOC_PCNT_SUPPORTED
+#if SOC_PCNT_SUPPORTED // Note. C3, C2, H2 do not have PCNT peripheral, the following test cases cannot be tested
 
 #include "driver/pulse_cnt.h"
 
@@ -487,7 +494,29 @@ TEST_CASE("LEDC set and get frequency", "[ledc][timeout=60][ignore]")
     tear_testbench();
 }
 
-TEST_CASE("LEDC timer set", "[ledc]")
+static void timer_set_clk_src_and_freq_test(ledc_mode_t speed_mode, ledc_clk_cfg_t clk_src, uint32_t duty_res,
+                                            uint32_t freq_hz)
+{
+    ledc_timer_config_t ledc_time_config = {
+        .speed_mode = speed_mode,
+        .duty_resolution = duty_res,
+        .timer_num = LEDC_TIMER_0,
+        .freq_hz = freq_hz,
+        .clk_cfg = clk_src,
+    };
+    TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
+    vTaskDelay(100 / portTICK_PERIOD_MS);
+    if (clk_src == LEDC_USE_RTC8M_CLK) {
+        // RTC8M_CLK freq is get from calibration, it is reasonable that divider calculation does a rounding
+        TEST_ASSERT_UINT32_WITHIN(5, ledc_get_freq(speed_mode, LEDC_TIMER_0), freq_hz);
+    } else {
+        TEST_ASSERT_EQUAL_INT32(ledc_get_freq(speed_mode, LEDC_TIMER_0), freq_hz);
+    }
+    int count = wave_count(1000);
+    TEST_ASSERT_UINT32_WITHIN(10, count, freq_hz);
+}
+
+TEST_CASE("LEDC timer select specific clock source", "[ledc]")
 {
     setup_testbench();
     const ledc_mode_t test_speed_mode = TEST_SPEED_MODE;
@@ -502,44 +531,32 @@ TEST_CASE("LEDC timer set", "[ledc]")
     };
     TEST_ESP_OK(ledc_channel_config(&ledc_ch_config));
 
-    ledc_timer_config_t ledc_time_config = {
-        .speed_mode = test_speed_mode,
-        .duty_resolution = 13,
-        .timer_num = LEDC_TIMER_0,
-        .freq_hz = 5000,
-        .clk_cfg = LEDC_USE_APB_CLK,
-    };
-    TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
-
-    uint32_t freq_get;
-    int count;
+    if (test_speed_mode == LEDC_LOW_SPEED_MODE) {
+        printf("Check LEDC_USE_RTC8M_CLK for a 100Hz signal\n");
+        timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_RTC8M_CLK, 10, 100);
+#if SOC_LEDC_SUPPORT_XTAL_CLOCK
+        printf("Check LEDC_USE_XTAL_CLK for a 400Hz signal\n");
+        timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_XTAL_CLK, 13, 400);
+#endif
+    }
 #if SOC_LEDC_SUPPORT_REF_TICK
-    //set timer 0 as 250Hz, use REF_TICK
-    TEST_ESP_OK(ledc_timer_set(test_speed_mode, LEDC_TIMER_0, 1000, 10, LEDC_REF_TICK));
-    TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0));
-    TEST_ASSERT_EQUAL_INT32(ledc_get_freq(test_speed_mode, LEDC_TIMER_0), 250);
-    freq_get = ledc_get_freq(test_speed_mode, LEDC_TIMER_0);
-    count = wave_count(1000);
-    TEST_ASSERT_UINT32_WITHIN(10, count, freq_get);
+    printf("Check LEDC_USE_REF_TICK for a 250Hz signal\n");
+    timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_REF_TICK, 10, 250);
+#endif
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+    printf("Check LEDC_USE_APB_CLK for a 500Hz signal\n");
+    timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_APB_CLK, 13, 500);
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    printf("Check LEDC_USE_PLL_DIV_CLK for a 500Hz signal\n");
+    timer_set_clk_src_and_freq_test(test_speed_mode, LEDC_USE_PLL_DIV_CLK, 13, 500);
 #endif
-
-    //set timer 0 as 500Hz, use APB_CLK
-    TEST_ESP_OK(ledc_timer_set(test_speed_mode, LEDC_TIMER_0, 5000, 13, LEDC_APB_CLK));
-    TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0));
-    TEST_ASSERT_EQUAL_INT32(ledc_get_freq(test_speed_mode, LEDC_TIMER_0), 500);
-    freq_get = ledc_get_freq(test_speed_mode, LEDC_TIMER_0);
-    count = wave_count(1000);
-    TEST_ASSERT_UINT32_WITHIN(50, count, freq_get);
 
     printf("Bind channel 0 to timer 0\n");
     TEST_ESP_OK(ledc_bind_channel_timer(test_speed_mode, LEDC_CHANNEL_0, LEDC_TIMER_0));
     vTaskDelay(1000 / portTICK_PERIOD_MS);
     TEST_ASSERT_EQUAL_INT32(ledc_get_freq(test_speed_mode, LEDC_TIMER_0), 500);
 
-    uint32_t current_level = LEDC.channel_group[test_speed_mode].channel[LEDC_CHANNEL_0].conf0.idle_lv;
-    TEST_ESP_OK(ledc_stop(test_speed_mode, LEDC_CHANNEL_0, !current_level));
-    vTaskDelay(1000 / portTICK_PERIOD_MS);
-    TEST_ASSERT_EQUAL_INT32( LEDC.channel_group[test_speed_mode].channel[LEDC_CHANNEL_0].conf0.idle_lv, !current_level);
     tear_testbench();
 }
 
@@ -564,10 +581,11 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]")
         .duty_resolution = LEDC_TIMER_13_BIT,
         .timer_num = LEDC_TIMER_0,
         .freq_hz = 5000,
-        .clk_cfg = LEDC_USE_APB_CLK,
+        .clk_cfg = TEST_DEFAULT_CLK_CFG,
     };
     TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
 
+    vTaskDelay(10 / portTICK_PERIOD_MS);
     count = wave_count(1000);
     TEST_ASSERT_INT16_WITHIN(5, count, 5000);
 

components/esp_hw_support/clk_ctrl_os.c

@@ -9,8 +9,6 @@
 #include "esp_check.h"
 #include "sdkconfig.h"
 
-#define DELAY_RTC_CLK_SWITCH 5
-
 static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
 
 static uint8_t s_periph_ref_counts = 0;
@@ -28,15 +26,13 @@ bool periph_rtc_dig_clk8m_enable(void)
     portENTER_CRITICAL(&periph_spinlock);
     if (s_periph_ref_counts == 0) {
         rtc_dig_clk8m_enable();
-#if CONFIG_IDF_TARGET_ESP32H2
-        s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC32K, 100));
-#else
+#if !CONFIG_IDF_TARGET_ESP32H2
         s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100));
-#endif
         if (s_rtc_clk_freq == 0) {
             portEXIT_CRITICAL(&periph_spinlock);
             return false;
         }
+#endif
     }
     s_periph_ref_counts++;
     portEXIT_CRITICAL(&periph_spinlock);
@@ -45,7 +41,12 @@ bool periph_rtc_dig_clk8m_enable(void)
 
 uint32_t periph_rtc_dig_clk8m_get_freq(void)
 {
+#if CONFIG_IDF_TARGET_ESP32H2
+    /* Workaround: H2 doesn't have 8MD256 clk, so calibration cannot be done, we just return its theoretic frequency */
+    return RTC_FAST_CLK_FREQ_APPROX;
+#else
     return s_rtc_clk_freq * 256;
+#endif
 }
 
 void periph_rtc_dig_clk8m_disable(void)

components/hal/esp32/include/hal/ledc_ll.h

@@ -13,7 +13,12 @@
 #include "soc/ledc_periph.h"
 #include "soc/ledc_struct.h"
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_LSCH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_LSCH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_LSCH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 
@@ -25,7 +30,7 @@
                             {\
                                 { \
                                     .clk = LEDC_REF_TICK, \
-                                    .freq = LEDC_REF_CLK_HZ, \
+                                    .freq = REF_CLK_FREQ, \
                                 } \
                             }
 
@@ -153,6 +158,9 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
  * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
  * @param clk_src Timer clock source
  *
+ * @note  REF_TICK can only be used when hw->conf.slow_clk_sel is set to 1 (through ledc_ll_set_slow_clk_sel()).
+ *        This is ensured in the LEDC driver layer.
+ *
  * @return None
  */
 static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src){

components/hal/esp32c2/include/hal/ledc_ll.h

@@ -11,19 +11,26 @@
 
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_CH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_CH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_CH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_CH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS { \
-                                LEDC_SLOW_CLK_APB, \
+                                LEDC_SLOW_CLK_PLL_DIV, \
                                 LEDC_SLOW_CLK_XTAL, \
                                 LEDC_SLOW_CLK_RTC8M, \
                               }
+#define LEDC_LL_PLL_DIV_CLK_FREQ    (60 * 1000000) // PLL_60M_CLK: 60MHz
 
 
 /**
@@ -37,7 +44,7 @@ extern "C" {
 static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel)
 {
     uint32_t clk_sel_val = 0;
-    if (slow_clk_sel == LEDC_SLOW_CLK_APB) {
+    if (slow_clk_sel == LEDC_SLOW_CLK_PLL_DIV) {
         clk_sel_val = 1;
     } else if (slow_clk_sel == LEDC_SLOW_CLK_RTC8M) {
         clk_sel_val = 2;
@@ -59,11 +66,13 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
 {
     uint32_t clk_sel_val = hw->conf.apb_clk_sel;
     if (clk_sel_val == 1) {
-        *slow_clk_sel = LEDC_SLOW_CLK_APB;
+        *slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV;
     } else if (clk_sel_val == 2) {
         *slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
     } else if (clk_sel_val == 3) {
         *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+    } else {
+        abort();
     }
 }
 
@@ -78,7 +87,7 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
  */
 static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
 {
-    hw->timer_group[speed_mode].timer[timer_sel].conf.low_speed_update = 1;
+    hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1;
 }
 
 /**
@@ -136,7 +145,7 @@ static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode,
  */
 static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider)
 {
-    hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider;
+    hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider;
 }
 
 /**
@@ -151,7 +160,7 @@ static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
  */
 static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider)
 {
-    *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider;
+    *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div;
 }
 
 /**
@@ -166,7 +175,7 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
  */
 static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
 {
-    *clk_src = LEDC_APB_CLK;
+    *clk_src = LEDC_SCLK;
 }
 
 /**
@@ -181,7 +190,7 @@ static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mo
  */
 static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution)
 {
-    hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution;
+    hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution;
 }
 
 /**
@@ -196,7 +205,7 @@ static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed
  */
 static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution)
 {
-    *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution;
+    *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res;
 }
 
 /**
@@ -210,7 +219,7 @@ static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed
  */
 static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
 {
-    hw->channel_group[speed_mode].channel[channel_num].conf0.low_speed_update = 1;
+    hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1;
 }
 
 /**
@@ -226,7 +235,7 @@ static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_m
 static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *max_duty)
 {
     uint32_t timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
-    *max_duty = (1 << (LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution));
+    *max_duty = (1 << (LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_res));
 }
 
 /**
@@ -286,7 +295,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m
  */
 static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val)
 {
-    *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_rd.duty_read >> 4);
+    *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_rd.duty_r >> 4);
 }
 
 /**
@@ -422,7 +431,7 @@ static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode
 static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en)
 {
     uint32_t value = hw->int_ena.val;
-    uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
     hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
 }
 
@@ -439,7 +448,7 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
 static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status)
 {
     uint32_t value = hw->int_st.val;
-    uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
@@ -454,7 +463,7 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
  */
 static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
 {
-    uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
     hw->int_clr.val = BIT(int_en_base + channel_num);
 }
 

components/hal/esp32c3/include/hal/ledc_ll.h

@@ -12,12 +12,18 @@
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
 #include "soc/ledc_struct.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_LSCH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_LSCH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_LSCH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS { \
@@ -64,6 +70,8 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
         *slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
     } else if (clk_sel_val == 3) {
         *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+    } else {
+        abort();
     }
 }
 

components/hal/esp32h2/include/hal/ledc_ll.h

@@ -12,12 +12,18 @@
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
 #include "soc/ledc_struct.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_LSCH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_LSCH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_LSCH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS { \
@@ -64,6 +70,8 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
         *slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
     } else if (clk_sel_val == 3) {
         *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+    } else {
+        abort();
     }
 }
 

components/hal/esp32s2/include/hal/ledc_ll.h

@@ -12,12 +12,18 @@
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
 #include "soc/ledc_struct.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_LSCH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_LSCH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_LSCH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS { \
@@ -29,7 +35,7 @@ extern "C" {
                             {\
                                 { \
                                     .clk = LEDC_REF_TICK, \
-                                    .freq = LEDC_REF_CLK_HZ, \
+                                    .freq = REF_CLK_FREQ, \
                                 } \
                             }
 
@@ -71,6 +77,8 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
         *slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
     } else if (clk_sel_val == 3) {
         *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+    } else {
+        abort();
     }
 }
 
@@ -163,13 +171,14 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
  * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
  * @param clk_src Timer clock source
  *
+ * @note  REF_TICK can only be used when hw->conf.apb_clk_sel is set to 1 (through ledc_ll_set_slow_clk_sel()).
+ *        This is ensured in the LEDC driver layer.
+ *
  * @return None
  */
 static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src){
     if (clk_src == LEDC_REF_TICK) {
-        //REF_TICK can only be used when APB is selected.
         hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1;
-        hw->conf.apb_clk_sel = 1;
     } else {
         hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0;
     }

components/hal/esp32s3/include/hal/ledc_ll.h

@@ -12,12 +12,18 @@
 #include "hal/ledc_types.h"
 #include "soc/ledc_periph.h"
 #include "soc/ledc_struct.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LEDC_LL_GET_HW() &LEDC
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_DUTY_NUM_LSCH0_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_DUTY_CYCLE_LSCH0_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_DUTY_SCALE_LSCH0_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS { \
@@ -64,6 +70,8 @@ static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
         *slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
     } else if (clk_sel_val == 3) {
         *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+    } else {
+        abort();
     }
 }
 

components/hal/include/hal/ledc_hal.h

@@ -1,16 +1,8 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 /*******************************************************************************
  * NOTICE
@@ -376,13 +368,3 @@ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t
  * @return None
  */
 void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg);
-
-/**
- * @brief Config low speed timer clock source with clock config
- *s
- * @param hal Context of the HAL layer
- * @param clk_cfg clock config
- *
- * @return None
- */
-void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg);

components/hal/include/hal/ledc_types.h

@@ -36,7 +36,12 @@ typedef enum {
 
 typedef enum {
     LEDC_SLOW_CLK_RTC8M = 0,  /*!< LEDC low speed timer clock source is 8MHz RTC clock*/
+#if SOC_LEDC_SUPPORT_APB_CLOCK
     LEDC_SLOW_CLK_APB,     /*!< LEDC low speed timer clock source is 80MHz APB clock*/
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    LEDC_SLOW_CLK_PLL_DIV, /*!< LEDC low speed timer clock source is a PLL_DIV clock*/
+#endif
 #if SOC_LEDC_SUPPORT_XTAL_CLOCK
     LEDC_SLOW_CLK_XTAL,    /*!< LEDC low speed timer clock source XTAL clock*/
 #endif
@@ -49,8 +54,13 @@ typedef enum {
  * here.
  */
 typedef enum {
-    LEDC_AUTO_CLK = 0,    /*!< The driver will automatically select the source clock(REF_TICK or APB) based on the giving resolution and duty parameter when init the timer*/
+    LEDC_AUTO_CLK = 0,    /*!< The driver will automatically select the source clock based on the giving resolution and duty parameter when init the timer*/
+#if SOC_LEDC_SUPPORT_APB_CLOCK
     LEDC_USE_APB_CLK,     /*!< LEDC timer select APB clock as source clock*/
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    LEDC_USE_PLL_DIV_CLK, /*!< LEDC timer select the PLL_DIV clock available to LEDC peripheral as source clock*/
+#endif
     LEDC_USE_RTC8M_CLK,   /*!< LEDC timer select RTC8M_CLK as source clock. Only for low speed channels and this parameter must be the same for all low speed channels*/
 #if SOC_LEDC_SUPPORT_REF_TICK
     LEDC_USE_REF_TICK,    /*!< LEDC timer select REF_TICK clock as source clock*/
@@ -67,8 +77,12 @@ typedef enum  {
 #if SOC_LEDC_SUPPORT_REF_TICK
     LEDC_REF_TICK = LEDC_USE_REF_TICK, /*!< LEDC timer clock divided from reference tick (1Mhz) */
 #endif
+#if SOC_LEDC_SUPPORT_APB_CLOCK
     LEDC_APB_CLK = LEDC_USE_APB_CLK,  /*!< LEDC timer clock divided from APB clock (80Mhz) */
-    LEDC_SCLK = LEDC_USE_APB_CLK      /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_APB_CLK_SEL */
+    LEDC_SCLK = LEDC_USE_APB_CLK,     /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_APB_CLK_SEL */
+#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    LEDC_SCLK = LEDC_USE_PLL_DIV_CLK, /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_CLK_SEL */
+#endif
 } ledc_clk_src_t;
 
 typedef enum {

components/hal/ledc_hal.c

@@ -9,6 +9,7 @@
 #include "esp_attr.h"
 #include "hal/ledc_hal.h"
 #include "soc/soc_caps.h"
+#include "hal/assert.h"
 
 void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
 {
@@ -19,11 +20,18 @@ void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
 
 static inline ledc_clk_cfg_t ledc_hal_get_slow_clock_helper(ledc_hal_context_t *hal)
 {
-    ledc_slow_clk_sel_t slow_clk = LEDC_SLOW_CLK_APB;
-
+    ledc_slow_clk_sel_t slow_clk;
     ledc_hal_get_slow_clk_sel(hal, &slow_clk);
 
     switch (slow_clk) {
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+        case LEDC_SLOW_CLK_APB:
+            return LEDC_USE_APB_CLK;
+#endif
+#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+        case LEDC_SLOW_CLK_PLL_DIV:
+            return LEDC_USE_PLL_DIV_CLK;
+#endif
         case LEDC_SLOW_CLK_RTC8M:
             return LEDC_USE_RTC8M_CLK;
 #if SOC_LEDC_SUPPORT_XTAL_CLOCK
@@ -31,18 +39,20 @@ static inline ledc_clk_cfg_t ledc_hal_get_slow_clock_helper(ledc_hal_context_t *
             return LEDC_USE_XTAL_CLK;
 #endif
         default:
-            return LEDC_USE_APB_CLK;
+            // Should never reach here
+            HAL_ASSERT(false && "invalid slow clock source");
+            return LEDC_AUTO_CLK;
     }
 }
 
 void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg)
 {
     /* Use the following variable to retrieve the clock source used by the LEDC
-     * hardware controler. */
+     * hardware controller. */
     ledc_clk_src_t clk_src;
 
     /* Clock configuration to return to the driver. */
-    ledc_clk_cfg_t driver_clk = LEDC_USE_APB_CLK;
+    ledc_clk_cfg_t driver_clk = LEDC_AUTO_CLK;
 
     /* Get the timer-specific mux value. */
     ledc_hal_get_clock_source(hal, timer_sel, &clk_src);
@@ -51,39 +61,24 @@ void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_
         driver_clk = LEDC_USE_REF_TICK;
     } else
 #endif
-    /* If the timer-specific mux is not set to REF_TICK, it either means that:
-     * - The controler is in fast mode, and thus using APB clock (driver_clk
-     *   variable's default value)
-     * - The controler is in slow mode and so, using a global clock,
-     *   so we have to retrieve that clock here.
-     */
-    if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
-        /* If the source clock used by LEDC hardware is not REF_TICKS, it is
-         * necessary to retrieve the global clock source used. */
-        driver_clk = ledc_hal_get_slow_clock_helper(hal);
-    }
-
-    *clk_cfg = driver_clk;
-}
-
-void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg)
-{
-    // For low speed channels, if RTC_8MCLK is used as the source clock, the `slow_clk_sel` register should be cleared, otherwise it should be set.
-    ledc_slow_clk_sel_t slow_clk_sel;
-
-    switch (clk_cfg) {
-        case LEDC_USE_RTC8M_CLK:
-            slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
-            break;
-#if SOC_LEDC_SUPPORT_XTAL_CLOCK
-        case LEDC_USE_XTAL_CLK:
-            slow_clk_sel = LEDC_SLOW_CLK_XTAL;
-            break;
+    {
+        /* If the timer-specific mux is not set to REF_TICK, it either means that:
+        * - The controler is in fast mode, and thus using APB clock (driver_clk
+        *   variable's default value)
+        * - The controler is in slow mode and so, using a global clock,
+        *   so we have to retrieve that clock here.
+        */
+        if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
+            /* If the source clock used by LEDC hardware is not REF_TICK, it is
+            * necessary to retrieve the global clock source used. */
+            driver_clk = ledc_hal_get_slow_clock_helper(hal);
+        }
+#if SOC_LEDC_SUPPORT_HS_MODE
+        else {
+            driver_clk = LEDC_USE_APB_CLK;
+        }
 #endif
-        default:
-            slow_clk_sel = LEDC_SLOW_CLK_APB;
-            break;
     }
 
-    ledc_hal_set_slow_clk_sel(hal, slow_clk_sel);
+    *clk_cfg = driver_clk;
 }

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -307,6 +307,10 @@ config SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
     bool
     default y
 
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_REF_TICK
     bool
     default y

components/soc/esp32/include/soc/soc_caps.h

@@ -198,10 +198,11 @@
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX  (1)
-#define SOC_LEDC_SUPPORT_REF_TICK    (1)
-#define SOC_LEDC_SUPPORT_HS_MODE     (1)
-#define SOC_LEDC_CHANNEL_NUM         (8)
-#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (20)
+#define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
+#define SOC_LEDC_SUPPORT_REF_TICK        (1)
+#define SOC_LEDC_SUPPORT_HS_MODE         (1)
+#define SOC_LEDC_CHANNEL_NUM             (8)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM      (20)
 
 /*-------------------------- MCPWM CAPS --------------------------------------*/
 #define SOC_MCPWM_GROUPS                     (2)    ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -227,6 +227,10 @@ config SOC_I2C_SUPPORT_RTC
     bool
     default y
 
+config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y

components/soc/esp32c2/include/soc/ledc_reg.h

@@ -3,1216 +3,1929 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_LEDC_REG_H_
-#define _SOC_LEDC_REG_H_
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
-#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
-/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH0  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH0_S  16
-/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH0_S  15
-/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH0  0x000003FF
-#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
-#define LEDC_OVF_NUM_LSCH0_V  0x3FF
-#define LEDC_OVF_NUM_LSCH0_S  5
-/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH0  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_V  0x1
-#define LEDC_PARA_UP_LSCH0_S  4
-/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH0  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_V  0x1
-#define LEDC_IDLE_LV_LSCH0_S  3
-/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH0_S  2
-/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH0  0x00000003
-#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
-#define LEDC_TIMER_SEL_LSCH0_V  0x3
-#define LEDC_TIMER_SEL_LSCH0_S  0
+/** Configuration Register */
 
-#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
-/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH0  0x00003FFF
-#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
-#define LEDC_HPOINT_LSCH0_V  0x3FFF
-#define LEDC_HPOINT_LSCH0_S  0
+/** LEDC_CH0_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  0
+ */
+#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0)
+/* LEDC_TIMER_SEL_CH0 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 0.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH0    0x00000003
+#define LEDC_TIMER_SEL_CH0_M  (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S)
+#define LEDC_TIMER_SEL_CH0_V  0x00000003
+#define LEDC_TIMER_SEL_CH0_S  0
+/* LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 0.
+ */
+#define LEDC_SIG_OUT_EN_CH0    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH0_M  (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S)
+#define LEDC_SIG_OUT_EN_CH0_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH0_S  2
+/* LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 0 is inactive
+ * (when LEDC_SIG_OUT_EN_CH0 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH0    (BIT(3))
+#define LEDC_IDLE_LV_CH0_M  (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S)
+#define LEDC_IDLE_LV_CH0_V  0x00000001
+#define LEDC_IDLE_LV_CH0_S  3
+/* LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0,
+ * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0,
+ * LEDC_DUTY_CYCLE_CH0, LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and
+ * LEDC_OVF_CNT_EN_CH0 fields for channel 0, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH0    (BIT(4))
+#define LEDC_PARA_UP_CH0_M  (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S)
+#define LEDC_PARA_UP_CH0_V  0x00000001
+#define LEDC_PARA_UP_CH0_S  4
+/* LEDC_OVF_NUM_CH0 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0
+ * overflows for (LEDC_OVF_NUM_CH0 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH0    0x000003FF
+#define LEDC_OVF_NUM_CH0_M  (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S)
+#define LEDC_OVF_NUM_CH0_V  0x000003FF
+#define LEDC_OVF_NUM_CH0_S  5
+/* LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 0.
+ */
+#define LEDC_OVF_CNT_EN_CH0    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH0_M  (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S)
+#define LEDC_OVF_CNT_EN_CH0_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH0_S  15
+/* LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 0.
+ */
+#define LEDC_OVF_CNT_RESET_CH0    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH0_M  (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S)
+#define LEDC_OVF_CNT_RESET_CH0_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH0_S  16
+
+/** LEDC_CH0_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  0
+ */
+#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc)
+/* LEDC_DUTY_SCALE_CH0 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 0.
+ */
+#define LEDC_DUTY_SCALE_CH0    0x000003FF
+#define LEDC_DUTY_SCALE_CH0_M  (LEDC_DUTY_SCALE_CH0_V << LEDC_DUTY_SCALE_CH0_S)
+#define LEDC_DUTY_SCALE_CH0_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH0_S  0
+/* LEDC_DUTY_CYCLE_CH0 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH0 on channel
+ * 0.
+ */
+#define LEDC_DUTY_CYCLE_CH0    0x000003FF
+#define LEDC_DUTY_CYCLE_CH0_M  (LEDC_DUTY_CYCLE_CH0_V << LEDC_DUTY_CYCLE_CH0_S)
+#define LEDC_DUTY_CYCLE_CH0_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH0_S  10
+/* LEDC_DUTY_NUM_CH0 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH0    0x000003FF
+#define LEDC_DUTY_NUM_CH0_M  (LEDC_DUTY_NUM_CH0_V << LEDC_DUTY_NUM_CH0_S)
+#define LEDC_DUTY_NUM_CH0_V  0x000003FF
+#define LEDC_DUTY_NUM_CH0_S  20
+/* LEDC_DUTY_INC_CH0 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 0. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH0    (BIT(30))
+#define LEDC_DUTY_INC_CH0_M  (LEDC_DUTY_INC_CH0_V << LEDC_DUTY_INC_CH0_S)
+#define LEDC_DUTY_INC_CH0_V  0x00000001
+#define LEDC_DUTY_INC_CH0_S  30
+/* LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH0    (BIT(31))
+#define LEDC_DUTY_START_CH0_M  (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S)
+#define LEDC_DUTY_START_CH0_V  0x00000001
+#define LEDC_DUTY_START_CH0_S  31
+
+/** LEDC_CH1_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  1
+ */
+#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14)
+/* LEDC_TIMER_SEL_CH1 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 1.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH1    0x00000003
+#define LEDC_TIMER_SEL_CH1_M  (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S)
+#define LEDC_TIMER_SEL_CH1_V  0x00000003
+#define LEDC_TIMER_SEL_CH1_S  0
+/* LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 1.
+ */
+#define LEDC_SIG_OUT_EN_CH1    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH1_M  (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S)
+#define LEDC_SIG_OUT_EN_CH1_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH1_S  2
+/* LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 1 is inactive
+ * (when LEDC_SIG_OUT_EN_CH1 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH1    (BIT(3))
+#define LEDC_IDLE_LV_CH1_M  (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S)
+#define LEDC_IDLE_LV_CH1_V  0x00000001
+#define LEDC_IDLE_LV_CH1_S  3
+/* LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1,
+ * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1,
+ * LEDC_DUTY_CYCLE_CH1, LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and
+ * LEDC_OVF_CNT_EN_CH1 fields for channel 1, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH1    (BIT(4))
+#define LEDC_PARA_UP_CH1_M  (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S)
+#define LEDC_PARA_UP_CH1_V  0x00000001
+#define LEDC_PARA_UP_CH1_S  4
+/* LEDC_OVF_NUM_CH1 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1
+ * overflows for (LEDC_OVF_NUM_CH1 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH1    0x000003FF
+#define LEDC_OVF_NUM_CH1_M  (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S)
+#define LEDC_OVF_NUM_CH1_V  0x000003FF
+#define LEDC_OVF_NUM_CH1_S  5
+/* LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 1.
+ */
+#define LEDC_OVF_CNT_EN_CH1    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH1_M  (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S)
+#define LEDC_OVF_CNT_EN_CH1_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH1_S  15
+/* LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 1.
+ */
+#define LEDC_OVF_CNT_RESET_CH1    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH1_M  (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S)
+#define LEDC_OVF_CNT_RESET_CH1_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH1_S  16
+
+/** LEDC_CH1_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  1
+ */
+#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20)
+/* LEDC_DUTY_SCALE_CH1 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 1.
+ */
+#define LEDC_DUTY_SCALE_CH1    0x000003FF
+#define LEDC_DUTY_SCALE_CH1_M  (LEDC_DUTY_SCALE_CH1_V << LEDC_DUTY_SCALE_CH1_S)
+#define LEDC_DUTY_SCALE_CH1_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH1_S  0
+/* LEDC_DUTY_CYCLE_CH1 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH1 on channel
+ * 1.
+ */
+#define LEDC_DUTY_CYCLE_CH1    0x000003FF
+#define LEDC_DUTY_CYCLE_CH1_M  (LEDC_DUTY_CYCLE_CH1_V << LEDC_DUTY_CYCLE_CH1_S)
+#define LEDC_DUTY_CYCLE_CH1_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH1_S  10
+/* LEDC_DUTY_NUM_CH1 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH1    0x000003FF
+#define LEDC_DUTY_NUM_CH1_M  (LEDC_DUTY_NUM_CH1_V << LEDC_DUTY_NUM_CH1_S)
+#define LEDC_DUTY_NUM_CH1_V  0x000003FF
+#define LEDC_DUTY_NUM_CH1_S  20
+/* LEDC_DUTY_INC_CH1 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 1. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH1    (BIT(30))
+#define LEDC_DUTY_INC_CH1_M  (LEDC_DUTY_INC_CH1_V << LEDC_DUTY_INC_CH1_S)
+#define LEDC_DUTY_INC_CH1_V  0x00000001
+#define LEDC_DUTY_INC_CH1_S  30
+/* LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH1    (BIT(31))
+#define LEDC_DUTY_START_CH1_M  (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S)
+#define LEDC_DUTY_START_CH1_V  0x00000001
+#define LEDC_DUTY_START_CH1_S  31
+
+/** LEDC_CH2_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  2
+ */
+#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28)
+/* LEDC_TIMER_SEL_CH2 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 2.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH2    0x00000003
+#define LEDC_TIMER_SEL_CH2_M  (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S)
+#define LEDC_TIMER_SEL_CH2_V  0x00000003
+#define LEDC_TIMER_SEL_CH2_S  0
+/* LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 2.
+ */
+#define LEDC_SIG_OUT_EN_CH2    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH2_M  (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S)
+#define LEDC_SIG_OUT_EN_CH2_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH2_S  2
+/* LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 2 is inactive
+ * (when LEDC_SIG_OUT_EN_CH2 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH2    (BIT(3))
+#define LEDC_IDLE_LV_CH2_M  (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S)
+#define LEDC_IDLE_LV_CH2_V  0x00000001
+#define LEDC_IDLE_LV_CH2_S  3
+/* LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2,
+ * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2,
+ * LEDC_DUTY_CYCLE_CH2, LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and
+ * LEDC_OVF_CNT_EN_CH2 fields for channel 2, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH2    (BIT(4))
+#define LEDC_PARA_UP_CH2_M  (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S)
+#define LEDC_PARA_UP_CH2_V  0x00000001
+#define LEDC_PARA_UP_CH2_S  4
+/* LEDC_OVF_NUM_CH2 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2
+ * overflows for (LEDC_OVF_NUM_CH2 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH2    0x000003FF
+#define LEDC_OVF_NUM_CH2_M  (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S)
+#define LEDC_OVF_NUM_CH2_V  0x000003FF
+#define LEDC_OVF_NUM_CH2_S  5
+/* LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 2.
+ */
+#define LEDC_OVF_CNT_EN_CH2    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH2_M  (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S)
+#define LEDC_OVF_CNT_EN_CH2_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH2_S  15
+/* LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 2.
+ */
+#define LEDC_OVF_CNT_RESET_CH2    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH2_M  (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S)
+#define LEDC_OVF_CNT_RESET_CH2_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH2_S  16
+
+/** LEDC_CH2_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  2
+ */
+#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34)
+/* LEDC_DUTY_SCALE_CH2 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 2.
+ */
+#define LEDC_DUTY_SCALE_CH2    0x000003FF
+#define LEDC_DUTY_SCALE_CH2_M  (LEDC_DUTY_SCALE_CH2_V << LEDC_DUTY_SCALE_CH2_S)
+#define LEDC_DUTY_SCALE_CH2_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH2_S  0
+/* LEDC_DUTY_CYCLE_CH2 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH2 on channel
+ * 2.
+ */
+#define LEDC_DUTY_CYCLE_CH2    0x000003FF
+#define LEDC_DUTY_CYCLE_CH2_M  (LEDC_DUTY_CYCLE_CH2_V << LEDC_DUTY_CYCLE_CH2_S)
+#define LEDC_DUTY_CYCLE_CH2_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH2_S  10
+/* LEDC_DUTY_NUM_CH2 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH2    0x000003FF
+#define LEDC_DUTY_NUM_CH2_M  (LEDC_DUTY_NUM_CH2_V << LEDC_DUTY_NUM_CH2_S)
+#define LEDC_DUTY_NUM_CH2_V  0x000003FF
+#define LEDC_DUTY_NUM_CH2_S  20
+/* LEDC_DUTY_INC_CH2 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 2. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH2    (BIT(30))
+#define LEDC_DUTY_INC_CH2_M  (LEDC_DUTY_INC_CH2_V << LEDC_DUTY_INC_CH2_S)
+#define LEDC_DUTY_INC_CH2_V  0x00000001
+#define LEDC_DUTY_INC_CH2_S  30
+/* LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH2    (BIT(31))
+#define LEDC_DUTY_START_CH2_M  (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S)
+#define LEDC_DUTY_START_CH2_V  0x00000001
+#define LEDC_DUTY_START_CH2_S  31
+
+/** LEDC_CH3_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  3
+ */
+#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c)
+/* LEDC_TIMER_SEL_CH3 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 3.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH3    0x00000003
+#define LEDC_TIMER_SEL_CH3_M  (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S)
+#define LEDC_TIMER_SEL_CH3_V  0x00000003
+#define LEDC_TIMER_SEL_CH3_S  0
+/* LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 3.
+ */
+#define LEDC_SIG_OUT_EN_CH3    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH3_M  (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S)
+#define LEDC_SIG_OUT_EN_CH3_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH3_S  2
+/* LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 3 is inactive
+ * (when LEDC_SIG_OUT_EN_CH3 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH3    (BIT(3))
+#define LEDC_IDLE_LV_CH3_M  (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S)
+#define LEDC_IDLE_LV_CH3_V  0x00000001
+#define LEDC_IDLE_LV_CH3_S  3
+/* LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3,
+ * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3,
+ * LEDC_DUTY_CYCLE_CH3, LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and
+ * LEDC_OVF_CNT_EN_CH3 fields for channel 3, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH3    (BIT(4))
+#define LEDC_PARA_UP_CH3_M  (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S)
+#define LEDC_PARA_UP_CH3_V  0x00000001
+#define LEDC_PARA_UP_CH3_S  4
+/* LEDC_OVF_NUM_CH3 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3
+ * overflows for (LEDC_OVF_NUM_CH3 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH3    0x000003FF
+#define LEDC_OVF_NUM_CH3_M  (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S)
+#define LEDC_OVF_NUM_CH3_V  0x000003FF
+#define LEDC_OVF_NUM_CH3_S  5
+/* LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 3.
+ */
+#define LEDC_OVF_CNT_EN_CH3    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH3_M  (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S)
+#define LEDC_OVF_CNT_EN_CH3_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH3_S  15
+/* LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 3.
+ */
+#define LEDC_OVF_CNT_RESET_CH3    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH3_M  (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S)
+#define LEDC_OVF_CNT_RESET_CH3_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH3_S  16
+
+/** LEDC_CH3_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  3
+ */
+#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48)
+/* LEDC_DUTY_SCALE_CH3 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 3.
+ */
+#define LEDC_DUTY_SCALE_CH3    0x000003FF
+#define LEDC_DUTY_SCALE_CH3_M  (LEDC_DUTY_SCALE_CH3_V << LEDC_DUTY_SCALE_CH3_S)
+#define LEDC_DUTY_SCALE_CH3_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH3_S  0
+/* LEDC_DUTY_CYCLE_CH3 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH3 on channel
+ * 3.
+ */
+#define LEDC_DUTY_CYCLE_CH3    0x000003FF
+#define LEDC_DUTY_CYCLE_CH3_M  (LEDC_DUTY_CYCLE_CH3_V << LEDC_DUTY_CYCLE_CH3_S)
+#define LEDC_DUTY_CYCLE_CH3_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH3_S  10
+/* LEDC_DUTY_NUM_CH3 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH3    0x000003FF
+#define LEDC_DUTY_NUM_CH3_M  (LEDC_DUTY_NUM_CH3_V << LEDC_DUTY_NUM_CH3_S)
+#define LEDC_DUTY_NUM_CH3_V  0x000003FF
+#define LEDC_DUTY_NUM_CH3_S  20
+/* LEDC_DUTY_INC_CH3 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 3. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH3    (BIT(30))
+#define LEDC_DUTY_INC_CH3_M  (LEDC_DUTY_INC_CH3_V << LEDC_DUTY_INC_CH3_S)
+#define LEDC_DUTY_INC_CH3_V  0x00000001
+#define LEDC_DUTY_INC_CH3_S  30
+/* LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH3    (BIT(31))
+#define LEDC_DUTY_START_CH3_M  (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S)
+#define LEDC_DUTY_START_CH3_V  0x00000001
+#define LEDC_DUTY_START_CH3_S  31
+
+/** LEDC_CH4_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  4
+ */
+#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50)
+/* LEDC_TIMER_SEL_CH4 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 4.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH4    0x00000003
+#define LEDC_TIMER_SEL_CH4_M  (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S)
+#define LEDC_TIMER_SEL_CH4_V  0x00000003
+#define LEDC_TIMER_SEL_CH4_S  0
+/* LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 4.
+ */
+#define LEDC_SIG_OUT_EN_CH4    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH4_M  (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S)
+#define LEDC_SIG_OUT_EN_CH4_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH4_S  2
+/* LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 4 is inactive
+ * (when LEDC_SIG_OUT_EN_CH4 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH4    (BIT(3))
+#define LEDC_IDLE_LV_CH4_M  (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S)
+#define LEDC_IDLE_LV_CH4_V  0x00000001
+#define LEDC_IDLE_LV_CH4_S  3
+/* LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4,
+ * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4,
+ * LEDC_DUTY_CYCLE_CH4, LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and
+ * LEDC_OVF_CNT_EN_CH4 fields for channel 4, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH4    (BIT(4))
+#define LEDC_PARA_UP_CH4_M  (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S)
+#define LEDC_PARA_UP_CH4_V  0x00000001
+#define LEDC_PARA_UP_CH4_S  4
+/* LEDC_OVF_NUM_CH4 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4
+ * overflows for (LEDC_OVF_NUM_CH4 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH4    0x000003FF
+#define LEDC_OVF_NUM_CH4_M  (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S)
+#define LEDC_OVF_NUM_CH4_V  0x000003FF
+#define LEDC_OVF_NUM_CH4_S  5
+/* LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 4.
+ */
+#define LEDC_OVF_CNT_EN_CH4    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH4_M  (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S)
+#define LEDC_OVF_CNT_EN_CH4_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH4_S  15
+/* LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 4.
+ */
+#define LEDC_OVF_CNT_RESET_CH4    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH4_M  (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S)
+#define LEDC_OVF_CNT_RESET_CH4_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH4_S  16
+
+/** LEDC_CH4_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  4
+ */
+#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c)
+/* LEDC_DUTY_SCALE_CH4 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 4.
+ */
+#define LEDC_DUTY_SCALE_CH4    0x000003FF
+#define LEDC_DUTY_SCALE_CH4_M  (LEDC_DUTY_SCALE_CH4_V << LEDC_DUTY_SCALE_CH4_S)
+#define LEDC_DUTY_SCALE_CH4_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH4_S  0
+/* LEDC_DUTY_CYCLE_CH4 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH4 on channel
+ * 4.
+ */
+#define LEDC_DUTY_CYCLE_CH4    0x000003FF
+#define LEDC_DUTY_CYCLE_CH4_M  (LEDC_DUTY_CYCLE_CH4_V << LEDC_DUTY_CYCLE_CH4_S)
+#define LEDC_DUTY_CYCLE_CH4_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH4_S  10
+/* LEDC_DUTY_NUM_CH4 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH4    0x000003FF
+#define LEDC_DUTY_NUM_CH4_M  (LEDC_DUTY_NUM_CH4_V << LEDC_DUTY_NUM_CH4_S)
+#define LEDC_DUTY_NUM_CH4_V  0x000003FF
+#define LEDC_DUTY_NUM_CH4_S  20
+/* LEDC_DUTY_INC_CH4 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 4. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH4    (BIT(30))
+#define LEDC_DUTY_INC_CH4_M  (LEDC_DUTY_INC_CH4_V << LEDC_DUTY_INC_CH4_S)
+#define LEDC_DUTY_INC_CH4_V  0x00000001
+#define LEDC_DUTY_INC_CH4_S  30
+/* LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH4    (BIT(31))
+#define LEDC_DUTY_START_CH4_M  (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S)
+#define LEDC_DUTY_START_CH4_V  0x00000001
+#define LEDC_DUTY_START_CH4_S  31
+
+/** LEDC_CH5_CONF0_REG register
+ *  Configuration register 0 for channel
+ *  5
+ */
+#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64)
+/* LEDC_TIMER_SEL_CH5 : R/W; bitpos: [2:0]; default: 0;
+ * This field is used to select one of timers for channel 5.
+ * 0: select timer0; 1: select timer1; 2: select timer2; 3: select
+ * timer3
+ */
+#define LEDC_TIMER_SEL_CH5    0x00000003
+#define LEDC_TIMER_SEL_CH5_M  (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S)
+#define LEDC_TIMER_SEL_CH5_V  0x00000003
+#define LEDC_TIMER_SEL_CH5_S  0
+/* LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel
+ * 5.
+ */
+#define LEDC_SIG_OUT_EN_CH5    (BIT(2))
+#define LEDC_SIG_OUT_EN_CH5_M  (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S)
+#define LEDC_SIG_OUT_EN_CH5_V  0x00000001
+#define LEDC_SIG_OUT_EN_CH5_S  2
+/* LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 5 is inactive
+ * (when LEDC_SIG_OUT_EN_CH5 is
+ * 0).
+ */
+#define LEDC_IDLE_LV_CH5    (BIT(3))
+#define LEDC_IDLE_LV_CH5_M  (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S)
+#define LEDC_IDLE_LV_CH5_V  0x00000001
+#define LEDC_IDLE_LV_CH5_S  3
+/* LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0;
+ * This bit is used to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5,
+ * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5,
+ * LEDC_DUTY_CYCLE_CH5, LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and
+ * LEDC_OVF_CNT_EN_CH5 fields for channel 5, and will be automatically
+ * cleared by
+ * hardware.
+ */
+#define LEDC_PARA_UP_CH5    (BIT(4))
+#define LEDC_PARA_UP_CH5_M  (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S)
+#define LEDC_PARA_UP_CH5_V  0x00000001
+#define LEDC_PARA_UP_CH5_S  4
+/* LEDC_OVF_NUM_CH5 : R/W; bitpos: [15:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus
+ * 1.
+ * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5
+ * overflows for (LEDC_OVF_NUM_CH5 + 1)
+ * times.
+ */
+#define LEDC_OVF_NUM_CH5    0x000003FF
+#define LEDC_OVF_NUM_CH5_M  (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S)
+#define LEDC_OVF_NUM_CH5_V  0x000003FF
+#define LEDC_OVF_NUM_CH5_S  5
+/* LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel
+ * 5.
+ */
+#define LEDC_OVF_CNT_EN_CH5    (BIT(15))
+#define LEDC_OVF_CNT_EN_CH5_M  (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S)
+#define LEDC_OVF_CNT_EN_CH5_V  0x00000001
+#define LEDC_OVF_CNT_EN_CH5_S  15
+/* LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel
+ * 5.
+ */
+#define LEDC_OVF_CNT_RESET_CH5    (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH5_M  (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S)
+#define LEDC_OVF_CNT_RESET_CH5_V  0x00000001
+#define LEDC_OVF_CNT_RESET_CH5_S  16
+
+/** LEDC_CH5_CONF1_REG register
+ *  Configuration register 1 for channel
+ *  5
+ */
+#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70)
+/* LEDC_DUTY_SCALE_CH5 : R/W; bitpos: [10:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel
+ * 5.
+ */
+#define LEDC_DUTY_SCALE_CH5    0x000003FF
+#define LEDC_DUTY_SCALE_CH5_M  (LEDC_DUTY_SCALE_CH5_V << LEDC_DUTY_SCALE_CH5_S)
+#define LEDC_DUTY_SCALE_CH5_V  0x000003FF
+#define LEDC_DUTY_SCALE_CH5_S  0
+/* LEDC_DUTY_CYCLE_CH5 : R/W; bitpos: [20:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH5 on channel
+ * 5.
+ */
+#define LEDC_DUTY_CYCLE_CH5    0x000003FF
+#define LEDC_DUTY_CYCLE_CH5_M  (LEDC_DUTY_CYCLE_CH5_V << LEDC_DUTY_CYCLE_CH5_S)
+#define LEDC_DUTY_CYCLE_CH5_V  0x000003FF
+#define LEDC_DUTY_CYCLE_CH5_S  10
+/* LEDC_DUTY_NUM_CH5 : R/W; bitpos: [30:20]; default: 0;
+ * This register is used to control the number of times the duty cycle
+ * will be
+ * changed.
+ */
+#define LEDC_DUTY_NUM_CH5    0x000003FF
+#define LEDC_DUTY_NUM_CH5_M  (LEDC_DUTY_NUM_CH5_V << LEDC_DUTY_NUM_CH5_S)
+#define LEDC_DUTY_NUM_CH5_V  0x000003FF
+#define LEDC_DUTY_NUM_CH5_S  20
+/* LEDC_DUTY_INC_CH5 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 5. 1: Increase; 0:
+ * Decrease.
+ */
+#define LEDC_DUTY_INC_CH5    (BIT(30))
+#define LEDC_DUTY_INC_CH5_M  (LEDC_DUTY_INC_CH5_V << LEDC_DUTY_INC_CH5_S)
+#define LEDC_DUTY_INC_CH5_V  0x00000001
+#define LEDC_DUTY_INC_CH5_S  30
+/* LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect
+ * when this bit is set to
+ * 1.
+ */
+#define LEDC_DUTY_START_CH5    (BIT(31))
+#define LEDC_DUTY_START_CH5_M  (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S)
+#define LEDC_DUTY_START_CH5_V  0x00000001
+#define LEDC_DUTY_START_CH5_S  31
 
-#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
-/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0  0x0007FFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x7FFFF
-#define LEDC_DUTY_LSCH0_S  0
+/** LEDC_CONF_REG register
+ *  Global ledc configuration
+ *  register
+ */
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0xd0)
+/* LEDC_APB_CLK_SEL : R/W; bitpos: [2:0]; default: 0;
+ * This bit is used to select clock source for the 4 timers .
+ * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3:
+ * XTAL_CLK
+ */
+#define LEDC_APB_CLK_SEL    0x00000003
+#define LEDC_APB_CLK_SEL_M  (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S)
+#define LEDC_APB_CLK_SEL_V  0x00000003
+#define LEDC_APB_CLK_SEL_S  0
+/* LEDC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ * This bit is used to control clock.
+ * 1'b1: Force clock on for register. 1'h0: Support clock only when
+ * application writes
+ * registers.
+ */
+#define LEDC_CLK_EN    (BIT(31))
+#define LEDC_CLK_EN_M  (LEDC_CLK_EN_V << LEDC_CLK_EN_S)
+#define LEDC_CLK_EN_V  0x00000001
+#define LEDC_CLK_EN_S  31
 
-#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
-/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH0  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_V  0x1
-#define LEDC_DUTY_START_LSCH0_S  31
-/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH0  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_V  0x1
-#define LEDC_DUTY_INC_LSCH0_S  30
-/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH0  0x000003FF
-#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
-#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH0_S  20
-/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
-#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH0_S  10
-/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
-#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH0_S  0
 
-#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
-/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0  0x0007FFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x7FFFF
-#define LEDC_DUTY_LSCH0_S  0
+/** Hpoint Register */
 
-#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
-/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH1  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH1_S  16
-/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH1_S  15
-/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH1  0x000003FF
-#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
-#define LEDC_OVF_NUM_LSCH1_V  0x3FF
-#define LEDC_OVF_NUM_LSCH1_S  5
-/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH1  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_V  0x1
-#define LEDC_PARA_UP_LSCH1_S  4
-/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH1  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_V  0x1
-#define LEDC_IDLE_LV_LSCH1_S  3
-/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH1_S  2
-/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH1  0x00000003
-#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
-#define LEDC_TIMER_SEL_LSCH1_V  0x3
-#define LEDC_TIMER_SEL_LSCH1_S  0
+/** LEDC_CH0_HPOINT_REG register
+ *  High point register for channel
+ *  0
+ */
+#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4)
+/* LEDC_HPOINT_CH0 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH0    0x00003FFF
+#define LEDC_HPOINT_CH0_M  (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S)
+#define LEDC_HPOINT_CH0_V  0x00003FFF
+#define LEDC_HPOINT_CH0_S  0
 
-#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
-/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH1  0x00003FFF
-#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
-#define LEDC_HPOINT_LSCH1_V  0x3FFF
-#define LEDC_HPOINT_LSCH1_S  0
+/** LEDC_CH1_HPOINT_REG register
+ *  High point register for channel
+ *  1
+ */
+#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18)
+/* LEDC_HPOINT_CH1 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH1    0x00003FFF
+#define LEDC_HPOINT_CH1_M  (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S)
+#define LEDC_HPOINT_CH1_V  0x00003FFF
+#define LEDC_HPOINT_CH1_S  0
 
-#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
-/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1  0x0007FFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x7FFFF
-#define LEDC_DUTY_LSCH1_S  0
+/** LEDC_CH2_HPOINT_REG register
+ *  High point register for channel
+ *  2
+ */
+#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c)
+/* LEDC_HPOINT_CH2 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH2    0x00003FFF
+#define LEDC_HPOINT_CH2_M  (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S)
+#define LEDC_HPOINT_CH2_V  0x00003FFF
+#define LEDC_HPOINT_CH2_S  0
 
-#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
-/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH1  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_V  0x1
-#define LEDC_DUTY_START_LSCH1_S  31
-/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH1  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_V  0x1
-#define LEDC_DUTY_INC_LSCH1_S  30
-/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH1  0x000003FF
-#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
-#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH1_S  20
-/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
-#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH1_S  10
-/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
-#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH1_S  0
+/** LEDC_CH3_HPOINT_REG register
+ *  High point register for channel
+ *  3
+ */
+#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40)
+/* LEDC_HPOINT_CH3 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH3    0x00003FFF
+#define LEDC_HPOINT_CH3_M  (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S)
+#define LEDC_HPOINT_CH3_V  0x00003FFF
+#define LEDC_HPOINT_CH3_S  0
 
-#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
-/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1  0x0007FFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x7FFFF
-#define LEDC_DUTY_LSCH1_S  0
+/** LEDC_CH4_HPOINT_REG register
+ *  High point register for channel
+ *  4
+ */
+#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54)
+/* LEDC_HPOINT_CH4 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH4    0x00003FFF
+#define LEDC_HPOINT_CH4_M  (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S)
+#define LEDC_HPOINT_CH4_V  0x00003FFF
+#define LEDC_HPOINT_CH4_S  0
 
-#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
-/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH2  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH2_S  16
-/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH2_S  15
-/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH2  0x000003FF
-#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
-#define LEDC_OVF_NUM_LSCH2_V  0x3FF
-#define LEDC_OVF_NUM_LSCH2_S  5
-/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH2  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_V  0x1
-#define LEDC_PARA_UP_LSCH2_S  4
-/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH2  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_V  0x1
-#define LEDC_IDLE_LV_LSCH2_S  3
-/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH2_S  2
-/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH2  0x00000003
-#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
-#define LEDC_TIMER_SEL_LSCH2_V  0x3
-#define LEDC_TIMER_SEL_LSCH2_S  0
+/** LEDC_CH5_HPOINT_REG register
+ *  High point register for channel
+ *  5
+ */
+#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68)
+/* LEDC_HPOINT_CH5 : R/W; bitpos: [14:0]; default: 0;
+ * The output value changes to high when the selected timers has reached
+ * the value specified by this
+ * register.
+ */
+#define LEDC_HPOINT_CH5    0x00003FFF
+#define LEDC_HPOINT_CH5_M  (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S)
+#define LEDC_HPOINT_CH5_V  0x00003FFF
+#define LEDC_HPOINT_CH5_S  0
 
-#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
-/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH2  0x00003FFF
-#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
-#define LEDC_HPOINT_LSCH2_V  0x3FFF
-#define LEDC_HPOINT_LSCH2_S  0
 
-#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
-/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2  0x0007FFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x7FFFF
-#define LEDC_DUTY_LSCH2_S  0
+/** Duty Cycle Register */
 
-#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
-/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH2  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_V  0x1
-#define LEDC_DUTY_START_LSCH2_S  31
-/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH2  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_V  0x1
-#define LEDC_DUTY_INC_LSCH2_S  30
-/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH2  0x000003FF
-#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
-#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH2_S  20
-/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
-#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH2_S  10
-/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
-#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH2_S  0
+/** LEDC_CH0_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  0
+ */
+#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8)
+/* LEDC_DUTY_CH0 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH0    0x0007FFFF
+#define LEDC_DUTY_CH0_M  (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S)
+#define LEDC_DUTY_CH0_V  0x0007FFFF
+#define LEDC_DUTY_CH0_S  0
 
-#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
-/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2  0x0007FFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x7FFFF
-#define LEDC_DUTY_LSCH2_S  0
+/** LEDC_CH0_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  0
+ */
+#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10)
+/* LEDC_DUTY_R_CH0 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 0.
+ */
+#define LEDC_DUTY_R_CH0    0x0007FFFF
+#define LEDC_DUTY_R_CH0_M  (LEDC_DUTY_R_CH0_V << LEDC_DUTY_R_CH0_S)
+#define LEDC_DUTY_R_CH0_V  0x0007FFFF
+#define LEDC_DUTY_R_CH0_S  0
 
-#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
-/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH3  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH3_S  16
-/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH3_S  15
-/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH3  0x000003FF
-#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
-#define LEDC_OVF_NUM_LSCH3_V  0x3FF
-#define LEDC_OVF_NUM_LSCH3_S  5
-/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH3  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_V  0x1
-#define LEDC_PARA_UP_LSCH3_S  4
-/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH3  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_V  0x1
-#define LEDC_IDLE_LV_LSCH3_S  3
-/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH3_S  2
-/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH3  0x00000003
-#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
-#define LEDC_TIMER_SEL_LSCH3_V  0x3
-#define LEDC_TIMER_SEL_LSCH3_S  0
+/** LEDC_CH1_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  1
+ */
+#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c)
+/* LEDC_DUTY_CH1 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH1    0x0007FFFF
+#define LEDC_DUTY_CH1_M  (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S)
+#define LEDC_DUTY_CH1_V  0x0007FFFF
+#define LEDC_DUTY_CH1_S  0
 
-#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
-/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH3  0x00003FFF
-#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
-#define LEDC_HPOINT_LSCH3_V  0x3FFF
-#define LEDC_HPOINT_LSCH3_S  0
+/** LEDC_CH1_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  1
+ */
+#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24)
+/* LEDC_DUTY_R_CH1 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 1.
+ */
+#define LEDC_DUTY_R_CH1    0x0007FFFF
+#define LEDC_DUTY_R_CH1_M  (LEDC_DUTY_R_CH1_V << LEDC_DUTY_R_CH1_S)
+#define LEDC_DUTY_R_CH1_V  0x0007FFFF
+#define LEDC_DUTY_R_CH1_S  0
 
-#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
-/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3  0x0007FFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x7FFFF
-#define LEDC_DUTY_LSCH3_S  0
+/** LEDC_CH2_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  2
+ */
+#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30)
+/* LEDC_DUTY_CH2 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH2    0x0007FFFF
+#define LEDC_DUTY_CH2_M  (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S)
+#define LEDC_DUTY_CH2_V  0x0007FFFF
+#define LEDC_DUTY_CH2_S  0
+
+/** LEDC_CH2_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  2
+ */
+#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38)
+/* LEDC_DUTY_R_CH2 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 2.
+ */
+#define LEDC_DUTY_R_CH2    0x0007FFFF
+#define LEDC_DUTY_R_CH2_M  (LEDC_DUTY_R_CH2_V << LEDC_DUTY_R_CH2_S)
+#define LEDC_DUTY_R_CH2_V  0x0007FFFF
+#define LEDC_DUTY_R_CH2_S  0
 
-#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
-/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH3  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_V  0x1
-#define LEDC_DUTY_START_LSCH3_S  31
-/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH3  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_V  0x1
-#define LEDC_DUTY_INC_LSCH3_S  30
-/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH3  0x000003FF
-#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
-#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH3_S  20
-/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
-#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH3_S  10
-/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
-#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH3_S  0
+/** LEDC_CH3_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  3
+ */
+#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44)
+/* LEDC_DUTY_CH3 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH3    0x0007FFFF
+#define LEDC_DUTY_CH3_M  (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S)
+#define LEDC_DUTY_CH3_V  0x0007FFFF
+#define LEDC_DUTY_CH3_S  0
 
-#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
-/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3  0x0007FFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x7FFFF
-#define LEDC_DUTY_LSCH3_S  0
+/** LEDC_CH3_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  3
+ */
+#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c)
+/* LEDC_DUTY_R_CH3 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 3.
+ */
+#define LEDC_DUTY_R_CH3    0x0007FFFF
+#define LEDC_DUTY_R_CH3_M  (LEDC_DUTY_R_CH3_V << LEDC_DUTY_R_CH3_S)
+#define LEDC_DUTY_R_CH3_V  0x0007FFFF
+#define LEDC_DUTY_R_CH3_S  0
 
-#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
-/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH4  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH4_S  16
-/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH4_S  15
-/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH4  0x000003FF
-#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
-#define LEDC_OVF_NUM_LSCH4_V  0x3FF
-#define LEDC_OVF_NUM_LSCH4_S  5
-/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH4  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_V  0x1
-#define LEDC_PARA_UP_LSCH4_S  4
-/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH4  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_V  0x1
-#define LEDC_IDLE_LV_LSCH4_S  3
-/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH4_S  2
-/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH4  0x00000003
-#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
-#define LEDC_TIMER_SEL_LSCH4_V  0x3
-#define LEDC_TIMER_SEL_LSCH4_S  0
+/** LEDC_CH4_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  4
+ */
+#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58)
+/* LEDC_DUTY_CH4 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH4    0x0007FFFF
+#define LEDC_DUTY_CH4_M  (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S)
+#define LEDC_DUTY_CH4_V  0x0007FFFF
+#define LEDC_DUTY_CH4_S  0
 
-#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
-/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH4  0x00003FFF
-#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
-#define LEDC_HPOINT_LSCH4_V  0x3FFF
-#define LEDC_HPOINT_LSCH4_S  0
+/** LEDC_CH4_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  4
+ */
+#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60)
+/* LEDC_DUTY_R_CH4 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 4.
+ */
+#define LEDC_DUTY_R_CH4    0x0007FFFF
+#define LEDC_DUTY_R_CH4_M  (LEDC_DUTY_R_CH4_V << LEDC_DUTY_R_CH4_S)
+#define LEDC_DUTY_R_CH4_V  0x0007FFFF
+#define LEDC_DUTY_R_CH4_S  0
 
-#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
-/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4  0x0007FFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x7FFFF
-#define LEDC_DUTY_LSCH4_S  0
+/** LEDC_CH5_DUTY_REG register
+ *  Initial duty cycle for channel
+ *  5
+ */
+#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c)
+/* LEDC_DUTY_CH5 : R/W; bitpos: [19:0]; default: 0;
+ * This register is used to change the output duty by controlling the
+ * Lpoint.
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+#define LEDC_DUTY_CH5    0x0007FFFF
+#define LEDC_DUTY_CH5_M  (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S)
+#define LEDC_DUTY_CH5_V  0x0007FFFF
+#define LEDC_DUTY_CH5_S  0
 
-#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
-/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH4  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_V  0x1
-#define LEDC_DUTY_START_LSCH4_S  31
-/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH4  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_V  0x1
-#define LEDC_DUTY_INC_LSCH4_S  30
-/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH4  0x000003FF
-#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
-#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH4_S  20
-/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
-#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH4_S  10
-/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
-#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH4_S  0
+/** LEDC_CH5_DUTY_R_REG register
+ *  Current duty cycle for channel
+ *  5
+ */
+#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74)
+/* LEDC_DUTY_R_CH5 : RO; bitpos: [19:0]; default: 0;
+ * This register stores the current duty of output signal on channel
+ * 5.
+ */
+#define LEDC_DUTY_R_CH5    0x0007FFFF
+#define LEDC_DUTY_R_CH5_M  (LEDC_DUTY_R_CH5_V << LEDC_DUTY_R_CH5_S)
+#define LEDC_DUTY_R_CH5_V  0x0007FFFF
+#define LEDC_DUTY_R_CH5_S  0
 
-#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
-/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4  0x0007FFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x7FFFF
-#define LEDC_DUTY_LSCH4_S  0
 
-#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
-/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH5  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH5_S  16
-/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH5_S  15
-/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH5  0x000003FF
-#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
-#define LEDC_OVF_NUM_LSCH5_V  0x3FF
-#define LEDC_OVF_NUM_LSCH5_S  5
-/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH5  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_V  0x1
-#define LEDC_PARA_UP_LSCH5_S  4
-/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH5  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_V  0x1
-#define LEDC_IDLE_LV_LSCH5_S  3
-/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH5_S  2
-/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH5  0x00000003
-#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
-#define LEDC_TIMER_SEL_LSCH5_V  0x3
-#define LEDC_TIMER_SEL_LSCH5_S  0
+/** Timer Register */
 
-#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
-/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH5  0x00003FFF
-#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
-#define LEDC_HPOINT_LSCH5_V  0x3FFF
-#define LEDC_HPOINT_LSCH5_S  0
+/** LEDC_TIMER0_CONF_REG register
+ *  Timer 0
+ *  configuration
+ */
+#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0)
+/* LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ * This register is used to control the range of the counter in timer
+ * 0.
+ */
+#define LEDC_TIMER0_DUTY_RES    0x0000000F
+#define LEDC_TIMER0_DUTY_RES_M  (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S)
+#define LEDC_TIMER0_DUTY_RES_V  0x0000000F
+#define LEDC_TIMER0_DUTY_RES_S  0
+/* LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer
+ * 0.
+ * The least significant eight bits represent the fractional
+ * part.
+ */
+#define LEDC_CLK_DIV_TIMER0    0x0003FFFF
+#define LEDC_CLK_DIV_TIMER0_M  (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S)
+#define LEDC_CLK_DIV_TIMER0_V  0x0003FFFF
+#define LEDC_CLK_DIV_TIMER0_S  4
+/* LEDC_TIMER0_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer
+ * 0.
+ */
+#define LEDC_TIMER0_PAUSE    (BIT(22))
+#define LEDC_TIMER0_PAUSE_M  (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S)
+#define LEDC_TIMER0_PAUSE_V  0x00000001
+#define LEDC_TIMER0_PAUSE_S  22
+/* LEDC_TIMER0_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 0. The counter will show 0 after
+ * reset.
+ */
+#define LEDC_TIMER0_RST    (BIT(23))
+#define LEDC_TIMER0_RST_M  (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S)
+#define LEDC_TIMER0_RST_V  0x00000001
+#define LEDC_TIMER0_RST_S  23
+/* LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 0. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ * 1'h0: SLOW_CLK 1'h1:
+ * REF_TICK
+ */
+#define LEDC_TICK_SEL_TIMER0    (BIT(24))
+#define LEDC_TICK_SEL_TIMER0_M  (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S)
+#define LEDC_TICK_SEL_TIMER0_V  0x00000001
+#define LEDC_TICK_SEL_TIMER0_S  24
+/* LEDC_TIMER0_PARA_UP : WT; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER0 and
+ * LEDC_TIMER0_DUTY_RES.
+ */
+#define LEDC_TIMER0_PARA_UP    (BIT(25))
+#define LEDC_TIMER0_PARA_UP_M  (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S)
+#define LEDC_TIMER0_PARA_UP_V  0x00000001
+#define LEDC_TIMER0_PARA_UP_S  25
 
-#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
-/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5  0x0007FFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x7FFFF
-#define LEDC_DUTY_LSCH5_S  0
+/** LEDC_TIMER0_VALUE_REG register
+ *  Timer 0 current counter
+ *  value
+ */
+#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4)
+/* LEDC_TIMER0_CNT : RO; bitpos: [14:0]; default: 0;
+ * This register stores the current counter value of timer
+ * 0.
+ */
+#define LEDC_TIMER0_CNT    0x00003FFF
+#define LEDC_TIMER0_CNT_M  (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S)
+#define LEDC_TIMER0_CNT_V  0x00003FFF
+#define LEDC_TIMER0_CNT_S  0
 
-#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
-/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH5  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_V  0x1
-#define LEDC_DUTY_START_LSCH5_S  31
-/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH5  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_V  0x1
-#define LEDC_DUTY_INC_LSCH5_S  30
-/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH5  0x000003FF
-#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
-#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH5_S  20
-/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
-#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH5_S  10
-/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
-#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH5_S  0
+/** LEDC_TIMER1_CONF_REG register
+ *  Timer 1
+ *  configuration
+ */
+#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8)
+/* LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ * This register is used to control the range of the counter in timer
+ * 1.
+ */
+#define LEDC_TIMER1_DUTY_RES    0x0000000F
+#define LEDC_TIMER1_DUTY_RES_M  (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S)
+#define LEDC_TIMER1_DUTY_RES_V  0x0000000F
+#define LEDC_TIMER1_DUTY_RES_S  0
+/* LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer
+ * 1.
+ * The least significant eight bits represent the fractional
+ * part.
+ */
+#define LEDC_CLK_DIV_TIMER1    0x0003FFFF
+#define LEDC_CLK_DIV_TIMER1_M  (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S)
+#define LEDC_CLK_DIV_TIMER1_V  0x0003FFFF
+#define LEDC_CLK_DIV_TIMER1_S  4
+/* LEDC_TIMER1_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer
+ * 1.
+ */
+#define LEDC_TIMER1_PAUSE    (BIT(22))
+#define LEDC_TIMER1_PAUSE_M  (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S)
+#define LEDC_TIMER1_PAUSE_V  0x00000001
+#define LEDC_TIMER1_PAUSE_S  22
+/* LEDC_TIMER1_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 1. The counter will show 0 after
+ * reset.
+ */
+#define LEDC_TIMER1_RST    (BIT(23))
+#define LEDC_TIMER1_RST_M  (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S)
+#define LEDC_TIMER1_RST_V  0x00000001
+#define LEDC_TIMER1_RST_S  23
+/* LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 1. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ * 1'h0: SLOW_CLK 1'h1:
+ * REF_TICK
+ */
+#define LEDC_TICK_SEL_TIMER1    (BIT(24))
+#define LEDC_TICK_SEL_TIMER1_M  (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S)
+#define LEDC_TICK_SEL_TIMER1_V  0x00000001
+#define LEDC_TICK_SEL_TIMER1_S  24
+/* LEDC_TIMER1_PARA_UP : WT; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER1 and
+ * LEDC_TIMER1_DUTY_RES.
+ */
+#define LEDC_TIMER1_PARA_UP    (BIT(25))
+#define LEDC_TIMER1_PARA_UP_M  (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S)
+#define LEDC_TIMER1_PARA_UP_V  0x00000001
+#define LEDC_TIMER1_PARA_UP_S  25
 
-#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
-/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5  0x0007FFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x7FFFF
-#define LEDC_DUTY_LSCH5_S  0
+/** LEDC_TIMER1_VALUE_REG register
+ *  Timer 1 current counter
+ *  value
+ */
+#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac)
+/* LEDC_TIMER1_CNT : RO; bitpos: [14:0]; default: 0;
+ * This register stores the current counter value of timer
+ * 1.
+ */
+#define LEDC_TIMER1_CNT    0x00003FFF
+#define LEDC_TIMER1_CNT_M  (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S)
+#define LEDC_TIMER1_CNT_V  0x00003FFF
+#define LEDC_TIMER1_CNT_S  0
 
-#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x00a0)
-/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_V  0x1
-#define LEDC_LSTIMER0_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER0  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_V  0x1
-#define LEDC_TICK_SEL_LSTIMER0_S  24
-/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER0_RST  (BIT(23))
-#define LEDC_LSTIMER0_RST_M  (BIT(23))
-#define LEDC_LSTIMER0_RST_V  0x1
-#define LEDC_LSTIMER0_RST_S  23
-/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PAUSE  (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_V  0x1
-#define LEDC_LSTIMER0_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
-#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER0_S  4
-/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
-#define LEDC_LSTIMER0_DUTY_RES_V  0xF
-#define LEDC_LSTIMER0_DUTY_RES_S  0
+/** LEDC_TIMER2_CONF_REG register
+ *  Timer 2
+ *  configuration
+ */
+#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0)
+/* LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ * This register is used to control the range of the counter in timer
+ * 2.
+ */
+#define LEDC_TIMER2_DUTY_RES    0x0000000F
+#define LEDC_TIMER2_DUTY_RES_M  (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S)
+#define LEDC_TIMER2_DUTY_RES_V  0x0000000F
+#define LEDC_TIMER2_DUTY_RES_S  0
+/* LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer
+ * 2.
+ * The least significant eight bits represent the fractional
+ * part.
+ */
+#define LEDC_CLK_DIV_TIMER2    0x0003FFFF
+#define LEDC_CLK_DIV_TIMER2_M  (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S)
+#define LEDC_CLK_DIV_TIMER2_V  0x0003FFFF
+#define LEDC_CLK_DIV_TIMER2_S  4
+/* LEDC_TIMER2_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer
+ * 2.
+ */
+#define LEDC_TIMER2_PAUSE    (BIT(22))
+#define LEDC_TIMER2_PAUSE_M  (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S)
+#define LEDC_TIMER2_PAUSE_V  0x00000001
+#define LEDC_TIMER2_PAUSE_S  22
+/* LEDC_TIMER2_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 2. The counter will show 0 after
+ * reset.
+ */
+#define LEDC_TIMER2_RST    (BIT(23))
+#define LEDC_TIMER2_RST_M  (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S)
+#define LEDC_TIMER2_RST_V  0x00000001
+#define LEDC_TIMER2_RST_S  23
+/* LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 2. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ * 1'h0: SLOW_CLK 1'h1:
+ * REF_TICK
+ */
+#define LEDC_TICK_SEL_TIMER2    (BIT(24))
+#define LEDC_TICK_SEL_TIMER2_M  (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S)
+#define LEDC_TICK_SEL_TIMER2_V  0x00000001
+#define LEDC_TICK_SEL_TIMER2_S  24
+/* LEDC_TIMER2_PARA_UP : WT; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER2 and
+ * LEDC_TIMER2_DUTY_RES.
+ */
+#define LEDC_TIMER2_PARA_UP    (BIT(25))
+#define LEDC_TIMER2_PARA_UP_M  (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S)
+#define LEDC_TIMER2_PARA_UP_V  0x00000001
+#define LEDC_TIMER2_PARA_UP_S  25
 
-#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x00a4)
-/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_CNT  0x00003FFF
-#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
-#define LEDC_LSTIMER0_CNT_V  0x3FFF
-#define LEDC_LSTIMER0_CNT_S  0
+/** LEDC_TIMER2_VALUE_REG register
+ *  Timer 2 current counter
+ *  value
+ */
+#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4)
+/* LEDC_TIMER2_CNT : RO; bitpos: [14:0]; default: 0;
+ * This register stores the current counter value of timer
+ * 2.
+ */
+#define LEDC_TIMER2_CNT    0x00003FFF
+#define LEDC_TIMER2_CNT_M  (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S)
+#define LEDC_TIMER2_CNT_V  0x00003FFF
+#define LEDC_TIMER2_CNT_S  0
 
-#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x00a8)
-/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_V  0x1
-#define LEDC_LSTIMER1_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER1  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_V  0x1
-#define LEDC_TICK_SEL_LSTIMER1_S  24
-/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER1_RST  (BIT(23))
-#define LEDC_LSTIMER1_RST_M  (BIT(23))
-#define LEDC_LSTIMER1_RST_V  0x1
-#define LEDC_LSTIMER1_RST_S  23
-/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PAUSE  (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_V  0x1
-#define LEDC_LSTIMER1_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
-#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER1_S  4
-/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
-#define LEDC_LSTIMER1_DUTY_RES_V  0xF
-#define LEDC_LSTIMER1_DUTY_RES_S  0
+/** LEDC_TIMER3_CONF_REG register
+ *  Timer 3
+ *  configuration
+ */
+#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8)
+/* LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
+ * This register is used to control the range of the counter in timer
+ * 3.
+ */
+#define LEDC_TIMER3_DUTY_RES    0x0000000F
+#define LEDC_TIMER3_DUTY_RES_M  (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S)
+#define LEDC_TIMER3_DUTY_RES_V  0x0000000F
+#define LEDC_TIMER3_DUTY_RES_S  0
+/* LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer
+ * 3.
+ * The least significant eight bits represent the fractional
+ * part.
+ */
+#define LEDC_CLK_DIV_TIMER3    0x0003FFFF
+#define LEDC_CLK_DIV_TIMER3_M  (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S)
+#define LEDC_CLK_DIV_TIMER3_V  0x0003FFFF
+#define LEDC_CLK_DIV_TIMER3_S  4
+/* LEDC_TIMER3_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer
+ * 3.
+ */
+#define LEDC_TIMER3_PAUSE    (BIT(22))
+#define LEDC_TIMER3_PAUSE_M  (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S)
+#define LEDC_TIMER3_PAUSE_V  0x00000001
+#define LEDC_TIMER3_PAUSE_S  22
+/* LEDC_TIMER3_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 3. The counter will show 0 after
+ * reset.
+ */
+#define LEDC_TIMER3_RST    (BIT(23))
+#define LEDC_TIMER3_RST_M  (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S)
+#define LEDC_TIMER3_RST_V  0x00000001
+#define LEDC_TIMER3_RST_S  23
+/* LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 3. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ * 1'h0: SLOW_CLK 1'h1:
+ * REF_TICK
+ */
+#define LEDC_TICK_SEL_TIMER3    (BIT(24))
+#define LEDC_TICK_SEL_TIMER3_M  (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S)
+#define LEDC_TICK_SEL_TIMER3_V  0x00000001
+#define LEDC_TICK_SEL_TIMER3_S  24
+/* LEDC_TIMER3_PARA_UP : WT; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER3 and
+ * LEDC_TIMER3_DUTY_RES.
+ */
+#define LEDC_TIMER3_PARA_UP    (BIT(25))
+#define LEDC_TIMER3_PARA_UP_M  (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S)
+#define LEDC_TIMER3_PARA_UP_V  0x00000001
+#define LEDC_TIMER3_PARA_UP_S  25
 
-#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x00aC)
-/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_CNT  0x00003FFF
-#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
-#define LEDC_LSTIMER1_CNT_V  0x3FFF
-#define LEDC_LSTIMER1_CNT_S  0
+/** LEDC_TIMER3_VALUE_REG register
+ *  Timer 3 current counter
+ *  value
+ */
+#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc)
+/* LEDC_TIMER3_CNT : RO; bitpos: [14:0]; default: 0;
+ * This register stores the current counter value of timer
+ * 3.
+ */
+#define LEDC_TIMER3_CNT    0x00003FFF
+#define LEDC_TIMER3_CNT_M  (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S)
+#define LEDC_TIMER3_CNT_V  0x00003FFF
+#define LEDC_TIMER3_CNT_S  0
 
-#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x00b0)
-/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_V  0x1
-#define LEDC_LSTIMER2_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER2  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_V  0x1
-#define LEDC_TICK_SEL_LSTIMER2_S  24
-/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER2_RST  (BIT(23))
-#define LEDC_LSTIMER2_RST_M  (BIT(23))
-#define LEDC_LSTIMER2_RST_V  0x1
-#define LEDC_LSTIMER2_RST_S  23
-/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PAUSE  (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_V  0x1
-#define LEDC_LSTIMER2_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
-#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER2_S  4
-/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
-#define LEDC_LSTIMER2_DUTY_RES_V  0xF
-#define LEDC_LSTIMER2_DUTY_RES_S  0
 
-#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x00b4)
-/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_CNT  0x00003FFF
-#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
-#define LEDC_LSTIMER2_CNT_V  0x3FFF
-#define LEDC_LSTIMER2_CNT_S  0
+/** Interrupt Register */
 
-#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x00b8)
-/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_V  0x1
-#define LEDC_LSTIMER3_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER3  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_V  0x1
-#define LEDC_TICK_SEL_LSTIMER3_S  24
-/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER3_RST  (BIT(23))
-#define LEDC_LSTIMER3_RST_M  (BIT(23))
-#define LEDC_LSTIMER3_RST_V  0x1
-#define LEDC_LSTIMER3_RST_S  23
-/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PAUSE  (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_V  0x1
-#define LEDC_LSTIMER3_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
-#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER3_S  4
-/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
-#define LEDC_LSTIMER3_DUTY_RES_V  0xF
-#define LEDC_LSTIMER3_DUTY_RES_S  0
+/** LEDC_INT_RAW_REG register
+ *  Raw interrupt
+ *  status
+ */
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0)
+/* LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * Triggered when the timer0 has reached its maximum counter
+ * value.
+ */
+#define LEDC_TIMER0_OVF_INT_RAW    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_RAW_M  (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S)
+#define LEDC_TIMER0_OVF_INT_RAW_V  0x00000001
+#define LEDC_TIMER0_OVF_INT_RAW_S  0
+/* LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * Triggered when the timer1 has reached its maximum counter
+ * value.
+ */
+#define LEDC_TIMER1_OVF_INT_RAW    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_RAW_M  (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S)
+#define LEDC_TIMER1_OVF_INT_RAW_V  0x00000001
+#define LEDC_TIMER1_OVF_INT_RAW_S  1
+/* LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * Triggered when the timer2 has reached its maximum counter
+ * value.
+ */
+#define LEDC_TIMER2_OVF_INT_RAW    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_RAW_M  (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S)
+#define LEDC_TIMER2_OVF_INT_RAW_V  0x00000001
+#define LEDC_TIMER2_OVF_INT_RAW_S  2
+/* LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ * Triggered when the timer3 has reached its maximum counter
+ * value.
+ */
+#define LEDC_TIMER3_OVF_INT_RAW    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_RAW_M  (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S)
+#define LEDC_TIMER3_OVF_INT_RAW_V  0x00000001
+#define LEDC_TIMER3_OVF_INT_RAW_S  3
+/* LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * Interrupt raw bit for channel 0. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S  4
+/* LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * Interrupt raw bit for channel 1. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S  5
+/* LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * Interrupt raw bit for channel 2. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S  6
+/* LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * Interrupt raw bit for channel 3. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S  7
+/* LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ * Interrupt raw bit for channel 4. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S  8
+/* LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * Interrupt raw bit for channel 5. Triggered when the gradual change of
+ * duty has
+ * finished.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S  9
+/* LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH0.
+ */
+#define LEDC_OVF_CNT_CH0_INT_RAW    (BIT(10))
+#define LEDC_OVF_CNT_CH0_INT_RAW_M  (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S)
+#define LEDC_OVF_CNT_CH0_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH0_INT_RAW_S  10
+/* LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_RAW    (BIT(11))
+#define LEDC_OVF_CNT_CH1_INT_RAW_M  (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S)
+#define LEDC_OVF_CNT_CH1_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH1_INT_RAW_S  11
+/* LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH2.
+ */
+#define LEDC_OVF_CNT_CH2_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_CH2_INT_RAW_M  (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S)
+#define LEDC_OVF_CNT_CH2_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH2_INT_RAW_S  12
+/* LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH3.
+ */
+#define LEDC_OVF_CNT_CH3_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_CH3_INT_RAW_M  (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S)
+#define LEDC_OVF_CNT_CH3_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH3_INT_RAW_S  13
+/* LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH4.
+ */
+#define LEDC_OVF_CNT_CH4_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_CH4_INT_RAW_M  (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S)
+#define LEDC_OVF_CNT_CH4_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH4_INT_RAW_S  14
+/* LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached
+ * the value specified by
+ * LEDC_OVF_NUM_CH5.
+ */
+#define LEDC_OVF_CNT_CH5_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_CH5_INT_RAW_M  (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S)
+#define LEDC_OVF_CNT_CH5_INT_RAW_V  0x00000001
+#define LEDC_OVF_CNT_CH5_INT_RAW_S  15
 
-#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x00BC)
-/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_CNT  0x00003FFF
-#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
-#define LEDC_LSTIMER3_CNT_V  0x3FFF
-#define LEDC_LSTIMER3_CNT_S  0
+/** LEDC_INT_ST_REG register
+ *  Masked interrupt
+ *  status
+ */
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4)
+/* LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT
+ * interrupt when LEDC_TIMER0_OVF_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_TIMER0_OVF_INT_ST    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ST_M  (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S)
+#define LEDC_TIMER0_OVF_INT_ST_V  0x00000001
+#define LEDC_TIMER0_OVF_INT_ST_S  0
+/* LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT
+ * interrupt when LEDC_TIMER1_OVF_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_TIMER1_OVF_INT_ST    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ST_M  (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S)
+#define LEDC_TIMER1_OVF_INT_ST_V  0x00000001
+#define LEDC_TIMER1_OVF_INT_ST_S  1
+/* LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT
+ * interrupt when LEDC_TIMER2_OVF_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_TIMER2_OVF_INT_ST    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ST_M  (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S)
+#define LEDC_TIMER2_OVF_INT_ST_V  0x00000001
+#define LEDC_TIMER2_OVF_INT_ST_S  2
+/* LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT
+ * interrupt when LEDC_TIMER3_OVF_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_TIMER3_OVF_INT_ST    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ST_M  (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S)
+#define LEDC_TIMER3_OVF_INT_ST_V  0x00000001
+#define LEDC_TIMER3_OVF_INT_ST_S  3
+/* LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH0_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M  (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S  4
+/* LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH1_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M  (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S  5
+/* LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH2_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M  (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S  6
+/* LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH3_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M  (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S  7
+/* LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH4_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M  (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S  8
+/* LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH5_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to
+ * 1.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M  (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S  9
+/* LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT
+ * interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ST    (BIT(10))
+#define LEDC_OVF_CNT_CH0_INT_ST_M  (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S)
+#define LEDC_OVF_CNT_CH0_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH0_INT_ST_S  10
+/* LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT
+ * interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ST    (BIT(11))
+#define LEDC_OVF_CNT_CH1_INT_ST_M  (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S)
+#define LEDC_OVF_CNT_CH1_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH1_INT_ST_S  11
+/* LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT
+ * interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_CH2_INT_ST_M  (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S)
+#define LEDC_OVF_CNT_CH2_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH2_INT_ST_S  12
+/* LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [13]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT
+ * interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ST    (BIT(13))
+#define LEDC_OVF_CNT_CH3_INT_ST_M  (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S)
+#define LEDC_OVF_CNT_CH3_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH3_INT_ST_S  13
+/* LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [14]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT
+ * interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ST    (BIT(14))
+#define LEDC_OVF_CNT_CH4_INT_ST_M  (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S)
+#define LEDC_OVF_CNT_CH4_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH4_INT_ST_S  14
+/* LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [15]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT
+ * interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to
+ * 1.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ST    (BIT(15))
+#define LEDC_OVF_CNT_CH5_INT_ST_M  (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S)
+#define LEDC_OVF_CNT_CH5_INT_ST_V  0x00000001
+#define LEDC_OVF_CNT_CH5_INT_ST_S  15
 
-#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x00C0)
-/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_RAW    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_RAW    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_RAW    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_RAW    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_RAW    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_RAW    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  4
-/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_RAW_S  3
-/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_RAW_S  2
-/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_RAW_S  1
-/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_RAW_S  0
+/** LEDC_INT_ENA_REG register
+ *  Interrupt enable
+ *  bits
+ */
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8)
+/* LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER0_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER0_OVF_INT_ENA    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ENA_M  (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S)
+#define LEDC_TIMER0_OVF_INT_ENA_V  0x00000001
+#define LEDC_TIMER0_OVF_INT_ENA_S  0
+/* LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER1_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER1_OVF_INT_ENA    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ENA_M  (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S)
+#define LEDC_TIMER1_OVF_INT_ENA_V  0x00000001
+#define LEDC_TIMER1_OVF_INT_ENA_S  1
+/* LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER2_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER2_OVF_INT_ENA    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ENA_M  (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S)
+#define LEDC_TIMER2_OVF_INT_ENA_V  0x00000001
+#define LEDC_TIMER2_OVF_INT_ENA_S  2
+/* LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER3_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER3_OVF_INT_ENA    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ENA_M  (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S)
+#define LEDC_TIMER3_OVF_INT_ENA_V  0x00000001
+#define LEDC_TIMER3_OVF_INT_ENA_S  3
+/* LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S  4
+/* LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S  5
+/* LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S  6
+/* LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S  7
+/* LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S  8
+/* LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S  9
+/* LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH0_INT_ENA    (BIT(10))
+#define LEDC_OVF_CNT_CH0_INT_ENA_M  (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S)
+#define LEDC_OVF_CNT_CH0_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH0_INT_ENA_S  10
+/* LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH1_INT_ENA    (BIT(11))
+#define LEDC_OVF_CNT_CH1_INT_ENA_M  (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S)
+#define LEDC_OVF_CNT_CH1_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH1_INT_ENA_S  11
+/* LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH2_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_CH2_INT_ENA_M  (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S)
+#define LEDC_OVF_CNT_CH2_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH2_INT_ENA_S  12
+/* LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [13]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH3_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_CH3_INT_ENA_M  (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S)
+#define LEDC_OVF_CNT_CH3_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH3_INT_ENA_S  13
+/* LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [14]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH4_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_CH4_INT_ENA_M  (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S)
+#define LEDC_OVF_CNT_CH4_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH4_INT_ENA_S  14
+/* LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [15]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH5_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_CH5_INT_ENA_M  (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S)
+#define LEDC_OVF_CNT_CH5_INT_ENA_V  0x00000001
+#define LEDC_OVF_CNT_CH5_INT_ENA_S  15
 
-#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x00c4)
-/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ST_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ST_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ST_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ST    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ST_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ST    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ST_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ST    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ST_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  4
-/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ST_S  3
-/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ST_S  2
-/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ST_S  1
-/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ST_S  0
+/** LEDC_INT_CLR_REG register
+ *  Interrupt clear
+ *  bits
+ */
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc)
+/* LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the LEDC_TIMER0_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER0_OVF_INT_CLR    (BIT(0))
+#define LEDC_TIMER0_OVF_INT_CLR_M  (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S)
+#define LEDC_TIMER0_OVF_INT_CLR_V  0x00000001
+#define LEDC_TIMER0_OVF_INT_CLR_S  0
+/* LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the LEDC_TIMER1_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER1_OVF_INT_CLR    (BIT(1))
+#define LEDC_TIMER1_OVF_INT_CLR_M  (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S)
+#define LEDC_TIMER1_OVF_INT_CLR_V  0x00000001
+#define LEDC_TIMER1_OVF_INT_CLR_S  1
+/* LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the LEDC_TIMER2_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER2_OVF_INT_CLR    (BIT(2))
+#define LEDC_TIMER2_OVF_INT_CLR_M  (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S)
+#define LEDC_TIMER2_OVF_INT_CLR_V  0x00000001
+#define LEDC_TIMER2_OVF_INT_CLR_S  2
+/* LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the LEDC_TIMER3_OVF_INT
+ * interrupt.
+ */
+#define LEDC_TIMER3_OVF_INT_CLR    (BIT(3))
+#define LEDC_TIMER3_OVF_INT_CLR_M  (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S)
+#define LEDC_TIMER3_OVF_INT_CLR_V  0x00000001
+#define LEDC_TIMER3_OVF_INT_CLR_S  3
+/* LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR    (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S  4
+/* LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR    (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S  5
+/* LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR    (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S  6
+/* LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR    (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S  7
+/* LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR    (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S  8
+/* LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT
+ * interrupt.
+ */
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR    (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V  0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S  9
+/* LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH0_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH0_INT_CLR    (BIT(10))
+#define LEDC_OVF_CNT_CH0_INT_CLR_M  (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S)
+#define LEDC_OVF_CNT_CH0_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH0_INT_CLR_S  10
+/* LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH1_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH1_INT_CLR    (BIT(11))
+#define LEDC_OVF_CNT_CH1_INT_CLR_M  (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S)
+#define LEDC_OVF_CNT_CH1_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH1_INT_CLR_S  11
+/* LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH2_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH2_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_CH2_INT_CLR_M  (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S)
+#define LEDC_OVF_CNT_CH2_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH2_INT_CLR_S  12
+/* LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [13]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH3_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH3_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_CH3_INT_CLR_M  (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S)
+#define LEDC_OVF_CNT_CH3_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH3_INT_CLR_S  13
+/* LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [14]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH4_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH4_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_CH4_INT_CLR_M  (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S)
+#define LEDC_OVF_CNT_CH4_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH4_INT_CLR_S  14
+/* LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [15]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH5_INT
+ * interrupt.
+ */
+#define LEDC_OVF_CNT_CH5_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_CH5_INT_CLR_M  (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S)
+#define LEDC_OVF_CNT_CH5_INT_CLR_V  0x00000001
+#define LEDC_OVF_CNT_CH5_INT_CLR_S  15
 
-#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0xC8)
-/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ENA    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ENA    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ENA    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ENA    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ENA    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ENA    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  4
-/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ENA_S  3
-/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ENA_S  2
-/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ENA_S  1
-/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ENA_S  0
 
-#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0xCC)
-/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_CLR    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_CLR    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_CLR    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_CLR    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_CLR    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_CLR    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: reg_duty_chng_end_lsch5_int_clr..*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  4
-/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_CLR_S  3
-/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_CLR_S  2
-/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_CLR_S  1
-/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_CLR_S  0
+/** Version Register */
 
-#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x00d0)
-/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_CLK_EN  (BIT(31))
-#define LEDC_CLK_EN_M  (BIT(31))
-#define LEDC_CLK_EN_V  0x1
-#define LEDC_CLK_EN_S  31
-/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define LEDC_APB_CLK_SEL  0x00000003
-#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
-#define LEDC_APB_CLK_SEL_V  0x3
-#define LEDC_APB_CLK_SEL_S  0
+/** LEDC_DATE_REG register
+ *  Version control
+ *  register
+ */
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0xfc)
+/* LEDC_LEDC_DATE : R/W; bitpos: [32:0]; default: 419829504;
+ * This is the version control
+ * register.
+ */
+#define LEDC_LEDC_DATE    0xFFFFFFFF
+#define LEDC_LEDC_DATE_M  (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S)
+#define LEDC_LEDC_DATE_V  0xFFFFFFFF
+#define LEDC_LEDC_DATE_S  0
 
-#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x00FC)
-/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */
-/*description: */
-#define LEDC_DATE  0xFFFFFFFF
-#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
-#define LEDC_DATE_V  0xFFFFFFFF
-#define LEDC_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LEDC_REG_H_ */

components/soc/esp32c2/include/soc/ledc_struct.h

@@ -1,209 +1,596 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_LEDC_STRUCT_H_
-#define _SOC_LEDC_STRUCT_H_
+#pragma once
+
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct ledc_dev_s {
+/** Group: Configuration Register */
+/** Type of chn_conf0 register
+ *  Configuration register 0 for channel n
+ */
+typedef union {
+    struct {
+        /** timer_sel : R/W; bitpos: [1:0]; default: 0;
+         *  This field is used to select one of timers for channel n.
+         *
+         *  0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3
+         */
+        uint32_t timer_sel:2;
+        /** sig_out_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable signal output on channel n.
+         */
+        uint32_t sig_out_en:1;
+        /** idle_lv : R/W; bitpos: [3]; default: 0;
+         *  This bit is used to control the output value when channel n is inactive (when
+         *  LEDC_SIG_OUT_EN_CHn is 0).
+         */
+        uint32_t idle_lv:1;
+        /** para_up : WT; bitpos: [4]; default: 0;
+         *  This bit is used to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
+         *  LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn,
+         *  LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel
+         *  n, and will be automatically cleared by hardware.
+         */
+        uint32_t para_up:1;
+        /** ovf_num : R/W; bitpos: [14:5]; default: 0;
+         *  This register is used to configure the maximum times of overflow minus 1.
+         *
+         *  The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for
+         *  (LEDC_OVF_NUM_CHn + 1) times.
+         */
+        uint32_t ovf_num:10;
+        /** ovf_cnt_en : R/W; bitpos: [15]; default: 0;
+         *  This bit is used to enable the ovf_cnt of channel n.
+         */
+        uint32_t ovf_cnt_en:1;
+        /** ovf_cnt_reset : WT; bitpos: [16]; default: 0;
+         *  Set this bit to reset the ovf_cnt of channel n.
+         */
+        uint32_t ovf_cnt_reset:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} ledc_chn_conf0_reg_t;
+
+/** Type of chn_conf1 register
+ *  Configuration register 1 for channel n
+ */
+typedef union {
+    struct {
+        /** duty_scale : R/W; bitpos: [9:0]; default: 0;
+         *  This register is used to configure the changing step scale of duty on channel n.
+         */
+        uint32_t duty_scale:10;
+        /** duty_cycle : R/W; bitpos: [19:10]; default: 0;
+         *  The duty will change every LEDC_DUTY_CYCLE_CHn on channel n.
+         */
+        uint32_t duty_cycle:10;
+        /** duty_num : R/W; bitpos: [29:20]; default: 0;
+         *  This register is used to control the number of times the duty cycle will be changed.
+         */
+        uint32_t duty_num:10;
+        /** duty_inc : R/W; bitpos: [30]; default: 1;
+         *  This register is used to increase or decrease the duty of output signal on channel
+         *  n. 1: Increase; 0: Decrease.
+         */
+        uint32_t duty_inc:1;
+        /** duty_start : R/W/SC; bitpos: [31]; default: 0;
+         *  Other configured fields in LEDC_CHn_CONF1_REG will start to take effect when this
+         *  bit is set to 1.
+         */
+        uint32_t duty_start:1;
+    };
+    uint32_t val;
+} ledc_chn_conf1_reg_t;
+
+/** Type of conf register
+ *  Global ledc configuration register
+ */
+typedef union {
+    struct {
+        /** apb_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  This bit is used to select clock source for the 4 timers .
+         *
+         *  2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK
+         */
+        uint32_t apb_clk_sel:2;
+        uint32_t reserved_2:29;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  This bit is used to control clock.
+         *
+         *  1'b1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} ledc_conf_reg_t;
+
+
+/** Group: Hpoint Register */
+/** Type of chn_hpoint register
+ *  High point register for channel n
+ */
+typedef union {
+    struct {
+        /** hpoint : R/W; bitpos: [13:0]; default: 0;
+         *  The output value changes to high when the selected timers has reached the value
+         *  specified by this register.
+         */
+        uint32_t hpoint:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ledc_chn_hpoint_reg_t;
+
+
+/** Group: Duty Cycle Register */
+/** Type of chn_duty register
+ *  Initial duty cycle for channel n
+ */
+typedef union {
+    struct {
+        /** duty : R/W; bitpos: [18:0]; default: 0;
+         *  This register is used to change the output duty by controlling the Lpoint.
+         *
+         *  The output value turns to low when the selected timers has reached the Lpoint.
+         */
+        uint32_t duty:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} ledc_chn_duty_reg_t;
+
+/** Type of chn_duty_r register
+ *  Current duty cycle for channel n
+ */
+typedef union {
+    struct {
+        /** duty_r : RO; bitpos: [18:0]; default: 0;
+         *  This register stores the current duty of output signal on channel n.
+         */
+        uint32_t duty_r:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} ledc_chn_duty_r_reg_t;
+
+
+/** Group: Timer Register */
+/** Type of timerx_conf register
+ *  Timer x configuration
+ */
+typedef union {
+    struct {
+        /** duty_res : R/W; bitpos: [3:0]; default: 0;
+         *  This register is used to control the range of the counter in timer x.
+         */
+        uint32_t duty_res:4;
+        /** clk_div : R/W; bitpos: [21:4]; default: 0;
+         *  This register is used to configure the divisor for the divider in timer x.
+         *
+         *  The least significant eight bits represent the fractional part.
+         */
+        uint32_t clk_div:18;
+        /** pause : R/W; bitpos: [22]; default: 0;
+         *  This bit is used to suspend the counter in timer x.
+         */
+        uint32_t pause:1;
+        /** rst : R/W; bitpos: [23]; default: 1;
+         *  This bit is used to reset timer x. The counter will show 0 after reset.
+         */
+        uint32_t rst:1;
+        uint32_t reserved_24:1;
+        /** para_up : WT; bitpos: [25]; default: 0;
+         *  Set this bit to update LEDC_CLK_DIV_TIMERx and LEDC_TIMERx_DUTY_RES.
+         */
+        uint32_t para_up:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} ledc_timerx_conf_reg_t;
+
+/** Type of timerx_value register
+ *  Timer x current counter value
+ */
+typedef union {
+    struct {
+        /** timer_cnt : RO; bitpos: [13:0]; default: 0;
+         *  This register stores the current counter value of timer x.
+         */
+        uint32_t timer_cnt:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} ledc_timerx_value_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Triggered when the timer0 has reached its maximum counter value.
+         */
+        uint32_t timer0_ovf_int_raw:1;
+        /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Triggered when the timer1 has reached its maximum counter value.
+         */
+        uint32_t timer1_ovf_int_raw:1;
+        /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Triggered when the timer2 has reached its maximum counter value.
+         */
+        uint32_t timer2_ovf_int_raw:1;
+        /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Triggered when the timer3 has reached its maximum counter value.
+         */
+        uint32_t timer3_ovf_int_raw:1;
+        /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Interrupt raw bit for channel 0. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch0_int_raw:1;
+        /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Interrupt raw bit for channel 1. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch1_int_raw:1;
+        /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Interrupt raw bit for channel 2. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch2_int_raw:1;
+        /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Interrupt raw bit for channel 3. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch3_int_raw:1;
+        /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Interrupt raw bit for channel 4. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch4_int_raw:1;
+        /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Interrupt raw bit for channel 5. Triggered when the gradual change of duty has
+         *  finished.
+         */
+        uint32_t duty_chng_end_ch5_int_raw:1;
+        /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH0.
+         */
+        uint32_t ovf_cnt_ch0_int_raw:1;
+        /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH1.
+         */
+        uint32_t ovf_cnt_ch1_int_raw:1;
+        /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH2.
+         */
+        uint32_t ovf_cnt_ch2_int_raw:1;
+        /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH3.
+         */
+        uint32_t ovf_cnt_ch3_int_raw:1;
+        /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH4.
+         */
+        uint32_t ovf_cnt_ch4_int_raw:1;
+        /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value
+         *  specified by LEDC_OVF_NUM_CH5.
+         */
+        uint32_t ovf_cnt_ch5_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ledc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when
+         *  LEDC_TIMER0_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer0_ovf_int_st:1;
+        /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when
+         *  LEDC_TIMER1_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer1_ovf_int_st:1;
+        /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when
+         *  LEDC_TIMER2_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer2_ovf_int_st:1;
+        /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when
+         *  LEDC_TIMER3_OVF_INT_ENA is set to 1.
+         */
+        uint32_t timer3_ovf_int_st:1;
+        /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch0_int_st:1;
+        /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch1_int_st:1;
+        /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch2_int_st:1;
+        /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch3_int_st:1;
+        /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch4_int_st:1;
+        /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT
+         *  interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.
+         */
+        uint32_t duty_chng_end_ch5_int_st:1;
+        /** ovf_cnt_ch0_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when
+         *  LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch0_int_st:1;
+        /** ovf_cnt_ch1_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when
+         *  LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch1_int_st:1;
+        /** ovf_cnt_ch2_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when
+         *  LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch2_int_st:1;
+        /** ovf_cnt_ch3_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when
+         *  LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch3_int_st:1;
+        /** ovf_cnt_ch4_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when
+         *  LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch4_int_st:1;
+        /** ovf_cnt_ch5_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when
+         *  LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+         */
+        uint32_t ovf_cnt_ch5_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ledc_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
     struct {
-        struct {
-            union {
-                struct {
-                    uint32_t timer_sel                     :    2;  /*This field is used to select one of timers for channel $n.; ; 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3*/
-                    uint32_t sig_out_en                    :    1;  /*Set this bit to enable signal output on channel $n.*/
-                    uint32_t idle_lv                       :    1;  /*This bit is used to control the output value when channel $n is inactive (when LEDC_SIG_OUT_EN_CH$n is 0).*/
-                    uint32_t low_speed_update              :    1;  /*This bit is used to update LEDC_HPOINT_CH$n, LEDC_DUTY_START_CH$n, LEDC_SIG_OUT_EN_CH$n, LEDC_TIMER_SEL_CH$n, LEDC_DUTY_NUM_CH$n, LEDC_DUTY_CYCLE_CH$n, LEDC_DUTY_SCALE_CH$n, LEDC_DUTY_INC_CH$n, and LEDC_OVF_CNT_EN_CH$n fields for channel $n, and will be automatically cleared by hardware.*/
-                    uint32_t ovf_num                       :    10;  /*This register is used to configure the maximum times of overflow minus 1.; ; The LEDC_OVF_CNT_CH$n_INT interrupt will be triggered when channel $n overflows for (LEDC_OVF_NUM_CH$n + 1) times.*/
-                    uint32_t ovf_cnt_en                    :    1;  /*This bit is used to enable the ovf_cnt of channel $n.*/
-                    uint32_t ovf_cnt_rst                   :    1;  /*Set this bit to reset the ovf_cnt of channel $n.*/
-                    uint32_t reserved17                    :    15;  /*Reserved*/
-                };
-                uint32_t val;
-            } conf0;
-            union {
-                struct {
-                    uint32_t hpoint                        :    14;  /*The output value changes to high when the selected timers has reached the value specified by this register.*/
-                    uint32_t reserved14                    :    18;  /*Reserved*/
-                };
-                uint32_t val;
-            } hpoint;
-            union {
-                struct {
-                    uint32_t duty                          :    19;  /*This register is used to change the output duty by controlling the Lpoint.; ; The output value turns to low when the selected timers has reached the Lpoint.*/
-                    uint32_t reserved19                    :    13;  /*Reserved*/
-                };
-                uint32_t val;
-            } duty;
-            union {
-                struct {
-                    uint32_t duty_scale                    :    10;  /*This register is used to configure the changing step scale of duty on channel $n.*/
-                    uint32_t duty_cycle                    :    10;  /*The duty will change every LEDC_DUTY_CYCLE_CH$n on channel $n.*/
-                    uint32_t duty_num                      :    10;  /*This register is used to control the number of times the duty cycle will be changed.*/
-                    uint32_t duty_inc                      :    1;  /*This register is used to increase or decrease the duty of output signal on channel $n. 1: Increase; 0: Decrease.*/
-                    uint32_t duty_start                    :    1;  /*Other configured fields in LEDC_CH$n_CONF1_REG will start to take effect when this bit is set to 1.*/
-                };
-                uint32_t val;
-            } conf1;
-            union {
-                struct {
-                    uint32_t duty_read                     :    19;  /*This register stores the current duty of output signal on channel $n.*/
-                    uint32_t reserved19                    :    13;  /*Reserved*/
-                };
-                uint32_t val;
-            } duty_rd;
-        } channel[6];
-    } channel_group[1];
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
+        /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.
+         */
+        uint32_t timer0_ovf_int_ena:1;
+        /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.
+         */
+        uint32_t timer1_ovf_int_ena:1;
+        /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.
+         */
+        uint32_t timer2_ovf_int_ena:1;
+        /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.
+         */
+        uint32_t timer3_ovf_int_ena:1;
+        /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch0_int_ena:1;
+        /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch1_int_ena:1;
+        /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch2_int_ena:1;
+        /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch3_int_ena:1;
+        /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch4_int_ena:1;
+        /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch5_int_ena:1;
+        /** ovf_cnt_ch0_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch0_int_ena:1;
+        /** ovf_cnt_ch1_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch1_int_ena:1;
+        /** ovf_cnt_ch2_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch2_int_ena:1;
+        /** ovf_cnt_ch3_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch3_int_ena:1;
+        /** ovf_cnt_ch4_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch4_int_ena:1;
+        /** ovf_cnt_ch5_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch5_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ledc_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
     struct {
-        struct {
-            union {
-                struct {
-                    uint32_t duty_resolution               :    4;  /*This register is used to control the range of the counter in timer $x.*/
-                    uint32_t clock_divider                 :    18;  /*This register is used to configure the divisor for the divider in timer $x.; ; The least significant eight bits represent the fractional part.*/
-                    uint32_t pause                         :    1;  /*This bit is used to suspend the counter in timer $x.*/
-                    uint32_t rst                           :    1;  /*This bit is used to reset timer $x. The counter will show 0 after reset.*/
-                    uint32_t reserved24                    :    1;  /*Reserved*/
-                    uint32_t low_speed_update              :    1;  /*Set this bit to update LEDC_CLK_DIV_TIMER$x and LEDC_TIMER$x_DUTY_RES.*/
-                    uint32_t reserved26                    :    6;  /*Reserved*/
-                };
-                uint32_t val;
-            } conf;
-            union {
-                struct {
-                    uint32_t timer_cnt                     :    14;  /*This register stores the current counter value of timer $x.*/
-                    uint32_t reserved14                    :    18;  /*Reserved*/
-                };
-                uint32_t val;
-            } value;
-        } timer[4];
-    } timer_group[1];
-    union {
-        struct {
-            uint32_t lstimer0_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
-            uint32_t lstimer1_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
-            uint32_t lstimer2_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
-            uint32_t lstimer3_ovf                  :    1;  /*Triggered when the timer$x has reached its maximum counter value.*/
-            uint32_t duty_chng_end_ch0             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t duty_chng_end_ch1             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t duty_chng_end_ch2             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t duty_chng_end_ch3             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t duty_chng_end_ch4             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t duty_chng_end_ch5             :    1;  /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
-            uint32_t ovf_cnt_ch0                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t ovf_cnt_ch1                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t ovf_cnt_ch2                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t ovf_cnt_ch3                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t ovf_cnt_ch4                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t ovf_cnt_ch5                   :    1;  /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t lstimer0_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
-            uint32_t lstimer1_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
-            uint32_t lstimer2_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
-            uint32_t lstimer3_ovf                  :    1;  /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
-            uint32_t duty_chng_end_ch0             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t duty_chng_end_ch1             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t duty_chng_end_ch2             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t duty_chng_end_ch3             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t duty_chng_end_ch4             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t duty_chng_end_ch5             :    1;  /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
-            uint32_t ovf_cnt_ch0                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t ovf_cnt_ch1                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t ovf_cnt_ch2                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t ovf_cnt_ch3                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t ovf_cnt_ch4                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t ovf_cnt_ch5                   :    1;  /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t lstimer0_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer1_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer2_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer3_ovf                  :    1;  /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t duty_chng_end_ch0             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch1             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch2             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch3             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch4             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch5             :    1;  /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch0                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch1                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch2                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch3                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch4                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch5                   :    1;  /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t lstimer0_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer1_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer2_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t lstimer3_ovf                  :    1;  /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
-            uint32_t duty_chng_end_ch0             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch1             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch2             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch3             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch4             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t duty_chng_end_ch5             :    1;  /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch0                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch1                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch2                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch3                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch4                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t ovf_cnt_ch5                   :    1;  /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t apb_clk_sel                   :    2;  /*This bit is used to select clock source for the 4 timers .; ; 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK*/
-            uint32_t reserved2                     :    29;  /*Reserved*/
-            uint32_t clk_en                        :    1;  /*This bit is used to control clock.; ; 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-        };
-        uint32_t val;
-    } conf;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;
+        /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.
+         */
+        uint32_t timer0_ovf_int_clr:1;
+        /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.
+         */
+        uint32_t timer1_ovf_int_clr:1;
+        /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.
+         */
+        uint32_t timer2_ovf_int_clr:1;
+        /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.
+         */
+        uint32_t timer3_ovf_int_clr:1;
+        /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch0_int_clr:1;
+        /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch1_int_clr:1;
+        /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch2_int_clr:1;
+        /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch3_int_clr:1;
+        /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch4_int_clr:1;
+        /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.
+         */
+        uint32_t duty_chng_end_ch5_int_clr:1;
+        /** ovf_cnt_ch0_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch0_int_clr:1;
+        /** ovf_cnt_ch1_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch1_int_clr:1;
+        /** ovf_cnt_ch2_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch2_int_clr:1;
+        /** ovf_cnt_ch3_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch3_int_clr:1;
+        /** ovf_cnt_ch4_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch4_int_clr:1;
+        /** ovf_cnt_ch5_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.
+         */
+        uint32_t ovf_cnt_ch5_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ledc_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** ledc_date : R/W; bitpos: [31:0]; default: 419829504;
+         *  This is the version control register.
+         */
+        uint32_t ledc_date:32;
+    };
+    uint32_t val;
+} ledc_date_reg_t;
+
+typedef struct {
+    volatile ledc_chn_conf0_reg_t conf0;
+    volatile ledc_chn_hpoint_reg_t hpoint;
+    volatile ledc_chn_duty_reg_t duty;
+    volatile ledc_chn_conf1_reg_t conf1;
+    volatile ledc_chn_duty_r_reg_t duty_rd;
+} ledc_chn_reg_t;
+
+typedef struct {
+    volatile ledc_chn_reg_t channel[6];
+} ledc_ch_group_reg_t;
+
+typedef struct {
+    volatile ledc_timerx_conf_reg_t conf;
+    volatile ledc_timerx_value_reg_t value;
+} ledc_timerx_reg_t;
+
+typedef struct {
+    volatile ledc_timerx_reg_t timer[4];
+} ledc_timer_group_reg_t;
+
+typedef struct ledc_dev_t {
+    volatile ledc_ch_group_reg_t channel_group[1];
+    uint32_t reserved_078[10];
+    volatile ledc_timer_group_reg_t timer_group[1];
+    volatile ledc_int_raw_reg_t int_raw;
+    volatile ledc_int_st_reg_t int_st;
+    volatile ledc_int_ena_reg_t int_ena;
+    volatile ledc_int_clr_reg_t int_clr;
+    volatile ledc_conf_reg_t conf;
+    uint32_t reserved_0d4[10];
+    volatile ledc_date_reg_t date;
 } ledc_dev_t;
+
 extern ledc_dev_t LEDC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ledc_dev_t) == 0x100, "Invalid size of ledc_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_LEDC_STRUCT_H_ */

components/soc/esp32c2/include/soc/soc_caps.h

@@ -125,10 +125,11 @@
 #define SOC_I2C_SUPPORT_RTC         (1)
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
-#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
-#define SOC_LEDC_CHANNEL_NUM         (6)
-#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
-#define SOC_LEDC_SUPPORT_FADE_STOP   (1)
+#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK  (1)
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK     (1)
+#define SOC_LEDC_CHANNEL_NUM            (6)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM     (14)
+#define SOC_LEDC_SUPPORT_FADE_STOP      (1)
 
 /*-------------------------- MPU CAPS ----------------------------------------*/
 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -335,6 +335,10 @@ config SOC_I2S_SUPPORTS_TDM
     bool
     default y
 
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -171,6 +171,7 @@
 #define SOC_I2S_SUPPORTS_TDM        (1)
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_APB_CLOCK   (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
 #define SOC_LEDC_CHANNEL_NUM         (6)
 #define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -327,6 +327,10 @@ config SOC_I2S_SUPPORTS_TDM
     bool
     default y
 
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -182,6 +182,7 @@
 #define SOC_I2S_SUPPORTS_TDM        (1)
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_APB_CLOCK   (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
 #define SOC_LEDC_CHANNEL_NUM         (6)
 #define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -359,6 +359,10 @@ config SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
     bool
     default y
 
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_REF_TICK
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -183,11 +183,12 @@
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX  (1)
-#define SOC_LEDC_SUPPORT_REF_TICK    (1)
-#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
-#define SOC_LEDC_CHANNEL_NUM         (8)
-#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
-#define SOC_LEDC_SUPPORT_FADE_STOP   (1)
+#define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
+#define SOC_LEDC_SUPPORT_REF_TICK        (1)
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_CHANNEL_NUM             (8)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM      (14)
+#define SOC_LEDC_SUPPORT_FADE_STOP       (1)
 
 /*-------------------------- MPU CAPS ----------------------------------------*/
 //TODO: correct the caller and remove unsupported lines

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -23,6 +23,10 @@ config SOC_CPU_HAS_FPU
     bool
     default y
 
+config SOC_LEDC_SUPPORT_APB_CLOCK
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y

components/soc/esp32s3/include/soc/ledc_caps.h

@@ -10,8 +10,9 @@
 extern "C" {
 #endif
 
+#define SOC_LEDC_SUPPORT_APB_CLOCK   (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
-#define SOC_LEDC_CHANNEL_NUM 8
+#define SOC_LEDC_CHANNEL_NUM         (8)
 #define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP   (1)
 

docs/docs_not_updated/esp32c2.txt

@@ -88,7 +88,6 @@ api-reference/peripherals/adc
 api-reference/peripherals/sdspi_host
 api-reference/peripherals/lcd
 api-reference/peripherals/secure_element
-api-reference/peripherals/ledc
 api-reference/peripherals/temp_sensor
 api-reference/peripherals/spi_slave_hd
 api-reference/peripherals/i2c

docs/en/api-reference/peripherals/ledc.rst

@@ -1,6 +1,6 @@
 LED Control (LEDC)
 ==================
-{IDF_TARGET_LEDC_CHAN_NUM:default="8", esp32="16", esp32s2="8", esp32c3="6", esp32s3="8"}
+{IDF_TARGET_LEDC_CHAN_NUM:default="8", esp32="16", esp32s2="8", esp32c3="6", esp32s3="8", esp32c2="6", esp32h2="6"}
 
 :link_to_translation:`zh_CN:[中文]`
 
@@ -127,9 +127,57 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - 40 MHz
          - Dynamic Frequency Scaling compatible
 
-    .. note::
+.. only:: esp32c2
+
+    .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
+       :widths: 15 15 30
+       :header-rows: 1
+
+       * - Clock name
+         - Clock freq
+         - Clock capabilities
+       * - PLL_60M_CLK
+         - 60 MHz
+         - /
+       * - RTC20M_CLK
+         - ~20 MHz
+         - Dynamic Frequency Scaling compatible, Light sleep compatible
+       * - XTAL_CLK
+         - 40 MHz
+         - Dynamic Frequency Scaling compatible
+
+.. only:: esp32h2
+
+    .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
+       :widths: 15 15 30
+       :header-rows: 1
+
+       * - Clock name
+         - Clock freq
+         - Clock capabilities
+       * - APB_CLK
+         - 96 MHz
+         - /
+       * - RTC8M_CLK
+         - ~8 MHz
+         - Dynamic Frequency Scaling compatible, Light sleep compatible
+       * - XTAL_CLK
+         - 32 MHz
+         - Dynamic Frequency Scaling compatible
+
+.. note::
+
+    .. only:: not esp32h2
+
+        1. On {IDF_TARGET_NAME}, if RTCxM_CLK is chosen as the LEDC clock source, an internal calibration will be performed to get the exact frequency of the clock. This ensures the accuracy of output PWM signal frequency.
+
+    .. only:: esp32h2
+
+        1. On {IDF_TARGET_NAME}, if RTC8M_CLK is chosen as the LEDC clock source, you may see the frequency of output PWM signal is not very accurate. This is because no internal calibration is performed to get the exact frequency of the clock due to hardware limitation, a theoretic frequency value is used.
+
+    .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
 
-        For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers.
+        2. For {IDF_TARGET_NAME}, all timers share one clock source. In other words, it is impossible to use different clock sources for different timers.
 
 
 .. _ledc-api-configure-channel:

docs/zh_CN/api-reference/peripherals/ledc.rst

@@ -1,6 +1,6 @@
 LED PWM 控制器
 ==============
-{IDF_TARGET_LEDC_CHAN_NUM:default="8", esp32="16", esp32s2="8", esp32c3="6", esp32s3="8"}
+{IDF_TARGET_LEDC_CHAN_NUM:default="8", esp32="16", esp32s2="8", esp32c3="6", esp32s3="8", esp32c2="6", esp32h2="6"}
 
 :link_to_translation:`en:[English]`
 
@@ -127,9 +127,57 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实
          - 40 MHz
          - 支持动态调频（DFS）功能
 
-    .. note::
+.. only:: esp32c2
+
+    .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性
+       :widths: 10 10 30
+       :header-rows: 1
+
+       * - 时钟名称
+         - 时钟频率
+         - 时钟功能
+       * - PLL_60M_CLK
+         - 60 MHz
+         - /
+       * - RTC20M_CLK
+         - ~20 MHz
+         - 支持动态调频（DFS）功能，支持Light-sleep模式
+       * - XTAL_CLK
+         - 40 MHz
+         - 支持动态调频（DFS）功能
+
+.. only:: esp32h2
+
+    .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性
+       :widths: 10 10 30
+       :header-rows: 1
+
+       * - 时钟名称
+         - 时钟频率
+         - 时钟功能
+       * - APB_CLK
+         - 96 MHz
+         - /
+       * - RTC8M_CLK
+         - ~8 MHz
+         - 支持动态调频（DFS）功能，支持Light-sleep模式
+       * - XTAL_CLK
+         - 32 MHz
+         - 支持动态调频（DFS）功能
+
+.. note::
+
+    .. only:: not esp32h2
+
+        1. 如果 {IDF_TARGET_NAME} 的定时器选用了RTCxM_CLK作为其时钟源，驱动会通过内部校准来得知这个时钟源的实际频率。这样确保了输出PWM信号频率的精准性。
+
+    .. only:: esp32h2
+
+        1. 如果 {IDF_TARGET_NAME} 的定时器选用了RTC8M_CLK作为其时钟源，LEDC的输出PWM信号频率可能会与设定值有一定偏差。由于{IDF_TARGET_NAME} 的硬件限制，驱动无法通过内部校准得知这个时钟源的实际频率。因此驱动默认使用其理论频率进行计算。
+
+    .. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
 
-        {IDF_TARGET_NAME}的所有定时器共用一个时钟源。因此{IDF_TARGET_NAME}不支持给不同的定时器配置不同的时钟源。
+        2. {IDF_TARGET_NAME} 的所有定时器共用一个时钟源。因此 {IDF_TARGET_NAME} 不支持给不同的定时器配置不同的时钟源。
 
 
 .. _ledc-api-configure-channel:

examples/bluetooth/esp_ble_mesh/common_components/light_driver/iot_led.c

@@ -150,9 +150,9 @@ static IRAM_ATTR esp_err_t _iot_set_fade_with_time(ledc_mode_t speed_mode, ledc_
     uint32_t precision = (0x1U << duty_resolution);
 
     if (timer_source_clk == LEDC_APB_CLK) {
-        freq = ((uint64_t)LEDC_APB_CLK_HZ << 8) / precision / clock_divider;
+        freq = ((uint64_t)APB_CLK_FREQ << 8) / precision / clock_divider;
     } else {
-        freq = ((uint64_t)LEDC_REF_CLK_HZ << 8) / precision / clock_divider;
+        freq = ((uint64_t)REF_CLK_FREQ << 8) / precision / clock_divider;
     }
 
     if (duty_delta == 0) {

examples/peripherals/gpio/generic_gpio/README.md

@@ -31,7 +31,7 @@ Before project configuration and build, be sure to set the correct chip target u
 
 ### Hardware Required
 
-* A development board with with any Espressif SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
+* A development board with any Espressif SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
 * A USB cable for Power supply and programming
 * Some jumper wires to connect GPIOs.
 

examples/peripherals/ledc/ledc_basic/README.md

@@ -9,7 +9,7 @@ To use `HIGH SPEED` mode check if the selected SoC supports this mode.
 
 ### Hardware Required
 
-* A development board with ESP32, ESP32-S2, ESP32-C3 or ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
+* A development board with any Espressif SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
 * A USB cable for power supply and programming
 
 Connect the GPIO to an oscilloscope to see the generated signal:

examples/peripherals/ledc/ledc_fade/README.md

@@ -2,23 +2,21 @@
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
 
-This example shows how to control intensity of LEDs using ESP32's on-board hardware LED PWM Controller module.
+This example shows how to control intensity of LEDs using selected SoC's on-board hardware LED PWM Controller module.
 
 ## How to use example
 
 ### Hardware Required
 
-* A development board with ESP32 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
+* A development board with any Espressif SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
 * A USB cable for power supply and programming
 
 Connect four LEDs to the following LEDC channels / individual GPIOs:
 
-|ledc channel|GPIO|
-|:---:|:---:|
-|channel 0|GPIO18|
-|channel 1|GPIO19|
-|channel 2|GPIO4|
-|channel 3|GPIO5|
+|                 | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
+| --------------- | --------- | --------- | --------- | --------- |
+|     ESP32       | GPIO18    | GPIO19    | GPIO4     | GPIO5     |
+| All other chips | GPIO8     | GPIO9     | GPIO4     | GPIO5     |
 
 ### Configure the project
 
@@ -28,19 +26,13 @@ idf.py menuconfig
 
 ### Build and Flash
 
-* [ESP-IDF Getting Started Guide on ESP32](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html)
-* [ESP-IDF Getting Started Guide on ESP32-S2](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/get-started/index.html)
-* [ESP-IDF Getting Started Guide on ESP32-C3](https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/get-started/index.html)
+Build the project and flash it to the board, then run the monitor tool to view the serial output:
 
-Build the project and flash it to the board, then run monitor tool to view serial output:
-
-```
-idf.py -p PORT flash monitor
-```
+Run `idf.py -p PORT flash monitor` to build, flash and monitor the project.
 
 (To exit the serial monitor, type ``Ctrl-]``.)
 
-See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
 
 ## Example Output
 

examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c

@@ -27,11 +27,14 @@
  *
  * 3. You can also set a target duty directly without fading.
  *
- * 4. This example uses GPIO18/19/4/5 as LEDC output,
- *    and it will change the duty repeatedly.
+ * 4. On ESP32, GPIO18/19/4/5 are used as the LEDC outputs:
+ *              GPIO18/19 are from the high speed channel group
+ *              GPIO4/5 are from the low speed channel group
  *
- * 5. GPIO18/19 are from high speed channel group.
- *    GPIO4/5 are from low speed channel group.
+ *    On other targets, GPIO8/9/4/5 are used as the LEDC outputs,
+ *    and they are all from the low speed channel group.
+ *
+ * 5. All the LEDC outputs change the duty repeatedly.
  *
  */
 #if CONFIG_IDF_TARGET_ESP32
@@ -45,9 +48,9 @@
 #define LEDC_LS_TIMER          LEDC_TIMER_1
 #define LEDC_LS_MODE           LEDC_LOW_SPEED_MODE
 #if !CONFIG_IDF_TARGET_ESP32
-#define LEDC_LS_CH0_GPIO       (18)
+#define LEDC_LS_CH0_GPIO       (8)
 #define LEDC_LS_CH0_CHANNEL    LEDC_CHANNEL_0
-#define LEDC_LS_CH1_GPIO       (19)
+#define LEDC_LS_CH1_GPIO       (9)
 #define LEDC_LS_CH1_CHANNEL    LEDC_CHANNEL_1
 #endif
 #define LEDC_LS_CH2_GPIO       (4)

tools/ci/check_copyright_ignore.txt

@@ -909,7 +909,6 @@ components/hal/include/hal/ds_hal.h
 components/hal/include/hal/esp_flash_err.h
 components/hal/include/hal/interrupt_controller_hal.h
 components/hal/include/hal/interrupt_controller_types.h
-components/hal/include/hal/ledc_hal.h
 components/hal/include/hal/mcpwm_hal.h
 components/hal/include/hal/mcpwm_types.h
 components/hal/include/hal/mpu_hal.h