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@@ -86,6 +86,7 @@ typedef struct {
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i2s_mode_t mode; /*!< I2S Working mode*/
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uint32_t sample_rate; /*!< I2S sample rate */
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bool use_apll; /*!< I2S use APLL clock */
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+ bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
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int fixed_mclk; /*!< I2S fixed MLCK clock */
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} i2s_obj_t;
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@@ -502,6 +503,12 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
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// All buffers are empty. This means we have an underflow on our hands.
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if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) {
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xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &high_priority_task_awoken);
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+ // See if tx descriptor needs to be auto cleared:
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+ // This will avoid any kind of noise that may get introduced due to transmission
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+ // of previous data from tx descriptor on I2S line.
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+ if (p_i2s->tx_desc_auto_clear == true) {
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+ memset((void *) dummy, 0, p_i2s->tx->buf_size);
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+ }
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}
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xQueueSendFromISR(p_i2s->tx->queue, (void*)(&finish_desc->buf), &high_priority_task_awoken);
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if (p_i2s->i2s_queue) {
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@@ -991,6 +998,7 @@ static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_co
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}
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p_i2s_obj[i2s_num]->use_apll = i2s_config->use_apll;
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+ p_i2s_obj[i2s_num]->tx_desc_auto_clear = i2s_config->tx_desc_auto_clear;
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p_i2s_obj[i2s_num]->fixed_mclk = i2s_config->fixed_mclk;
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return ESP_OK;
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}
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