Merge branch 'refactor/mspi_clk_src_switch_h2' into 'master'

spi_flash: Small code refactor on MSPI clock source switch at bootloader

See merge request espressif/esp-idf!22763

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c

@@ -27,6 +27,7 @@
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
 #include "hal/mmu_ll.h"
+#include "soc/pcr_reg.h"
 
 void bootloader_flash_update_id()
 {
@@ -81,6 +82,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
     esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
 }
 
+static void IRAM_ATTR bootloader_flash_clock_init(void)
+{
+    // At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
+    REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
+}
+
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
     uint32_t size;
@@ -180,6 +187,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
 
 static void IRAM_ATTR bootloader_init_flash_configure(void)
 {
+    bootloader_flash_clock_init();
     bootloader_configure_spi_pins(1);
     bootloader_flash_cs_timing_config();
 }

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -18,7 +18,6 @@
 #include "esp_rom_sys.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
-#include "hal/spimem_flash_ll.h"
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "soc/lp_clkrst_reg.h"
@@ -154,7 +153,6 @@ static void rtc_clk_bbpll_disable(void)
 static void rtc_clk_bbpll_enable(void)
 {
     clk_ll_bbpll_enable();
-    spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_PLL_F64M); // Switch clock to PLL at same time.
 }
 
 static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)