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@@ -44,6 +44,8 @@ static const char* UART_TAG = "uart";
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#define UART_FULL_THRESH_DEFAULT (120)
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#define UART_TOUT_THRESH_DEFAULT (10)
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#define UART_TX_IDLE_NUM_DEFAULT (0)
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+#define UART_PATTERN_DET_QLEN_DEFAULT (10)
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+
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#define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
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#define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
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#define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
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@@ -58,6 +60,13 @@ typedef struct {
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} tx_data;
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} uart_tx_data_t;
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+typedef struct {
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+ int wr;
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+ int rd;
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+ int len;
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+ int* data;
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+} uart_pat_rb_t;
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+
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typedef struct {
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uart_port_t uart_num; /*!< UART port number*/
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int queue_size; /*!< UART event queue size*/
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@@ -74,6 +83,8 @@ typedef struct {
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uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/
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uint8_t rx_data_buf[UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
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uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
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+ uart_pat_rb_t rx_pattern_pos;
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+
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//tx parameters
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SemaphoreHandle_t tx_fifo_sem; /*!< UART TX FIFO semaphore*/
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SemaphoreHandle_t tx_mux; /*!< UART TX mutex*/
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@@ -91,8 +102,6 @@ typedef struct {
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uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/
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} uart_obj_t;
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-
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-
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static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
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/* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */
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static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2};
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@@ -308,6 +317,120 @@ esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
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return ESP_OK;
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}
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+static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
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+{
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
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+ if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
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+ int* pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ p_uart_obj[uart_num]->rx_pattern_pos.data = NULL;
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+ p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
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+ p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ free(pdata);
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+ }
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+ return ESP_OK;
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+}
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+
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+static esp_err_t uart_pattern_enqueue(uart_port_t uart_num, int pos)
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+{
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
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+ esp_err_t ret = ESP_OK;
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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+ int next = p_pos->wr + 1;
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+ if (next >= p_pos->len) {
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+ next = 0;
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+ }
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+ if (next == p_pos->rd) {
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+ ESP_EARLY_LOGW(UART_TAG, "Fail to enqueue pattern position, pattern queue is full.");
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+ ret = ESP_FAIL;
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+ } else {
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+ p_pos->data[p_pos->wr] = pos;
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+ p_pos->wr = next;
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+ ret = ESP_OK;
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+ }
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ return ret;
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+}
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+
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+static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
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+{
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
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+ if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
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+ return ESP_ERR_INVALID_STATE;
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+ } else {
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+ esp_err_t ret = ESP_OK;
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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+ if (p_pos->rd == p_pos->wr) {
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+ ret = ESP_FAIL;
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+ } else {
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+ p_pos->rd++;
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+ }
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+ if (p_pos->rd >= p_pos->len) {
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+ p_pos->rd = 0;
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+ }
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ return ret;
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+ }
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+}
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+
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+static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
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+{
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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+ int rd = p_pos->rd;
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+ while(rd != p_pos->wr) {
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+ p_pos->data[rd] -= diff_len;
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+ int rd_rec = rd;
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+ rd ++;
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+ if (rd >= p_pos->len) {
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+ rd = 0;
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+ }
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+ if (p_pos->data[rd_rec] < 0) {
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+ p_pos->rd = rd;
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+ }
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+ }
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ return ESP_OK;
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+}
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+
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+int uart_pattern_pop_pos(uart_port_t uart_num)
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+{
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
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+ int pos = -1;
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+ if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
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+ pos = pat_pos->data[pat_pos->rd];
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+ uart_pattern_dequeue(uart_num);
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+ }
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ return pos;
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+}
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+
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+esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
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+{
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+ UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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+ UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
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+
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+ int* pdata = (int*) malloc(queue_length * sizeof(int));
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+ if(pdata == NULL) {
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+ return ESP_ERR_NO_MEM;
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+ }
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+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
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+ int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
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+ p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
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+ p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
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+ p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
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+ p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
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+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
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+ free(ptmp);
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+ return ESP_OK;
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+}
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+
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esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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@@ -534,25 +657,42 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
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return ESP_OK;
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}
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+static int uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, int pat_num)
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+{
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+ int cnt = 0;
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+ int len = length;
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+ while (len >= 0) {
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+ if (buf[len] == pat_chr) {
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+ cnt++;
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+ } else {
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+ cnt = 0;
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+ }
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+ if (cnt >= pat_num) {
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+ break;
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+ }
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+ len --;
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+ }
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+ return len;
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+}
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+
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//internal isr handler for default driver code.
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static void uart_rx_intr_handler_default(void *param)
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{
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uart_obj_t *p_uart = (uart_obj_t*) param;
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uint8_t uart_num = p_uart->uart_num;
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uart_dev_t* uart_reg = UART[uart_num];
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+ int rx_fifo_len = uart_reg->status.rxfifo_cnt;
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uint8_t buf_idx = 0;
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uint32_t uart_intr_status = UART[uart_num]->int_st.val;
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- int rx_fifo_len = 0;
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uart_event_t uart_event;
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portBASE_TYPE HPTaskAwoken = 0;
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+ static uint8_t pat_flg = 0;
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while(uart_intr_status != 0x0) {
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buf_idx = 0;
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uart_event.type = UART_EVENT_MAX;
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if(uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) {
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- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_reg->int_ena.txfifo_empty = 0;
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- uart_reg->int_clr.txfifo_empty = 1;
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- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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+ uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
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+ uart_disable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
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if(p_uart->tx_waiting_brk) {
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continue;
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}
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@@ -563,8 +703,7 @@ static void uart_rx_intr_handler_default(void *param)
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if(HPTaskAwoken == pdTRUE) {
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portYIELD_FROM_ISR() ;
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}
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- }
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- else {
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+ } else {
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//We don't use TX ring buffer, because the size is zero.
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if(p_uart->tx_buf_size == 0) {
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continue;
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@@ -606,7 +745,7 @@ static void uart_rx_intr_handler_default(void *param)
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break;
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}
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}
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- if(p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
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+ if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
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//To fill the TX FIFO.
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int send_len = p_uart->tx_len_cur > tx_fifo_rem ? tx_fifo_rem : p_uart->tx_len_cur;
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for(buf_idx = 0; buf_idx < send_len; buf_idx++) {
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@@ -615,7 +754,7 @@ static void uart_rx_intr_handler_default(void *param)
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p_uart->tx_len_tot -= send_len;
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p_uart->tx_len_cur -= send_len;
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tx_fifo_rem -= send_len;
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- if(p_uart->tx_len_cur == 0) {
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+ if (p_uart->tx_len_cur == 0) {
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//Return item to ring buffer.
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vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
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if(HPTaskAwoken == pdTRUE) {
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@@ -644,58 +783,94 @@ static void uart_rx_intr_handler_default(void *param)
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}
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}
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}
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- if(en_tx_flg) {
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- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_reg->int_clr.txfifo_empty = 1;
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- uart_reg->int_ena.txfifo_empty = 1;
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- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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+ if (en_tx_flg) {
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+ uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M);
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+ uart_enable_intr_mask(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M);
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}
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}
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}
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- else if((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M) || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)) {
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- if(p_uart->rx_buffer_full_flg == false) {
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- //Get the buffer from the FIFO
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- rx_fifo_len = uart_reg->status.rxfifo_cnt;
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- p_uart->rx_stash_len = rx_fifo_len;
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+ else if ((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M)
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+ || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M)
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+ || (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M)
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+ ) {
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+ rx_fifo_len = uart_reg->status.rxfifo_cnt;
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+ if(pat_flg == 1) {
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+ uart_intr_status |= UART_AT_CMD_CHAR_DET_INT_ST_M;
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+ pat_flg = 0;
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+ }
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+ if (p_uart->rx_buffer_full_flg == false) {
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//We have to read out all data in RX FIFO to clear the interrupt signal
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- while(buf_idx < rx_fifo_len) {
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+ while (buf_idx < rx_fifo_len) {
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p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
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}
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- //After Copying the Data From FIFO ,Clear intr_status
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- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_reg->int_clr.rxfifo_tout = 1;
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- uart_reg->int_clr.rxfifo_full = 1;
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- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_event.size = rx_fifo_len;
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+ uint8_t pat_chr = uart_reg->at_cmd_char.data;
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+ int pat_num = uart_reg->at_cmd_char.char_num;
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+ int pat_idx = -1;
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+
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+ //Get the buffer from the FIFO
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+ if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
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+ uart_clear_intr_status(uart_num, UART_AT_CMD_CHAR_DET_INT_CLR_M);
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+ uart_event.type = UART_PATTERN_DET;
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+ uart_event.size = rx_fifo_len;
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+ pat_idx = uart_find_pattern_from_last(p_uart->rx_data_buf, rx_fifo_len - 1, pat_chr, pat_num);
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+ } else {
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+ //After Copying the Data From FIFO ,Clear intr_status
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+ uart_clear_intr_status(uart_num, UART_RXFIFO_TOUT_INT_CLR_M | UART_RXFIFO_FULL_INT_CLR_M);
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+ uart_event.type = UART_DATA;
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+ uart_event.size = rx_fifo_len;
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+ }
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+ p_uart->rx_stash_len = rx_fifo_len;
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//If we fail to push data to ring buffer, we will have to stash the data, and send next time.
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//Mainly for applications that uses flow control or small ring buffer.
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if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
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- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_reg->int_ena.rxfifo_full = 0;
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- uart_reg->int_ena.rxfifo_tout = 0;
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- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- p_uart->rx_buffer_full_flg = true;
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+ uart_disable_intr_mask(uart_num, UART_RXFIFO_TOUT_INT_ENA_M | UART_RXFIFO_FULL_INT_ENA_M);
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+ if (uart_event.type == UART_PATTERN_DET) {
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+ if (rx_fifo_len < pat_num) {
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+ //some of the characters are read out in last interrupt
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+ uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
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+ } else {
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+ uart_pattern_enqueue(uart_num,
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+ pat_idx <= -1 ?
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+ //can not find the pattern in buffer,
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+ p_uart->rx_buffered_len + p_uart->rx_stash_len :
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+ // find the pattern in buffer
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+ p_uart->rx_buffered_len + pat_idx);
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+ }
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+ if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) {
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+ ESP_EARLY_LOGW(UART_TAG, "UART event queue full");
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+ }
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+ }
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uart_event.type = UART_BUFFER_FULL;
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+ p_uart->rx_buffer_full_flg = true;
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} else {
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UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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|
|
+ if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
|
|
|
+ if (rx_fifo_len < pat_num) {
|
|
|
+ //some of the characters are read out in last interrupt
|
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|
+ uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
|
|
|
+ } else if(pat_idx >= 0) {
|
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|
+ // find pattern in statsh buffer.
|
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|
+ uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
|
|
|
+ }
|
|
|
+ }
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p_uart->rx_buffered_len += p_uart->rx_stash_len;
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UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_event.type = UART_DATA;
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}
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if(HPTaskAwoken == pdTRUE) {
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portYIELD_FROM_ISR() ;
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}
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|
} else {
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- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_reg->int_ena.rxfifo_full = 0;
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- uart_reg->int_ena.rxfifo_tout = 0;
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- uart_reg->int_clr.val = UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M;
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- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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- uart_event.type = UART_BUFFER_FULL;
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- }
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- }
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- // When fifo overflows, we reset the fifo.
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- else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
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+ uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA_M | UART_RXFIFO_TOUT_INT_ENA_M);
|
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+ uart_clear_intr_status(uart_num, UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M);
|
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+ if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
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+ uart_reg->int_clr.at_cmd_char_det = 1;
|
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+ uart_event.type = UART_PATTERN_DET;
|
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+ uart_event.size = rx_fifo_len;
|
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+ pat_flg = 1;
|
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|
+ }
|
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+ }
|
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+ } else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
|
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+ // When fifo overflows, we reset the fifo.
|
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|
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
|
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|
uart_reset_rx_fifo(uart_num);
|
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|
uart_reg->int_clr.rxfifo_ovf = 1;
|
|
|
@@ -729,18 +904,14 @@ static void uart_rx_intr_handler_default(void *param)
|
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|
}
|
|
|
}
|
|
|
} else if(uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) {
|
|
|
- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
|
|
|
- uart_reg->int_ena.tx_brk_idle_done = 0;
|
|
|
- uart_reg->int_clr.tx_brk_idle_done = 1;
|
|
|
- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
|
|
|
+ uart_disable_intr_mask(uart_num, UART_TX_BRK_IDLE_DONE_INT_ENA_M);
|
|
|
+ uart_clear_intr_status(uart_num, UART_TX_BRK_IDLE_DONE_INT_CLR_M);
|
|
|
} else if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) {
|
|
|
uart_reg->int_clr.at_cmd_char_det = 1;
|
|
|
uart_event.type = UART_PATTERN_DET;
|
|
|
} else if(uart_intr_status & UART_TX_DONE_INT_ST_M) {
|
|
|
- UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
|
|
|
- uart_reg->int_ena.tx_done = 0;
|
|
|
- uart_reg->int_clr.tx_done = 1;
|
|
|
- UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
|
|
|
+ uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M);
|
|
|
+ uart_clear_intr_status(uart_num, UART_TX_DONE_INT_CLR_M);
|
|
|
xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
|
|
|
if(HPTaskAwoken == pdTRUE) {
|
|
|
portYIELD_FROM_ISR() ;
|
|
|
@@ -751,7 +922,9 @@ static void uart_rx_intr_handler_default(void *param)
|
|
|
}
|
|
|
|
|
|
if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
|
|
|
- xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken);
|
|
|
+ if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) {
|
|
|
+ ESP_EARLY_LOGW(UART_TAG, "UART event queue full");
|
|
|
+ }
|
|
|
if(HPTaskAwoken == pdTRUE) {
|
|
|
portYIELD_FROM_ISR() ;
|
|
|
}
|
|
|
@@ -920,9 +1093,6 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
|
|
|
p_uart_obj[uart_num]->rx_cur_remain = size;
|
|
|
} else {
|
|
|
xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
|
|
|
- UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
- p_uart_obj[uart_num]->rx_buffered_len -= copy_len;
|
|
|
- UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
return copy_len;
|
|
|
}
|
|
|
}
|
|
|
@@ -932,7 +1102,11 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
|
|
|
len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
|
|
|
}
|
|
|
memcpy(buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp);
|
|
|
+ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
+ p_uart_obj[uart_num]->rx_buffered_len -= len_tmp;
|
|
|
+ uart_pattern_queue_update(uart_num, len_tmp);
|
|
|
p_uart_obj[uart_num]->rx_ptr += len_tmp;
|
|
|
+ UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
|
|
|
copy_len += len_tmp;
|
|
|
length -= len_tmp;
|
|
|
@@ -952,10 +1126,8 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
+
|
|
|
xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
|
|
|
- UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
- p_uart_obj[uart_num]->rx_buffered_len -= copy_len;
|
|
|
- UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
return copy_len;
|
|
|
}
|
|
|
|
|
|
@@ -967,7 +1139,9 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
|
|
|
return ESP_OK;
|
|
|
}
|
|
|
|
|
|
-esp_err_t uart_flush(uart_port_t uart_num)
|
|
|
+esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
|
|
|
+
|
|
|
+esp_err_t uart_flush_input(uart_port_t uart_num)
|
|
|
{
|
|
|
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
|
|
|
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
|
|
|
@@ -983,6 +1157,7 @@ esp_err_t uart_flush(uart_port_t uart_num)
|
|
|
vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
|
|
|
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
|
|
|
+ uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain);
|
|
|
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
p_uart->rx_ptr = NULL;
|
|
|
p_uart->rx_cur_remain = 0;
|
|
|
@@ -994,6 +1169,7 @@ esp_err_t uart_flush(uart_port_t uart_num)
|
|
|
}
|
|
|
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
p_uart_obj[uart_num]->rx_buffered_len -= size;
|
|
|
+ uart_pattern_queue_update(uart_num, size);
|
|
|
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
|
|
|
vRingbufferReturnItem(p_uart->rx_ring_buf, data);
|
|
|
if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
|
|
|
@@ -1024,7 +1200,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
|
|
UART_CHECK((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM set in intr_alloc_flags", ESP_FAIL); /* uart_rx_intr_handler_default is not in IRAM */
|
|
|
|
|
|
if(p_uart_obj[uart_num] == NULL) {
|
|
|
- p_uart_obj[uart_num] = (uart_obj_t*) malloc(sizeof(uart_obj_t));
|
|
|
+ p_uart_obj[uart_num] = (uart_obj_t*) calloc(1, sizeof(uart_obj_t));
|
|
|
if(p_uart_obj[uart_num] == NULL) {
|
|
|
ESP_LOGE(UART_TAG, "UART driver malloc error");
|
|
|
return ESP_FAIL;
|
|
|
@@ -1044,6 +1220,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
|
|
|
p_uart_obj[uart_num]->tx_brk_len = 0;
|
|
|
p_uart_obj[uart_num]->tx_waiting_brk = 0;
|
|
|
p_uart_obj[uart_num]->rx_buffered_len = 0;
|
|
|
+ uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
|
|
|
|
|
|
if(uart_queue) {
|
|
|
p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
|
|
|
@@ -1103,6 +1280,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
|
|
|
esp_intr_free(p_uart_obj[uart_num]->intr_handle);
|
|
|
uart_disable_rx_intr(uart_num);
|
|
|
uart_disable_tx_intr(uart_num);
|
|
|
+ uart_pattern_link_free(uart_num);
|
|
|
|
|
|
if(p_uart_obj[uart_num]->tx_fifo_sem) {
|
|
|
vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);
|